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andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/lib_fifo_v1_0/hdl/src/vhdl/sync_fifo_fg.vhd | 7 | 70413 | -- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** but not limited to any warranties or representations that this **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_regdirect.vhd | 4 | 414905 | -------------------------------------------------------------------------------
-- axi_vdma_regdirect
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_regdirect.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_regdirect is
generic(
C_NUM_REGISTERS : integer := 6 ;
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
C_NUM_FSTORES_64 : integer range 1 to 32 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
stop : in std_logic ; --
--
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
-- Register Direct Support --
prmtr_updt_complete : out std_logic ; --
regdir_idle : out std_logic ; --
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_strid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : out STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
reg_module_start_address1 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address2 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address3 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address4 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address5 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address6 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address7 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address8 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address9 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address10 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address11 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address12 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address13 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address14 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address15 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address16 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address17 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address18 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address19 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address20 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address21 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address22 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address23 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address24 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address25 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address26 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address27 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address28 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address29 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address30 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address31 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address32 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_regdirect;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_regdirect is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSYNC_INDEX : integer := 0; -- VSYNC Register index
constant HSYNC_INDEX : integer := 1; -- HSYNC Register index
constant DLY_STRIDE_INDEX : integer := 2; -- STRIDE/DLY Reg index
--constant RESERVED_INDEX3 : integer := 3; -- Reserved
constant STARTADDR1_INDEX : integer := 3; -- Start Address 1 Reg index
constant STARTADDR2_INDEX : integer := 4; -- Start Address 2 Reg index
constant STARTADDR3_INDEX : integer := 5; -- Start Address 3 Reg index
constant STARTADDR4_INDEX : integer := 6; -- Start Address 3 Reg index
constant STARTADDR5_INDEX : integer := 7; -- Start Address 3 Reg index
constant STARTADDR6_INDEX : integer := 8; -- Start Address 3 Reg index
constant STARTADDR7_INDEX : integer := 9; -- Start Address 3 Reg index
constant STARTADDR8_INDEX : integer := 10; -- Start Address 3 Reg index
constant STARTADDR9_INDEX : integer := 11; -- Start Address 3 Reg index
constant STARTADDR10_INDEX : integer := 12; -- Start Address 3 Reg index
constant STARTADDR11_INDEX : integer := 13; -- Start Address 3 Reg index
constant STARTADDR12_INDEX : integer := 14; -- Start Address 3 Reg index
constant STARTADDR13_INDEX : integer := 15; -- Start Address 3 Reg index
constant STARTADDR14_INDEX : integer := 16; -- Start Address 3 Reg index
constant STARTADDR15_INDEX : integer := 17; -- Start Address 3 Reg index
constant STARTADDR16_INDEX : integer := 18; -- Start Address 3 Reg index
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal prmtr_updt_complete_i : std_logic := '0';
signal reg_config_locked_i : std_logic := '0';
signal regdir_idle_i : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal run_stop_re : std_logic := '0';
--signal reg_module_strt_addr_i : STARTADDR_ARRAY_TYPE(0 to MAX_FSTORES-1);
signal reg_module_start_address1_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address2_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address3_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address4_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address5_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address6_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address7_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address8_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address9_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address10_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address11_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address12_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address13_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address14_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address15_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address16_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address17_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address18_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address19_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address20_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address21_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address22_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address23_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address24_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address25_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address26_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address27_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address28_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address29_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address30_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address31_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address32_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register DMACR RunStop bit to create a RE pulse
REG_RUN_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_RE;
run_stop_re <= run_stop and not run_stop_d1;
-- Gen register direct idle flag to indicate when not idle.
-- Flag is asserted to NOT idle at start of run and to Idle
-- on reset, halt, or stop (i.e. error)
-- This is used to generate first fsync in free run mode.
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or stop = '1')then
regdir_idle_i <= '1';
elsif(run_stop_re = '1')then
regdir_idle_i <= '0';
elsif(prmtr_updt_complete_i = '1')then
regdir_idle_i <= '1';
end if;
end if;
end process REG_IDLE;
regdir_idle <= regdir_idle_i;
-- Vertical Size Register
VSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_vsize <= (others => '0');
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_vsize <= axi2ip_wrdata(VSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process VSIZE_REGISTER;
VIDEO_PRMTR_UPDATE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or run_stop = '0')then
prmtr_updt_complete_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
prmtr_updt_complete_i <= '1';
else
prmtr_updt_complete_i <= '0';
end if;
end if;
end process VIDEO_PRMTR_UPDATE;
prmtr_updt_complete <= prmtr_updt_complete_i;
-- Horizontal Size Register
HSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_hsize <= (others => '0');
elsif(axi2ip_wrce(HSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_hsize <= axi2ip_wrdata(HSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process HSIZE_REGISTER;
-- Delay/Stride Register
--Genlock Slave mode
S_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
--reg_module_frmdly <= (others => '0');
reg_module_frmdly <= "00001"; --CR 709007
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_frmdly <= axi2ip_wrdata(FRMDLY_MSB downto FRMDLY_LSB);
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process S_DLYSTRIDE_REGISTER;
end generate S_GEN_DLYSTRIDE_REGISTER;
--Genlock Master mode
M_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
reg_module_frmdly <= (others => '0');
M_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process M_DLYSTRIDE_REGISTER;
end generate M_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Master mode
DM_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
reg_module_frmdly <= (others => '0');
DM_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DM_DLYSTRIDE_REGISTER;
end generate DM_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Slave mode
DS_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
reg_module_frmdly <= (others => '0');
DS_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DS_DLYSTRIDE_REGISTER;
end generate DS_GEN_DLYSTRIDE_REGISTER;
--No Dynamic resolution
GEN_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 0 generate
begin
REG_CONFIG_LOCKED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
reg_config_locked_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1')then
reg_config_locked_i <= '1';
end if;
end if;
end process REG_CONFIG_LOCKED;
end generate GEN_REG_CONFIG_LOCK_BIT;
--Dynamic resolution
GEN_NO_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 1 generate
begin
reg_config_locked_i <= '0';
end generate GEN_NO_REG_CONFIG_LOCK_BIT;
--*****************************************************************************
--** START ADDRESS REGISTERS
--*****************************************************************************
-- Generate C_NUM_FSTORE start address registeres
--GEN_START_ADDR_REG : for i in 1 to MAX_FSTORES generate
----signal j : integer := 1;
--
--begin
----j<= i;
--
-- -- Start Address Registers
-- START_ADDR : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
-- -- Write to appropriate Start Address
--
-- elsif(i>= C_NUM_FSTORES)then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
--
--
-- elsif(i<C_NUM_FSTORES and axi2ip_wrce(i+2) = '1'and C_NUM_FSTORES <17)then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '0')then
-- --if(i<17 and axi2ip_wrce(i+2) = '1')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i+15) <= axi2ip_wrdata;
-- --end if;
-- --elsif(i>=17 and axi2ip_wrce(i-14) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '0')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-17) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --end if;
-- --end if;
-- -- For frames greater than fstores the vectors are reserved
-- -- and set to zero
-- end if;
-- end if;
-- end process START_ADDR;
--end generate GEN_START_ADDR_REG;
-- Map only C_NUM_FSTORE vectors to output port
-- Number of Fstores Generate
GEN_NUM_FSTORES_1 : if C_NUM_FSTORES = 1 generate
-- Start Address Register
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
reg_module_start_address2_i <= (others => '0');
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_1;
-- Number of Fstores Generate
GEN_NUM_FSTORES_2 : if C_NUM_FSTORES = 2 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_2;
-- Number of Fstores Generate
GEN_NUM_FSTORES_3 : if C_NUM_FSTORES = 3 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_3;
-- Number of Fstores Generate
GEN_NUM_FSTORES_4 : if C_NUM_FSTORES = 4 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_4;
-- Number of Fstores Generate
GEN_NUM_FSTORES_5 : if C_NUM_FSTORES = 5 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_5;
-- Number of Fstores Generate
GEN_NUM_FSTORES_6 : if C_NUM_FSTORES = 6 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_6;
-- Number of Fstores Generate
GEN_NUM_FSTORES_7 : if C_NUM_FSTORES = 7 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_7;
-- Number of Fstores Generate
GEN_NUM_FSTORES_8 : if C_NUM_FSTORES = 8 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_8;
-- Number of Fstores Generate
GEN_NUM_FSTORES_9 : if C_NUM_FSTORES = 9 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_9;
-- Number of Fstores Generate
GEN_NUM_FSTORES_10 : if C_NUM_FSTORES = 10 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_10;
-- Number of Fstores Generate
GEN_NUM_FSTORES_11 : if C_NUM_FSTORES = 11 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_11;
-- Number of Fstores Generate
GEN_NUM_FSTORES_12 : if C_NUM_FSTORES = 12 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_12;
-- Number of Fstores Generate
GEN_NUM_FSTORES_13 : if C_NUM_FSTORES = 13 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_13;
-- Number of Fstores Generate
GEN_NUM_FSTORES_14 : if C_NUM_FSTORES = 14 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_14;
-- Number of Fstores Generate
GEN_NUM_FSTORES_15 : if C_NUM_FSTORES = 15 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_15;
-- Number of Fstores Generate
GEN_NUM_FSTORES_16 : if C_NUM_FSTORES = 16 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_16;
-- Number of Fstores Generate
GEN_NUM_FSTORES_17 : if C_NUM_FSTORES = 17 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_17;
-- Number of Fstores Generate
GEN_NUM_FSTORES_18 : if C_NUM_FSTORES = 18 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_18;
-- Number of Fstores Generate
GEN_NUM_FSTORES_19 : if C_NUM_FSTORES = 19 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_19;
-- Number of Fstores Generate
GEN_NUM_FSTORES_20 : if C_NUM_FSTORES = 20 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_20;
-- Number of Fstores Generate
GEN_NUM_FSTORES_21 : if C_NUM_FSTORES = 21 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_21;
-- Number of Fstores Generate
GEN_NUM_FSTORES_22 : if C_NUM_FSTORES = 22 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_22;
-- Number of Fstores Generate
GEN_NUM_FSTORES_23 : if C_NUM_FSTORES = 23 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_23;
-- Number of Fstores Generate
GEN_NUM_FSTORES_24 : if C_NUM_FSTORES = 24 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_24;
-- Number of Fstores Generate
GEN_NUM_FSTORES_25 : if C_NUM_FSTORES = 25 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_25;
-- Number of Fstores Generate
GEN_NUM_FSTORES_26 : if C_NUM_FSTORES = 26 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_26;
-- Number of Fstores Generate
GEN_NUM_FSTORES_27 : if C_NUM_FSTORES = 27 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_27;
-- Number of Fstores Generate
GEN_NUM_FSTORES_28 : if C_NUM_FSTORES = 28 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_28;
-- Number of Fstores Generate
GEN_NUM_FSTORES_29 : if C_NUM_FSTORES = 29 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_29;
-- Number of Fstores Generate
GEN_NUM_FSTORES_30 : if C_NUM_FSTORES = 30 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_30;
-- Number of Fstores Generate
GEN_NUM_FSTORES_31 : if C_NUM_FSTORES = 31 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_31;
-- Number of Fstores Generate
GEN_NUM_FSTORES_32 : if C_NUM_FSTORES = 32 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
--START_ADDR16 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address16_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address16_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
START_ADDR32 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address32_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR32;
end generate GEN_NUM_FSTORES_32;
-- Number of Fstores Generate
GEN_1 : if C_NUM_FSTORES = 1 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
end generate GEN_1;
-- Number of Fstores Generate
GEN_2 : if C_NUM_FSTORES = 2 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
end generate GEN_2;
-- Number of Fstores Generate
GEN_3 : if C_NUM_FSTORES = 3 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
end generate GEN_3;
-- Number of Fstores Generate
GEN_4 : if C_NUM_FSTORES = 4 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
end generate GEN_4;
-- Number of Fstores Generate
GEN_5 : if C_NUM_FSTORES = 5 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
end generate GEN_5;
-- Number of Fstores Generate
GEN_6 : if C_NUM_FSTORES = 6 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
end generate GEN_6;
-- Number of Fstores Generate
GEN_7 : if C_NUM_FSTORES = 7 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
end generate GEN_7;
-- Number of Fstores Generate
GEN_8 : if C_NUM_FSTORES = 8 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
end generate GEN_8;
-- Number of Fstores Generate
GEN_9 : if C_NUM_FSTORES = 9 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
end generate GEN_9;
-- Number of Fstores Generate
GEN_10 : if C_NUM_FSTORES = 10 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
end generate GEN_10;
-- Number of Fstores Generate
GEN_11 : if C_NUM_FSTORES = 11 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
end generate GEN_11;
-- Number of Fstores Generate
GEN_12 : if C_NUM_FSTORES = 12 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
end generate GEN_12;
-- Number of Fstores Generate
GEN_13 : if C_NUM_FSTORES = 13 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
end generate GEN_13;
-- Number of Fstores Generate
GEN_14 : if C_NUM_FSTORES = 14 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
end generate GEN_14;
-- Number of Fstores Generate
GEN_15 : if C_NUM_FSTORES = 15 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
end generate GEN_15;
-- Number of Fstores Generate
GEN_16 : if C_NUM_FSTORES = 16 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
end generate GEN_16;
-- Number of Fstores Generate
GEN_17 : if C_NUM_FSTORES = 17 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
end generate GEN_17;
-- Number of Fstores Generate
GEN_18 : if C_NUM_FSTORES = 18 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
end generate GEN_18;
-- Number of Fstores Generate
GEN_19 : if C_NUM_FSTORES = 19 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
end generate GEN_19;
-- Number of Fstores Generate
GEN_20 : if C_NUM_FSTORES = 20 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
end generate GEN_20;
-- Number of Fstores Generate
GEN_21 : if C_NUM_FSTORES = 21 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
end generate GEN_21;
-- Number of Fstores Generate
GEN_22 : if C_NUM_FSTORES = 22 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
end generate GEN_22;
-- Number of Fstores Generate
GEN_23 : if C_NUM_FSTORES = 23 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
end generate GEN_23;
-- Number of Fstores Generate
GEN_24 : if C_NUM_FSTORES = 24 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
end generate GEN_24;
-- Number of Fstores Generate
GEN_25 : if C_NUM_FSTORES = 25 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
end generate GEN_25;
-- Number of Fstores Generate
GEN_26 : if C_NUM_FSTORES = 26 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
end generate GEN_26;
-- Number of Fstores Generate
GEN_27 : if C_NUM_FSTORES = 27 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
end generate GEN_27;
-- Number of Fstores Generate
GEN_28 : if C_NUM_FSTORES = 28 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
end generate GEN_28;
-- Number of Fstores Generate
GEN_29 : if C_NUM_FSTORES = 29 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
end generate GEN_29;
-- Number of Fstores Generate
GEN_30 : if C_NUM_FSTORES = 30 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
end generate GEN_30;
-- Number of Fstores Generate
GEN_31 : if C_NUM_FSTORES = 31 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
end generate GEN_31;
-- Number of Fstores Generate
GEN_32 : if C_NUM_FSTORES = 32 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
reg_module_strt_addr(31) <= reg_module_start_address32_i ;
end generate GEN_32;
--GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
--begin
--
-- reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
--
--end generate GEN_START_ADDR_MAP;
--reg_module_strt_addr(0) <= reg_module_start_address1_i ;
--reg_module_strt_addr(1) <= reg_module_start_address2_i ;
--reg_module_strt_addr(2) <= reg_module_start_address3_i ;
--reg_module_strt_addr(3) <= reg_module_start_address4_i ;
--reg_module_strt_addr(4) <= reg_module_start_address5_i ;
--reg_module_strt_addr(5) <= reg_module_start_address6_i ;
--reg_module_strt_addr(6) <= reg_module_start_address7_i ;
--reg_module_strt_addr(7) <= reg_module_start_address8_i ;
--reg_module_strt_addr(8) <= reg_module_start_address9_i ;
--reg_module_strt_addr(9) <= reg_module_start_address10_i ;
--reg_module_strt_addr(10) <= reg_module_start_address11_i ;
--reg_module_strt_addr(11) <= reg_module_start_address12_i ;
--reg_module_strt_addr(12) <= reg_module_start_address13_i ;
--reg_module_strt_addr(13) <= reg_module_start_address14_i ;
--reg_module_strt_addr(14) <= reg_module_start_address15_i ;
--reg_module_strt_addr(15) <= reg_module_start_address16_i ;
--reg_module_strt_addr(16) <= reg_module_start_address17_i ;
--reg_module_strt_addr(17) <= reg_module_start_address18_i ;
--reg_module_strt_addr(18) <= reg_module_start_address19_i ;
--reg_module_strt_addr(19) <= reg_module_start_address20_i ;
--reg_module_strt_addr(20) <= reg_module_start_address21_i ;
--reg_module_strt_addr(21) <= reg_module_start_address22_i ;
--reg_module_strt_addr(22) <= reg_module_start_address23_i ;
--reg_module_strt_addr(23) <= reg_module_start_address24_i ;
--reg_module_strt_addr(24) <= reg_module_start_address25_i ;
--reg_module_strt_addr(25) <= reg_module_start_address26_i ;
--reg_module_strt_addr(26) <= reg_module_start_address27_i ;
--reg_module_strt_addr(27) <= reg_module_start_address28_i ;
--reg_module_strt_addr(28) <= reg_module_start_address29_i ;
--reg_module_strt_addr(29) <= reg_module_start_address30_i ;
--reg_module_strt_addr(30) <= reg_module_start_address31_i ;
--reg_module_strt_addr(31) <= reg_module_start_address32_i ;
---- Map for use in read mux.
reg_module_start_address1 <= reg_module_start_address1_i ;
reg_module_start_address2 <= reg_module_start_address2_i ;
reg_module_start_address3 <= reg_module_start_address3_i ;
reg_module_start_address4 <= reg_module_start_address4_i ;
reg_module_start_address5 <= reg_module_start_address5_i ;
reg_module_start_address6 <= reg_module_start_address6_i ;
reg_module_start_address7 <= reg_module_start_address7_i ;
reg_module_start_address8 <= reg_module_start_address8_i ;
reg_module_start_address9 <= reg_module_start_address9_i ;
reg_module_start_address10 <= reg_module_start_address10_i ;
reg_module_start_address11 <= reg_module_start_address11_i ;
reg_module_start_address12 <= reg_module_start_address12_i ;
reg_module_start_address13 <= reg_module_start_address13_i ;
reg_module_start_address14 <= reg_module_start_address14_i ;
reg_module_start_address15 <= reg_module_start_address15_i ;
reg_module_start_address16 <= reg_module_start_address16_i ;
reg_module_start_address17 <= reg_module_start_address17_i ;
reg_module_start_address18 <= reg_module_start_address18_i ;
reg_module_start_address19 <= reg_module_start_address19_i ;
reg_module_start_address20 <= reg_module_start_address20_i ;
reg_module_start_address21 <= reg_module_start_address21_i ;
reg_module_start_address22 <= reg_module_start_address22_i ;
reg_module_start_address23 <= reg_module_start_address23_i ;
reg_module_start_address24 <= reg_module_start_address24_i ;
reg_module_start_address25 <= reg_module_start_address25_i ;
reg_module_start_address26 <= reg_module_start_address26_i ;
reg_module_start_address27 <= reg_module_start_address27_i ;
reg_module_start_address28 <= reg_module_start_address28_i ;
reg_module_start_address29 <= reg_module_start_address29_i ;
reg_module_start_address30 <= reg_module_start_address30_i ;
reg_module_start_address31 <= reg_module_start_address31_i ;
reg_module_start_address32 <= reg_module_start_address32_i ;
--------*****************************************************************************
--------** START ADDRESS REGISTERS
--------*****************************************************************************
------
-------- Generate C_NUM_FSTORE start address registeres
------GEN_START_ADDR_REG : for i in 0 to MAX_FSTORES-1 generate
------begin
------
------ -- Start Address Registers
------ START_ADDR : process(prmry_aclk)
------ begin
------ if(prmry_aclk'EVENT and prmry_aclk = '1')then
------ if(prmry_resetn = '0')then
------ reg_module_strt_addr_i(i) <= (others => '0');
------ -- Write to appropriate Start Address
------ -- Index based on [(i+1)*2]+2. This gives an index increment
------ -- starting at 4 then going 6,8,10,12, etc. skipping each
------ -- reserved space between 32-bit start addresses. For
------ -- 64bit addressing this index calculation will need to be
------ -- modified.
------ elsif(i<C_NUM_FSTORES and axi2ip_wrce(((i+1)*2)+2) = '1')then
------ reg_module_strt_addr_i(i) <= axi2ip_wrdata;
------
------ -- For frames greater than fstores the vectors are reserved
------ -- and set to zero
------ elsif(i>= C_NUM_FSTORES)then
------ reg_module_strt_addr_i(i) <= (others => '0');
------
------ end if;
------ end if;
------ end process START_ADDR;
------end generate GEN_START_ADDR_REG;
------
-------- Map only C_NUM_FSTORE vectors to output port
------GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
------begin
------
------ reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
------
------end generate GEN_START_ADDR_MAP;
------
------
-------- Map for use in read mux.
------reg_module_start_address1_i <= reg_module_strt_addr_i(0);
------reg_module_start_address2_i <= reg_module_strt_addr_i(1);
------reg_module_start_address3_i <= reg_module_strt_addr_i(2);
------reg_module_start_address4_i <= reg_module_strt_addr_i(3);
------reg_module_start_address5_i <= reg_module_strt_addr_i(4);
------reg_module_start_address6_i <= reg_module_strt_addr_i(5);
------reg_module_start_address7_i <= reg_module_strt_addr_i(6);
------reg_module_start_address8_i <= reg_module_strt_addr_i(7);
------reg_module_start_address9_i <= reg_module_strt_addr_i(8);
------reg_module_start_address10_i <= reg_module_strt_addr_i(9);
------reg_module_start_address11_i <= reg_module_strt_addr_i(10);
------reg_module_start_address12_i <= reg_module_strt_addr_i(11);
------reg_module_start_address13_i <= reg_module_strt_addr_i(12);
------reg_module_start_address14_i <= reg_module_strt_addr_i(13);
------reg_module_start_address15_i <= reg_module_strt_addr_i(14);
------reg_module_start_address16_i <= reg_module_strt_addr_i(15);
------reg_module_start_address17_i <= reg_module_strt_addr_i(16);
------reg_module_start_address18_i <= reg_module_strt_addr_i(17);
------reg_module_start_address19_i <= reg_module_strt_addr_i(18);
------reg_module_start_address20_i <= reg_module_strt_addr_i(19);
------reg_module_start_address21_i <= reg_module_strt_addr_i(20);
------reg_module_start_address22_i <= reg_module_strt_addr_i(21);
------reg_module_start_address23_i <= reg_module_strt_addr_i(22);
------reg_module_start_address24_i <= reg_module_strt_addr_i(23);
------reg_module_start_address25_i <= reg_module_strt_addr_i(24);
------reg_module_start_address26_i <= reg_module_strt_addr_i(25);
------reg_module_start_address27_i <= reg_module_strt_addr_i(26);
------reg_module_start_address28_i <= reg_module_strt_addr_i(27);
------reg_module_start_address29_i <= reg_module_strt_addr_i(28);
------reg_module_start_address30_i <= reg_module_strt_addr_i(29);
------reg_module_start_address31_i <= reg_module_strt_addr_i(30);
------reg_module_start_address32_i <= reg_module_strt_addr_i(31);
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd | 5 | 74551 | -------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd | 5 | 74551 | -------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_sg_cdc.vhd | 4 | 43586 | -------------------------------------------------------------------------------
-- axi_vdma_sg_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sg_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator for Scatter Gather signals
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_vdma_sg_cdc is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- From Register Module (Primary Clk Domain) --
reg2cdc_run_stop : in std_logic ; --
reg2cdc_stop : in std_logic ; --
reg2cdc_taildesc_wren : in std_logic ; --
reg2cdc_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
reg2cdc_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- To Scatter Gather Engine (Secondary Clk Domain --
cdc2sg_run_stop : out std_logic ; --
cdc2sg_stop : out std_logic ; --
cdc2sg_taildesc_wren : out std_logic ; --
cdc2sg_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2sg_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- From Scatter Gather Engine (Secondary Clk Domain) --
sg2cdc_ftch_idle : in std_logic ; --
sg2cdc_ftch_interr_set : in std_logic ; --
sg2cdc_ftch_slverr_set : in std_logic ; --
sg2cdc_ftch_decerr_set : in std_logic ; --
sg2cdc_ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
sg2cdc_ftch_err : in std_logic ; --
--
-- To DMA Controller --
cdc2dmac_ftch_idle : out std_logic ; --
--
-- To Register Module --
cdc2reg_ftch_interr_set : out std_logic ; --
cdc2reg_ftch_slverr_set : out std_logic ; --
cdc2reg_ftch_decerr_set : out std_logic ; --
cdc2reg_ftch_err_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2reg_ftch_err : out std_logic --
);
end axi_vdma_sg_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sg_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg2cdc_taildesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal sg2cdc_ftch_err_addr_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal reg2cdc_curdesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Aysnchronous mode therefore instantiate clock domain crossing logic
GEN_CDC_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- CUR_DESC_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '1' ,
---- prmry_vect_in => reg2cdc_curdesc ,
---- scndry_vect_out => cdc2sg_curdesc
---- );
-- Register signal in to give clear FF output to CDC
P_IN_CUR_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_curdesc_i <= (others => '0');
else
reg2cdc_curdesc_i <= reg2cdc_curdesc;
end if;
end if;
end process P_IN_CUR_DESC;
CUR_DESC_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_curdesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_curdesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_taildesc_wren ,
---- scndry_out => cdc2sg_taildesc_wren ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- scndry_vect_out => open
---- );
TAIL_DESC_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_taildesc_wren,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_taildesc_wren,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_VECT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => reg2cdc_taildesc_wren ,
---- prmry_vect_in => reg2cdc_taildesc ,
---- scndry_vect_out => cdc2sg_taildesc
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_TAIL_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_taildesc_i <= (others => '0');
elsif(reg2cdc_taildesc_wren = '1')then
reg2cdc_taildesc_i <= reg2cdc_taildesc;
end if;
end if;
end process P_IN_TAIL_DESC;
TAIL_DESC_VECT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_taildesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_taildesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- RUNSTOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_run_stop ,
---- scndry_out => cdc2sg_run_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
RUNSTOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_run_stop,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_stop ,
---- scndry_out => cdc2sg_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_stop,
scndry_vect_out => open
);
-- From SG Engine (secondary clock domain) to
-- DMA Controller (primary clock domain)
---- FTCH_IDLE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1 ,
---- C_RESET_STATE => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_idle ,
---- prmry_out => cdc2dmac_ftch_idle ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_IDLE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2dmac_ftch_idle,
scndry_vect_out => open
);
--sg to reg
-- From SG Engine (secondary clock domain) to
-- Register Block (primary clock domain)
---- FTCH_INTERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_interr_set ,
---- prmry_out => cdc2reg_ftch_interr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_INTERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_interr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_interr_set,
scndry_vect_out => open
);
---- FTCH_SLVERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_slverr_set ,
---- prmry_out => cdc2reg_ftch_slverr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_SLVERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_slverr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_slverr_set,
scndry_vect_out => open
);
---- FTCH_DECERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_decerr_set ,
---- prmry_out => cdc2reg_ftch_decerr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_DECERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_decerr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_decerr_set,
scndry_vect_out => open
);
---- ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_err ,
---- prmry_out => cdc2reg_ftch_err ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_err,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_err,
scndry_vect_out => open
);
---- ERR_VECT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => sg2cdc_ftch_err ,
---- scndry_vect_in => sg2cdc_ftch_err_addr ,
---- prmry_vect_out => cdc2reg_ftch_err_addr ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_ERR_VECT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
sg2cdc_ftch_err_addr_i <= (others => '0');
elsif(sg2cdc_ftch_err = '1')then
sg2cdc_ftch_err_addr_i <= sg2cdc_ftch_err_addr;
end if;
end if;
end process P_IN_ERR_VECT;
ERR_VECT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => '0',
prmry_vect_in => sg2cdc_ftch_err_addr_i,
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => open,
scndry_vect_out => cdc2reg_ftch_err_addr
);
end generate GEN_CDC_FOR_ASYNC;
-- Synchronous Mode therefore map inputs to associated
-- outputs directly.
GEN_NO_CDC_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
cdc2sg_run_stop <= reg2cdc_run_stop ;
cdc2sg_stop <= reg2cdc_stop ;
cdc2sg_taildesc_wren <= reg2cdc_taildesc_wren ;
cdc2sg_taildesc <= reg2cdc_taildesc ;
cdc2sg_curdesc <= reg2cdc_curdesc ;
cdc2dmac_ftch_idle <= sg2cdc_ftch_idle ;
cdc2reg_ftch_interr_set <= sg2cdc_ftch_interr_set ;
cdc2reg_ftch_slverr_set <= sg2cdc_ftch_slverr_set ;
cdc2reg_ftch_decerr_set <= sg2cdc_ftch_decerr_set ;
cdc2reg_ftch_err <= sg2cdc_ftch_err ;
cdc2reg_ftch_err_addr <= sg2cdc_ftch_err_addr ;
end generate GEN_NO_CDC_FOR_SYNC;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/lib_pkg_v1_0/hdl/src/vhdl/lib_pkg.vhd | 28 | 16351 | -- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_genlock_mngr.vhd | 4 | 139378 | -------------------------------------------------------------------------------
-- axi_vdma_genlock_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_genlock_mngr.vhd
--
-- Description: This entity encompasses the Gen Lock Manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_genlock_mngr is
generic(
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1 ;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_NUM_FSTORES : integer range 1 to 32 := 5
-- Number of Frame Stores
);
port (
-- Secondary Clock Domain
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Dynamic Frame Store Support --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Gen-Lock Slave Signals --
mstr_in_control : in std_logic_vector(3 downto 0) ; --
genlock_select : in std_logic ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
slv_frame_ref_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
fsize_mismatch_err_flag : in std_logic ;
--
-- Gen-Lock Master Signals --
dmasr_halt : in std_logic ; --
circular_prk_mode : in std_logic ; --
mstr_frame_update : in std_logic ; --
mstr_frame_ref_in : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) --
);
end axi_vdma_genlock_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_genlock_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-- Number of bits to analyze for grey code enconding and decoding
constant GREY_NUM_BITS : integer := max2(1,clog2(C_NUM_FSTORES));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Slave only signals
signal grey_frame_ptr : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal grey_frmstr_adjusted : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal partial_frame_ptr : std_logic_vector(GREY_NUM_BITS-1 downto 0) := (others => '0');
signal padded_partial_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
-- Master and Slave signals
signal s_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rvc_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal reg_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal grey_frame_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal dm_mstr_reverse_order : std_logic := '0';
signal dm_mstr_reverse_order_d1 : std_logic := '0';
signal s_mstr_reverse_order : std_logic := '0';
signal ds_mstr_reverse_order : std_logic := '0';
signal s_mstr_reverse_order_d1 : std_logic := '0';
signal ds_mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order : std_logic := '0';
signal mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order_d2 : std_logic := '0';
-- Test signals
signal mstrfrm_tstsync_d1 : std_logic := '0';
signal mstrfrm_tstsync_d2 : std_logic := '0';
signal mstrfrm_tstsync_d3 : std_logic := '0';
signal mstrfrm_tstsync_d4 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for slave
-------------------------------------------------------------------------------
GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 1 generate
begin
-----------------------------------------------------------------------------------------------------------------------------------
--Output GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
-------------------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
S_GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
S_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= '0';
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process S_PARTIAL_NOT_P2;
-- Register to break long timing paths
S_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_binary_frame_ptr <= (others => '0');
else
s_binary_frame_ptr <= s_inv_raw_frame_ptr;
end if;
end if;
end process S_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
s_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
s_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
s_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
S_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_mstr_reverse_order_d1 <= '1';
else
s_mstr_reverse_order_d1 <= s_mstr_reverse_order;
end if;
end if;
end process S_REG_DELAY_FLAG;
FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(s_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(s_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= s_binary_frame_ptr;
end if;
end if;
end process FRAME_CONVERT_P3;
mstrfrm_tstsync_out <= '0'; -- Not used for slaves
end generate GENLOCK_FOR_SLAVE;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 0 generate
begin
-- Only used for slave mode
slv_frame_ref_out <= (others => '0');
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 2 generate
begin
----------------------------------------------------------------------------------------------------------
--un-greying Dynamic slave's (internal or external) frame number
----------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DM_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= '0';
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DM_PARTIAL_NOT_P2;
-- Register to break long timing paths
DM_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_binary_frame_ptr <= (others => '0');
else
dm_binary_frame_ptr <= dm_inv_raw_frame_ptr;
end if;
end if;
end process DM_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DM_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
dm_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
dm_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
dm_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DM_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DM_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_mstr_reverse_order_d1 <= '1';
else
dm_mstr_reverse_order_d1 <= dm_mstr_reverse_order;
end if;
end if;
end process DM_REG_DELAY_FLAG;
DM_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(dm_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(dm_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= dm_binary_frame_ptr;
end if;
end if;
end process DM_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------
--grey frame number out for dynamic genlock master
-----------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for Dynamic slave
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 3 generate
begin
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DS_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= '0';
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DS_PARTIAL_NOT_P2;
-- Register to break long timing paths
DS_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_binary_frame_ptr <= (others => '0');
else
ds_binary_frame_ptr <= ds_inv_raw_frame_ptr;
end if;
end if;
end process DS_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DS_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
ds_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
ds_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
ds_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DS_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DS_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_mstr_reverse_order_d1 <= '1';
else
ds_mstr_reverse_order_d1 <= ds_mstr_reverse_order;
end if;
end if;
end process DS_REG_DELAY_FLAG;
DS_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(ds_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(ds_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= ds_binary_frame_ptr;
end if;
end if;
end process DS_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--Output Dynamic GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
DS2_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process DS2_REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_SLAVE;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/hdl/block_design_wrapper.vhd | 1 | 7768 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design_wrapper.bd
--Design : block_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_wrapper is
port (
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MCLK : out STD_LOGIC;
AC_MUTE_N : out STD_LOGIC;
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_I : in STD_LOGIC;
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
ac_i2c_scl_io : inout STD_LOGIC;
ac_i2c_sda_io : inout STD_LOGIC;
mic_spi_io0_io : inout STD_LOGIC;
mic_spi_io1_io : inout STD_LOGIC;
mic_spi_sck_io : inout STD_LOGIC;
mic_spi_ss1_o : out STD_LOGIC;
mic_spi_ss2_o : out STD_LOGIC;
mic_spi_ss_io : inout STD_LOGIC
);
end block_design_wrapper;
architecture STRUCTURE of block_design_wrapper is
component block_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
AC_I2C_sda_i : in STD_LOGIC;
AC_I2C_sda_o : out STD_LOGIC;
AC_I2C_sda_t : out STD_LOGIC;
AC_I2C_scl_i : in STD_LOGIC;
AC_I2C_scl_o : out STD_LOGIC;
AC_I2C_scl_t : out STD_LOGIC;
MIC_SPI_sck_i : in STD_LOGIC;
MIC_SPI_sck_o : out STD_LOGIC;
MIC_SPI_sck_t : out STD_LOGIC;
MIC_SPI_io0_i : in STD_LOGIC;
MIC_SPI_io0_o : out STD_LOGIC;
MIC_SPI_io0_t : out STD_LOGIC;
MIC_SPI_io1_i : in STD_LOGIC;
MIC_SPI_io1_o : out STD_LOGIC;
MIC_SPI_io1_t : out STD_LOGIC;
MIC_SPI_ss_i : in STD_LOGIC;
MIC_SPI_ss_o : out STD_LOGIC;
MIC_SPI_ss1_o : out STD_LOGIC;
MIC_SPI_ss2_o : out STD_LOGIC;
MIC_SPI_ss_t : out STD_LOGIC;
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MCLK : out STD_LOGIC;
AC_SDATA_I : in STD_LOGIC;
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MUTE_N : out STD_LOGIC
);
end component block_design;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal ac_i2c_scl_i : STD_LOGIC;
signal ac_i2c_scl_o : STD_LOGIC;
signal ac_i2c_scl_t : STD_LOGIC;
signal ac_i2c_sda_i : STD_LOGIC;
signal ac_i2c_sda_o : STD_LOGIC;
signal ac_i2c_sda_t : STD_LOGIC;
signal mic_spi_io0_i : STD_LOGIC;
signal mic_spi_io0_o : STD_LOGIC;
signal mic_spi_io0_t : STD_LOGIC;
signal mic_spi_io1_i : STD_LOGIC;
signal mic_spi_io1_o : STD_LOGIC;
signal mic_spi_io1_t : STD_LOGIC;
signal mic_spi_sck_i : STD_LOGIC;
signal mic_spi_sck_o : STD_LOGIC;
signal mic_spi_sck_t : STD_LOGIC;
signal mic_spi_ss_i : STD_LOGIC;
signal mic_spi_ss_o : STD_LOGIC;
signal mic_spi_ss_t : STD_LOGIC;
begin
ac_i2c_scl_iobuf: component IOBUF
port map (
I => ac_i2c_scl_o,
IO => ac_i2c_scl_io,
O => ac_i2c_scl_i,
T => ac_i2c_scl_t
);
ac_i2c_sda_iobuf: component IOBUF
port map (
I => ac_i2c_sda_o,
IO => ac_i2c_sda_io,
O => ac_i2c_sda_i,
T => ac_i2c_sda_t
);
block_design_i: component block_design
port map (
AC_BCLK(0) => AC_BCLK(0),
AC_I2C_scl_i => ac_i2c_scl_i,
AC_I2C_scl_o => ac_i2c_scl_o,
AC_I2C_scl_t => ac_i2c_scl_t,
AC_I2C_sda_i => ac_i2c_sda_i,
AC_I2C_sda_o => ac_i2c_sda_o,
AC_I2C_sda_t => ac_i2c_sda_t,
AC_MCLK => AC_MCLK,
AC_MUTE_N => AC_MUTE_N,
AC_PBLRC(0) => AC_PBLRC(0),
AC_RELRC(0) => AC_RELRC(0),
AC_SDATA_I => AC_SDATA_I,
AC_SDATA_O(0) => AC_SDATA_O(0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
MIC_SPI_io0_i => mic_spi_io0_i,
MIC_SPI_io0_o => mic_spi_io0_o,
MIC_SPI_io0_t => mic_spi_io0_t,
MIC_SPI_io1_i => mic_spi_io1_i,
MIC_SPI_io1_o => mic_spi_io1_o,
MIC_SPI_io1_t => mic_spi_io1_t,
MIC_SPI_sck_i => mic_spi_sck_i,
MIC_SPI_sck_o => mic_spi_sck_o,
MIC_SPI_sck_t => mic_spi_sck_t,
MIC_SPI_ss1_o => mic_spi_ss1_o,
MIC_SPI_ss2_o => mic_spi_ss2_o,
MIC_SPI_ss_i => mic_spi_ss_i,
MIC_SPI_ss_o => mic_spi_ss_o,
MIC_SPI_ss_t => mic_spi_ss_t
);
mic_spi_io0_iobuf: component IOBUF
port map (
I => mic_spi_io0_o,
IO => mic_spi_io0_io,
O => mic_spi_io0_i,
T => mic_spi_io0_t
);
mic_spi_io1_iobuf: component IOBUF
port map (
I => mic_spi_io1_o,
IO => mic_spi_io1_io,
O => mic_spi_io1_i,
T => mic_spi_io1_t
);
mic_spi_sck_iobuf: component IOBUF
port map (
I => mic_spi_sck_o,
IO => mic_spi_sck_io,
O => mic_spi_sck_i,
T => mic_spi_sck_t
);
mic_spi_ss_iobuf: component IOBUF
port map (
I => mic_spi_ss_o,
IO => mic_spi_ss_io,
O => mic_spi_ss_i,
T => mic_spi_ss_t
);
end STRUCTURE;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_rst_module.vhd | 4 | 25470 | -------------------------------------------------------------------------------
-- axi_vdma_rst_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axis_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
s_axis_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_soft_reset : in std_logic ; --
mm2s_soft_reset_clr : out std_logic := '0' ; --
mm2s_all_idle : in std_logic ; --
mm2s_fsize_mismatch_err : in std_logic ; -- CR591965
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_run_stop : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_soft_reset : in std_logic ; --
s2mm_soft_reset_clr : out std_logic := '0' ; --
s2mm_all_idle : in std_logic ; --
s2mm_fsize_mismatch_err : in std_logic ; -- CR591965
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_run_stop : in std_logic ; --
--
----------------------------------------------------------------------- --
-- SG Status --
----------------------------------------------------------------------- --
ftch_err : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Primary Reset (Raw) --
mm2s_dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Logic Reset --
mm2s_axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Outputs --
mm2s_axis_reset_out_n : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Primary Reset (Raw) --
s2mm_dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Logic Reset --
s2mm_axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Outputs --
s2mm_axis_reset_out_n : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_resetn : out std_logic := '1' ; --
m_axi_dm_sg_resetn : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
s_axi_lite_resetn : out std_logic := '1' ; --
mm2s_hrd_resetn : out std_logic := '1' ; --
s2mm_hrd_resetn : out std_logic := '1' --
);
end axi_vdma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal hrd_resetn_i : std_logic := '1';
--signal axi_lite_resetn_d1 : std_logic := '1';
signal mm2s_axi_sg_resetn : std_logic := '1';
signal mm2s_dm_axi_sg_resetn : std_logic := '1';
signal s2mm_axi_sg_resetn : std_logic := '1';
signal s2mm_dm_axi_sg_resetn : std_logic := '1';
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
REG_HRD_RST : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
hrd_resetn_i <= axi_resetn;
end if;
end process REG_HRD_RST;
s_axi_lite_resetn <= hrd_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
signal sig_mm2s_dm_prmry_resetn : std_logic := '1';
signal sig_mm2s_axis_resetn : std_logic := '1';
signal sig_mm2s_prmry_resetn : std_logic := '1';
Attribute KEEP of sig_mm2s_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_prmry_resetn : signal is "no";
Attribute KEEP of sig_mm2s_dm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_dm_prmry_resetn : signal is "no";
Attribute KEEP of sig_mm2s_axis_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_axis_resetn : signal is "no";
begin
mm2s_prmry_resetn <= sig_mm2s_prmry_resetn;
mm2s_dm_prmry_resetn <= sig_mm2s_dm_prmry_resetn;
mm2s_axis_resetn <= sig_mm2s_axis_resetn;
RESET_I : entity axi_vdma_v6_2_8.axi_vdma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SG => C_INCLUDE_SG -- CR622081
)
port map(
-- Clock Sources
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
prmry_axi_aclk => m_axi_mm2s_aclk ,
prmry_axis_aclk => m_axis_mm2s_aclk ,
-- Hard Reset
axi_resetn => hrd_resetn_i ,
hrd_axi_resetn => mm2s_hrd_resetn ,
-- Soft Reset
soft_reset => mm2s_soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
run_stop => mm2s_run_stop ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
-- MM2S Main Primary Reset (Hard and Soft)
prmry_resetn => sig_mm2s_prmry_resetn ,
-- MM2S Main Datamover Primary Reset (RAW) (Hard and Soft)
dm_prmry_resetn => sig_mm2s_dm_prmry_resetn ,
-- AXI Stream Reset (Hard and Soft)
axis_resetn => sig_mm2s_axis_resetn ,
-- AXI Stream Reset Out (Hard and Soft)
axis_reset_out_n => mm2s_axis_reset_out_n ,
-- AXI Scatter/Gather Reset (Hard and Soft)
axi_sg_resetn => mm2s_axi_sg_resetn ,
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft)
axi_dm_sg_resetn => mm2s_dm_axi_sg_resetn
);
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_resetn <= '1';
mm2s_dm_prmry_resetn <= '1';
mm2s_axis_resetn <= '1';
mm2s_axis_reset_out_n <= '1';
mm2s_axi_sg_resetn <= '1';
mm2s_dm_axi_sg_resetn <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
signal sig_s2mm_dm_prmry_resetn : std_logic := '1';
signal sig_s2mm_axis_resetn : std_logic := '1';
signal sig_s2mm_prmry_resetn : std_logic := '1';
Attribute KEEP of sig_s2mm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_prmry_resetn : signal is "no";
Attribute KEEP of sig_s2mm_dm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_dm_prmry_resetn : signal is "no";
Attribute KEEP of sig_s2mm_axis_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_axis_resetn : signal is "no";
begin
s2mm_prmry_resetn <= sig_s2mm_prmry_resetn;
s2mm_dm_prmry_resetn <= sig_s2mm_dm_prmry_resetn;
s2mm_axis_resetn <= sig_s2mm_axis_resetn;
RESET_I : entity axi_vdma_v6_2_8.axi_vdma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SG => C_INCLUDE_SG -- CR622081
)
port map(
-- Clock Sources
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
prmry_axi_aclk => m_axi_s2mm_aclk ,
prmry_axis_aclk => s_axis_s2mm_aclk ,
-- Hard Reset
axi_resetn => hrd_resetn_i ,
hrd_axi_resetn => s2mm_hrd_resetn ,
-- Soft Reset
soft_reset => s2mm_soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
run_stop => s2mm_run_stop ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
-- MM2S Main Primary Reset (Hard and Soft)
prmry_resetn => sig_s2mm_prmry_resetn ,
-- MM2S Main Datamover Primary Reset (RAW) (Hard and Soft)
dm_prmry_resetn => sig_s2mm_dm_prmry_resetn ,
-- AXI Stream Reset (Hard and Soft)
axis_resetn => sig_s2mm_axis_resetn ,
-- AXI Stream Reset Out (Hard and Soft)
axis_reset_out_n => s2mm_axis_reset_out_n ,
-- AXI Scatter/Gather Reset (Hard and Soft)
axi_sg_resetn => s2mm_axi_sg_resetn ,
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft)
axi_dm_sg_resetn => s2mm_dm_axi_sg_resetn
);
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_resetn <= '1';
s2mm_dm_prmry_resetn <= '1';
s2mm_axis_resetn <= '1';
s2mm_axis_reset_out_n <= '1';
s2mm_axi_sg_resetn <= '1';
s2mm_dm_axi_sg_resetn <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
end generate GEN_NO_RESET_FOR_S2MM;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
REG_SG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If there is a scatter gather error, then a reset on either channel
-- (soft or hard) will reset axi_sg engine
if(ftch_err = '1')then
m_axi_sg_resetn <= mm2s_axi_sg_resetn and s2mm_axi_sg_resetn;
m_axi_dm_sg_resetn <= mm2s_dm_axi_sg_resetn and s2mm_dm_axi_sg_resetn;
-- If no scatter gather erros then only a hard reset will reset scatter gather engine
else
m_axi_sg_resetn <= hrd_resetn_i;
m_axi_dm_sg_resetn <= hrd_resetn_i;
end if;
end if;
end process REG_SG_RESET_OUT;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
m_axi_sg_resetn <= '1';
m_axi_dm_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_rst_module.vhd | 4 | 25470 | -------------------------------------------------------------------------------
-- axi_vdma_rst_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axis_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
s_axis_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_soft_reset : in std_logic ; --
mm2s_soft_reset_clr : out std_logic := '0' ; --
mm2s_all_idle : in std_logic ; --
mm2s_fsize_mismatch_err : in std_logic ; -- CR591965
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_run_stop : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_soft_reset : in std_logic ; --
s2mm_soft_reset_clr : out std_logic := '0' ; --
s2mm_all_idle : in std_logic ; --
s2mm_fsize_mismatch_err : in std_logic ; -- CR591965
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_run_stop : in std_logic ; --
--
----------------------------------------------------------------------- --
-- SG Status --
----------------------------------------------------------------------- --
ftch_err : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Primary Reset (Raw) --
mm2s_dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Logic Reset --
mm2s_axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Outputs --
mm2s_axis_reset_out_n : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Primary Reset (Raw) --
s2mm_dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Logic Reset --
s2mm_axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Outputs --
s2mm_axis_reset_out_n : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_resetn : out std_logic := '1' ; --
m_axi_dm_sg_resetn : out std_logic := '1' ; --
--
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
s_axi_lite_resetn : out std_logic := '1' ; --
mm2s_hrd_resetn : out std_logic := '1' ; --
s2mm_hrd_resetn : out std_logic := '1' --
);
end axi_vdma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal hrd_resetn_i : std_logic := '1';
--signal axi_lite_resetn_d1 : std_logic := '1';
signal mm2s_axi_sg_resetn : std_logic := '1';
signal mm2s_dm_axi_sg_resetn : std_logic := '1';
signal s2mm_axi_sg_resetn : std_logic := '1';
signal s2mm_dm_axi_sg_resetn : std_logic := '1';
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
REG_HRD_RST : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
hrd_resetn_i <= axi_resetn;
end if;
end process REG_HRD_RST;
s_axi_lite_resetn <= hrd_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
signal sig_mm2s_dm_prmry_resetn : std_logic := '1';
signal sig_mm2s_axis_resetn : std_logic := '1';
signal sig_mm2s_prmry_resetn : std_logic := '1';
Attribute KEEP of sig_mm2s_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_prmry_resetn : signal is "no";
Attribute KEEP of sig_mm2s_dm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_dm_prmry_resetn : signal is "no";
Attribute KEEP of sig_mm2s_axis_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_mm2s_axis_resetn : signal is "no";
begin
mm2s_prmry_resetn <= sig_mm2s_prmry_resetn;
mm2s_dm_prmry_resetn <= sig_mm2s_dm_prmry_resetn;
mm2s_axis_resetn <= sig_mm2s_axis_resetn;
RESET_I : entity axi_vdma_v6_2_8.axi_vdma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SG => C_INCLUDE_SG -- CR622081
)
port map(
-- Clock Sources
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
prmry_axi_aclk => m_axi_mm2s_aclk ,
prmry_axis_aclk => m_axis_mm2s_aclk ,
-- Hard Reset
axi_resetn => hrd_resetn_i ,
hrd_axi_resetn => mm2s_hrd_resetn ,
-- Soft Reset
soft_reset => mm2s_soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
run_stop => mm2s_run_stop ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
-- MM2S Main Primary Reset (Hard and Soft)
prmry_resetn => sig_mm2s_prmry_resetn ,
-- MM2S Main Datamover Primary Reset (RAW) (Hard and Soft)
dm_prmry_resetn => sig_mm2s_dm_prmry_resetn ,
-- AXI Stream Reset (Hard and Soft)
axis_resetn => sig_mm2s_axis_resetn ,
-- AXI Stream Reset Out (Hard and Soft)
axis_reset_out_n => mm2s_axis_reset_out_n ,
-- AXI Scatter/Gather Reset (Hard and Soft)
axi_sg_resetn => mm2s_axi_sg_resetn ,
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft)
axi_dm_sg_resetn => mm2s_dm_axi_sg_resetn
);
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_resetn <= '1';
mm2s_dm_prmry_resetn <= '1';
mm2s_axis_resetn <= '1';
mm2s_axis_reset_out_n <= '1';
mm2s_axi_sg_resetn <= '1';
mm2s_dm_axi_sg_resetn <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
signal sig_s2mm_dm_prmry_resetn : std_logic := '1';
signal sig_s2mm_axis_resetn : std_logic := '1';
signal sig_s2mm_prmry_resetn : std_logic := '1';
Attribute KEEP of sig_s2mm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_prmry_resetn : signal is "no";
Attribute KEEP of sig_s2mm_dm_prmry_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_dm_prmry_resetn : signal is "no";
Attribute KEEP of sig_s2mm_axis_resetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s2mm_axis_resetn : signal is "no";
begin
s2mm_prmry_resetn <= sig_s2mm_prmry_resetn;
s2mm_dm_prmry_resetn <= sig_s2mm_dm_prmry_resetn;
s2mm_axis_resetn <= sig_s2mm_axis_resetn;
RESET_I : entity axi_vdma_v6_2_8.axi_vdma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SG => C_INCLUDE_SG -- CR622081
)
port map(
-- Clock Sources
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
prmry_axi_aclk => m_axi_s2mm_aclk ,
prmry_axis_aclk => s_axis_s2mm_aclk ,
-- Hard Reset
axi_resetn => hrd_resetn_i ,
hrd_axi_resetn => s2mm_hrd_resetn ,
-- Soft Reset
soft_reset => s2mm_soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
run_stop => s2mm_run_stop ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
-- MM2S Main Primary Reset (Hard and Soft)
prmry_resetn => sig_s2mm_prmry_resetn ,
-- MM2S Main Datamover Primary Reset (RAW) (Hard and Soft)
dm_prmry_resetn => sig_s2mm_dm_prmry_resetn ,
-- AXI Stream Reset (Hard and Soft)
axis_resetn => sig_s2mm_axis_resetn ,
-- AXI Stream Reset Out (Hard and Soft)
axis_reset_out_n => s2mm_axis_reset_out_n ,
-- AXI Scatter/Gather Reset (Hard and Soft)
axi_sg_resetn => s2mm_axi_sg_resetn ,
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft)
axi_dm_sg_resetn => s2mm_dm_axi_sg_resetn
);
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_resetn <= '1';
s2mm_dm_prmry_resetn <= '1';
s2mm_axis_resetn <= '1';
s2mm_axis_reset_out_n <= '1';
s2mm_axi_sg_resetn <= '1';
s2mm_dm_axi_sg_resetn <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
end generate GEN_NO_RESET_FOR_S2MM;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
REG_SG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If there is a scatter gather error, then a reset on either channel
-- (soft or hard) will reset axi_sg engine
if(ftch_err = '1')then
m_axi_sg_resetn <= mm2s_axi_sg_resetn and s2mm_axi_sg_resetn;
m_axi_dm_sg_resetn <= mm2s_dm_axi_sg_resetn and s2mm_dm_axi_sg_resetn;
-- If no scatter gather erros then only a hard reset will reset scatter gather engine
else
m_axi_sg_resetn <= hrd_resetn_i;
m_axi_dm_sg_resetn <= hrd_resetn_i;
end if;
end if;
end process REG_SG_RESET_OUT;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
m_axi_sg_resetn <= '1';
m_axi_dm_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/bd/block_design/ipshared/analogdeviceinc.com/axi_i2s_adi_v1_0/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd | 7 | 1587 | library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_tx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_tx_fifo is
signal in_ack : std_logic;
signal drain_dma : Boolean;
begin
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => S_AXIS_TVALID,
in_ack => in_ack,
in_data => S_AXIS_TDATA,
out_stb => out_stb,
out_ack => out_ack,
out_data => out_data
);
drain_process: process (S_AXIS_ACLK) is
variable enable_d1 : Boolean;
begin
if rising_edge(S_AXIS_ACLK) then
if resetn = '0' then
drain_dma <= False;
else
if S_AXIS_TLAST = '1' then
drain_dma <= False;
elsif enable_d1 and enable then
drain_dma <= True;
end if;
enable_d1 := enable;
end if;
end if;
end process;
S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0';
end;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_intrpt.vhd | 4 | 31463 | -------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_intrpt.vhd | 4 | 31463 | -------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd | 4 | 37201 | -------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Created top level for descriptor update queue management
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
ch2_updt_curdesc_wren : out std_logic ; --
ch2_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 1 generate
begin
--*****************************************************************************
--** CHANNEL 1 - DESCRIPTOR QUEUE **
--*****************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH1_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH1_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_NO_QUEUE;
end generate GEN_CH1_UPDATE_Q_IF;
-- Channel 1 NOT included therefore tie ch1 outputs off
GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
begin
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '1';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
m_axis_ch1_updt_tdata <= (others => '0');
m_axis_ch1_updt_tlast <= '0';
m_axis_ch1_updt_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
begin
--*************************************************************************
--** CHANNEL 2 - DESCRIPTOR QUEUE **
--*************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
---------------------------------------------------------------------------
I_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_FAMILY => C_FAMILY
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_QUEUE;
--*****************************************************************************
--** CHANNEL 2 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
I_NO_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_NO_QUEUE;
end generate GEN_CH2_UPDATE_Q_IF;
-- Channel 2 NOT included therefore tie ch2 outputs off
GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
begin
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '1';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
m_axis_ch2_updt_tdata <= (others => '0');
m_axis_ch2_updt_tlast <= '0';
m_axis_ch2_updt_tvalid <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
TO_DATAMVR_MUX : process(ch1_updt_active,
ch2_updt_active,
m_axis_ch1_updt_tdata,
m_axis_ch1_updt_tlast,
m_axis_ch1_updt_tvalid,
m_axis_ch2_updt_tdata,
m_axis_ch2_updt_tlast,
m_axis_ch2_updt_tvalid)
begin
if(ch1_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
elsif(ch2_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
else
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
end if;
end process TO_DATAMVR_MUX;
m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set_nodre.vhd | 18 | 43117 | -------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set_nodre.vhd | 18 | 43117 | -------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma.vhd | 4 | 284148 | -------------------------------------------------------------------------------
-- axi_vdma
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma.vhd
-- Description: This entity is the top level entity for the AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v5_1_11.axi_datamover.vhd (FULL)
-- |- axi_vdma_v6_2_8.axi_sg_v4_03.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
--library axi_sg_v4_03;
--use axi_sg_v4_03.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - all clocks may be asynchronous.
-----------------------------------------------------------------------
-- Video Specific Parameters
-----------------------------------------------------------------------
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads (Saves FPGA Resources)
-- 1 = Enable Video Parameter Reads
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_NUM_FSTORES : integer range 1 to 32 := 3;
-- Number of Frame Stores
C_USE_FSYNC : integer range 0 to 3 := 1;
-- 2013.1 : Spilt into C_USE_MM2S_FSYNC & C_USE_S2MM_FSYNC. C_USE_FSYNC is no longer used.
C_USE_MM2S_FSYNC : integer range 0 to 1 := 0; --2013.1
-- Specifies MM2S channel operation synchronized to frame sync input
-- 0 = channel is Free running
-- 1 = channel uses mm2s_fsync as a frame_sync
C_USE_S2MM_FSYNC : integer range 0 to 2 := 2; --2013.1
-- Specifies MM2S channel operation synchronized to frame sync input
-- 0 = channel is Free running
-- 1 = channel uses s2mm_fsync as a frame_sync
-- 2 = channel uses s2mm_tuser(0) as a frame_sync
C_FLUSH_ON_FSYNC : integer range 0 to 3 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Specifies VDMA will flush on frame sync
-- 0 = Disabled - both channel halts on error detection
-- 1 = Enabled - both channel does not halt and will flush on next fsync
-- 2 = Enabled - ONLY MM2S channel does not halt and will flush on next fsync
-- 3 = Enabled - ONLY S2MM channel does not halt and will flush on next fsync
C_INCLUDE_INTERNAL_GENLOCK : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Include or exclude the use of internal genlock bus.
-- 0 = Exclude internal genlock bus
-- 1 = Include internal genlock bus
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_MM2S_GENLOCK_MODE : integer range 0 to 3 := 3;
-- Specifies the Gen-Lock mode for the MM2S Channel
-- 0 = Master Mode
-- 1 = Slave Mode
C_MM2S_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1;
-- Specifies the number of Gen-Lock masters a Gen-Lock slave
-- can be synchronized with
C_MM2S_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0;
-- In flush on frame sync mode specifies whether frame number
-- will increment on error'ed frame or repeat error'ed frame
-- 0 = increment frame
-- 1 = repeat frame
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Enable/Disable start of frame generation on tuser(0).
-- 0 = disable SOF
-- 1 = enable SOF
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_MM2S_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Depth of line buffer. Width of the line buffer is derived from Streaming width.
C_MM2S_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Almost Empty Threshold. Threshold point at which MM2S line buffer
-- almost empty flag asserts high. Must be a resolution of
-- C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Minimum valid value is C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Maximum valid value is C_MM2S_LINEBUFFER_DEPTH
C_MM2S_MAX_BURST_LENGTH : integer range 2 to 256 := 8;
-- Maximum burst size in databeats per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 64;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_S2MM_GENLOCK_MODE : integer range 0 to 3 := 2;
-- Specifies the Gen-Lock mode for the S2MM Channel
-- 0 = Master Mode
-- 1 = Slave Mode
C_S2MM_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1;
-- Specifies the number of Gen-Lock masters a Gen-Lock slave
-- can be synchronized with
C_S2MM_GENLOCK_REPEAT_EN : integer range 0 to 1 := 1;
-- In flush on frame sync mode specifies whether frame number
-- will increment on error'ed frame or repeat error'ed frame
-- 0 = increment frame
-- 1 = repeat frame
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Enable/Disable start of frame generation on tuser(0).
-- 0 = disable SOF
-- 1 = enable SOF
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_S2MM_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Depth of line buffer. Width of the line buffer is derived from Streaming width.
C_S2MM_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Almost Full Threshold. Threshold point at which S2MM line buffer
-- almost full flag asserts high. Must be a resolution of
-- C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Minimum valid value is C_S_AXIS_S2MM_TDATA_WIDTH/8
-- Maximum valid value is C_S2MM_LINEBUFFER_DEPTH
C_S2MM_MAX_BURST_LENGTH : integer range 2 to 256 := 8;
-- Maximum burst size in data beats per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 64;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_S_AXIS_S2MM_TUSER_BITS : integer range 1 to 1 := 1;
-- Slave AXI Stream User Width for S2MM Channel
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '0');
-- Enable debug information
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 0;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 0;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 0;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 0;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 0;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 0;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 0;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 0;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 0;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 0;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 0;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 0;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 0;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INSTANCE : string := "axi_vdma";
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Control Clocks
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
-- MM2S Clocks
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axis_mm2s_aclk : in std_logic := '0' ; --
-- S2MM Clocks
m_axi_s2mm_aclk : in std_logic := '0' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Video Interface --
----------------------------------------------------------------------- --
mm2s_fsync : in std_logic := '0' ; --
mm2s_frame_ptr_in : in std_logic_vector --
((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); --
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0); --
s2mm_fsync : in std_logic := '0'; --
s2mm_frame_ptr_in : in std_logic_vector --
((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); --
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0); --
mm2s_buffer_empty : out std_logic ; --
mm2s_buffer_almost_empty : out std_logic ; --
s2mm_buffer_full : out std_logic ; --
s2mm_buffer_almost_full : out std_logic ; --
--
mm2s_fsync_out : out std_logic ; --
s2mm_fsync_out : out std_logic ; --
mm2s_prmtr_update : out std_logic ; --
s2mm_prmtr_update : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := (others => '0') ; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := (others => '0'); --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; --
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := (others => '0'); --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; --
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); --
s_axis_s2mm_tuser : in std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
--
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_vdma_tstvec : out std_logic_vector(63 downto 0) --
);
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
attribute IP_GROUP : string;
attribute IP_GROUP of axi_vdma : entity is "LOGICORE";
attribute IPTYPE : string;
attribute IPTYPE of axi_vdma : entity is "PERIPHERAL";
attribute RUN_NGCBUILD : string;
attribute RUN_NGCBUILD of axi_vdma : entity is "TRUE";
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_vdma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_vdma,{"
--& "C_FAMILY= " & C_FAMILY
--& ",C_INSTANCE = " & C_INSTANCE
--& ",C_DLYTMR_RESOLUTION= " & integer'image(C_DLYTMR_RESOLUTION)
--& ",C_PRMRY_IS_ACLK_ASYNC= " & integer'image(C_PRMRY_IS_ACLK_ASYNC)
--& ",C_ENABLE_VIDPRMTR_READS= " & integer'image(C_ENABLE_VIDPRMTR_READS)
--& ",C_DYNAMIC_RESOLUTION= " & integer'image(C_DYNAMIC_RESOLUTION)
--& ",C_NUM_FSTORES= " & integer'image(C_NUM_FSTORES)
--& ",C_USE_MM2S_FSYNC= " & integer'image(C_USE_MM2S_FSYNC)
--& ",C_USE_S2MM_FSYNC= " & integer'image(C_USE_S2MM_FSYNC)
--& ",C_INCLUDE_SG= " & integer'image(C_INCLUDE_SG)
--& ",C_INCLUDE_MM2S= " & integer'image(C_INCLUDE_MM2S)
--& ",C_MM2S_GENLOCK_MODE= " & integer'image(C_MM2S_GENLOCK_MODE)
--& ",C_MM2S_GENLOCK_NUM_MASTERS= " & integer'image(C_MM2S_GENLOCK_NUM_MASTERS)
--& ",C_INCLUDE_MM2S_DRE= " & integer'image(C_INCLUDE_MM2S_DRE)
--& ",C_MM2S_LINEBUFFER_DEPTH= " & integer'image(C_MM2S_LINEBUFFER_DEPTH)
--& ",C_MM2S_MAX_BURST_LENGTH= " & integer'image(C_MM2S_MAX_BURST_LENGTH)
--& ",C_M_AXI_MM2S_DATA_WIDTH = " & integer'image(C_M_AXI_MM2S_DATA_WIDTH)
--& ",C_M_AXIS_MM2S_TDATA_WIDTH = " & integer'image(C_M_AXIS_MM2S_TDATA_WIDTH)
--& ",C_INCLUDE_S2MM= " & integer'image(C_INCLUDE_S2MM)
--& ",C_S2MM_GENLOCK_MODE= " & integer'image(C_S2MM_GENLOCK_MODE)
--& ",C_S2MM_GENLOCK_NUM_MASTERS= " & integer'image(C_S2MM_GENLOCK_NUM_MASTERS)
--& ",C_INCLUDE_S2MM_DRE= " & integer'image(C_INCLUDE_S2MM_DRE)
--& ",C_S2MM_LINEBUFFER_DEPTH= " & integer'image(C_S2MM_LINEBUFFER_DEPTH)
--& ",C_S2MM_MAX_BURST_LENGTH= " & integer'image(C_S2MM_MAX_BURST_LENGTH)
--& ",C_M_AXI_S2MM_DATA_WIDTH= " & integer'image(C_M_AXI_S2MM_DATA_WIDTH)
--& ",C_S_AXIS_S2MM_TDATA_WIDTH= " & integer'image(C_S_AXIS_S2MM_TDATA_WIDTH)
--& "}";
--attribute CORE_GENERATION_INFO : string;
--attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Major Version number 0, 1, 2, 3 etc.
constant VERSION_MAJOR : std_logic_vector (3 downto 0) := X"6" ;
-- Minor Version Number 00, 01, 02, etc.
constant VERSION_MINOR : std_logic_vector (7 downto 0) := X"20";
-- Version Revision character (EDK) a,b,c,etc
constant VERSION_REVISION : std_logic_vector (3 downto 0) := X"0" ;
-- Internal build number
constant REVISION_NUMBER : string := "Build Number: P80";
constant C_M_AXI_MM2S_ADDR_WIDTH_NEW : integer := width_calc (C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_NEW : integer := width_calc (C_M_AXI_S2MM_ADDR_WIDTH);
--*****************************************************************************
--** Scatter Gather Engine Configuration
--*****************************************************************************
constant SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
-- Number of Fetch Descriptors to Queue
constant SG_FTCH_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 7;
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 7;
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERR : integer := 0;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERR : integer := 0;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor pointer update bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor status update bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33;
-- Include SG Descriptor Updates
constant EXCLUDE_DESC_UPDATE : integer := 0; -- No Descriptor update for video
-- Include SG Interrupt Logic
constant EXCLUDE_INTRPT : integer := 0; -- Interrupt logic external to sg engine
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
constant EXCLUDE_DLYTMR : integer := 0;
--*****************************************************************************
--** General/Misc Constants
--*****************************************************************************
--constant C_USE_MM2S_FSYNC : integer :=find_mm2s_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM);
--constant C_USE_S2MM_FSYNC : integer :=find_s2mm_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM);
constant C_USE_S2MM_FSYNC_01 : integer :=find_s2mm_fsync_01(C_USE_S2MM_FSYNC);
--constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC);
--constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC);
--constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC);
--constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC);
constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer := C_USE_MM2S_FSYNC;
constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer := C_USE_S2MM_FSYNC_01;
--*****************************************************************************
--** AXI LITE Interface Constants
--*****************************************************************************
--constant TOTAL_NUM_REGISTER : integer := NUM_REG_TOTAL_REGDIR;
constant TOTAL_NUM_REGISTER : integer := get_num_registers(C_INCLUDE_SG,NUM_REG_TOTAL_SG,NUM_REG_TOTAL_REGDIR);
constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := calculated_mm2s_tdata_width(C_M_AXIS_MM2S_TDATA_WIDTH);
constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED : integer := calculated_s2mm_tdata_width(C_S_AXIS_S2MM_TDATA_WIDTH);
constant C_MM2S_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_M_AXIS_MM2S_TDATA_WIDTH,C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED,C_INCLUDE_MM2S_DRE);
constant C_S2MM_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_S_AXIS_S2MM_TDATA_WIDTH,C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED,C_INCLUDE_S2MM_DRE);
-- Specifies to register module which channel is which
constant CHANNEL_IS_MM2S : integer := 1;
constant CHANNEL_IS_S2MM : integer := 0;
--*****************************************************************************
--** DataMover General Constants
--*****************************************************************************
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
constant DM_CMDSTS_FIFO_DEPTH : integer := 4;
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 4;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- Datamover clock always synchronous
constant DM_CLOCK_SYNC : integer := 0;
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
constant ZERO_VALUE : std_logic_vector(1023 downto 0) := (others => '0');
--*****************************************************************************
--** S2MM DataMover Specific Constants
--*****************************************************************************
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := C_INCLUDE_S2MM * AXI_FULL_MODE;
-- CR591965 - Modified for flush on frame sync
-- Enable indeterminate BTT on datamover when S2MM Store And Forward Present
-- In this mode, the DataMovers S2MM store and forward buffer will be used
-- and underflow and overflow will be detected via receive byte compare
-- Enable indeterminate BTT on datamover when S2MM flush on frame sync is
-- enabled allowing S2MM AXIS stream absorption and prevent datamover
-- halt. Overflow and Underfow error detected external to datamover
-- in axi_vdma_cmdsts.vhd
constant DM_SUPPORT_INDET_BTT : integer := 1;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- DataMover status width is based on mode of operation
constant S2MM_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- Never extend on S2MM
constant S2MM_DM_CMD_EXTENDED : integer := 0;
-- Minimum value required for length width based on burst size and stream dwidth
-- If hsize is too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant S2MM_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED,
C_S2MM_MAX_BURST_LENGTH,
HSIZE_DWIDTH);
constant C_INCLUDE_S2MM_SF_INT : integer := 1;
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF_INT,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED);
--*****************************************************************************
--** MM2S DataMover Specific Constants
--*****************************************************************************
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := C_INCLUDE_MM2S * AXI_FULL_MODE;
-- Never extend on MM2S
constant MM2S_DM_CMD_NOT_EXTENDED : integer := 0;
-- DataMover status width - fixed to 8 for MM2S
constant MM2S_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH;
-- Minimum value required for length width based on burst size and stream dwidth
-- If hsize is too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant MM2S_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED,
C_MM2S_MAX_BURST_LENGTH,
HSIZE_DWIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
----constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
---- C_M_AXI_MM2S_DATA_WIDTH,
---- C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED);
----
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(0,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED);
--constant DM_MM2S_INCLUDE_SF : integer := 0;
--*****************************************************************************
--** Line Buffer Constants
--*****************************************************************************
-- For LineBuffer, track vertical lines to allow de-assertion of tready
-- when s2mm finished with frame. MM2S does not need to track lines
constant TRACK_NO_LINES : integer := 0;
constant TRACK_LINES : integer := 1;
-- zero vector of vsize width used to tie off mm2s line tracking ports
constant VSIZE_ZERO : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer default Almost Empty Threshold and Almost Full threshold
constant LINEBUFFER_AE_THRESH : integer := 1;
constant LINEBUFFER_AF_THRESH : integer := max2(1,C_MM2S_LINEBUFFER_DEPTH/2);
-- Include and Exclude settings for linebuffer skid buffers
constant INCLUDE_MSTR_SKID_BUFFER : integer := 1;
constant EXCLUDE_MSTR_SKID_BUFFER : integer := 0;
constant INCLUDE_SLV_SKID_BUFFER : integer := 1;
constant EXCLUDE_SLV_SKID_BUFFER : integer := 0;
-------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
-------- Also converts depth in bytes to depth in data beats
------constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_MM2S_LINEBUFFER_DEPTH/(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)),
------ (C_PRMRY_IS_ACLK_ASYNC*512))));
------
-------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
-------- Also converts depth in bytes to depth in data beats
------constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_S2MM_LINEBUFFER_DEPTH/(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)),
------ (C_PRMRY_IS_ACLK_ASYNC*512))));
------
--2013.1
--constant MM2S_LINEBUFFER_DEPTH : integer := C_MM2S_LINEBUFFER_DEPTH;
--constant S2MM_LINEBUFFER_DEPTH : integer := C_S2MM_LINEBUFFER_DEPTH;
-- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_MM2S_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512))));
-- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_S2MM_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512))));
-- Enable SOF only for external frame sync and when SOF Enable parameter set
----constant MM2S_SOF_ENABLE : integer := C_USE_MM2S_FSYNC * C_MM2S_SOF_ENABLE;
--constant MM2S_SOF_ENABLE : integer := C_MM2S_SOF_ENABLE;
constant MM2S_SOF_ENABLE : integer := 1;
--constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC * C_S2MM_SOF_ENABLE;
--constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC ;
constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC_01 ;
--*****************************************************************************
--** GenLock Constants
--*****************************************************************************
-- GenLock Data Widths for Clock Domain Crossing Module
constant MM2S_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_MM2S_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH);
constant S2MM_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_S2MM_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH);
--constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, C_INCLUDE_INTERNAL_GENLOCK,
-- C_MM2S_GENLOCK_MODE,
-- C_S2MM_GENLOCK_MODE);
--
constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, 1,
C_MM2S_GENLOCK_MODE,
C_S2MM_GENLOCK_MODE);
constant C_MM2S_LINEBUFFER_THRESH_INT : integer := calculated_minimum_mm2s_linebuffer_thresh(C_INCLUDE_MM2S, C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED, C_MM2S_LINEBUFFER_DEPTH);
constant C_S2MM_LINEBUFFER_THRESH_INT : integer := calculated_minimum_s2mm_linebuffer_thresh(C_INCLUDE_S2MM, C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED, C_S2MM_LINEBUFFER_DEPTH);
Constant C_ROOT_FAMILY : string := C_FAMILY; -- function from family_support.vhd
constant C_NUM_FSTORES_64 : integer := C_NUM_FSTORES/(C_M_AXI_S2MM_ADDR_WIDTH_NEW/32);
constant CMD_WIDTH : integer := C_M_AXI_MM2S_ADDR_WIDTH_NEW+CMD_BASE_WIDTH;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
--type STARTADDR_ARRAY_TYPE_64 is array(natural range <>)
-- of std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH - 1 downto 0);
signal mm2s_prmry_resetn : std_logic := '1'; -- AXI MM2S Primary Reset
signal mm2s_dm_prmry_resetn : std_logic := '1'; -- AXI MM2S DataMover Primary Reset (Raw)
signal mm2s_axis_resetn : std_logic := '1'; -- AXIS MM2S Primary Reset
signal mm2s_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_axis_linebuf_reset_out_inv : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_prmry_resetn : std_logic := '1'; -- AXI S2MM Primary Reset
signal s2mm_dm_prmry_resetn : std_logic := '1'; -- AXI S2MM DataMover Primary Reset (Raw)
signal s2mm_axis_resetn : std_logic := '1'; -- AXIS S2MM Primary Reset
signal s_axi_lite_resetn : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset
signal m_axi_dm_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset (Raw)
signal mm2s_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for MM2S
signal s2mm_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for S2MM
-- MM2S Register Module Signals
signal mm2s_stop : std_logic := '0';
signal mm2s_stop_reg : std_logic := '0';
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_interr_set_minus_frame_errors : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0');
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_cmdsts_idle : std_logic := '0';
signal mm2s_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_dlyirq_dsble : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0';
signal mm2s_valid_video_prmtrs : std_logic := '0';
signal mm2s_all_lines_xfred : std_logic := '0';
signal mm2s_all_lines_xfred_s : std_logic := '0';
signal mm2s_all_lines_xfred_s_dwidth : std_logic := '0';
signal mm2s_fsize_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_lsize_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_lsize_more_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_to_s2mm_fsync : std_logic := '0';
-- MM2S Register Direct Support
signal mm2s_regdir_idle : std_logic := '0';
signal mm2s_prmtr_updt_complete : std_logic := '0';
signal mm2s_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0);
signal mm2s_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0);
signal mm2s_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0);
signal mm2s_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0);
signal mm2s_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
signal mm2s_reg_module_strt_addr_64 : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES_64 - 1);
-- MM2S Register Interface Signals
signal mm2s_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0');
signal mm2s_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ;
signal mm2s_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0') ;
--signal mm2s_axi2ip_rden : std_logic := '0';
signal mm2s_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ;
--signal mm2s_ip2axi_rddata_valid : std_logic := '0';
signal mm2s_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_introut : std_logic := '0';
-- MM2S Scatter Gather clock domain crossing signals
signal mm2s_cdc2sg_run_stop : std_logic := '0';
signal mm2s_cdc2sg_stop : std_logic := '0';
signal mm2s_cdc2sg_taildesc_wren : std_logic := '0';
signal mm2s_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sg2cdc_ftch_idle : std_logic := '0';
signal mm2s_sg2cdc_ftch_interr_set : std_logic := '0';
signal mm2s_sg2cdc_ftch_slverr_set : std_logic := '0';
signal mm2s_sg2cdc_ftch_decerr_set : std_logic := '0';
-- MM2S DMA Controller Signals
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_ftchcmdsts_idle : std_logic := '0';
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH_NEW+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(MM2S_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521
signal m_axis_mm2s_sts_tkeep : std_logic_vector((MM2S_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_reg : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- DataMover To Line Buffer AXI Stream Signals
signal dm2linebuf_mm2s_tdata : std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
signal dm2linebuf_mm2s_tkeep : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0);
signal dm2linebuf_mm2s_tlast : std_logic := '0';
signal dm2linebuf_mm2s_tvalid : std_logic := '0';
signal linebuf2dm_mm2s_tready : std_logic := '0';
-- MM2S Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
-- MM2S Soft Reset support
signal mm2s_soft_reset : std_logic := '0';
signal mm2s_soft_reset_clr : std_logic := '0';
-- MM2S SOF generation support
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal m_axis_mm2s_tvalid_i_axis_dw_conv : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_axis_dw_conv : std_logic := '0';
signal s_axis_s2mm_tdata_i : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tkeep_i : std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tuser_i : std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tvalid_i : std_logic ; --
signal s_axis_s2mm_tvalid_int : std_logic ; --
signal s_axis_s2mm_tlast_i : std_logic ;
signal m_axis_mm2s_tdata_i : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tkeep_i : std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tuser_i : std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tready_i : std_logic ; --
-- S2MM Register Module Signals
signal s2mm_stop : std_logic := '0';
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_interr_set_minus_frame_errors : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0');
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_cmdsts_idle : std_logic := '0';
signal s2mm_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dlyirq_dsble : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0';
signal s2mm_valid_video_prmtrs : std_logic := '0';
signal s2mm_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');-- CR575884
signal s2mm_update_frmstore : std_logic := '0'; --CR582182
signal s2mm_frmstr_err_addr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); --CR582182
signal s2mm_all_lines_xfred : std_logic := '0'; -- CR591965
signal all_lasts_rcvd : std_logic := '0';
signal s2mm_capture_hsize_at_uf_err_sig : std_logic_vector(15 downto 0) ;
signal s2mm_capture_dm_done_vsize_counter_sig : std_logic_vector(12 downto 0) ;
signal s2mm_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965
signal s2mm_fsize_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_lsize_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_lsize_more_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_tuser_fsync : std_logic := '0';
signal s2mm_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_to_mm2s_fsync : std_logic := '0';
-- S2MM Register Direct Support
signal s2mm_regdir_idle : std_logic := '0';
signal s2mm_prmtr_updt_complete : std_logic := '0';
signal s2mm_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0);
signal s2mm_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0);
signal s2mm_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0);
signal s2mm_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0);
signal s2mm_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
signal s2mm_reg_module_strt_addr_64 : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES_64 - 1);
-- S2MM Register Interface Signals
signal s2mm_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0');
signal s2mm_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
--signal s2mm_axi2ip_rden : std_logic := '0';
signal s2mm_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
--signal s2mm_ip2axi_rddata_valid : std_logic := '0';
signal s2mm_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ip2axi_introut : std_logic := '0';
-- S2MM Scatter Gather clock domain crossing signals
signal s2mm_cdc2sg_run_stop : std_logic := '0';
signal s2mm_cdc2sg_stop : std_logic := '0';
signal s2mm_cdc2sg_taildesc_wren : std_logic := '0';
signal s2mm_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_sg2cdc_ftch_idle : std_logic := '0';
signal s2mm_sg2cdc_ftch_interr_set : std_logic := '0';
signal s2mm_sg2cdc_ftch_slverr_set : std_logic := '0';
signal s2mm_sg2cdc_ftch_decerr_set : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_ftchcmdsts_idle : std_logic := '0';
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH_NEW+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(S2MM_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521
signal m_axis_s2mm_sts_tkeep : std_logic_vector((S2MM_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Line Buffer To DataMover AXI Stream Signals
signal linebuf2dm_s2mm_tdata : std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0);
signal linebuf2dm_s2mm_tkeep : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0);
signal linebuf2dm_s2mm_tlast : std_logic := '0';
signal linebuf2dm_s2mm_tvalid : std_logic := '0';
signal dm2linebuf_s2mm_tready : std_logic := '0';
-- S2MM Error Status Control
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
-- S2MM Soft Reset support
signal s2mm_soft_reset : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
-- S2MM SOF generation support
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_i_axis_dw_conv : std_logic := '0';
-- Video specific
signal s2mm_frame_sync : std_logic := '0';
signal mm2s_frame_sync : std_logic := '0';
signal mm2s_parameter_update : std_logic := '0';
signal s2mm_parameter_update : std_logic := '0';
-- Line Buffer Support
signal mm2s_allbuffer_empty : std_logic := '0';
signal mm2s_dwidth_fifo_pipe_empty : std_logic := '0';
signal mm2s_dwidth_fifo_pipe_empty_m : std_logic := '0';
-- Video CDC support
signal mm2s_cdc2dmac_fsync : std_logic := '0';
signal mm2s_dmac2cdc_fsync_out : std_logic := '0';
signal mm2s_dmac2cdc_prmtr_update : std_logic := '0';
signal mm2s_vid2cdc_packet_sof : std_logic := '0';
signal s2mm_cdc2dmac_fsync : std_logic := '0';
signal s2mm_dmac2cdc_fsync_out : std_logic := '0';
signal s2mm_dmac2cdc_prmtr_update : std_logic := '0';
signal s2mm_vid2cdc_packet_sof : std_logic := '0';
-- fsync qualified by valid parameters for frame count
-- decrement
signal mm2s_valid_frame_sync : std_logic := '0';
signal s2mm_valid_frame_sync : std_logic := '0';
signal mm2s_valid_frame_sync_cmb : std_logic := '0';
signal s2mm_valid_frame_sync_cmb : std_logic := '0';
--signal for test bench and for output
signal s2mm_tstvect_err : std_logic := '0';
signal mm2s_tstvect_err : std_logic := '0';
signal s2mm_tstvect_fsync : std_logic := '0';
signal mm2s_tstvect_fsync : std_logic := '0';
signal s2mm_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_fsync_out_i : std_logic := '0';
signal s2mm_fsync_out_m_i : std_logic := '0';
signal mm2s_fsync_out_i : std_logic := '0';
signal mm2s_mask_fsync_out : std_logic := '0';
signal s2mm_mask_fsync_out : std_logic := '0';
signal mm2s_mstrfrm_tstsync_out : std_logic := '0';
signal s2mm_mstrfrm_tstsync_out : std_logic := '0';
-- Genlock pointer signals
signal mm2s_mstrfrm_tstsync : std_logic := '0';
signal mm2s_s_frame_ptr_in : std_logic_vector(MM2S_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_mstrfrm_tstsync : std_logic := '0';
signal s2mm_s_frame_ptr_in : std_logic_vector(S2MM_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0');
signal s2mm_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal sg2cdc_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sg2cdc_ftch_err : std_logic := '0';
signal mm2s_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ftch_err : std_logic := '0';
signal s2mm_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ftch_err : std_logic := '0';
-- Internal GenLock bus support
signal s2mm_to_mm2s_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_to_s2mm_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal s2mm_fsync_src_select_s : std_logic_vector(1 downto 0) := (others => '0');
signal hold_dummy_tready_low : std_logic := '0';
signal hold_dummy_tready_low2 : std_logic := '0';
signal drop_fsync_d_pulse_gen_fsize_less_err : std_logic := '0';
signal s2mm_tuser_fsync_top : std_logic := '0';
signal s2mm_fsync_core : std_logic := '0';
signal s2mm_chnl_ready : std_logic := '0';
signal s2mm_strm_not_finished : std_logic := '0';
signal s2mm_strm_all_lines_rcvd : std_logic := '0';
signal s2mm_all_vount_rcvd : std_logic := '0';
signal s2mm_fsize_mismatch_err_s : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating : std_logic := '0';
signal s2mm_dummy_tready : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_s : std_logic := '0';
signal s2mm_fsize_more_or_sof_late : std_logic := '0';
signal s_axis_s2mm_tdata_signal : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tkeep_signal : std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tuser_signal : std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tvalid_signal : std_logic := '0'; --
signal s_axis_s2mm_tready_signal : std_logic := '0'; --
signal s_axis_s2mm_tlast_signal : std_logic := '0'; --
signal mm2s_fsync_core : std_logic := '0';
signal mm2s_fsize_mismatch_err_s : std_logic := '0';
signal mm2s_fsize_mismatch_err_m : std_logic := '0';
signal MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : std_logic := '0';
signal m_axis_mm2s_tready_i2 : std_logic ; --
signal m_axis_mm2s_tvalid_i2 : std_logic ; --
signal mm2s_fsync_out_m : std_logic := '0';
signal mm2s_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965
signal mm2s_vsize_cntr_clr_flag : std_logic := '0'; -- CR591965
signal mm2s_fsync_d1 : std_logic := '0';
signal mm2s_fsync_d2 : std_logic := '0';
signal mm2s_fsync_fe : std_logic := '0';
signal s2mm_fsync_d1 : std_logic := '0';
signal s2mm_fsync_d2 : std_logic := '0';
signal s2mm_fsync_fe : std_logic := '0';
signal mm2s_buffer_empty_i : std_logic := '0';
signal s2mm_buffer_full_i : std_logic := '0';
signal mm2s_buffer_almost_empty_i : std_logic := '0';
signal s2mm_buffer_almost_full_i : std_logic := '0';
signal mm2s_prmtr_update_i : std_logic := '0';
signal s2mm_prmtr_update_i : std_logic := '0';
signal mm2s_fsync_out_sig : std_logic := '0';
signal s2mm_fsync_out_sig : std_logic := '0';
signal axi_vdma_tstvec_i : std_logic_vector(63 downto 0) := (others => '0');
signal mm2s_prmry_reset_out_n_i : std_logic := '1';
signal s2mm_prmry_reset_out_n_i : std_logic := '1';
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_NEW-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_NEW-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ENABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_0 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_prmry_reset_out_n <= mm2s_prmry_reset_out_n_i;
end generate ENABLE_MM2S_PRMRY_RESET_OUT_N;
DISABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_0 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_prmry_reset_out_n <= '1';
end generate DISABLE_MM2S_PRMRY_RESET_OUT_N;
ENABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_buffer_empty <= mm2s_buffer_empty_i;
mm2s_buffer_almost_empty <= mm2s_buffer_almost_empty_i;
end generate ENABLE_MM2S_BUFFER_EMPTY;
DISABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_buffer_empty <= '0';
mm2s_buffer_almost_empty <= '0';
end generate DISABLE_MM2S_BUFFER_EMPTY;
ENABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_2 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_prmtr_update <= mm2s_prmtr_update_i;
end generate ENABLE_MM2S_PRMTR_UPDATE;
DISABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_2 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_prmtr_update <= '0';
end generate DISABLE_MM2S_PRMTR_UPDATE;
ENABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_3 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_fsync_out <= mm2s_fsync_out_sig;
end generate ENABLE_MM2S_FSYNC_OUT;
DISABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_3 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_fsync_out <= '0';
end generate DISABLE_MM2S_FSYNC_OUT;
ENABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
axi_vdma_tstvec <= axi_vdma_tstvec_i;
end generate ENABLE_AXI_VDMA_TSTVEC;
DISABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
axi_vdma_tstvec <= (others => '0');
end generate DISABLE_AXI_VDMA_TSTVEC;
ENABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_8 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_prmry_reset_out_n <= s2mm_prmry_reset_out_n_i;
end generate ENABLE_S2MM_PRMRY_RESET_OUT_N;
DISABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_8 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_prmry_reset_out_n <= '1';
end generate DISABLE_S2MM_PRMRY_RESET_OUT_N;
ENABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_buffer_full <= s2mm_buffer_full_i;
s2mm_buffer_almost_full <= s2mm_buffer_almost_full_i;
end generate ENABLE_S2MM_BUFFER_FULL;
DISABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_buffer_full <= '0';
s2mm_buffer_almost_full <= '0';
end generate DISABLE_S2MM_BUFFER_FULL;
ENABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_10 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_prmtr_update <= s2mm_prmtr_update_i;
end generate ENABLE_S2MM_PRMTR_UPDATE;
DISABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_10 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_prmtr_update <= '0';
end generate DISABLE_S2MM_PRMTR_UPDATE;
ENABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_11 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_fsync_out <= s2mm_fsync_out_sig;
end generate ENABLE_S2MM_FSYNC_OUT;
DISABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_11 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_fsync_out <= '0';
end generate DISABLE_S2MM_FSYNC_OUT;
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_vdma_tstvec_i(63 downto 59) <= s2mm_tstvect_frm_ptr_out; ---
axi_vdma_tstvec_i(58 downto 54) <= mm2s_tstvect_frm_ptr_out; ---
axi_vdma_tstvec_i(53 downto 49) <= s2mm_tstvect_frame; ---
axi_vdma_tstvec_i(48 downto 44) <= mm2s_tstvect_frame; ---
axi_vdma_tstvec_i(43 downto 33) <= (others => '0');
axi_vdma_tstvec_i(32) <= s2mm_strm_all_lines_rcvd; --
axi_vdma_tstvec_i(31) <= s2mm_halt; -- DataMover halt tracking
axi_vdma_tstvec_i(30) <= mm2s_halt; -- DataMover halt tracking
axi_vdma_tstvec_i(29) <= s2mm_tstvect_err;
axi_vdma_tstvec_i(28) <= mm2s_tstvect_err;
axi_vdma_tstvec_i(27 downto 24) <= s2mm_tstvect_frm_ptr_out(3 downto 0); --
axi_vdma_tstvec_i(23 downto 20) <= mm2s_tstvect_frm_ptr_out(3 downto 0); --
axi_vdma_tstvec_i(19) <= s2mm_mstrfrm_tstsync_out;
axi_vdma_tstvec_i(18) <= mm2s_mstrfrm_tstsync_out;
axi_vdma_tstvec_i(17) <= s2mm_dmasr(DMASR_HALTED_BIT);
axi_vdma_tstvec_i(16) <= mm2s_dmasr(DMASR_HALTED_BIT);
axi_vdma_tstvec_i(15 downto 12) <= s2mm_tstvect_frame(3 downto 0); --
axi_vdma_tstvec_i(11 downto 8) <= mm2s_tstvect_frame(3 downto 0); --
axi_vdma_tstvec_i(7) <= s2mm_tstvect_fsync
and not s2mm_mask_fsync_out;
axi_vdma_tstvec_i(6) <= mm2s_tstvect_fsync
and not mm2s_mask_fsync_out;
axi_vdma_tstvec_i(5) <= s2mm_tstvect_fsync;
axi_vdma_tstvec_i(4) <= mm2s_tstvect_fsync;
axi_vdma_tstvec_i(3) <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal;
axi_vdma_tstvec_i(2) <= s2mm_packet_sof;
axi_vdma_tstvec_i(1) <= mm2s_all_lines_xfred;
axi_vdma_tstvec_i(0) <= mm2s_packet_sof;
GEN_MM2S_D1_REG : process(m_axis_mm2s_aclk)
begin
if(m_axis_mm2s_aclk'EVENT and m_axis_mm2s_aclk = '1')then
mm2s_fsync_d1 <= mm2s_fsync;
mm2s_fsync_d2 <= mm2s_fsync_d1;
end if;
end process GEN_MM2S_D1_REG;
mm2s_fsync_fe <= mm2s_fsync_d2 and not mm2s_fsync_d1;
GEN_S2MM_D1_REG : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
s2mm_fsync_d1 <= s2mm_fsync;
s2mm_fsync_d2 <= s2mm_fsync_d1;
end if;
end process GEN_S2MM_D1_REG;
s2mm_fsync_fe <= s2mm_fsync_d2 and not s2mm_fsync_d1;
s2mm_fsize_more_or_sof_late_s <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal and not s2mm_fsize_less_err_internal_tvalid_gating;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_i_axis_dw_conv;
--m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i2;
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i_axis_dw_conv;
mm2s_frame_ptr_out <= mm2s_frame_ptr_out_i ;
s2mm_frame_ptr_out <= s2mm_frame_ptr_out_i ;
--*****************************************************************************
--** RESET MODULE **
--*****************************************************************************
I_RST_MODULE : entity axi_vdma_v6_2_8.axi_vdma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axis_mm2s_aclk => m_axis_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
s_axis_s2mm_aclk => s_axis_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- MM2S Soft Reset Support
-----------------------------------------------------------------------
mm2s_soft_reset => mm2s_soft_reset ,
mm2s_soft_reset_clr => mm2s_soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_ftchcmdsts_idle ,
mm2s_fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
-----------------------------------------------------------------------
-- MM2S Soft Reset Support
-----------------------------------------------------------------------
s2mm_soft_reset => s2mm_soft_reset ,
s2mm_soft_reset_clr => s2mm_soft_reset_clr ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
-----------------------------------------------------------------------
-- SG Status
-----------------------------------------------------------------------
ftch_err => sg2cdc_ftch_err ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out
-----------------------------------------------------------------------
-- AXI Upsizer and Line Buffer
mm2s_prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
mm2s_dm_prmry_resetn => mm2s_dm_prmry_resetn ,
-- AXI Stream Logic Reset
mm2s_axis_resetn => mm2s_axis_resetn ,
-- AXI Stream Reset Outputs
mm2s_axis_reset_out_n => mm2s_prmry_reset_out_n_i ,
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out
-----------------------------------------------------------------------
s2mm_prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
s2mm_dm_prmry_resetn => s2mm_dm_prmry_resetn ,
-- AXI Stream Logic Reset
s2mm_axis_resetn => s2mm_axis_resetn ,
-- AXI Stream Reset Outputs
s2mm_axis_reset_out_n => s2mm_prmry_reset_out_n_i ,
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out
-----------------------------------------------------------------------
m_axi_sg_resetn => m_axi_sg_resetn ,
m_axi_dm_sg_resetn => m_axi_dm_sg_resetn ,
-----------------------------------------------------------------------
-- AXI Lite Interface Reset Out (Hard Only)
-----------------------------------------------------------------------
s_axi_lite_resetn => s_axi_lite_resetn ,
mm2s_hrd_resetn => mm2s_hrd_resetn ,
s2mm_hrd_resetn => s2mm_hrd_resetn
);
--*****************************************************************************
--** AXI LITE REGISTER INTERFACE **
--*****************************************************************************
-------------------------------------------------------------------------------
-- Provides the s_axi_lite inteface and clock domain crossing between
-- axi lite and mm2s/s2mm register modules
-------------------------------------------------------------------------------
AXI_LITE_REG_INTERFACE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_if
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_VERSION_MAJOR => VERSION_MAJOR ,
C_VERSION_MINOR => VERSION_MINOR ,
C_VERSION_REVISION => VERSION_REVISION ,
C_REVISION_NUMBER => REVISION_NUMBER
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_reset_n => s_axi_lite_resetn ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S Register Interface
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_hrd_resetn => mm2s_hrd_resetn ,
mm2s_axi2ip_wrce => mm2s_axi2ip_wrce ,
mm2s_axi2ip_wrdata => mm2s_axi2ip_wrdata ,
mm2s_axi2ip_rdaddr => mm2s_axi2ip_rdaddr ,
--mm2s_axi2ip_rden => mm2s_axi2ip_rden ,
mm2s_ip2axi_rddata => mm2s_ip2axi_rddata ,
--mm2s_ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid ,
mm2s_ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
mm2s_ip2axi_frame_store => mm2s_ip2axi_frame_store ,
mm2s_chnl_current_frame => mm2s_chnl_current_frame ,
mm2s_genlock_pair_frame => mm2s_genlock_pair_frame ,
mm2s_ip2axi_introut => mm2s_ip2axi_introut ,
mm2s_introut => mm2s_introut ,
-- S2MM Register Interface
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_hrd_resetn => s2mm_hrd_resetn ,
s2mm_axi2ip_wrce => s2mm_axi2ip_wrce ,
s2mm_axi2ip_wrdata => s2mm_axi2ip_wrdata ,
--s2mm_axi2ip_rden => s2mm_axi2ip_rden ,
s2mm_axi2ip_rdaddr => s2mm_axi2ip_rdaddr ,
s2mm_ip2axi_rddata => s2mm_ip2axi_rddata ,
--s2mm_ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid ,
s2mm_ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
s2mm_ip2axi_frame_store => s2mm_ip2axi_frame_store ,
s2mm_capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig ,
s2mm_capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
s2mm_chnl_current_frame => s2mm_chnl_current_frame ,
s2mm_genlock_pair_frame => s2mm_genlock_pair_frame ,
s2mm_ip2axi_introut => s2mm_ip2axi_introut ,
s2mm_introut => s2mm_introut
);
--*****************************************************************************
--** INTERRUPT CONTROLLER **
--*****************************************************************************
I_AXI_DMA_INTRPT : entity axi_vdma_v6_2_8.axi_vdma_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
m_axi_ch1_aclk => m_axi_mm2s_aclk ,
m_axi_ch1_aresetn => mm2s_prmry_resetn ,
m_axi_ch2_aclk => m_axi_s2mm_aclk ,
m_axi_ch2_aresetn => s2mm_prmry_resetn ,
ch1_irqthresh_decr => mm2s_tstvect_fsync ,
ch1_irqthresh_decr_mask => mm2s_fsize_mismatch_err_flag ,
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl ,
ch1_dlyirq_dsble => mm2s_dlyirq_dsble ,
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) ,
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) ,
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_tstvect_fsync ,
ch1_packet_eof_mask => mm2s_fsize_mismatch_err_flag ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
ch2_irqthresh_decr => s2mm_tstvect_fsync ,
ch2_irqthresh_decr_mask => s2mm_fsize_mismatch_err_flag ,
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl ,
ch2_dlyirq_dsble => s2mm_dlyirq_dsble ,
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) ,
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) ,
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_tstvect_fsync ,
ch2_packet_eof_mask => s2mm_fsize_mismatch_err_flag ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status
);
--*****************************************************************************
--** SCATTER GATHER ENGINE **
--*****************************************************************************
-- If Scatter Gather Engine is included the instantiate axi_sg
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
-------------------------------------------------------------------------------
-- Scatter Gather Engine
-------------------------------------------------------------------------------
I_SG_ENGINE : entity axi_vdma_v6_2_8.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERR ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => EXCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => EXCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => EXCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_AXIS_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_resetn ,
dm_resetn => m_axi_dm_sg_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => open ,
m_axi_sg_awlen => open ,
m_axi_sg_awsize => open ,
m_axi_sg_awburst => open ,
m_axi_sg_awprot => open ,
m_axi_sg_awcache => open ,
m_axi_sg_awvalid => open ,
m_axi_sg_awready => '0' ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => open ,
m_axi_sg_wstrb => open ,
m_axi_sg_wlast => open ,
m_axi_sg_wvalid => open ,
m_axi_sg_wready => '0' ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => "00" ,
m_axi_sg_bvalid => '0' ,
m_axi_sg_bready => open ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_cdc2sg_run_stop ,
ch1_desc_flush => mm2s_cdc2sg_stop ,
ch1_ftch_idle => mm2s_sg2cdc_ftch_idle ,
ch1_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set ,
ch1_ftch_err_early => open ,
ch1_ftch_stale_desc => open ,
ch1_updt_idle => open ,
ch1_updt_ioc_irq_set => open ,
ch1_updt_interr_set => open ,
ch1_updt_slverr_set => open ,
ch1_updt_decerr_set => open ,
ch1_dma_interr_set => open ,
ch1_dma_slverr_set => open ,
ch1_dma_decerr_set => open ,
ch1_tailpntr_enabled => '1' ,
ch1_taildesc_wren => mm2s_cdc2sg_taildesc_wren ,
ch1_taildesc => mm2s_cdc2sg_taildesc ,
ch1_curdesc => mm2s_cdc2sg_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
ch1_dlyirq_dsble => '0' ,
ch1_irqthresh_rstdsbl => '0' ,
ch1_irqdelay_wren => '0' ,
ch1_irqdelay => ZERO_VALUE(7 downto 0) ,
ch1_irqthresh_wren => '0' ,
ch1_irqthresh => ZERO_VALUE(7 downto 0) ,
ch1_packet_sof => '0' ,
ch1_packet_eof => '0' ,
ch1_ioc_irq_set => open ,
ch1_dly_irq_set => open ,
ch1_irqdelay_status => open ,
ch1_irqthresh_status => open ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axi_mm2s_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => '0' ,
s_axis_ch1_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0),
s_axis_ch1_updtptr_tvalid => '0' ,
s_axis_ch1_updtptr_tready => open ,
s_axis_ch1_updtptr_tlast => '0' ,
s_axis_ch1_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0),
s_axis_ch1_updtsts_tvalid => '0' ,
s_axis_ch1_updtsts_tready => open ,
s_axis_ch1_updtsts_tlast => '0' ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_cdc2sg_run_stop ,
ch2_desc_flush => s2mm_cdc2sg_stop ,
ch2_ftch_idle => s2mm_sg2cdc_ftch_idle ,
ch2_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set ,
ch2_ftch_err_early => open ,
ch2_ftch_stale_desc => open ,
ch2_updt_idle => open ,
ch2_updt_ioc_irq_set => open ,
ch2_updt_interr_set => open ,
ch2_updt_slverr_set => open ,
ch2_updt_decerr_set => open ,
ch2_dma_interr_set => open ,
ch2_dma_slverr_set => open ,
ch2_dma_decerr_set => open ,
ch2_tailpntr_enabled => '1' ,
ch2_taildesc_wren => s2mm_cdc2sg_taildesc_wren ,
ch2_taildesc => s2mm_cdc2sg_taildesc ,
ch2_curdesc => s2mm_cdc2sg_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
ch2_dlyirq_dsble => '0' ,
ch2_irqthresh_rstdsbl => '0' ,
ch2_irqdelay_wren => '0' ,
ch2_irqdelay => ZERO_VALUE(7 downto 0) ,
ch2_irqthresh_wren => '0' ,
ch2_irqthresh => ZERO_VALUE(7 downto 0) ,
ch2_packet_sof => '0' ,
ch2_packet_eof => '0' ,
ch2_ioc_irq_set => open ,
ch2_dly_irq_set => open ,
ch2_irqdelay_status => open ,
ch2_irqthresh_status => open ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axi_s2mm_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => '0' ,
s_axis_ch2_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0),
s_axis_ch2_updtptr_tvalid => '0' ,
s_axis_ch2_updtptr_tready => open ,
s_axis_ch2_updtptr_tlast => '0' ,
s_axis_ch2_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0),
s_axis_ch2_updtsts_tvalid => '0' ,
s_axis_ch2_updtsts_tready => open ,
s_axis_ch2_updtsts_tlast => '0' ,
-- Error addresses
ftch_error_addr => sg2cdc_ftch_err_addr ,
ftch_error => sg2cdc_ftch_err ,
updt_error => open ,
updt_error_addr => open
);
--*********************************************************************
--** MM2S Clock Domain To/From Scatter Gather Clock Domain **
--*********************************************************************
MM2S_SG_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_sg_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
scndry_aclk => m_axi_sg_aclk ,
scndry_resetn => m_axi_sg_resetn ,
-- From Register Module (Primary Clk Domain)
reg2cdc_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
reg2cdc_stop => mm2s_stop ,
reg2cdc_taildesc_wren => mm2s_tailpntr_updated ,
reg2cdc_taildesc => mm2s_taildesc ,
reg2cdc_curdesc => mm2s_curdesc ,
-- To Scatter Gather Engine (Secondary Clk Domain)
cdc2sg_run_stop => mm2s_cdc2sg_run_stop ,
cdc2sg_stop => mm2s_cdc2sg_stop ,
cdc2sg_taildesc_wren => mm2s_cdc2sg_taildesc_wren ,
cdc2sg_taildesc => mm2s_cdc2sg_taildesc ,
cdc2sg_curdesc => mm2s_cdc2sg_curdesc ,
-- From Scatter Gather Engine (Secondary Clk Domain)
sg2cdc_ftch_idle => mm2s_sg2cdc_ftch_idle ,
sg2cdc_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set ,
sg2cdc_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set ,
sg2cdc_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set ,
sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr ,
sg2cdc_ftch_err => sg2cdc_ftch_err ,
-- To DMA Controller
cdc2dmac_ftch_idle => mm2s_ftch_idle ,
-- To Register Module
cdc2reg_ftch_interr_set => mm2s_ftch_interr_set ,
cdc2reg_ftch_slverr_set => mm2s_ftch_slverr_set ,
cdc2reg_ftch_decerr_set => mm2s_ftch_decerr_set ,
cdc2reg_ftch_err_addr => mm2s_ftch_err_addr ,
cdc2reg_ftch_err => mm2s_ftch_err
);
--*********************************************************************
--** S2MM Clock Domain To/From Scatter Gather Clock Domain **
--*********************************************************************
S2MM_SG_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_sg_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
scndry_aclk => m_axi_sg_aclk ,
scndry_resetn => m_axi_sg_resetn ,
-- From Register Module (Primary Clk Domain)
reg2cdc_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
reg2cdc_stop => s2mm_stop ,
reg2cdc_taildesc_wren => s2mm_tailpntr_updated ,
reg2cdc_taildesc => s2mm_taildesc ,
reg2cdc_curdesc => s2mm_curdesc ,
-- To Scatter Gather Engine (Secondary Clk Domain)
cdc2sg_run_stop => s2mm_cdc2sg_run_stop ,
cdc2sg_stop => s2mm_cdc2sg_stop ,
cdc2sg_taildesc_wren => s2mm_cdc2sg_taildesc_wren ,
cdc2sg_taildesc => s2mm_cdc2sg_taildesc ,
cdc2sg_curdesc => s2mm_cdc2sg_curdesc ,
-- From Scatter Gather Engine (Secondary Clk Domain)
sg2cdc_ftch_idle => s2mm_sg2cdc_ftch_idle ,
sg2cdc_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set ,
sg2cdc_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set ,
sg2cdc_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set ,
sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr ,
sg2cdc_ftch_err => sg2cdc_ftch_err ,
-- To DMA Controller
cdc2dmac_ftch_idle => s2mm_ftch_idle ,
-- To Register Module
cdc2reg_ftch_interr_set => s2mm_ftch_interr_set ,
cdc2reg_ftch_slverr_set => s2mm_ftch_slverr_set ,
cdc2reg_ftch_decerr_set => s2mm_ftch_decerr_set ,
cdc2reg_ftch_err_addr => s2mm_ftch_err_addr ,
cdc2reg_ftch_err => s2mm_ftch_err
);
end generate GEN_SG_ENGINE;
-- No scatter gather engine therefore tie off unused signals
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
mm2s_ftch_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s2mm_ftch_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
mm2s_ftch_err_addr <= (others => '0');
mm2s_ftch_err <= '0';
s2mm_ftch_err_addr <= (others => '0');
s2mm_ftch_err <= '0';
sg2cdc_ftch_err <= '0';
end generate GEN_NO_SG_ENGINE;
--*****************************************************************************
--** MM2S CHANNEL **
--*****************************************************************************
-- Generate support logic for MM2S
GEN_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
GEN_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and MM2S_SOF_ENABLE = 1) generate
begin
--m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0'
-- else '0';
m_axis_mm2s_tvalid_i2 <= '0' when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '1' or mm2s_fsync_core = '1'
else m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0'
else '1';
end generate GEN_FLUSH_SOF_MM2S;
GEN_NO_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or MM2S_SOF_ENABLE = 0) generate
begin
m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready;
end generate GEN_NO_FLUSH_SOF_MM2S;
GEN_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8;
constant C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH/8;
signal m_axis_mm2s_dwidth_tuser_i : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_dwidth_tuser : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); --
begin
m_axis_mm2s_dwidth_tuser_i(0) <= m_axis_mm2s_tuser_i(0);
MM2S_TUSER_CNCT : for i in 1 to C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 generate
begin
m_axis_mm2s_dwidth_tuser_i(i) <= '0';
end generate MM2S_TUSER_CNCT;
m_axis_mm2s_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) <= m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0);
AXIS_MM2S_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2_8.axi_vdma_mm2s_axis_dwidth_converter
generic map(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
--C_AXIS_SIGNAL_SET => 255 ,
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC,
C_AXIS_TID_WIDTH => 1 ,
C_AXIS_TDEST_WIDTH => 1 ,
C_FAMILY => C_ROOT_FAMILY )
port map(
ACLK => m_axis_mm2s_aclk ,
ARESETN => mm2s_axis_linebuf_reset_out ,
ACLKEN => '1' ,
dm_halt_reg => mm2s_halt_reg ,
stop_reg => mm2s_stop_reg ,
crnt_vsize_d2 => mm2s_crnt_vsize_d2 ,
fsync_out => mm2s_fsync_out_i ,
mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty ,
all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth ,
S_AXIS_TVALID => m_axis_mm2s_tvalid_i ,
S_AXIS_TREADY => m_axis_mm2s_tready_i ,
S_AXIS_TDATA => m_axis_mm2s_tdata_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
--S_AXIS_TSTRB => ZERO_VALUE(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TSTRB => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => m_axis_mm2s_tlast_i ,
S_AXIS_TID => ZERO_VALUE(0 downto 0) ,
S_AXIS_TDEST => ZERO_VALUE(0 downto 0) ,
S_AXIS_TUSER => m_axis_mm2s_dwidth_tuser_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => m_axis_mm2s_tvalid_i_axis_dw_conv ,
M_AXIS_TREADY => m_axis_mm2s_tready_i2 ,
M_AXIS_TDATA => m_axis_mm2s_tdata(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => open ,
M_AXIS_TKEEP => m_axis_mm2s_tkeep(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => m_axis_mm2s_tlast_i_axis_dw_conv ,
M_AXIS_TID => open ,
M_AXIS_TDEST => open ,
M_AXIS_TUSER => m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
) ;
end generate GEN_AXIS_MM2S_DWIDTH_CONV;
GEN_NO_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
m_axis_mm2s_tvalid_i_axis_dw_conv <= m_axis_mm2s_tvalid_i;
m_axis_mm2s_tdata <= m_axis_mm2s_tdata_i;
m_axis_mm2s_tkeep <= m_axis_mm2s_tkeep_i;
m_axis_mm2s_tlast_i_axis_dw_conv <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tuser <= m_axis_mm2s_tuser_i;
m_axis_mm2s_tready_i <= m_axis_mm2s_tready_i2;
mm2s_dwidth_fifo_pipe_empty <= '1';
mm2s_all_lines_xfred_s_dwidth <= '0';
end generate GEN_NO_AXIS_MM2S_DWIDTH_CONV;
--*************************************************************************
--** MM2S AXI4 Clock Domain - (m_axi_mm2s_aclk)
--*************************************************************************
---------------------------------------------------------------------------
-- MM2S Register Module
---------------------------------------------------------------------------
MM2S_REGISTER_MODULE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_module
generic map(
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_CHANNEL_IS_MM2S => CHANNEL_IS_MM2S ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_THRESH => C_MM2S_LINEBUFFER_THRESH_INT ,
C_NUM_FSTORES => C_NUM_FSTORES ,
C_NUM_FSTORES_64 => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH --C_M_AXI_MM2S_ADDR_WIDTH_NEW
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
-- Register to AXI Lite Interface
axi2ip_wrce => mm2s_axi2ip_wrce ,
axi2ip_wrdata => mm2s_axi2ip_wrdata ,
axi2ip_rdaddr => mm2s_axi2ip_rdaddr ,
--axi2ip_rden => mm2s_axi2ip_rden ,
axi2ip_rden => '0' ,
ip2axi_rddata => mm2s_ip2axi_rddata ,
--ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid ,
ip2axi_rddata_valid => open ,
ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
ip2axi_frame_store => mm2s_ip2axi_frame_store ,
ip2axi_introut => mm2s_ip2axi_introut ,
-- Soft Reset
soft_reset => mm2s_soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
-- DMA Control / Status Register Signals
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
frame_sync => mm2s_frame_sync ,
fsync_mask => mm2s_mask_fsync_out ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
update_frmstore => '1' , -- Always Update
new_frmstr => mm2s_frame_number ,
tstvect_fsync => mm2s_tstvect_fsync ,
valid_frame_sync => mm2s_valid_frame_sync ,
irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl ,
dlyirq_dsble => mm2s_dlyirq_dsble ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- Error Detection Control
stop => mm2s_stop ,
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
fsize_mismatch_err => mm2s_fsize_mismatch_err ,
lsize_mismatch_err => mm2s_lsize_mismatch_err ,
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err ,
s2mm_fsize_more_or_sof_late => '0' ,
-- VDMA Base Registers
reg_index => mm2s_reg_index ,
dmacr => mm2s_dmacr ,
dmasr => mm2s_dmasr ,
curdesc => mm2s_curdesc ,
taildesc => mm2s_taildesc ,
num_frame_store => mm2s_num_frame_store ,
linebuf_threshold => mm2s_linebuf_threshold ,
-- Register Direct Support
regdir_idle => mm2s_regdir_idle ,
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr ,
-- Fetch/Update error addresses
frmstr_err_addr => mm2s_frame_number ,
ftch_err_addr => mm2s_ftch_err_addr
);
ADDR32: if C_M_AXI_MM2S_ADDR_WIDTH_NEW = 32 generate
begin
---------------------------------------------------------------------------
-- MM2S DMA Controller
---------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_USE_FSYNC => C_USE_MM2S_FSYNC , -- CR582182
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_GENLOCK_NUM_MASTERS => C_MM2S_GENLOCK_NUM_MASTERS ,
--C_GENLOCK_REPEAT_EN => C_MM2S_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => MM2S_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => MM2S_DM_CMD_NOT_EXTENDED ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_S2MM_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => 0 ,
C_SELECT_XPM => C_SELECT_XPM,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
soft_reset => mm2s_soft_reset ,
scndry_aclk => '0' ,
scndry_resetn => '1' ,
-- MM2S Control and Status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => mm2s_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => mm2s_dmasr(DMASR_HALTED_BIT) ,
sync_enable => mm2s_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => mm2s_regdir_idle ,
ftch_idle => mm2s_ftch_idle ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
stop => mm2s_stop ,
s2mm_dmasr_lsize_less_err => '0' ,
s2mm_fsize_more_or_sof_late => '0' ,
capture_hsize_at_uf_err => open ,
all_idle => mm2s_all_idle ,
cmdsts_idle => mm2s_cmdsts_idle ,
ftchcmdsts_idle => mm2s_ftchcmdsts_idle ,
s2mm_fsync_out_m => '0' ,
frame_sync => mm2s_frame_sync ,
mm2s_fsync_out_m => mm2s_fsync_out_m , -- CR616211
update_frmstore => open , -- Not Needed for MM2S channel
frmstr_err_addr => open , -- Not Needed for MM2S channel
frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
frame_ptr_in => mm2s_s_frame_ptr_in ,
frame_ptr_out => mm2s_m_frame_ptr_out ,
internal_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
valid_frame_sync => mm2s_valid_frame_sync ,
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
parameter_update => mm2s_parameter_update ,
circular_prk_mode => mm2s_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => mm2s_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => mm2s_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => mm2s_allbuffer_empty ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty_m ,
crnt_vsize => mm2s_crnt_vsize , -- CR616211
num_frame_store => mm2s_num_frame_store ,
all_lines_xfred => mm2s_all_lines_xfred , -- CR616211
all_lasts_rcvd => all_lasts_rcvd , --
fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , -- CR591965
s2mm_fsize_mismatch_err_s => open , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => '0' ,
s2mm_strm_all_lines_rcvd => '0' , -- : out std_logic;
s2mm_fsync_core => '0' ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , -- CR591965
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , -- CR591965
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => mm2s_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , -- CR591965
-- Register Direct Support
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr ,
-- Fsync signals and Genlock for test vector
tstvect_err => mm2s_tstvect_err ,
tstvect_fsync => mm2s_tstvect_fsync ,
tstvect_frame => mm2s_tstvect_frame ,
tstvect_frm_ptr_out => mm2s_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => mm2s_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => '1' , -- NOT Used for MM2S
-- Primary DMA Errors
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => mm2s_frame_number ,
chnl_current_frame => mm2s_chnl_current_frame ,
genlock_pair_frame => mm2s_genlock_pair_frame ,
new_curdesc => mm2s_new_curdesc ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_sts_tkeep => m_axis_mm2s_sts_tkeep ,
err => mm2s_err ,
ftch_err => mm2s_ftch_err
);
end generate ADDR32;
ADDR64: if C_M_AXI_MM2S_ADDR_WIDTH_NEW > 32 generate
begin
FSTORES64 : for i in 0 to C_NUM_FSTORES_64-1 generate
mm2s_reg_module_strt_addr_64 (i) <= mm2s_reg_module_strt_addr (i*2+1) & mm2s_reg_module_strt_addr (i*2);
end generate FSTORES64;
---------------------------------------------------------------------------
-- MM2S DMA Controller
---------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr_64
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_USE_FSYNC => C_USE_MM2S_FSYNC , -- CR582182
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_GENLOCK_NUM_MASTERS => C_MM2S_GENLOCK_NUM_MASTERS ,
--C_GENLOCK_REPEAT_EN => C_MM2S_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => MM2S_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => MM2S_DM_CMD_NOT_EXTENDED ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_S2MM_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => 0 ,
C_SELECT_XPM => C_SELECT_XPM,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
soft_reset => mm2s_soft_reset ,
scndry_aclk => '0' ,
scndry_resetn => '1' ,
-- MM2S Control and Status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => mm2s_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => mm2s_dmasr(DMASR_HALTED_BIT) ,
sync_enable => mm2s_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => mm2s_regdir_idle ,
ftch_idle => mm2s_ftch_idle ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
stop => mm2s_stop ,
s2mm_dmasr_lsize_less_err => '0' ,
s2mm_fsize_more_or_sof_late => '0' ,
capture_hsize_at_uf_err => open ,
all_idle => mm2s_all_idle ,
cmdsts_idle => mm2s_cmdsts_idle ,
ftchcmdsts_idle => mm2s_ftchcmdsts_idle ,
s2mm_fsync_out_m => '0' ,
frame_sync => mm2s_frame_sync ,
mm2s_fsync_out_m => mm2s_fsync_out_m , -- CR616211
update_frmstore => open , -- Not Needed for MM2S channel
frmstr_err_addr => open , -- Not Needed for MM2S channel
frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
frame_ptr_in => mm2s_s_frame_ptr_in ,
frame_ptr_out => mm2s_m_frame_ptr_out ,
internal_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
valid_frame_sync => mm2s_valid_frame_sync ,
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
parameter_update => mm2s_parameter_update ,
circular_prk_mode => mm2s_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => mm2s_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => mm2s_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => mm2s_allbuffer_empty ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty_m ,
crnt_vsize => mm2s_crnt_vsize , -- CR616211
num_frame_store => mm2s_num_frame_store ,
all_lines_xfred => mm2s_all_lines_xfred , -- CR616211
all_lasts_rcvd => all_lasts_rcvd , --
fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , -- CR591965
s2mm_fsize_mismatch_err_s => open , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => '0' ,
s2mm_strm_all_lines_rcvd => '0' , -- : out std_logic;
s2mm_fsync_core => '0' ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , -- CR591965
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , -- CR591965
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => mm2s_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , -- CR591965
-- Register Direct Support
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr_64 ,
-- Fsync signals and Genlock for test vector
tstvect_err => mm2s_tstvect_err ,
tstvect_fsync => mm2s_tstvect_fsync ,
tstvect_frame => mm2s_tstvect_frame ,
tstvect_frm_ptr_out => mm2s_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => mm2s_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => '1' , -- NOT Used for MM2S
-- Primary DMA Errors
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => mm2s_frame_number ,
chnl_current_frame => mm2s_chnl_current_frame ,
genlock_pair_frame => mm2s_genlock_pair_frame ,
new_curdesc => mm2s_new_curdesc ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_sts_tkeep => m_axis_mm2s_sts_tkeep ,
err => mm2s_err ,
ftch_err => mm2s_ftch_err
);
end generate ADDR64;
---------------------------------------------------------------------------
-- MM2S Frame sync generator
---------------------------------------------------------------------------
MM2S_FSYNC_I : entity axi_vdma_v6_2_8.axi_vdma_fsync_gen
generic map(
C_USE_FSYNC => C_USE_MM2S_FSYNC ,
ENABLE_FLUSH_ON_S2MM_FSYNC => 0 ,
ENABLE_FLUSH_ON_MM2S_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC ,
C_INCLUDE_S2MM => 0 ,
C_INCLUDE_MM2S => 1 ,
C_SOF_ENABLE => MM2S_SOF_ENABLE -- Always disabled
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
-- Frame Count Enable Support
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
frmcnt_ioc => mm2s_ioc_irq_set ,
dmacr_frmcnt_enbl => mm2s_dmacr(DMACR_FRMCNTEN_BIT) ,
dmasr_frmcnt_status => mm2s_irqthresh_status ,
mask_fsync_out => mm2s_mask_fsync_out ,
-- VDMA process status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
all_idle => mm2s_all_idle ,
parameter_update => mm2s_parameter_update ,
-- VDMA Frame Sync Sources
fsync => mm2s_cdc2dmac_fsync ,
tuser_fsync => '0' , -- Not used by MM2S
othrchnl_fsync => s2mm_to_mm2s_fsync ,
fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- VDMA frame sync output to core
frame_sync => mm2s_frame_sync ,
-- VDMA frame sync output to ports
frame_sync_out => mm2s_dmac2cdc_fsync_out ,
prmtr_update => mm2s_dmac2cdc_prmtr_update
);
-- Clock Domain Crossing between m_axi_mm2s_aclk and m_axis_mm2s_aclk
MM2S_VID_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_vid_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH ,
C_GENLOCK_SLVE_PTR_DWIDTH => MM2S_GENLOCK_SLVE_PTR_DWIDTH ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
scndry_aclk => m_axis_mm2s_aclk ,
scndry_resetn => mm2s_axis_resetn ,
-- Genlock internal bus cdc
othrchnl_aclk => m_axi_s2mm_aclk ,
othrchnl_resetn => s2mm_prmry_resetn ,
othrchnl2cdc_frame_ptr_out => s2mm_frame_ptr_out_i ,
cdc2othrchnl_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
cdc2othrchnl_fsync => mm2s_to_s2mm_fsync ,
-- GenLock Clock Domain Crossing
dmac2cdc_frame_ptr_out => mm2s_m_frame_ptr_out ,
cdc2top_frame_ptr_out => mm2s_frame_ptr_out_i ,
top2cdc_frame_ptr_in => mm2s_frame_ptr_in ,
cdc2dmac_frame_ptr_in => mm2s_s_frame_ptr_in ,
dmac2cdc_mstrfrm_tstsync => mm2s_mstrfrm_tstsync ,
cdc2dmac_mstrfrm_tstsync => mm2s_mstrfrm_tstsync_out ,
-- SOF Detection Domain Crossing
vid2cdc_packet_sof => mm2s_vid2cdc_packet_sof ,
cdc2dmac_packet_sof => mm2s_packet_sof ,
-- Frame Sync Generation Domain Crossing
vid2cdc_fsync => mm2s_fsync_core ,
cdc2dmac_fsync => mm2s_cdc2dmac_fsync ,
dmac2cdc_fsync_out => mm2s_dmac2cdc_fsync_out ,
dmac2cdc_prmtr_update => mm2s_dmac2cdc_prmtr_update ,
cdc2vid_fsync_out => mm2s_fsync_out_i ,
cdc2vid_prmtr_update => mm2s_prmtr_update_i
);
mm2s_fsync_out_sig <= mm2s_fsync_out_i;
-- Start of Frame Detection - used for interrupt coalescing
MM2S_SOF_I : entity axi_vdma_v6_2_8.axi_vdma_sof_gen
port map(
scndry_aclk => m_axis_mm2s_aclk ,
scndry_resetn => mm2s_axis_resetn ,
axis_tready => m_axis_mm2s_tready_i2 ,
---axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tvalid => m_axis_mm2s_tvalid_i2 ,
fsync => mm2s_fsync_out_i , -- CR622884
packet_sof => mm2s_vid2cdc_packet_sof
);
---------------------------------------------------------------------------
-- Primary MM2S Line Buffer
---------------------------------------------------------------------------
MM2S_LINEBUFFER_I : entity axi_vdma_v6_2_8.axi_vdma_mm2s_linebuf
generic map(
C_DATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
--C_INCLUDE_MM2S_SF => C_INCLUDE_MM2S_SF ,
C_INCLUDE_MM2S_SF => 0 ,
C_INCLUDE_MM2S_DRE => C_MM2S_ENABLE_TKEEP ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_M_AXIS_MM2S_TUSER_BITS => C_M_AXIS_MM2S_TUSER_BITS ,
C_TOPLVL_LINEBUFFER_DEPTH => C_MM2S_LINEBUFFER_DEPTH , -- CR625142
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_DEPTH => MM2S_LINEBUFFER_DEPTH ,
C_LINEBUFFER_AE_THRESH => C_MM2S_LINEBUFFER_THRESH_INT ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-------------------------------------------------------------------
-- AXI Scatter Gather Interface
-------------------------------------------------------------------
-- MM2S AXIS Datamover side
s_axis_aclk => m_axi_mm2s_aclk ,
s_axis_resetn => mm2s_prmry_resetn ,
-- MM2S AXIS Out side
m_axis_aclk => m_axis_mm2s_aclk ,
m_axis_resetn => mm2s_axis_resetn ,
mm2s_axis_linebuf_reset_out => mm2s_axis_linebuf_reset_out ,
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
s2mm_axis_resetn => s2mm_axis_resetn ,
s_axis_s2mm_aclk => s_axis_s2mm_aclk ,
mm2s_fsync => mm2s_fsync_fe ,
s2mm_fsync => s2mm_fsync_fe ,
mm2s_fsync_core => mm2s_fsync_core ,
mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag ,
mm2s_fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag ,
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S => MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S ,
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s ,
fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- Graceful shut down control
cmdsts_idle => mm2s_cmdsts_idle ,
dm_halt => mm2s_halt ,
dm_halt_reg_out => mm2s_halt_reg ,
stop => mm2s_stop , -- CR623291
stop_reg_out => mm2s_stop_reg , -- CR623291
-- Vertical Line Count control
crnt_vsize => mm2s_crnt_vsize , -- CR616211
crnt_vsize_d2_out => mm2s_crnt_vsize_d2 , -- CR616211
fsync_out => mm2s_fsync_out_i , -- CR616211
fsync_out_m => mm2s_fsync_out_m , -- CR616211
frame_sync => mm2s_frame_sync , -- CR616211
-- Threshold
linebuf_threshold => mm2s_linebuf_threshold ,
-- Stream In (Datamover to Linebuffer)
s_axis_tdata => dm2linebuf_mm2s_tdata ,
s_axis_tkeep => dm2linebuf_mm2s_tkeep ,
s_axis_tlast => dm2linebuf_mm2s_tlast ,
s_axis_tvalid => dm2linebuf_mm2s_tvalid ,
s_axis_tready => linebuf2dm_mm2s_tready ,
-- Stream Out (Linebuffer to AXIS Out)
m_axis_tdata => m_axis_mm2s_tdata_i ,
m_axis_tkeep => m_axis_mm2s_tkeep_i ,
m_axis_tlast => m_axis_mm2s_tlast_i ,
m_axis_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_tready => m_axis_mm2s_tready_i ,
m_axis_tuser => m_axis_mm2s_tuser_i ,
-- Fifo Status Flags
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty ,
dwidth_fifo_pipe_empty_m => mm2s_dwidth_fifo_pipe_empty_m ,
mm2s_fifo_pipe_empty => mm2s_allbuffer_empty ,
mm2s_fifo_empty => mm2s_buffer_empty_i ,
mm2s_fifo_almost_empty => mm2s_buffer_almost_empty_i ,
mm2s_all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth ,
mm2s_all_lines_xfred_s => mm2s_all_lines_xfred_s ,
mm2s_all_lines_xfred => mm2s_all_lines_xfred -- CR616211
);
end generate GEN_SPRT_FOR_MM2S;
-- Do not generate support logic for MM2S
GEN_NO_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
-- Register Module Tie-Offs
mm2s_ip2axi_rddata <= (others => '0');
--mm2s_ip2axi_rddata_valid <= '0';
mm2s_ip2axi_frame_ptr_ref <= (others => '0');
mm2s_ip2axi_frame_store <= (others => '0');
mm2s_ip2axi_introut <= '0';
mm2s_soft_reset <= '0';
mm2s_irqthresh_rstdsbl <= '0';
mm2s_dlyirq_dsble <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_dmacr <= (others => '0');
mm2s_dmasr <= (others => '0');
mm2s_curdesc <= (others => '0');
mm2s_taildesc <= (others => '0');
--internal to mm2s generate (dont really need to tie off)
mm2s_num_frame_store <= (others => '0');
mm2s_linebuf_threshold <= (others => '0');
mm2s_regdir_idle <= '0';
mm2s_prmtr_updt_complete <= '0';
mm2s_reg_module_vsize <= (others => '0');
mm2s_reg_module_hsize <= (others => '0');
mm2s_reg_module_stride <= (others => '0');
mm2s_reg_module_frmdly <= (others => '0');
-- Must zero each element of an array of vectors to zero
-- all vectors.
GEN_MM2S_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate
begin
mm2s_reg_module_strt_addr(i) <= (others => '0');
end generate GEN_MM2S_ZERO_STRT;
-- Line Buffer Tie-Offs
linebuf2dm_mm2s_tready <= '0';
m_axis_mm2s_tdata <= (others => '0');
m_axis_mm2s_tdata_i <= (others => '0');
m_axis_mm2s_tkeep <= (others => '0');
m_axis_mm2s_tkeep_i <= (others => '0');
m_axis_mm2s_tlast_i <= '0';
m_axis_mm2s_tlast_i_axis_dw_conv <= '0';
m_axis_mm2s_tuser <= (others => '0');
m_axis_mm2s_tuser_i <= (others => '0');
m_axis_mm2s_tvalid_i <= '0';
m_axis_mm2s_tvalid_i2 <= '0';
m_axis_mm2s_tvalid_i_axis_dw_conv <= '0';
mm2s_allbuffer_empty <= '0';
mm2s_dwidth_fifo_pipe_empty <= '0';
mm2s_buffer_empty_i <= '0';
mm2s_buffer_almost_empty_i <= '0';
mm2s_all_lines_xfred <= '0';
-- SOF generator
mm2s_packet_sof <= '0';
-- DMA Controller
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
mm2s_frame_number <= (others => '0');
mm2s_chnl_current_frame <= (others => '0');
mm2s_genlock_pair_frame <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_stop <= '0';
mm2s_stop_reg <= '0';
mm2s_all_idle <= '1';
mm2s_cmdsts_idle <= '1';
mm2s_ftchcmdsts_idle <= '1';
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
m_axis_mm2s_sts_tready <= '0';
mm2s_m_frame_ptr_out <= (others => '0');
mm2s_frame_ptr_out_i <= (others => '0');
s2mm_to_mm2s_frame_ptr_in <= (others => '0');
mm2s_valid_frame_sync <= '0';
mm2s_valid_frame_sync_cmb <= '0';
mm2s_valid_video_prmtrs <= '0';
mm2s_parameter_update <= '0';
mm2s_tstvect_err <= '0';
mm2s_tstvect_fsync <= '0';
mm2s_tstvect_frame <= (others => '0');
mm2s_dma_interr_set <= '0';
mm2s_dma_interr_set_minus_frame_errors <= '0';
mm2s_dma_slverr_set <= '0';
mm2s_dma_decerr_set <= '0';
mm2s_crnt_vsize <= (others => '0');
mm2s_crnt_vsize_d2 <= (others => '0');
mm2s_fsize_mismatch_err <= '0';
mm2s_lsize_mismatch_err <= '0';
mm2s_lsize_more_mismatch_err <= '0';
-- Frame Sync generator
mm2s_frame_sync <= '0';
mm2s_fsync_out_sig <= '0';
mm2s_prmtr_update_i <= '0';
mm2s_mask_fsync_out <= '0';
mm2s_mstrfrm_tstsync <= '0';
mm2s_mstrfrm_tstsync_out <= '0';
mm2s_tstvect_frm_ptr_out <= (others => '0');
mm2s_to_s2mm_fsync <= '0';
end generate GEN_NO_SPRT_FOR_MM2S;
--*****************************************************************************
--** S2MM CHANNEL **
--*****************************************************************************
-- Generate support logic for S2MM
GEN_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
signal no_fsync_before_vsize_sel_00_01 : std_logic := '0';
begin
------------------------------------------------------------------------------------------------------------------------------------------------------
s2mm_axis_linebuf_reset_out_inv <= not s2mm_axis_linebuf_reset_out;
GEN_S2MM_DRE_ON_SKID : if C_S2MM_ENABLE_TKEEP = 1 generate
begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
)
port map(
-- System Ports
ACLK => s_axis_s2mm_aclk ,
ARST => s2mm_axis_linebuf_reset_out_inv ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_tvalid ,
S_READY => s_axis_s2mm_tready ,
S_Data => s_axis_s2mm_tdata ,
S_STRB => s_axis_s2mm_tkeep ,
S_Last => s_axis_s2mm_tlast ,
S_User => s_axis_s2mm_tuser ,
-- Master Side (Stream Data Output)
M_VALID => s_axis_s2mm_tvalid_signal ,
M_READY => s_axis_s2mm_tready_signal ,
M_Data => s_axis_s2mm_tdata_signal ,
M_STRB => s_axis_s2mm_tkeep_signal ,
M_Last => s_axis_s2mm_tlast_signal ,
M_User => s_axis_s2mm_tuser_signal
);
end generate GEN_S2MM_DRE_ON_SKID;
GEN_S2MM_DRE_OFF_SKID : if C_S2MM_ENABLE_TKEEP = 0 generate
begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
)
port map(
-- System Ports
ACLK => s_axis_s2mm_aclk ,
ARST => s2mm_axis_linebuf_reset_out_inv ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_tvalid ,
S_READY => s_axis_s2mm_tready ,
S_Data => s_axis_s2mm_tdata ,
--S_STRB => s_axis_s2mm_tkeep ,
S_STRB => (others => '1') ,
S_Last => s_axis_s2mm_tlast ,
S_User => s_axis_s2mm_tuser ,
-- Master Side (Stream Data Output)
M_VALID => s_axis_s2mm_tvalid_signal ,
M_READY => s_axis_s2mm_tready_signal ,
M_Data => s_axis_s2mm_tdata_signal ,
M_STRB => s_axis_s2mm_tkeep_signal ,
M_Last => s_axis_s2mm_tlast_signal ,
M_User => s_axis_s2mm_tuser_signal
);
end generate GEN_S2MM_DRE_OFF_SKID;
GEN_FLUSH_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1 generate
signal s2mm_fsize_less_err_flag_10 : std_logic := '0';
signal s2mm_fsize_less_err_flag_00_01 : std_logic := '0';
signal s_axis_s2mm_tuser_d1 : std_logic := '0';
signal s2mm_tuser_to_fsync_out : std_logic := '0';
signal d_tready_sof_late : std_logic := '0';
signal d_tready_sof_late_cmb : std_logic := '0';
signal s2mm_sof_late_err : std_logic := '0';
signal s2mm_prmtr_or_tail_ptr_updt_complete : std_logic := '0';
signal s2mm_prmtr_updt_complete_s : std_logic := '0';
signal s2mm_dmasr_halted_s : std_logic := '0';
signal d_tready_before_fsync_clr_flag1 : std_logic := '0';
signal d_tready_before_fsync : std_logic := '0';
signal d_tready_before_fsync_cmb : std_logic := '0';
signal d_tready_after_prmtr_updt : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd_till_reset : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd : std_logic := '0';
signal d_tready_sof_late_prmtr_updt : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd_cmb : std_logic := '0';
signal s2mm_sof_late_err_prmtr_updt : std_logic := '0';
signal s2mm_fsync_src_select_s_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal s2mm_dummy_tready_fsync_src_sel_00_or_01 : std_logic := '0';
signal s2mm_dummy_tready_fsync_src_sel_10 : std_logic := '0';
signal d_tready_before_fsync_clr_flag1_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_clrd_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_clr_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_cmb_sel_00_01 : std_logic := '0';
signal d_tready_after_vcount_sel_00_01 : std_logic := '0';
signal after_vcount_flag_sel_00_01 : std_logic := '0';
signal d_tready_after_fsize_less_err_flag_00_01 : std_logic := '0';
signal d_tready_after_fsize_less_err_00_01 : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating_10 : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating_00_01 : std_logic := '0';
begin
no_fsync_before_vsize_sel_00_01 <= d_tready_before_fsync_clr_flag1_sel_00_01;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal and s2mm_chnl_ready ;
s_axis_s2mm_tready_signal <= (s_axis_s2mm_tready_i_axis_dw_conv and s2mm_chnl_ready) or s2mm_dummy_tready;
GEN_C_USE_S2MM_FSYNC_1 : if C_USE_S2MM_FSYNC = 1 generate
begin
s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
end generate GEN_C_USE_S2MM_FSYNC_1;
GEN_C_USE_S2MM_FSYNC_2 : if C_USE_S2MM_FSYNC = 2 generate
begin
s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10;
s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10;
end generate GEN_C_USE_S2MM_FSYNC_2;
---- FSYNC_SEL_TREADY_S2MM_S : process(s2mm_fsync_src_select_s_d1,
---- s2mm_dummy_tready,
---- s2mm_dummy_tready_fsync_src_sel_00_or_01,
---- s2mm_fsize_less_err_internal_tvalid_gating_10,
---- s2mm_fsize_less_err_internal_tvalid_gating_00_01,
---- s2mm_fsize_less_err_internal_tvalid_gating,
---- s2mm_dummy_tready_fsync_src_sel_10)
---- begin
---- case s2mm_fsync_src_select_s_d1 is
----
---- when "00" => -- primary fsync (default)
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
---- when "01" => -- other channel fsync
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
---- when "10" => -- s2mm_tuser_fsync_top_d1 fsync
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10;
---- when others =>
---- s2mm_dummy_tready <= '0';
---- s2mm_fsize_less_err_internal_tvalid_gating <= '0';
---- end case;
---- end process FSYNC_SEL_TREADY_S2MM_S;
----
----
----
---- D1_S2MM_FSYNC_SRC_SEL_STRM : process(s_axis_s2mm_aclk)
---- begin
---- if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
---- if(s2mm_axis_resetn = '0')then
---- s2mm_fsync_src_select_s_d1 <= (others => '0');
---- else
---- s2mm_fsync_src_select_s_d1 <= s2mm_fsync_src_select_s;
---- end if;
---- end if;
---- end process D1_S2MM_FSYNC_SRC_SEL_STRM;
----
--------------------------------------------------TUSER Start-------------------------------------------------------------------------------------------------------------------------
s2mm_dummy_tready_fsync_src_sel_10 <= d_tready_sof_late_cmb or d_tready_before_fsync_cmb ;
d_tready_sof_late_cmb <= d_tready_sof_late when s2mm_tuser_fsync_top = '0' and s2mm_tuser_to_fsync_out = '0' and s2mm_chnl_ready = '0' else '0';
TUSER_TO_FSYNC_OUT_FLAG : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_out_i = '1' )then
s2mm_tuser_to_fsync_out <= '0';
elsif(s2mm_tuser_fsync_top = '1' and d_tready_before_fsync_clr_flag1 = '0')then
s2mm_tuser_to_fsync_out <= '1';
end if;
end if;
end process TUSER_TO_FSYNC_OUT_FLAG;
s2mm_fsize_less_err_internal_tvalid_gating_10 <= '1' when s2mm_fsize_less_err_flag_10 = '1' and s2mm_tuser_fsync_top = '0'
else '0';
FSIZE_LESS_ERR_FLAG_10 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_tuser_fsync_top = '1')then
s2mm_fsize_less_err_flag_10 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
s2mm_fsize_less_err_flag_10 <= '1';
end if;
end if;
end process FSIZE_LESS_ERR_FLAG_10;
TOP_TUSER_RE_PROCESS : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0')then
s_axis_s2mm_tuser_d1 <= '0';
else
s_axis_s2mm_tuser_d1 <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal;
end if;
end if;
end process TOP_TUSER_RE_PROCESS;
s2mm_tuser_fsync_top <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal and (not s_axis_s2mm_tuser_d1);
SOF_LATE_ERR_PULSE_PROCESS : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_sof_late_err = '1' or s2mm_chnl_ready = '1' or d_tready_before_fsync_clr_flag1 = '1')then
s2mm_sof_late_err <= '0';
d_tready_sof_late <= '0';
elsif((s2mm_chnl_ready = '0' or s2mm_fsize_less_err_internal_tvalid_gating_10 = '1') and s_axis_s2mm_tvalid_signal = '1' and s_axis_s2mm_tuser_signal(0) = '0' ) then
s2mm_sof_late_err <= '1';
d_tready_sof_late <= '1';
end if;
end if;
end process SOF_LATE_ERR_PULSE_PROCESS;
--------------------------------------------------------------------------------------------------------
d_tready_before_fsync_cmb <= d_tready_before_fsync and d_tready_before_fsync_clr_flag1;
GEN_D_TREADY_BEFORE_FSYNC : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(d_tready_before_fsync_clr_flag1 = '0')then
d_tready_before_fsync <= '0';
elsif(s2mm_axis_resetn = '1' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync <= '1';
end if;
end if;
end process GEN_D_TREADY_BEFORE_FSYNC;
VALID_PRM_UPDT_FLAG_10 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clr_flag1 <= '1';
elsif(s2mm_prmtr_updt_complete_s = '1')then
d_tready_before_fsync_clr_flag1 <= '0';
end if;
end if;
end process VALID_PRM_UPDT_FLAG_10;
--------------------------------------------------TUSER End-------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------External Fsync Start-----------------------------------------------------------------------------------------------------------------------
s2mm_dummy_tready_fsync_src_sel_00_or_01 <= d_tready_after_fsize_less_err_00_01 or d_tready_after_vcount_sel_00_01 or d_tready_before_fsync_cmb_sel_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_after_fsize_less_err_00_01 <= '1' when d_tready_after_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0' and hold_dummy_tready_low2 = '0'
else '0';
TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low2 = '1')then
d_tready_after_fsize_less_err_flag_00_01 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
d_tready_after_fsize_less_err_flag_00_01 <= '1';
end if;
end if;
end process TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_after_vcount_sel_00_01 <= '1' when s2mm_fsync_core = '0' and after_vcount_flag_sel_00_01 = '1' and hold_dummy_tready_low = '0'
else '0';
REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low = '1')then
after_vcount_flag_sel_00_01 <= '0';
elsif(s2mm_all_vount_rcvd = '1')then
after_vcount_flag_sel_00_01 <= '1';
end if;
end if;
end process REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_before_fsync_cmb_sel_00_01 <= d_tready_before_fsync_sel_00_01 and d_tready_before_fsync_clr_sel_00_01;
GEN_D_TREADY_BEFORE_FSYNC_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then
d_tready_before_fsync_sel_00_01 <= '0';
elsif(s2mm_axis_resetn = '1')then
d_tready_before_fsync_sel_00_01 <= '1';
end if;
end if;
end process GEN_D_TREADY_BEFORE_FSYNC_00_01;
d_tready_before_fsync_clr_sel_00_01 <= '0' when d_tready_before_fsync_clr_flag1_sel_00_01 = '1' and s2mm_fsync_core = '1'
else d_tready_before_fsync_clrd_sel_00_01;
REG_INITIAL_FRM_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clrd_sel_00_01 <= '1';
elsif(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then
d_tready_before_fsync_clrd_sel_00_01 <= '0';
end if;
end if;
end process REG_INITIAL_FRM_FLAG_00_01;
VALID_PRM_UPDT_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clr_flag1_sel_00_01 <= '0';
elsif(s2mm_prmtr_updt_complete_s = '1')then
d_tready_before_fsync_clr_flag1_sel_00_01 <= '1';
end if;
end if;
end process VALID_PRM_UPDT_FLAG_00_01;
-----------------------------------------------------------------------------------
s2mm_fsize_less_err_internal_tvalid_gating_00_01 <= '1' when s2mm_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0'
else '0';
FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1')then
s2mm_fsize_less_err_flag_00_01 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
s2mm_fsize_less_err_flag_00_01 <= '1';
end if;
end if;
end process FSIZE_LESS_ERR_FLAG_00_01;
--------------------------------------------------External Fsync End-------------------------------------------------------------------------------------------------------------------------
SG_INCLUDED : if C_INCLUDE_SG = 1 generate
s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_tailpntr_updated;
end generate SG_INCLUDED;
SG_NOT_INCLUDED : if C_INCLUDE_SG = 0 generate
s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_prmtr_updt_complete;
end generate SG_NOT_INCLUDED;
GEN_FOR_ASYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---- S2MM_PRM_UPDT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete ,
---- scndry_out => s2mm_prmtr_updt_complete_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
S2MM_PRM_UPDT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_s2mm_aclk,
prmry_resetn => s2mm_prmry_resetn,
prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_s2mm_aclk,
scndry_resetn => s2mm_axis_resetn,
scndry_out => s2mm_prmtr_updt_complete_s,
scndry_vect_out => open
);
---- S2MM_HALTED_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_dmasr(DMASR_HALTED_BIT) ,
---- scndry_out => s2mm_dmasr_halted_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
S2MM_HALTED_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_s2mm_aclk,
prmry_resetn => s2mm_prmry_resetn,
prmry_in => s2mm_dmasr(DMASR_HALTED_BIT),
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_s2mm_aclk,
scndry_resetn => s2mm_axis_resetn,
scndry_out => s2mm_dmasr_halted_s,
scndry_vect_out => open
);
---- SOF_LATE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => s2mm_fsize_more_or_sof_late_s , -- Not Used
---- prmry_out => s2mm_fsize_more_or_sof_late , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
SOF_LATE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsize_more_or_sof_late_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_prmry_resetn,
scndry_out => s2mm_fsize_more_or_sof_late,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC_FLUSH_SOF;
GEN_FOR_SYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
s2mm_dmasr_halted_s <= s2mm_dmasr(DMASR_HALTED_BIT);
s2mm_prmtr_updt_complete_s <= s2mm_prmtr_or_tail_ptr_updt_complete;
s2mm_fsize_more_or_sof_late <= s2mm_fsize_more_or_sof_late_s;
end generate GEN_FOR_SYNC_FLUSH_SOF;
---------------------------------------------------------------------------
end generate GEN_FLUSH_SOF_TREADY;
----------------------------------------------------------------------------------------------------------------------------------------------------------
GEN_FLUSH_NO_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 0 generate
begin
--s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata;
--s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep;
--s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser;
--s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast;
--s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_signal;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal;
s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv;
s2mm_dummy_tready <= '0';
end generate GEN_FLUSH_NO_SOF_TREADY;
GEN_NO_FLUSH_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 0 generate
begin
--s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata;
--s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep;
--s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser;
--s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast;
--s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_signal;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal;
s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv;
s2mm_dummy_tready <= '0';
end generate GEN_NO_FLUSH_TREADY;
GEN_AXIS_S2MM_DWIDTH_CONV : if C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED /= C_S_AXIS_S2MM_TDATA_WIDTH generate
constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8;
constant C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH/8;
signal s_axis_s2mm_dwidth_tuser_i : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_dwidth_tuser : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); --
begin
S2MM_TUSER_CNCT : for i in 0 to C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 generate
begin
s_axis_s2mm_dwidth_tuser(i) <= s_axis_s2mm_tuser_signal(0);
end generate S2MM_TUSER_CNCT;
s_axis_s2mm_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) <= s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0);
AXIS_S2MM_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2_8.axi_vdma_s2mm_axis_dwidth_converter
generic map(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
--C_AXIS_SIGNAL_SET => 255 ,
C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 ,
C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC,
C_AXIS_TID_WIDTH => 1 ,
C_AXIS_TDEST_WIDTH => 1 ,
C_FAMILY => C_ROOT_FAMILY )
port map(
ACLK => s_axis_s2mm_aclk ,
ARESETN => s2mm_axis_linebuf_reset_out ,
--ARESETN => s2mm_axis_resetn ,
ACLKEN => '1' ,
s2mm_fsize_less_err_internal_tvalid_gating => s2mm_fsize_less_err_internal_tvalid_gating , -- : in std_logic ;
fsync_out => s2mm_fsync_out_i , -- : in std_logic ;
crnt_vsize_d2 => s2mm_crnt_vsize_d2 , -- : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ;
chnl_ready_dwidth => s2mm_chnl_ready , -- : out std_logic;
strm_not_finished_dwidth => s2mm_strm_not_finished , -- : out std_logic;
strm_all_lines_rcvd_dwidth => s2mm_strm_all_lines_rcvd , -- : out std_logic;
all_vount_rcvd_dwidth => s2mm_all_vount_rcvd , -- : out std_logic;
S_AXIS_TVALID => s_axis_s2mm_tvalid_int ,
S_AXIS_TREADY => s_axis_s2mm_tready_i_axis_dw_conv ,
S_AXIS_TDATA => s_axis_s2mm_tdata_signal(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) ,
--S_AXIS_TSTRB => ZERO_VALUE(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TSTRB => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TKEEP => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TLAST => s_axis_s2mm_tlast_signal ,
S_AXIS_TID => ZERO_VALUE(0 downto 0) ,
S_AXIS_TDEST => ZERO_VALUE(0 downto 0) ,
S_AXIS_TUSER => s_axis_s2mm_dwidth_tuser(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) ,
M_AXIS_TVALID => s_axis_s2mm_tvalid_i ,
M_AXIS_TREADY => s_axis_s2mm_tready_i ,
M_AXIS_TDATA => s_axis_s2mm_tdata_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) ,
M_AXIS_TSTRB => open ,
M_AXIS_TKEEP => s_axis_s2mm_tkeep_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TLAST => s_axis_s2mm_tlast_i ,
M_AXIS_TID => open ,
M_AXIS_TDEST => open ,
M_AXIS_TUSER => s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
) ;
end generate GEN_AXIS_S2MM_DWIDTH_CONV;
GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 0 or S2MM_SOF_ENABLE = 0) )generate
begin
s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int;
s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal;
s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal;
s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal;
s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal;
s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i;
s2mm_chnl_ready <= '0' ;
s2mm_strm_not_finished <= '0' ;
s2mm_strm_all_lines_rcvd <= '0' ;
s2mm_all_vount_rcvd <= '0' ;
end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF;
GEN_NO_AXIS_S2MM_DWIDTH_CONV : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1) ) generate
constant ZERO_VALUE : std_logic_vector(255 downto 0)
:= (others => '0');
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
signal chnl_ready_no_dwidth : std_logic := '0';
signal strm_not_finished_no_dwidth : std_logic := '0';
signal strm_all_lines_rcvd_no_dwidth : std_logic := '0';
signal decr_vcount_no_dwidth : std_logic := '0';
signal vsize_counter_no_dwidth : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal all_vount_rcvd_no_dwidth : std_logic := '0';
begin
s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int;
s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal;
s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal;
s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal;
s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal;
s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i;
-- Decrement vertical count with each accept tlast
decr_vcount_no_dwidth <= '1' when s_axis_s2mm_tlast_signal = '1'
and s_axis_s2mm_tvalid_int = '1'
and s_axis_s2mm_tready_i_axis_dw_conv = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
NO_DWIDTH_VERT_COUNTER : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
--if(s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0')then
--if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_flag = '1')then
if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_internal_tvalid_gating = '1')then
vsize_counter_no_dwidth <= (others => '0');
chnl_ready_no_dwidth <= '0';
strm_not_finished_no_dwidth <= '0';
strm_all_lines_rcvd_no_dwidth <= '1';
all_vount_rcvd_no_dwidth <= '0';
elsif(s2mm_fsync_out_i = '1')then
vsize_counter_no_dwidth <= s2mm_crnt_vsize_d2;
chnl_ready_no_dwidth <= '1';
strm_not_finished_no_dwidth <= '1';
strm_all_lines_rcvd_no_dwidth <= '0';
all_vount_rcvd_no_dwidth <= '0';
elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth = VSIZE_ONE_VALUE)then
vsize_counter_no_dwidth <= (others => '0');
chnl_ready_no_dwidth <= '0';
strm_not_finished_no_dwidth <= '0';
strm_all_lines_rcvd_no_dwidth <= '1';
all_vount_rcvd_no_dwidth <= '1';
elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth /= VSIZE_ZERO_VALUE)then
vsize_counter_no_dwidth <= std_logic_vector(unsigned(vsize_counter_no_dwidth) - 1);
chnl_ready_no_dwidth <= '1';
strm_not_finished_no_dwidth <= '1';
strm_all_lines_rcvd_no_dwidth <= '0';
all_vount_rcvd_no_dwidth <= '0';
else
all_vount_rcvd_no_dwidth <= '0';
end if;
end if;
end process NO_DWIDTH_VERT_COUNTER;
s2mm_chnl_ready <= chnl_ready_no_dwidth;
s2mm_strm_not_finished <= strm_not_finished_no_dwidth;
s2mm_strm_all_lines_rcvd <= strm_all_lines_rcvd_no_dwidth;
s2mm_all_vount_rcvd <= all_vount_rcvd_no_dwidth;
end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV;
---------------------------------------------------------------------------
-- S2MM Register Module
---------------------------------------------------------------------------
S2MM_REGISTER_MODULE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_module
generic map(
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_CHANNEL_IS_MM2S => CHANNEL_IS_S2MM ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_NUM_FSTORES => C_NUM_FSTORES ,
C_NUM_FSTORES_64 => C_NUM_FSTORES_64 ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_THRESH => C_S2MM_LINEBUFFER_THRESH_INT ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH --C_M_AXI_S2MM_ADDR_WIDTH_NEW
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
-- Register to AXI Lite Interface
axi2ip_wrce => s2mm_axi2ip_wrce ,
axi2ip_wrdata => s2mm_axi2ip_wrdata ,
axi2ip_rdaddr => s2mm_axi2ip_rdaddr ,
--axi2ip_rden => s2mm_axi2ip_rden ,
axi2ip_rden => '0' ,
ip2axi_rddata => s2mm_ip2axi_rddata ,
--ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid ,
ip2axi_rddata_valid => open ,
ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
ip2axi_frame_store => s2mm_ip2axi_frame_store ,
ip2axi_introut => s2mm_ip2axi_introut ,
-- Soft Reset
soft_reset => s2mm_soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
-- DMA Control / Status Register Signals
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
frame_sync => s2mm_frame_sync ,
fsync_mask => s2mm_mask_fsync_out ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
update_frmstore => s2mm_update_frmstore ,
new_frmstr => s2mm_frame_number ,
tstvect_fsync => s2mm_tstvect_fsync ,
valid_frame_sync => s2mm_valid_frame_sync ,
irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl ,
dlyirq_dsble => s2mm_dlyirq_dsble ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- Error Detection Control
stop => s2mm_stop ,
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
fsize_mismatch_err => s2mm_fsize_mismatch_err ,
lsize_mismatch_err => s2mm_lsize_mismatch_err ,
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
-- VDMA Base Registers
reg_index => s2mm_reg_index ,
dmacr => s2mm_dmacr ,
dmasr => s2mm_dmasr ,
curdesc => s2mm_curdesc ,
taildesc => s2mm_taildesc ,
num_frame_store => s2mm_num_frame_store ,
linebuf_threshold => s2mm_linebuf_threshold ,
-- Register Direct Support
regdir_idle => s2mm_regdir_idle ,
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr ,
-- Fetch/Update error addresses
frmstr_err_addr => s2mm_frmstr_err_addr ,
ftch_err_addr => s2mm_ftch_err_addr
);
S2MMADDR32: if C_M_AXI_S2MM_ADDR_WIDTH_NEW = 32 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA Controller
---------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , -- CR582182
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_GENLOCK_NUM_MASTERS => C_S2MM_GENLOCK_NUM_MASTERS ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_GENLOCK_REPEAT_EN => C_S2MM_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_SELECT_XPM => C_SELECT_XPM,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => S2MM_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => S2MM_DM_CMD_EXTENDED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE,
C_MM2S_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => 0 ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
soft_reset => s2mm_soft_reset ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- MM2S Control and Status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => s2mm_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => s2mm_dmasr(DMASR_HALTED_BIT) ,
sync_enable => s2mm_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => s2mm_regdir_idle ,
ftch_idle => s2mm_ftch_idle ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
stop => s2mm_stop ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
s2mm_dmasr_lsize_less_err => s2mm_dmasr(DMASR_LSIZEERR_BIT) ,
all_idle => s2mm_all_idle ,
cmdsts_idle => s2mm_cmdsts_idle ,
ftchcmdsts_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsync_out_m => s2mm_fsync_out_m_i ,
mm2s_fsync_out_m => '0' , -- CR616211
frame_sync => s2mm_frame_sync ,
update_frmstore => s2mm_update_frmstore , -- CR582182
frmstr_err_addr => s2mm_frmstr_err_addr , -- CR582182
frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
frame_ptr_in => s2mm_s_frame_ptr_in ,
frame_ptr_out => s2mm_m_frame_ptr_out ,
internal_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
valid_frame_sync => s2mm_valid_frame_sync ,
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
parameter_update => s2mm_parameter_update ,
circular_prk_mode => s2mm_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => s2mm_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => s2mm_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => '1' , -- NOT Used by S2MM therefore tie off
dwidth_fifo_pipe_empty => '1' , -- NOT Used by S2MM therefore tie off
crnt_vsize => s2mm_crnt_vsize , -- CR575884
num_frame_store => s2mm_num_frame_store ,
all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
mm2s_fsize_mismatch_err_m => '0' , -- Not Needed for MM2S channel
mm2s_fsize_mismatch_err_s => '0' , -- Not Needed for MM2S channel
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic;
s2mm_fsync_core => s2mm_fsync_core ,
fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , -- CR591965
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => s2mm_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , -- CR591965
capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
-- Register Direct Support
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr ,
-- Test vector signals
tstvect_err => s2mm_tstvect_err ,
tstvect_fsync => s2mm_tstvect_fsync ,
tstvect_frame => s2mm_tstvect_frame ,
tstvect_frm_ptr_out => s2mm_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => s2mm_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => s2mm_packet_sof ,
-- Primary DMA Errors
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => s2mm_frame_number ,
chnl_current_frame => s2mm_chnl_current_frame ,
genlock_pair_frame => s2mm_genlock_pair_frame ,
new_curdesc => s2mm_new_curdesc ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_sts_tkeep => m_axis_s2mm_sts_tkeep ,
err => s2mm_err ,
ftch_err => s2mm_ftch_err
);
end generate S2MMADDR32;
S2MMADDR64: if C_M_AXI_S2MM_ADDR_WIDTH_NEW > 32 generate
begin
S2MM_FSTORES64 : for i in 0 to C_NUM_FSTORES_64-1 generate
s2mm_reg_module_strt_addr_64 (i) <= s2mm_reg_module_strt_addr (i*2+1) & s2mm_reg_module_strt_addr (i*2);
end generate S2MM_FSTORES64;
---------------------------------------------------------------------------
-- S2MM DMA Controller
---------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr_64
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , -- CR582182
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_GENLOCK_NUM_MASTERS => C_S2MM_GENLOCK_NUM_MASTERS ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_GENLOCK_REPEAT_EN => C_S2MM_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_SELECT_XPM => C_SELECT_XPM,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => S2MM_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => S2MM_DM_CMD_EXTENDED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE,
C_MM2S_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => 0 ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
soft_reset => s2mm_soft_reset ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- MM2S Control and Status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => s2mm_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => s2mm_dmasr(DMASR_HALTED_BIT) ,
sync_enable => s2mm_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => s2mm_regdir_idle ,
ftch_idle => s2mm_ftch_idle ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
stop => s2mm_stop ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
s2mm_dmasr_lsize_less_err => s2mm_dmasr(DMASR_LSIZEERR_BIT) ,
all_idle => s2mm_all_idle ,
cmdsts_idle => s2mm_cmdsts_idle ,
ftchcmdsts_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsync_out_m => s2mm_fsync_out_m_i ,
mm2s_fsync_out_m => '0' , -- CR616211
frame_sync => s2mm_frame_sync ,
update_frmstore => s2mm_update_frmstore , -- CR582182
frmstr_err_addr => s2mm_frmstr_err_addr , -- CR582182
frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
frame_ptr_in => s2mm_s_frame_ptr_in ,
frame_ptr_out => s2mm_m_frame_ptr_out ,
internal_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
valid_frame_sync => s2mm_valid_frame_sync ,
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
parameter_update => s2mm_parameter_update ,
circular_prk_mode => s2mm_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => s2mm_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => s2mm_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => '1' , -- NOT Used by S2MM therefore tie off
dwidth_fifo_pipe_empty => '1' , -- NOT Used by S2MM therefore tie off
crnt_vsize => s2mm_crnt_vsize , -- CR575884
num_frame_store => s2mm_num_frame_store ,
all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
mm2s_fsize_mismatch_err_m => '0' , -- Not Needed for MM2S channel
mm2s_fsize_mismatch_err_s => '0' , -- Not Needed for MM2S channel
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic;
s2mm_fsync_core => s2mm_fsync_core ,
fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , -- CR591965
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => s2mm_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , -- CR591965
capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
-- Register Direct Support
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr_64 ,
-- Test vector signals
tstvect_err => s2mm_tstvect_err ,
tstvect_fsync => s2mm_tstvect_fsync ,
tstvect_frame => s2mm_tstvect_frame ,
tstvect_frm_ptr_out => s2mm_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => s2mm_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => s2mm_packet_sof ,
-- Primary DMA Errors
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => s2mm_frame_number ,
chnl_current_frame => s2mm_chnl_current_frame ,
genlock_pair_frame => s2mm_genlock_pair_frame ,
new_curdesc => s2mm_new_curdesc ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_sts_tkeep => m_axis_s2mm_sts_tkeep ,
err => s2mm_err ,
ftch_err => s2mm_ftch_err
);
end generate S2MMADDR64;
---------------------------------------------------------------------------
-- MM2S Frame sync generator
---------------------------------------------------------------------------
S2MM_FSYNC_I : entity axi_vdma_v6_2_8.axi_vdma_fsync_gen
generic map(
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 ,
ENABLE_FLUSH_ON_S2MM_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC ,
ENABLE_FLUSH_ON_MM2S_FSYNC => 0 ,
C_INCLUDE_S2MM => 1 ,
C_INCLUDE_MM2S => 0 ,
C_SOF_ENABLE => S2MM_SOF_ENABLE
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
-- Frame Count Enable Support
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
frmcnt_ioc => s2mm_ioc_irq_set ,
dmacr_frmcnt_enbl => s2mm_dmacr(DMACR_FRMCNTEN_BIT) ,
dmasr_frmcnt_status => s2mm_irqthresh_status ,
mask_fsync_out => s2mm_mask_fsync_out ,
-- VDMA process status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
all_idle => s2mm_all_idle ,
parameter_update => s2mm_parameter_update ,
-- VDMA Frame Sync sources
fsync => s2mm_cdc2dmac_fsync ,
tuser_fsync => s2mm_tuser_fsync ,
othrchnl_fsync => mm2s_to_s2mm_fsync ,
fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- VDMA frame sync output to core
frame_sync => s2mm_frame_sync ,
-- VDMA Frame Sync Output to ports
frame_sync_out => s2mm_dmac2cdc_fsync_out ,
prmtr_update => s2mm_dmac2cdc_prmtr_update
);
-- Clock Domain Crossing between m_axi_s2mm_aclk and s_axis_s2mm_aclk
S2MM_VID_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_vid_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH ,
C_GENLOCK_SLVE_PTR_DWIDTH => S2MM_GENLOCK_SLVE_PTR_DWIDTH ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- Genlock internal bus cdc
othrchnl_aclk => m_axi_mm2s_aclk ,
othrchnl_resetn => mm2s_prmry_resetn ,
othrchnl2cdc_frame_ptr_out => mm2s_frame_ptr_out_i ,
cdc2othrchnl_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
cdc2othrchnl_fsync => s2mm_to_mm2s_fsync ,
-- GenLock Clock Domain Crossing
dmac2cdc_frame_ptr_out => s2mm_m_frame_ptr_out ,
cdc2top_frame_ptr_out => s2mm_frame_ptr_out_i ,
top2cdc_frame_ptr_in => s2mm_frame_ptr_in ,
cdc2dmac_frame_ptr_in => s2mm_s_frame_ptr_in ,
dmac2cdc_mstrfrm_tstsync => s2mm_mstrfrm_tstsync ,
cdc2dmac_mstrfrm_tstsync => s2mm_mstrfrm_tstsync_out ,
-- SOF Detection Domain Crossing
vid2cdc_packet_sof => s2mm_vid2cdc_packet_sof ,
cdc2dmac_packet_sof => s2mm_packet_sof ,
-- Frame Sync Generation Domain Crossing
vid2cdc_fsync => s2mm_fsync_core ,
cdc2dmac_fsync => s2mm_cdc2dmac_fsync ,
dmac2cdc_fsync_out => s2mm_dmac2cdc_fsync_out ,
dmac2cdc_prmtr_update => s2mm_dmac2cdc_prmtr_update ,
cdc2vid_fsync_out => s2mm_fsync_out_i ,
cdc2vid_prmtr_update => s2mm_prmtr_update_i
);
s2mm_fsync_out_sig <= s2mm_fsync_out_i;
-- Start of Frame Detection - used for interrupt coalescing
S2MM_SOF_I : entity axi_vdma_v6_2_8.axi_vdma_sof_gen
port map(
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid_i ,
fsync => s2mm_fsync_out_i , -- CR622884
packet_sof => s2mm_vid2cdc_packet_sof
);
-------------------------------------------------------------------------------
-- Primary S2MM Line Buffer
-------------------------------------------------------------------------------
S2MM_LINEBUFFER_I : entity axi_vdma_v6_2_8.axi_vdma_s2mm_linebuf
generic map(
C_DATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 ,
C_USE_S2MM_FSYNC => C_USE_S2MM_FSYNC ,
C_S_AXIS_S2MM_TUSER_BITS => C_S_AXIS_S2MM_TUSER_BITS ,
C_INCLUDE_S2MM_DRE => C_S2MM_ENABLE_TKEEP ,
C_TOPLVL_LINEBUFFER_DEPTH => C_S2MM_LINEBUFFER_DEPTH , -- CR625142
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_DEPTH => S2MM_LINEBUFFER_DEPTH ,
C_LINEBUFFER_AF_THRESH => C_S2MM_LINEBUFFER_THRESH_INT ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
s_axis_aclk => s_axis_s2mm_aclk ,
s_axis_resetn => s2mm_axis_resetn ,
m_axis_aclk => m_axi_s2mm_aclk ,
m_axis_resetn => s2mm_prmry_resetn ,
s2mm_axis_linebuf_reset_out => s2mm_axis_linebuf_reset_out ,
-- Graceful shut down control
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dm_halt => s2mm_halt , -- CR591965
dm_halt_cmplt => s2mm_halt_cmplt , -- CR591965
capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig ,
s2mm_fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag ,
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s ,
s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err ,
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
no_fsync_before_vsize_sel_00_01 => no_fsync_before_vsize_sel_00_01 ,
hold_dummy_tready_low => hold_dummy_tready_low ,
hold_dummy_tready_low2 => hold_dummy_tready_low2 ,
mm2s_fsync => mm2s_fsync_fe ,
m_axis_mm2s_aclk => m_axis_mm2s_aclk ,
mm2s_axis_resetn => mm2s_axis_resetn ,
s2mm_fsync_core => s2mm_fsync_core ,
s2mm_fsync => s2mm_fsync_fe ,
s2mm_tuser_fsync_top => s2mm_tuser_fsync_top ,
s2mm_dmasr_fsize_less_err => s2mm_dmasr(DMASR_FSIZEERR_BIT) ,
fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
fsync_src_select_s => s2mm_fsync_src_select_s ,
chnl_ready_external => s2mm_chnl_ready ,
strm_not_finished => s2mm_strm_not_finished ,
crnt_vsize_d2_s => s2mm_crnt_vsize_d2 ,
-- Line Tracking Control
crnt_vsize => s2mm_crnt_vsize ,
fsync_out_m => s2mm_fsync_out_m_i ,
fsync_out => s2mm_fsync_out_i ,
frame_sync => s2mm_frame_sync ,
-- Threshold
linebuf_threshold => s2mm_linebuf_threshold ,
-- Stream In
s_axis_tdata => s_axis_s2mm_tdata_i ,
s_axis_tkeep => s_axis_s2mm_tkeep_i ,
s_axis_tlast => s_axis_s2mm_tlast_i ,
s_axis_tvalid => s_axis_s2mm_tvalid_i ,
s_axis_tready => s_axis_s2mm_tready_i ,
s_axis_tuser => s_axis_s2mm_tuser_i ,
-- Stream Out
m_axis_tdata => linebuf2dm_s2mm_tdata ,
m_axis_tkeep => linebuf2dm_s2mm_tkeep ,
m_axis_tlast => linebuf2dm_s2mm_tlast ,
m_axis_tvalid => linebuf2dm_s2mm_tvalid ,
m_axis_tready => dm2linebuf_s2mm_tready ,
-- Fifo Status Flags
s2mm_fifo_full => s2mm_buffer_full_i ,
s2mm_fifo_almost_full => s2mm_buffer_almost_full_i ,
s2mm_all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
s2mm_tuser_fsync => s2mm_tuser_fsync
);
end generate GEN_SPRT_FOR_S2MM;
-- Do not generate support logic for S2MM
GEN_NO_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
-- Register Module Tie-Offs
s2mm_ip2axi_rddata <= (others => '0');
--s2mm_ip2axi_rddata_valid <= '0';
s2mm_ip2axi_frame_ptr_ref <= (others => '0');
s2mm_ip2axi_frame_store <= (others => '0');
s2mm_ip2axi_introut <= '0';
s2mm_soft_reset <= '0';
s2mm_irqthresh_rstdsbl <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dmacr <= (others => '0');
s2mm_dmasr <= (others => '0');
s2mm_curdesc <= (others => '0');
s2mm_taildesc <= (others => '0');
s2mm_num_frame_store <= (others => '0');
s2mm_linebuf_threshold <= (others => '0');
s2mm_regdir_idle <= '0';
s2mm_prmtr_updt_complete <= '0';
s2mm_reg_module_vsize <= (others => '0');
s2mm_reg_module_hsize <= (others => '0');
s2mm_reg_module_stride <= (others => '0');
s2mm_reg_module_frmdly <= (others => '0');
s2mm_dummy_tready <= '0';
-- Must zero each element of an array of vectors to zero
-- all vectors.
GEN_S2MM_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate
begin
s2mm_reg_module_strt_addr(i) <= (others => '0');
end generate GEN_S2MM_ZERO_STRT;
-- Line buffer Tie-Offs
s_axis_s2mm_tready_i_axis_dw_conv <= '0';
s_axis_s2mm_tready_i <= '0';
s_axis_s2mm_tready <= '0';
s2mm_capture_dm_done_vsize_counter_sig <= (others => '0');
s2mm_capture_hsize_at_uf_err_sig <= (others => '0');
linebuf2dm_s2mm_tdata <= (others => '0');
linebuf2dm_s2mm_tkeep <= (others => '0');
linebuf2dm_s2mm_tlast <= '0';
linebuf2dm_s2mm_tvalid <= '0';
s2mm_buffer_full_i <= '0';
s2mm_buffer_almost_full_i <= '0';
s2mm_all_lines_xfred <= '0'; -- CR591965
s2mm_tuser_fsync <= '0';
-- Frame sync generator
s2mm_frame_sync <= '0';
-- SOF/EOF generator
s2mm_packet_sof <= '0';
-- DMA Controller
s2mm_halted_clr <= '0';
s2mm_halted_set <= '1';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s2mm_frame_number <= (others => '0');
s2mm_chnl_current_frame <= (others => '0');
s2mm_genlock_pair_frame <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_stop <= '0';
s2mm_all_idle <= '1';
s2mm_cmdsts_idle <= '1';
s2mm_ftchcmdsts_idle <= '1';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
m_axis_s2mm_sts_tready <= '0';
s2mm_frame_ptr_out_i <= (others => '0');
s2mm_m_frame_ptr_out <= (others => '0');
mm2s_to_s2mm_frame_ptr_in <= (others => '0');
s2mm_valid_frame_sync <= '0';
s2mm_valid_frame_sync_cmb <= '0';
s2mm_valid_video_prmtrs <= '0';
s2mm_parameter_update <= '0';
s2mm_tstvect_err <= '0';
s2mm_tstvect_fsync <= '0';
s2mm_tstvect_frame <= (others => '0');
s2mm_dma_interr_set <= '0';
s2mm_dma_interr_set_minus_frame_errors <= '0';
s2mm_dma_slverr_set <= '0';
s2mm_dma_decerr_set <= '0';
s2mm_fsize_mismatch_err <= '0';
s2mm_lsize_mismatch_err <= '0';
s2mm_lsize_more_mismatch_err <= '0';
-- Frame Sync generator
s2mm_fsync_out_sig <= '0';
s2mm_prmtr_update_i <= '0';
s2mm_crnt_vsize <= (others => '0'); -- CR575884
s2mm_mask_fsync_out <= '0';
s2mm_mstrfrm_tstsync <= '0';
s2mm_mstrfrm_tstsync_out <= '0';
s2mm_tstvect_frm_ptr_out <= (others => '0');
s2mm_frmstr_err_addr <= (others => '0');
s2mm_to_mm2s_fsync <= '0';
end generate GEN_NO_SPRT_FOR_S2MM;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_CLOCK_SYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_ENABLE_MM2S_TKEEP => C_MM2S_ENABLE_TKEEP ,
C_MM2S_BURST_SIZE => C_MM2S_MAX_BURST_LENGTH ,
C_MM2S_BTT_USED => MM2S_DM_BTT_LENGTH_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_ENABLE_SKID_BUF => "11100" ,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_CLOCK_SYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_ENABLE_S2MM_TKEEP => C_S2MM_ENABLE_TKEEP ,
C_S2MM_BURST_SIZE => C_S2MM_MAX_BURST_LENGTH ,
C_S2MM_BTT_USED => S2MM_DM_BTT_LENGTH_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_CMD_WIDTH => CMD_WIDTH ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => mm2s_dm_prmry_resetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_mm2s_aclk ,
m_axis_mm2s_cmdsts_aresetn => mm2s_dm_prmry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_int ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => dm2linebuf_mm2s_tdata ,
m_axis_mm2s_tkeep => dm2linebuf_mm2s_tkeep ,
m_axis_mm2s_tlast => dm2linebuf_mm2s_tlast ,
m_axis_mm2s_tvalid => dm2linebuf_mm2s_tvalid ,
m_axis_mm2s_tready => linebuf2dm_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- Datamover v4_02_a addional signals not needed for VDMA
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => s2mm_dm_prmry_resetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_s2mm_aclk ,
m_axis_s2mm_cmdsts_aresetn => s2mm_dm_prmry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_int ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => linebuf2dm_s2mm_tdata ,
s_axis_s2mm_tkeep => linebuf2dm_s2mm_tkeep ,
s_axis_s2mm_tlast => linebuf2dm_s2mm_tlast ,
s_axis_s2mm_tvalid => linebuf2dm_s2mm_tvalid ,
s_axis_s2mm_tready => dm2linebuf_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd | 21 | 17850 | -------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_sg_if.vhd | 4 | 18354 | -------------------------------------------------------------------------------
-- axi_vdma_sg_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sg_if.vhd
-- Description: This entity is the Scatter Gather Interface for Descriptor
-- Fetches.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_sg_if is
generic (
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
ftch_complete_clr : in std_logic ; --
ftch_complete : out std_logic ; --
--
-- SG Descriptor Fetch AXI Stream In --
m_axis_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : in std_logic ; --
m_axis_ftch_tready : out std_logic ; --
m_axis_ftch_tlast : in std_logic ; --
--
-- Descriptor Field Output --
new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
new_curdesc_wren : out std_logic ; --
--
--
desc_data_wren : out std_logic ; --
--
desc_strtaddress : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) --
);
end axi_vdma_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_strtaddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_strtaddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_data_wren_i : std_logic := '0';
signal ftch_idle_d1 : std_logic := '0';
signal ftch_idle_re : std_logic := '0';
signal ftch_complete_i : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate rising edge of ftch idle
REG_FETCH_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ftch_idle_d1 <= '1';
else
ftch_idle_d1 <= ftch_idle;
end if;
end if;
end process REG_FETCH_IDLE;
ftch_idle_re <= ftch_idle and not ftch_idle_d1;
DESC_FTCH_CMPLT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
ftch_complete_i <= '0';
-- SG Engine not going idle and commanded to clear flag
elsif(ftch_idle_re = '0' and ftch_complete_clr = '1')then
ftch_complete_i <= '0';
-- On SG Engine going idle flag descriptor fetches as complete
elsif(ftch_idle_re = '1')then
ftch_complete_i <= '1';
end if;
end if;
end process DESC_FTCH_CMPLT;
ftch_complete <= ftch_complete_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_ftch_tlast
and m_axis_ftch_tvalid
and ftch_tready;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_ftch_tvalid
and ftch_tready
and not desc_data_wren_i;
-- Passed curdes write out to register module
new_curdesc_wren <= desc_data_wren_i;
-- Drive ready if NOT writing video xfer paramters
-- and if not already fetched set of video paramerters/start addresses
ftch_tready <= not desc_data_wren_i and not ftch_complete_i;
-- Drive ready out to SG Engine
m_axis_ftch_tready <= ftch_tready;
-------------------------------------------------------------------------------
-- Large shift register to bring in descriptor fields
-------------------------------------------------------------------------------
DESC_WRD_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
desc_reg6 <= (others => '0');
desc_reg5 <= (others => '0');
desc_reg4 <= (others => '0');
desc_reg3 <= (others => '0');
desc_reg2 <= (others => '0');
desc_reg1 <= (others => '0');
desc_reg0 <= (others => '0');
-- Shift if enabled or if doing and overlay
elsif(ftch_shftenbl = '1')then
desc_reg6 <= m_axis_ftch_tdata;
desc_reg5 <= desc_reg6;
desc_reg4 <= desc_reg5;
desc_reg3 <= desc_reg4;
desc_reg2 <= desc_reg3;
desc_reg1 <= desc_reg2;
desc_reg0 <= desc_reg1;
end if;
end if;
end process DESC_WRD_PROCESS;
desc_curdesc_lsb <= desc_reg0;
desc_curdesc_msb <= desc_reg1;
desc_strtaddr_lsb <= desc_reg2;
desc_strtaddr_msb <= desc_reg3;
desc_vsize <= desc_reg4(DESC_WRD4_VSIZE_MSB_BIT downto DESC_WRD4_VSIZE_LSB_BIT);
desc_hsize <= desc_reg5(DESC_WRD5_HSIZE_MSB_BIT downto DESC_WRD5_HSIZE_LSB_BIT);
desc_stride <= desc_reg6(DESC_WRD6_STRIDE_MSB_BIT downto DESC_WRD6_STRIDE_LSB_BIT);
desc_frmdly <= desc_reg6(DESC_WRD6_FRMDLY_MSB_BIT downto DESC_WRD6_FRMDLY_LSB_BIT);
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_ADDR_WIDTH = 64 generate
desc_strtaddress <= desc_strtaddr_msb & desc_strtaddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_ADDR_WIDTH = 32 generate
desc_strtaddress <= desc_strtaddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
new_curdesc <= desc_curdesc_msb & desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
new_curdesc <= desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
-- Write new descriptor data out on last
REG_DESCDATA_WREN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
desc_data_wren_i <= '0';
-- Write new desc data on fetch done
elsif(desc_fetch_done_i = '1')then
desc_data_wren_i <= '1';
else
desc_data_wren_i <= '0';
end if;
end if;
end process REG_DESCDATA_WREN;
desc_data_wren <= desc_data_wren_i;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_pkg.vhd | 4 | 71734 | -------------------------------------------------------------------------------
-- axi_vdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI VDMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
package axi_vdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer;
-- CALCULATE mm2s_tdata_width for axi_vdma
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer;
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth: integer)
return integer;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth: integer)
return integer;
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Converts string to interger
function string2int(strngbuf: string)
return integer;
-- Return number of registers
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return enable genlock bus
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL_SG : integer := 62;
constant NUM_REG_TOTAL_REGDIR : integer := 62;
----constant NUM_REG_TOTAL_SG : integer := 20;
----constant NUM_REG_TOTAL_REGDIR : integer := 59;
--constant NUM_REG_TOTAL_REGDIR : integer := 156;
--constant NUM_REG_TOTAL_REGDIR : integer := 123;
constant NUM_REG_PER_CHANNEL : integer := 8;
constant NUM_DIRECT_REG_PER_CHANNEL : integer := 19;
--constant NUM_DIRECT_REG_PER_CHANNEL : integer := 67;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Clock Domain Crossing Constants
constant CDC_TYPE_PULSE_P_S : integer := 0;
constant CDC_TYPE_LEVEL_P_S : integer := 1;
constant CDC_TYPE_PULSE_S_P : integer := 2;
constant CDC_TYPE_LEVEL_S_P : integer := 3;
constant CDC_TYPE_VECTR_P_S : integer := 4;
constant CDC_TYPE_VECTR_S_P : integer := 5;
constant CDC_TYPE_PULSE_P_S_NO_RST : integer := 6;
constant CDC_TYPE_LEVEL_P_S_NO_RST : integer := 7;
constant CDC_TYPE_PULSE_S_P_NO_RST : integer := 8;
constant CDC_TYPE_LEVEL_S_P_NO_RST : integer := 9;
constant CDC_TYPE_PULSE_P_S_LL : integer := 10;
constant CDC_TYPE_PULSE_S_P_LL : integer := 11;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED : integer := 12;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED : integer := 13;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST : integer := 14;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST : integer := 15;
constant MTBF_STAGES : integer := 4;
constant MTBF_STAGES_LITE : integer := 3;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Frame Store
constant NUM_FRM_STORE_WIDTH : integer := 6;
constant FRAME_NUMBER_WIDTH : integer := NUM_FRM_STORE_WIDTH - 1;
constant ZERO_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
constant ONE_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH));
constant MAX_FSTORES : integer := 32;
-- Line Buffer
constant LINEBUFFER_THRESH_WIDTH : integer := 17;
-- Video parameter constants
constant VSIZE_DWIDTH : integer := 13;
constant HSIZE_DWIDTH : integer := 16;
constant STRIDE_DWIDTH : integer := 16;
constant FRMDLY_DWIDTH : integer := FRAME_NUMBER_WIDTH;
constant FRMDLY_MSB : integer := 28;
constant FRMDLY_LSB : integer := 24;
constant RSVD_BITS_31TO29 : std_logic_vector(2 downto 0) := (others => '0');
constant RSVD_BITS_23TO16 : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_REG_IND : integer := 5;
constant MM2S_FRAME_STORE_INDEX : integer := 6;
constant MM2S_THRESHOLD_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant VDMA_GLPTR_INDEX : integer := 9;
constant VDMA_PARKPTR_INDEX : integer := 10;
constant VDMA_VERISON_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_DMA_IRQ_MASK : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_REG_IND : integer := 17;
constant S2MM_FRAME_STORE_INDEX : integer := 18;
constant S2MM_THRESHOLD_INDEX : integer := 19;
-- Register direct
constant MM2S_VSIZE_INDEX : integer := 20;
constant MM2S_HSIZE_INDEX : integer := 21;
constant MM2S_DLYSTRD_INDEX : integer := 22;
constant MM2S_STARTADDR1_INDEX : integer := 23;
constant MM2S_STARTADDR2_INDEX : integer := 24;
constant MM2S_STARTADDR3_INDEX : integer := 25;
constant MM2S_STARTADDR4_INDEX : integer := 26;
constant MM2S_STARTADDR5_INDEX : integer := 27;
constant MM2S_STARTADDR6_INDEX : integer := 28;
constant MM2S_STARTADDR7_INDEX : integer := 29;
constant MM2S_STARTADDR8_INDEX : integer := 30;
constant MM2S_STARTADDR9_INDEX : integer := 31;
constant MM2S_STARTADDR10_INDEX : integer := 32;
constant MM2S_STARTADDR11_INDEX : integer := 33;
constant MM2S_STARTADDR12_INDEX : integer := 34;
constant MM2S_STARTADDR13_INDEX : integer := 35;
constant MM2S_STARTADDR14_INDEX : integer := 36;
constant MM2S_STARTADDR15_INDEX : integer := 37;
constant MM2S_STARTADDR16_INDEX : integer := 38;
constant RESERVED_9C_INDEX : integer := 39;
constant S2MM_VSIZE_INDEX : integer := 40;
constant S2MM_HSIZE_INDEX : integer := 41;
constant S2MM_DLYSTRD_INDEX : integer := 42;
constant S2MM_STARTADDR1_INDEX : integer := 43;
constant S2MM_STARTADDR2_INDEX : integer := 44;
constant S2MM_STARTADDR3_INDEX : integer := 45;
constant S2MM_STARTADDR4_INDEX : integer := 46;
constant S2MM_STARTADDR5_INDEX : integer := 47;
constant S2MM_STARTADDR6_INDEX : integer := 48;
constant S2MM_STARTADDR7_INDEX : integer := 49;
constant S2MM_STARTADDR8_INDEX : integer := 50;
constant S2MM_STARTADDR9_INDEX : integer := 51;
constant S2MM_STARTADDR10_INDEX : integer := 52;
constant S2MM_STARTADDR11_INDEX : integer := 53;
constant S2MM_STARTADDR12_INDEX : integer := 54;
constant S2MM_STARTADDR13_INDEX : integer := 55;
constant S2MM_STARTADDR14_INDEX : integer := 56;
constant S2MM_STARTADDR15_INDEX : integer := 57;
constant S2MM_STARTADDR16_INDEX : integer := 58;
constant RESERVED_EC_INDEX : integer := 59;
--constant RESERVED_F0_INDEX : integer := 60;
constant HSIZE_AT_LLESS_ERR_F0_INDEX : integer := 60;
--constant RESERVED_F4_INDEX : integer := 61;
constant VSIZE_AT_FLESS_ERR_F4_INDEX : integer := 61;
constant RESERVED_F8_INDEX : integer := 62;
constant RESERVED_FC_INDEX : integer := 63;
constant RESERVED_100_INDEX : integer := 64;
constant RESERVED_104_INDEX : integer := 65;
constant RESERVED_108_INDEX : integer := 66;
constant RESERVED_10C_INDEX : integer := 67;
constant RESERVED_110_INDEX : integer := 68;
constant RESERVED_114_INDEX : integer := 69;
constant RESERVED_118_INDEX : integer := 70;
constant RESERVED_11C_INDEX : integer := 71;
constant RESERVED_120_INDEX : integer := 72;
constant RESERVED_124_INDEX : integer := 73;
constant RESERVED_128_INDEX : integer := 74;
constant RESERVED_12C_INDEX : integer := 75;
constant RESERVED_130_INDEX : integer := 76;
constant RESERVED_134_INDEX : integer := 77;
constant RESERVED_138_INDEX : integer := 78;
constant RESERVED_13C_INDEX : integer := 79;
constant RESERVED_140_INDEX : integer := 80;
constant RESERVED_144_INDEX : integer := 81;
constant RESERVED_148_INDEX : integer := 82;
constant RESERVED_14C_INDEX : integer := 83;
constant RESERVED_150_INDEX : integer := 84;
constant RESERVED_154_INDEX : integer := 85;
constant RESERVED_158_INDEX : integer := 86;
constant MM2S_STARTADDR17_INDEX : integer := 87;
constant MM2S_STARTADDR18_INDEX : integer := 88;
constant MM2S_STARTADDR19_INDEX : integer := 89;
constant MM2S_STARTADDR20_INDEX : integer := 90;
constant MM2S_STARTADDR21_INDEX : integer := 91;
constant MM2S_STARTADDR22_INDEX : integer := 92;
constant MM2S_STARTADDR23_INDEX : integer := 93;
constant MM2S_STARTADDR24_INDEX : integer := 94;
constant MM2S_STARTADDR25_INDEX : integer := 95;
constant MM2S_STARTADDR26_INDEX : integer := 96;
constant MM2S_STARTADDR27_INDEX : integer := 97;
constant MM2S_STARTADDR28_INDEX : integer := 98;
constant MM2S_STARTADDR29_INDEX : integer := 99;
constant MM2S_STARTADDR30_INDEX : integer := 100;
constant MM2S_STARTADDR31_INDEX : integer := 101;
constant MM2S_STARTADDR32_INDEX : integer := 102;
constant RESERVED_19C_INDEX : integer := 103;
constant RESERVED_1A0_INDEX : integer := 104;
constant RESERVED_1A4_INDEX : integer := 105;
constant RESERVED_1A8_INDEX : integer := 106;
constant S2MM_STARTADDR17_INDEX : integer := 107;
constant S2MM_STARTADDR18_INDEX : integer := 108;
constant S2MM_STARTADDR19_INDEX : integer := 109;
constant S2MM_STARTADDR20_INDEX : integer := 110;
constant S2MM_STARTADDR21_INDEX : integer := 111;
constant S2MM_STARTADDR22_INDEX : integer := 112;
constant S2MM_STARTADDR23_INDEX : integer := 113;
constant S2MM_STARTADDR24_INDEX : integer := 114;
constant S2MM_STARTADDR25_INDEX : integer := 115;
constant S2MM_STARTADDR26_INDEX : integer := 116;
constant S2MM_STARTADDR27_INDEX : integer := 117;
constant S2MM_STARTADDR28_INDEX : integer := 118;
constant S2MM_STARTADDR29_INDEX : integer := 119;
constant S2MM_STARTADDR30_INDEX : integer := 120;
constant S2MM_STARTADDR31_INDEX : integer := 121;
constant S2MM_STARTADDR32_INDEX : integer := 122;
-- READ MUX Offsets
constant MM2S_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
-- }
constant MM2S_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_SG : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_SG : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant VDMA_PARK_PTRREF_OFFSET_SG : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_SG : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_8 : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_8 : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET_8 : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_8 : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000000"; -- 000
constant MM2S_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000100"; -- 004
constant MM2S_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001000"; -- 008
constant MM2S_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001100"; -- 00C
constant MM2S_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010000"; -- 010
constant MM2S_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 014
constant MM2S_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "000011000"; -- 018
constant MM2S_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "000011100"; -- 01C
constant RESERVED_20_OFFSET_90 : std_logic_vector(8 downto 0) := "000100000"; -- 020
constant RESERVED_24_OFFSET_90 : std_logic_vector(8 downto 0) := "000100100"; -- 024
constant VDMA_PARK_PTRREF_OFFSET_90 : std_logic_vector(8 downto 0) := "000101000"; -- 028
constant VDMA_VERSION_OFFSET_90 : std_logic_vector(8 downto 0) := "000101100"; -- 02C
constant S2MM_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110000"; -- 030
constant S2MM_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110100"; -- 034
constant S2MM_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111000"; -- 038
constant S2MM_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_DMA_IRQ_MASK_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000000"; -- 040
constant S2MM_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 044
constant S2MM_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "001001000"; -- 048
constant S2MM_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "001001100"; -- 04C
------
constant MM2S_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant MM2S_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant MM2S_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant MM2S_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant MM2S_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant MM2S_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant MM2S_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant MM2S_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_20_OFFSET_91 : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_24_OFFSET_91 : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant VDMA_PARK_PTRREF_OFFSET_91 : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant VDMA_VERSION_OFFSET_91 : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant S2MM_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant S2MM_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant S2MM_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant S2MM_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_DMA_IRQ_MASK_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant S2MM_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant S2MM_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant S2MM_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "101001100"; -- 14C
------
-------- Register direct READ MUX Offsets
constant MM2S_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010000"; -- 50
constant MM2S_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010100"; -- 54
constant MM2S_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "01011000"; -- 58
constant MM2S_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010000"; -- 050
constant MM2S_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "001011000"; -- 058
constant MM2S_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010000"; -- 050
constant MM2S_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "101011000"; -- 058
constant MM2S_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "01011100"; -- 5C
constant MM2S_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "01100000"; -- 60
constant MM2S_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "01100100"; -- 64
constant MM2S_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "01101000"; -- 68
constant MM2S_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "01101100"; -- 6C
constant MM2S_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "01110000"; -- 70
constant MM2S_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "01110100"; -- 74
constant MM2S_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "01111000"; -- 78
constant MM2S_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "01111100"; -- 7C
constant MM2S_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "10000000"; -- 80
constant MM2S_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "10000100"; -- 84
constant MM2S_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "10001000"; -- 88
constant MM2S_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "10001100"; -- 8C
constant MM2S_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "10010000"; -- 90
constant MM2S_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "10010100"; -- 94
constant MM2S_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "10011000"; -- 98
constant MM2S_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "001011100"; -- 05C
constant MM2S_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "001100000"; -- 060
constant MM2S_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "001100100"; -- 064
constant MM2S_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "001101000"; -- 068
constant MM2S_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "001101100"; -- 06C
constant MM2S_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "001110000"; -- 070
constant MM2S_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "001110100"; -- 074
constant MM2S_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "001111000"; -- 078
constant MM2S_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "001111100"; -- 07C
constant MM2S_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "010000000"; -- 080
constant MM2S_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "010000100"; -- 084
constant MM2S_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "010001000"; -- 088
constant MM2S_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "010001100"; -- 08C
constant MM2S_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "010010000"; -- 090
constant MM2S_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "010010100"; -- 094
constant MM2S_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "010011000"; -- 098
constant MM2S_STARTADDR1_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR2_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR3_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR4_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR5_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR6_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR7_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR8_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR9_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR10_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR11_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR12_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR13_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR14_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR15_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR16_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_9C_OFFSET_90 : std_logic_vector(8 downto 0) := "010011100"; -- 9C
constant S2MM_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100000"; -- A0
constant S2MM_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "10101000"; -- A8
constant S2MM_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100000"; -- A0
constant S2MM_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "010101000"; -- A8
constant S2MM_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100000"; -- A0
constant S2MM_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "110101000"; -- A8
constant S2MM_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "10101100"; -- AC
constant S2MM_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "10110000"; -- B0
constant S2MM_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "10110100"; -- B4
constant S2MM_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "10111000"; -- B8
constant S2MM_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "10111100"; -- BC
constant S2MM_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "11000000"; -- C0
constant S2MM_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "11000100"; -- C4
constant S2MM_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "11001000"; -- C8
constant S2MM_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "11001100"; -- CC
constant S2MM_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "11010000"; -- D0
constant S2MM_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "11010100"; -- D4
constant S2MM_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "11011000"; -- D8
constant S2MM_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "11011100"; -- DC
constant S2MM_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "11100000"; -- E0
constant S2MM_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "11100100"; -- E4
constant S2MM_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "11101000"; -- E8
constant S2MM_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "010101100"; -- 0AC
constant S2MM_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "010110000"; -- 0B0
constant S2MM_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "010110100"; -- 0B4
constant S2MM_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "010111000"; -- 0B8
constant S2MM_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "010111100"; -- 0BC
constant S2MM_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "011000000"; -- 0C0
constant S2MM_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "011000100"; -- 0C4
constant S2MM_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "011001000"; -- 0C8
constant S2MM_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "011001100"; -- 0CC
constant S2MM_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "011010000"; -- 0D0
constant S2MM_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "011010100"; -- 0D4
constant S2MM_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "011011000"; -- 0D8
constant S2MM_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "011011100"; -- 0DC
constant S2MM_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "011100000"; -- 0E0
constant S2MM_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "011100100"; -- 0E4
constant S2MM_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "011101000"; -- 0E8
constant RESERVED_EC_OFFSET : std_logic_vector(8 downto 0) := "011101100"; -- 0EC
constant RESERVED_F0_OFFSET : std_logic_vector(8 downto 0) := "011110000"; -- 0F0
constant RESERVED_F4_OFFSET : std_logic_vector(8 downto 0) := "011110100"; -- 0F4
constant RESERVED_F8_OFFSET : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
constant RESERVED_FC_OFFSET : std_logic_vector(8 downto 0) := "011111100"; -- 0FC
constant RESERVED_100_OFFSET : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant RESERVED_104_OFFSET : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant RESERVED_108_OFFSET : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant RESERVED_10C_OFFSET : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant RESERVED_110_OFFSET : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant RESERVED_114_OFFSET : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant RESERVED_118_OFFSET : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant RESERVED_11C_OFFSET : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_120_OFFSET : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_124_OFFSET : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant RESERVED_128_OFFSET : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant RESERVED_12C_OFFSET : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant RESERVED_130_OFFSET : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant RESERVED_134_OFFSET : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant RESERVED_138_OFFSET : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant RESERVED_13C_OFFSET : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant RESERVED_140_OFFSET : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant RESERVED_144_OFFSET : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant RESERVED_148_OFFSET : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant RESERVED_14C_OFFSET : std_logic_vector(8 downto 0) := "101001100"; -- 14C
constant RESERVED_150_OFFSET : std_logic_vector(8 downto 0) := "101010000"; -- 150
constant RESERVED_154_OFFSET : std_logic_vector(8 downto 0) := "101010100"; -- 154
constant RESERVED_158_OFFSET : std_logic_vector(8 downto 0) := "101011000"; -- 158
constant MM2S_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_19C_OFFSET : std_logic_vector(8 downto 0) := "110011100"; -- 19C
constant RESERVED_1A0_OFFSET : std_logic_vector(8 downto 0) := "110100000"; -- 1A0
constant RESERVED_1A4_OFFSET : std_logic_vector(8 downto 0) := "110100100"; -- 1A4
constant RESERVED_1A8_OFFSET : std_logic_vector(8 downto 0) := "110101000"; -- 1A8
constant S2MM_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "110101100"; -- 1AC
constant S2MM_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "110110000"; -- 1B0
constant S2MM_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "110110100"; -- 1B4
constant S2MM_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "110111000"; -- 1B8
constant S2MM_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "110111100"; -- 1BC
constant S2MM_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "111000000"; -- 1C0
constant S2MM_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "111000100"; -- 1C4
constant S2MM_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "111001000"; -- 1C8
constant S2MM_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "111001100"; -- 1CC
constant S2MM_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "111010000"; -- 1D0
constant S2MM_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "111010100"; -- 1D4
constant S2MM_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "111011000"; -- 1D8
constant S2MM_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "111011100"; -- 1DC
constant S2MM_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "111100000"; -- 1E0
constant S2MM_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "111100100"; -- 1E4
constant S2MM_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "111101000"; -- 1E8
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_CRCLPRK_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SYNCEN_BIT : integer := 3;
constant DMACR_FRMCNTEN_BIT : integer := 4;
constant DMACR_FSYNCSEL_LSB : integer := 5;
constant DMACR_FSYNCSEL_MSB : integer := 6;
constant DMACR_GENLOCK_SEL_BIT : integer := 7;
constant DMACR_PNTR_NUM_LSB : integer := 8;
constant DMACR_PNTR_NUM_MSB : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
--constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_REPEAT_EN_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_RESERVED2_BIT : integer := 2;
constant DMASR_ERR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_FSIZEERR_BIT : integer := 7;
constant DMASR_LSIZEERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
--constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_LSIZE_MORE_ERR_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
constant PARKPTR_FRMSTR_RSVD_BIT31 : integer := 31;
constant PARKPTR_FRMSTR_S2MM_MSB_BIT : integer := 28;
constant PARKPTR_FRMSTR_S2MM_LSB_BIT : integer := 24;
constant PARKPTR_FRMSTR_MM2S_MSB_BIT : integer := 20;
constant PARKPTR_FRMSTR_MM2S_LSB_BIT : integer := 16;
constant PARKPTR_FRMSTR_RSVD_BIT15 : integer := 15;
constant PARKPTR_FRMPTR_S2MM_MSB_BIT : integer := 12;
constant PARKPTR_FRMPTR_S2MM_LSB_BIT : integer := 8;
constant PARKPTR_FRMPTR_MM2S_MSB_BIT : integer := 4;
constant PARKPTR_FRMPTR_MM2S_LSB_BIT : integer := 0;
-- FRAMESTORE
constant FRMSTORE_LSB_BIT : integer := 0;
constant FRMSTORE_MSB_BIT : integer := NUM_FRM_STORE_WIDTH-1;
-- LineBuffer Threshold
constant THRESH_LSB_BIT : integer := 0;
constant THRESH_MSB_BIT : integer := LINEBUFFER_THRESH_WIDTH-1;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Word 0 : NXTDESC PTR LS-WORD
-- Descriptor Word 1 : NXTDESC PTR MS-WORD
-- Descriptor Word 2 : STARTADDR PTR LS-WORD
-- Descriptor Word 3 : STARTADDR PTR MS-WORD
-- Descriptor Word 4
constant DESC_WRD4_VSIZE_LSB_BIT : integer := 0;
constant DESC_WRD4_VSIZE_MSB_BIT : integer := 12;
-- Descriptor Word 5
constant DESC_WRD5_HSIZE_LSB_BIT : integer := 0;
constant DESC_WRD5_HSIZE_MSB_BIT : integer := 15;
-- Descriptor Word 6
constant DESC_WRD6_STRIDE_LSB_BIT : integer := 0;
constant DESC_WRD6_STRIDE_MSB_BIT : integer := 15;
constant DESC_WRD6_FRMDLY_LSB_BIT : integer := 24;
constant DESC_WRD6_FRMDLY_MSB_BIT : integer := 28;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Gen-Lock constants
constant MSTR0 : std_logic_vector(3 downto 0) := "0000";
constant MSTR1 : std_logic_vector(3 downto 0) := "0001";
constant MSTR2 : std_logic_vector(3 downto 0) := "0010";
constant MSTR3 : std_logic_vector(3 downto 0) := "0011";
constant MSTR4 : std_logic_vector(3 downto 0) := "0100";
constant MSTR5 : std_logic_vector(3 downto 0) := "0101";
constant MSTR6 : std_logic_vector(3 downto 0) := "0110";
constant MSTR7 : std_logic_vector(3 downto 0) := "0111";
constant MSTR8 : std_logic_vector(3 downto 0) := "1000";
constant MSTR9 : std_logic_vector(3 downto 0) := "1001";
constant MSTR10 : std_logic_vector(3 downto 0) := "1010";
constant MSTR11 : std_logic_vector(3 downto 0) := "1011";
constant MSTR12 : std_logic_vector(3 downto 0) := "1100";
constant MSTR13 : std_logic_vector(3 downto 0) := "1101";
constant MSTR14 : std_logic_vector(3 downto 0) := "1110";
constant MSTR15 : std_logic_vector(3 downto 0) := "1111";
constant MSTR0_LO_INDEX : integer := 0;
constant MSTR0_HI_INDEX : integer := 5;
constant MSTR1_LO_INDEX : integer := 6;
constant MSTR1_HI_INDEX : integer := 11;
constant MSTR2_LO_INDEX : integer := 12;
constant MSTR2_HI_INDEX : integer := 17;
constant MSTR3_LO_INDEX : integer := 18;
constant MSTR3_HI_INDEX : integer := 23;
constant MSTR4_LO_INDEX : integer := 24;
constant MSTR4_HI_INDEX : integer := 29;
constant MSTR5_LO_INDEX : integer := 30;
constant MSTR5_HI_INDEX : integer := 35;
constant MSTR6_LO_INDEX : integer := 36;
constant MSTR6_HI_INDEX : integer := 41;
constant MSTR7_LO_INDEX : integer := 42;
constant MSTR7_HI_INDEX : integer := 47;
constant MSTR8_LO_INDEX : integer := 48;
constant MSTR8_HI_INDEX : integer := 53;
constant MSTR9_LO_INDEX : integer := 54;
constant MSTR9_HI_INDEX : integer := 59;
constant MSTR10_LO_INDEX : integer := 60;
constant MSTR10_HI_INDEX : integer := 65;
constant MSTR11_LO_INDEX : integer := 66;
constant MSTR11_HI_INDEX : integer := 71;
constant MSTR12_LO_INDEX : integer := 72;
constant MSTR12_HI_INDEX : integer := 77;
constant MSTR13_LO_INDEX : integer := 78;
constant MSTR13_HI_INDEX : integer := 83;
constant MSTR14_LO_INDEX : integer := 84;
constant MSTR14_HI_INDEX : integer := 89;
constant MSTR15_LO_INDEX : integer := 90;
constant MSTR15_HI_INDEX : integer := 95;
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
constant BITS_PER_REG : integer := 32;
constant BITS_PER_REG_64 : integer := 64;
type STARTADDR_ARRAY_TYPE is array(natural range <>)
of std_logic_vector(BITS_PER_REG - 1 downto 0);
type STARTADDR_ARRAY_TYPE_64 is array(natural range <>)
of std_logic_vector(BITS_PER_REG_64 - 1 downto 0);
end axi_vdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_vdma_pkg is
-- coverage off
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- String to Integer Function
-------------------------------------------------------------------------------
function string2int(strngbuf: string)
return integer is
variable result : integer := 0;
begin
for i in 1 to strngbuf'length loop
case strngbuf(i) is
when '0' => result := result*10;
when '1' => result := result*10 + 1;
when '2' => result := result*10 + 2;
when '3' => result := result*10 + 3;
when '4' => result := result*10 + 4;
when '5' => result := result*10 + 5;
when '6' => result := result*10 + 6;
when '7' => result := result*10 + 7;
when '8' => result := result*10 + 8;
when '9' => result := result*10 + 9;
-- coverage off
when others => null;
-- coverage on
end case;
end loop;
return result;
end;
--------------------------------------------------------------------------------
--Channel Fsync & Flush decoding
--------------------------------------------------------------------------------
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 2) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_fsync;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer is
begin
if (use_s2mm_fsync = 1 or use_s2mm_fsync = 2)then
return 1;
else
return 0;
end if;
end function find_s2mm_fsync_01;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 3) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_fsync;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 2))then
return 1;
elsif (use_fsync = 2 and flush_on_fsync = 2)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_flush;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 3))then
return 1;
elsif (use_fsync = 3 and flush_on_fsync = 3)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_flush;
-- coverage on
----------------------------------------------------------------------------------------------------------
-- Function to calculate minimum threshold value for MM2S Line buffer based on TDATA, and LineBuffer Depth
----------------------------------------------------------------------------------------------------------
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth : integer)
return integer is
begin
if(mm2s_included = 0 or mm2s_linebuffer_depth = 0)then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 8) then
return 1;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 16) then
return 2;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 32) then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 64) then
return 8;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 128) then
return 16;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 256) then
return 32;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 512) then
return 64;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_mm2s_linebuffer_thresh;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth : integer)
return integer is
begin
if(s2mm_included = 0 or s2mm_linebuffer_depth = 0)then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 8) then
return 1;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 16) then
return 2;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 32) then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 64) then
return 8;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 128) then
return 16;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 256) then
return 32;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 512) then
return 64;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_s2mm_linebuffer_thresh;
-------------------------------------------------------------------------------
-- Function to calculate C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED from C_M_AXIS_MM2S_TDATA_WIDTH
-------------------------------------------------------------------------------
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer is
begin
if(mm2s_tdata_dwidth <= 16)then
return mm2s_tdata_dwidth;
elsif(mm2s_tdata_dwidth > 16 and mm2s_tdata_dwidth <= 32) then
return 32;
elsif(mm2s_tdata_dwidth > 32 and mm2s_tdata_dwidth <= 64) then
return 64;
elsif(mm2s_tdata_dwidth > 64 and mm2s_tdata_dwidth <= 128) then
return 128;
elsif(mm2s_tdata_dwidth > 128 and mm2s_tdata_dwidth <= 256) then
return 256;
elsif(mm2s_tdata_dwidth > 256 and mm2s_tdata_dwidth <= 512) then
return 512;
elsif(mm2s_tdata_dwidth > 512 and mm2s_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_mm2s_tdata_width;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer is
begin
if(s2mm_tdata_dwidth <= 16)then
return s2mm_tdata_dwidth;
elsif(s2mm_tdata_dwidth > 16 and s2mm_tdata_dwidth <= 32) then
return 32;
elsif(s2mm_tdata_dwidth > 32 and s2mm_tdata_dwidth <= 64) then
return 64;
elsif(s2mm_tdata_dwidth > 64 and s2mm_tdata_dwidth <= 128) then
return 128;
elsif(s2mm_tdata_dwidth > 128 and s2mm_tdata_dwidth <= 256) then
return 256;
elsif(s2mm_tdata_dwidth > 256 and s2mm_tdata_dwidth <= 512) then
return 512;
elsif(s2mm_tdata_dwidth > 512 and s2mm_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_s2mm_tdata_width;
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer is
begin
if(DRE_ON = 1 or ( tdata_width_calculated /= tdata_dwidth))then
return 1;
else
return 0 ;
end if;
end function enable_tkeep_connectivity;
-------------------------------------------------------------------------------
-- function to return number of registers depending on mode of operation
-------------------------------------------------------------------------------
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer is
begin
-- 1 = Scatter Gather Mode
-- 0 = Register Direct Mode
if(mode = 1)then
return sg_num;
else
return regdir_num;
end if;
end;
-- coverage off
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-- coverage on
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
return 0;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the base registers
-------------------------------------------------------------------------------
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
new_index := mm2s_index + 12;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the regdir registers
-------------------------------------------------------------------------------
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
--new_index := mm2s_index + 68;
new_index := mm2s_index + 20;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- enable internal genlock bus based on genlock modes and internal genlock
-- parameters.
-------------------------------------------------------------------------------
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer is
begin
-- internal genlock turned OFF at parameter or if NOT both channel enabled.
if(internal_genlock = 0 or mm2s_enabled = 0 or s2mm_enabled = 0)then
return 0;
-- at least one channel must be a master and one be a slave
-- before turning ON the internal genlock bus
elsif( (mm2s_genlock_mode = 0 and s2mm_genlock_mode = 1)
or (mm2s_genlock_mode = 1 and s2mm_genlock_mode = 0))then
return 1;
elsif( (mm2s_genlock_mode = 2 and s2mm_genlock_mode = 3)
or (mm2s_genlock_mode = 3 and s2mm_genlock_mode = 2))then
return 1;
-- either both are maters or both are slaves therefore
-- turn OFF internal genlock bus
else
return 0;
end if;
end;
end package body axi_vdma_pkg;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_sfifo.vhd | 4 | 58852 | -------------------------------------------------------------------------------
-- axi_vdma_sfifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sfifo.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
--use proc_common_v4_0_2.coregen_comp_defs.all;
--use proc_common_v4_0_2.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
ENTITY axi_vdma_sfifo IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_FAMILY : STRING := "virtex7"; --
C_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 0,1 ; Default 1
UW_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16
UW_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K
);
PORT (
-- Common signal
rst : in std_logic := '0';
sleep : in std_logic := '0';
wr_rst_busy : out std_logic := '0';
rd_rst_busy : out std_logic := '0';
-- Write Domain signals
clk : in std_logic := '0';
din : in std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
full : out std_logic := '0';
data_count : out std_logic_vector(clog2(uw_fifo_depth)-1 downto 0) := (others => '0');
-- Read Domain signals
rd_en : in std_logic := '0';
dout : out std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
empty : out std_logic := '1'
);
END ENTITY axi_vdma_sfifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
ARCHITECTURE xilinx OF axi_vdma_sfifo IS
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";
--CONSTANT GND : std_logic := '0';
CONSTANT VCC : std_logic := '1';
CONSTANT clog2_uw_fifo_depth : integer := clog2(uw_fifo_depth);
CONSTANT clog2_uw_fifo_depth_plus_1 : integer := clog2(uw_fifo_depth) + 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ZERO_pntr : std_logic_vector(clog2_uw_fifo_depth-1 downto 0) := (others => '0');
signal GND : std_logic := '0';
signal ALMOST_FULL : std_logic;
signal WR_ACK : std_logic;
signal OVERFLOW : std_logic;
signal ALMOST_EMPTY : std_logic;
signal VALID : std_logic;
signal UNDERFLOW : std_logic;
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RD_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal WR_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
signal sig_data_count : std_logic_vector(clog2(uw_fifo_depth) downto 0) := (others => '0');
begin
--FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate
--begin
--
--wr_rst_busy <= wr_rst_busy_sig;
--rd_rst_busy <= rd_rst_busy_sig;
--
--
--end generate FAMILY_8;
--
--FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate
--begin
--
--wr_rst_busy <= '0';
--rd_rst_busy <= '0';
--
--
--end generate FAMILY_NOT_8;
FAMILY_NOT_7 : if ((C_FAMILY /= "kintex7") and (C_FAMILY /= "virtex7") and (C_FAMILY /= "artix7") and (C_FAMILY /= "zynq")) generate
begin
wr_rst_busy <= wr_rst_busy_sig;
rd_rst_busy <= rd_rst_busy_sig;
end generate FAMILY_NOT_7;
FAMILY_7 : if ((C_FAMILY = "kintex7") or (C_FAMILY = "virtex7") or (C_FAMILY = "artix7") or (C_FAMILY = "zynq")) generate
begin
wr_rst_busy <= '0';
rd_rst_busy <= '0';
end generate FAMILY_7;
data_count <= sig_data_count(clog2(uw_fifo_depth)-1 downto 0);
ZERO_pntr <= (others => '0');
GND <= '0';
fg_inst : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
-- C_COUNT_TYPE => C_COUNT_TYPE,
C_COUNT_TYPE => 0, --my
-- C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DATA_COUNT_WIDTH => clog2_uw_fifo_depth_plus_1, --my
-- C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => uw_data_width,
-- C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => uw_data_width,
-- C_ENABLE_RLOCS => C_ENABLE_RLOCS,
--C_FAMILY => "virtex7",
C_FAMILY => C_FAMILY, --my
--C_FULL_FLAGS_RST_VAL => uw_full_flags_rst_val,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, --my
-- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
-- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
-- C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => 1, --my
-- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
-- C_HAS_INT_CLK => C_HAS_INT_CLK,
-- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
-- C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => 0, --my
-- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
-- C_HAS_RD_RST => C_HAS_RD_RST,
C_EN_SAFETY_CKT => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
-- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
-- C_HAS_VALID => C_HAS_VALID,
-- C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, --my
-- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
-- C_HAS_WR_RST => C_HAS_WR_RST,
--C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_IMPLEMENTATION_TYPE => 0, --my --Block RAM
-- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
--C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MEMORY_TYPE => 1, --my --Block RAM
-- C_MIF_FILE_NAME => C_MIF_FILE_NAME,
-- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
-- C_OVERFLOW_LOW => C_OVERFLOW_LOW,
--C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
--C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRELOAD_LATENCY => 0, --my
C_PRELOAD_REGS => 1, --my
--C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 10,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 9,
C_PROG_EMPTY_TYPE => 0,
--C_PROG_FULL_THRESH_ASSERT_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-150, 14), --my
--C_PROG_FULL_THRESH_NEGATE_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-160, 12), --my
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => uw_fifo_depth,
--C_RD_FREQ => C_RD_FREQ,
C_RD_FREQ => 1, --my
C_RD_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
-- C_USE_DOUT_RST => C_USE_DOUT_RST,
-- C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => 1, --my
-- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
-- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => 1, --my
-- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
-- C_VALID_LOW => C_VALID_LOW,
-- C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => uw_fifo_depth,
--C_WR_FREQ => C_WR_FREQ,
C_WR_FREQ => 1, --my
C_WR_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
-- C_MSGON_VAL => C_MSGON_VAL,
-- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
-- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => MTBF_STAGES,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
PORT MAP (
backup => GND,
backup_marker => GND,
clk => clk,
rst => GND,
srst => rst,
wr_clk => GND,
wr_rst => GND,
rd_clk => GND,
rd_rst => GND,
din => din,
wr_en => wr_en,
rd_en => rd_en,
sleep => sleep,
wr_rst_busy => wr_rst_busy_sig,
rd_rst_busy => rd_rst_busy_sig,
prog_empty_thresh => ZERO_pntr,
prog_empty_thresh_assert => ZERO_pntr,
prog_empty_thresh_negate => ZERO_pntr,
prog_full_thresh => ZERO_pntr,
prog_full_thresh_assert => ZERO_pntr,
prog_full_thresh_negate => ZERO_pntr,
int_clk => GND,
injectdbiterr => GND,
injectsbiterr => GND,
dout => dout,
full => full,
empty => empty,
almost_full => ALMOST_FULL,
wr_ack => WR_ACK,
overflow => OVERFLOW,
almost_empty => ALMOST_EMPTY,
valid => VALID,
underflow => UNDERFLOW,
data_count => sig_data_count,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
END ARCHITECTURE xilinx;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/ip_repo/axi_i2s_adi_1.0/hdl/adi_common/dma_fifo.vhd | 7 | 1646 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of dma_fifo is
constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1;
type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0);
signal data_fifo : MEM;
signal wr_addr : natural range 0 to FIFO_MAX;
signal rd_addr : natural range 0 to FIFO_MAX;
signal full, empty : Boolean;
begin
in_ack <= '0' when full else '1';
out_stb <= '0' when empty else '1';
out_data <= data_fifo(rd_addr);
fifo: process (clk) is
variable free_cnt : integer range 0 to FIFO_MAX + 1;
begin
if rising_edge(clk) then
if (resetn = '0') or (fifo_reset = '1') then
wr_addr <= 0;
rd_addr <= 0;
free_cnt := FIFO_MAX + 1;
empty <= True;
full <= False;
else
if in_stb = '1' and not full then
data_fifo(wr_addr) <= in_data;
wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt - 1;
end if;
if out_ack = '1' and not empty then
rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt + 1;
end if;
full <= free_cnt = 0;
empty <= free_cnt = FIFO_MAX + 1;
end if;
end if;
end process;
end;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/bd/block_design/ipshared/analogdeviceinc.com/axi_i2s_adi_v1_0/hdl/adi_common/dma_fifo.vhd | 7 | 1646 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of dma_fifo is
constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1;
type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0);
signal data_fifo : MEM;
signal wr_addr : natural range 0 to FIFO_MAX;
signal rd_addr : natural range 0 to FIFO_MAX;
signal full, empty : Boolean;
begin
in_ack <= '0' when full else '1';
out_stb <= '0' when empty else '1';
out_data <= data_fifo(rd_addr);
fifo: process (clk) is
variable free_cnt : integer range 0 to FIFO_MAX + 1;
begin
if rising_edge(clk) then
if (resetn = '0') or (fifo_reset = '1') then
wr_addr <= 0;
rd_addr <= 0;
free_cnt := FIFO_MAX + 1;
empty <= True;
full <= False;
else
if in_stb = '1' and not full then
data_fifo(wr_addr) <= in_data;
wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt - 1;
end if;
if out_ack = '1' and not empty then
rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt + 1;
end if;
full <= free_cnt = 0;
empty <= free_cnt = FIFO_MAX + 1;
end if;
end if;
end process;
end;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd | 18 | 6145 | -------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux8_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 8 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux8_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 8x Mux slice
);
port (
Sel : In std_logic_vector(2 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
I4 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 4 input
I5 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 5 input
I6 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 6 input
I7 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 7 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux8_1_x_n; --
Architecture implementation of axi_datamover_dre_mux8_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT8_1
--
-- Process Description:
-- This process implements an 8 to 1 mux.
--
-------------------------------------------------------------
SELECT8_1 : process (Sel, I0, I1, I2, I3,
I4, I5, I6, I7)
begin
case Sel is
when "000" =>
Y <= I0;
when "001" =>
Y <= I1;
when "010" =>
Y <= I2;
when "011" =>
Y <= I3;
when "100" =>
Y <= I4;
when "101" =>
Y <= I5;
when "110" =>
Y <= I6;
when "111" =>
Y <= I7;
when others =>
Y <= I0;
end case;
end process SELECT8_1;
end implementation; -- axi_datamover_dre_mux8_1_x_n
-------------------------------------------------------------------------------
-- End 8 to 1 xN Mux
-------------------------------------------------------------------------------
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd | 15 | 22231 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd | 5 | 89008 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_fsync_gen.vhd | 4 | 36967 | -------------------------------------------------------------------------------
-- axi_vdma_fsync_gen
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_fsync_gen.vhd
-- Description: This entity generates the frame sync for vdma operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_fsync_gen is
generic (
C_USE_FSYNC : integer range 0 to 1 := 0;
-- Specifies DMA oeration synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
ENABLE_FLUSH_ON_MM2S_FSYNC : integer range 0 to 1 := 0 ;
ENABLE_FLUSH_ON_S2MM_FSYNC : integer range 0 to 1 := 0 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 0 ;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_SOF_ENABLE : integer range 0 to 1 := 0
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Frame Count Enable Support --
valid_video_prmtrs : in std_logic ; --
valid_frame_sync_cmb : in std_logic ; --
frmcnt_ioc : in std_logic ; --
dmacr_frmcnt_enbl : in std_logic ; --
dmasr_frmcnt_status : in std_logic_vector(7 downto 0) ; --
mask_fsync_out : out std_logic ; --
--
-- VDMA status for free run (C_USE_FSYNC = 0) --
run_stop : in std_logic ; --
all_idle : in std_logic ; --
parameter_update : in std_logic ; --
--
-- Frame Sync Sources (C_USE_FSYNC = 1) --
fsync : in std_logic ; --
tuser_fsync : in std_logic ; --
othrchnl_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
-- Sync out for VDMA logic --
frame_sync : out std_logic ; --
--
-- Sync / Update out top level for Video IP --
frame_sync_out : out std_logic ; --
prmtr_update : out std_logic --
);
end axi_vdma_fsync_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_fsync_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant FRAME_COUNT_ONE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(1,8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Generate Free Run Mode (Internal Frame Sync)
-------------------------------------------------------------------------------
GEN_FREE_RUN_MODE : if C_USE_FSYNC = 0 generate
-- For internal fsync generation
signal all_idle_d1 : std_logic := '0';
signal all_idle_d2 : std_logic := '0';
signal all_idle_re : std_logic := '0';
-- For internal fsync and fsync out
signal frame_sync_aligned : std_logic := '0';
signal frame_sync_i : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Register all idle for use in creating rising edge pulse
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
-- On reset clear flag
if(prmry_resetn = '0')then
all_idle_d1 <= '0';
all_idle_d2 <= '0';
-- Otherwise pass idle state through to gen re pulse
else
all_idle_d1 <= all_idle;
all_idle_d2 <= all_idle_d1;
end if;
end if;
end process REG_IDLE;
all_idle_re <= all_idle_d1 and not all_idle_d2;
-- Register frame sync source to shift all processes started
-- by fsync 1 clock later in time. This allows initial FrameDelay
-- and resulting calculation to be registered before
-- being latched by frame_sync.
REG_FSYNC_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_i <= '0';
else
frame_sync_i <= all_idle_re and run_stop;
end if;
end if;
end process REG_FSYNC_PROCESS;
-- Pass out for internal use (secondary clock domain)
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FREE_RUN_MODE;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_MM2S_NO_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or C_SOF_ENABLE = 0)) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
---- end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_NO_SOF;
GEN_FSYNC_MODE_MM2S_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_NON_FLUSH : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- generate fsync from tuser
GEN_FSYNC_FOR_SOF : if C_SOF_ENABLE = 1 generate
begin
-- frame_sync_i <= tuser_fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync,
tuser_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when "10" => -- tuser fsync (used only by s2mm)
frame_sync_i <= tuser_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_FOR_SOF;
-- generate fsync from fsync
GEN_FSYNC_NO_SOF : if C_SOF_ENABLE = 0 generate
begin
-- Internal fsync on fe for vdma if running
--frame_sync_i <= fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_NON_FLUSH;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_SOF;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 4 | 15228 | -------------------------------------------------------------------------------
-- axi_sg_ftch_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 6/16/10 v4_03
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32
-- Master AXI Stream Data Width
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel Control --
desc_flush : in std_logic ; --
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
-- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active = '1')then
curdesc_tdata <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
curdesc_tvalid <= '1';
writing_lsb <= '1';
writing_msb <= '0';
-- On ready write MSB address
elsif(writing_lsb = '1' and ftch_tready = '1')then
curdesc_tdata <= msb_curdesc;
curdesc_tvalid <= '1';
writing_lsb <= '0';
writing_msb <= '1';
-- On MSB write and ready then clear all
elsif(writing_msb = '1' and ftch_tready = '1')then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
end if;
end if;
end process WRITE_CURDESC_PROCESS;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
TVALID_TDATA_MUX : process(writing_curdesc,
writing_nxtdesc,
ftch_active,
curdesc_tvalid,
curdesc_tdata,
m_axis_mm2s_tvalid,
m_axis_mm2s_tdata,
m_axis_mm2s_tlast)
begin
-- Select current descriptor to drive out (Queue or Channel Port)
if(writing_curdesc = '1')then
ftch_tvalid <= curdesc_tvalid;
ftch_tdata <= curdesc_tdata;
ftch_tlast <= '0';
-- Deassert tvalid when capturing next descriptor pointer
elsif(writing_nxtdesc = '1')then
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
-- Otherwise drive data from Datamover out (Queue or Channel Port)
elsif(ftch_active = '1')then
ftch_tvalid <= m_axis_mm2s_tvalid;
ftch_tdata <= m_axis_mm2s_tdata;
ftch_tlast <= m_axis_mm2s_tlast;
else
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
end if;
end process TVALID_TDATA_MUX;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
m_axis_ftch_tdata <= ftch_tdata;
m_axis_ftch_tlast <= ftch_tlast;
m_axis_ftch_tvalid <= ftch_tvalid;
ftch_tready <= m_axis_ftch_tready;
m_axis_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/bd/block_design/ip/block_design_proc_sys_reset_0_0/sim/block_design_proc_sys_reset_0_0.vhd | 8 | 5884 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY block_design_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END block_design_proc_sys_reset_0_0;
ARCHITECTURE block_design_proc_sys_reset_0_0_arch OF block_design_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END block_design_proc_sys_reset_0_0_arch;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_sof_gen.vhd | 6 | 10626 | -------------------------------------------------------------------------------
-- axi_vdma_sofeof_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sof_gen.vhd
-- Description: This entity manages SOF detection, EOF detection not used for
-- axi_vdma.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
entity axi_vdma_sof_gen is
port (
-----------------------------------------------------------------------
-- AXI System Signals
-----------------------------------------------------------------------
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- AXI Stream --
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
--
fsync : in std_logic ; -- CR622884
-- Detected SOF --
packet_sof : out std_logic --
);
end axi_vdma_sof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal packet_sof_i : std_logic := '0';
signal hold_sof : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
packet_sof <= packet_sof_i;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk = '1')then
if(scndry_resetn = '0')then
s_valid <= '0';
s_valid_d1 <= '0';
else
-- CR573962 qualify with tready
--s_valid <= axis_tvalid;
s_valid <= axis_tvalid and axis_tready;
s_valid_d1 <= s_valid;
end if;
end if;
end process REG_FOR_RE;
packet_sof_i <= s_valid and not s_valid_d1 and not hold_sof; -- CR622884
-- CR622884
-- Generate only 1 SOF (all that is needed) to prevent lockups
-- on CDC module with sof pulses being too close together.
SOF_HOLD_REG : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk = '1')then
if(scndry_resetn = '0' or fsync = '1')then
hold_sof <= '0';
elsif(packet_sof_i = '1')then
hold_sof <= '1';
end if;
end if;
end process SOF_HOLD_REG;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd | 5 | 87982 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd | 32 | 49938 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_vregister_64.vhd | 4 | 13365 | -------------------------------------------------------------------------------
-- axi_vdma_vregister_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vregister_64.vhd
--
-- Description: Top level for video register block. These registers provide
-- the video parameters to the DMA controllers.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister_64.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister_64.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vregister_64 is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 64 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Video Register Update control --
video_reg_update : in std_logic ; --
--
dmasr_halt : in std_logic ; --
-- Scatter Gather register Bank --
vsize_sg : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_sg : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_sg : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_sg : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_sg : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
-- Video Register Bank --
vsize_vid : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_vid : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_vid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_vid : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_vid : out STARTADDR_ARRAY_TYPE_64
(0 to C_NUM_FSTORES - 1) --
);
end axi_vdma_vregister_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vregister_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Vertical Size - Video Side
REG_VSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
vsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
vsize_vid <= vsize_sg;
end if;
end if;
end process REG_VSIZE;
-- Horizontal Size - Video Side
REG_HSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
hsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
hsize_vid <= hsize_sg;
end if;
end if;
end process REG_HSIZE;
-- Stride - Video Side
REG_STRIDE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
stride_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
stride_vid <= stride_sg;
end if;
end if;
end process REG_STRIDE;
-- Frame Delay - Video Side
REG_FRMDLY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
frmdly_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
frmdly_vid <= frmdly_sg;
end if;
end if;
end process REG_FRMDLY;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
-- Start Address Registers
REG_START_ADDR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
start_address_vid(i) <= (others => '0');
elsif(video_reg_update = '1')then
start_address_vid(i) <= start_address_sg(i);
end if;
end if;
end process REG_START_ADDR;
end generate GEN_START_ADDR_REG;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd | 18 | 30582 | -------------------------------------------------------------------------------
-- axi_datamover_stbs_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
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-- including negligence, or under any other theory of
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set;
architecture implementation of axi_datamover_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_128_STRB;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/digilent/axi_dispctrl_v1_0/hdl/axi_dispctrl_v1_0_S_AXI.vhd | 7 | 23770 | --------------------------------------------------------------------------------
--
-- File:
-- axi_dispctrl_v1_0_S_AXI.vhd
--
-- Module:
-- AXIS Display Controller AXI Slave Interface
--
-- Author:
-- Tinghui Wang (Steve)
--
-- Description:
-- AXI-Lite Register Interface for AXI Display Controller
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- Licence:
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity axi_dispctrl_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
FRAME_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dispctrl_v1_0_S_AXI;
architecture arch_imp of axi_dispctrl_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 13
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"0001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
-- slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '1');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= slv_reg5;
when b"0110" =>
reg_data_out <= slv_reg6;
when b"0111" =>
reg_data_out <= slv_reg7;
when b"1000" =>
reg_data_out <= slv_reg8;
when b"1001" =>
reg_data_out <= slv_reg9;
when b"1010" =>
reg_data_out <= slv_reg10;
when b"1011" =>
reg_data_out <= slv_reg11;
when b"1100" =>
reg_data_out <= slv_reg12;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
CTRL_REG <= slv_reg0;
FRAME_REG <= slv_reg2;
HPARAM1_REG <= slv_reg3;
HPARAM2_REG <= slv_reg4;
VPARAM1_REG <= slv_reg5;
VPARAM2_REG <= slv_reg6;
CLK_O_REG <= slv_reg7;
CLK_FB_REG <= slv_reg8;
CLK_FRAC_REG <= slv_reg9;
CLK_DIV_REG <= slv_reg10;
CLK_LOCK_REG <= slv_reg11;
CLK_FLTR_REG <= slv_reg12;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg1 <= (others => '0');
else
slv_reg1 <= STAT_REG;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_sm.vhd | 4 | 41496 | -------------------------------------------------------------------------------
-- axi_sg_updt_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- including negligence, or under any other theory of
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
ch2_updt_curdesc_wren : in std_logic ; --
ch2_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant UPDATE_CMD_TYPE : std_logic := '0';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
updt_ns <= IDLE;
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
when others =>
updt_ns <= IDLE;
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
ch1_updt_interr_set <= '1';
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
ch2_updt_interr_set <= '1';
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address <= (others => '0');
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address <= std_logic_vector(unsigned(ch1_updt_curdesc)
+ UPDATE_CH1_ADDR_OFFSET);
-- Channel 2 descriptor update pointer
elsif(ch2_updt_curdesc_wren = '1')then
update_address <= std_logic_vector(unsigned(ch2_updt_curdesc)
+ UPDATE_CH2_ADDR_OFFSET);
end if;
end if;
end process REG_UPDATE_ADDRESS;
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cmnd_wr <= '0';
updt_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= '1';
updt_cmnd_data <= UPDATE_CMD_RSVD
& UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
else
updt_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) & "000000";
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd | 18 | 16390 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_omit_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 0;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input --------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- MM2S Halt request input control-------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------------
-- Error discrete output ----------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-----------------------------------------------------------
-- Optional MM2S Command and Status clock and Reset -----------
-- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
---------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
----------------------------------------------------------------
-- Address Posting contols -------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
----------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_omit_wrap;
architecture implementation of axi_datamover_mm2s_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type
-- Just tie off output ports
mm2s_halt_cmplt <= mm2s_halt ;
mm2s_err <= '0' ;
mm2s_cmd_wready <= '0' ;
mm2s_sts_wvalid <= '0' ;
mm2s_sts_wdata <= (others => '0');
mm2s_sts_wstrb <= (others => '0');
mm2s_sts_wlast <= '0' ;
mm2s_arid <= (others => '0');
mm2s_araddr <= (others => '0');
mm2s_arlen <= (others => '0');
mm2s_arsize <= (others => '0');
mm2s_arburst <= (others => '0');
mm2s_arprot <= (others => '0');
mm2s_arcache <= (others => '0');
mm2s_aruser <= (others => '0');
mm2s_arvalid <= '0' ;
mm2s_rready <= '0' ;
mm2s_strm_wdata <= (others => '0');
mm2s_strm_wstrb <= (others => '0');
mm2s_strm_wlast <= '0' ;
mm2s_strm_wvalid <= '0' ;
mm2s_addr_req_posted <= '0' ;
mm2s_rd_xfer_cmplt <= '0' ;
-- Input ports are ignored
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_cmdsts_if.vhd | 4 | 14161 | -------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/bd/block_design/ipshared/analogdeviceinc.com/axi_i2s_adi_v1_0/hdl/i2s_controller.vhd | 7 | 8371 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.fifo_synchronizer;
use axi_i2s_adi_v1_00_a.i2s_clkgen;
use axi_i2s_adi_v1_00_a.i2s_tx;
use axi_i2s_adi_v1_00_a.i2s_rx;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
);
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
data_clk : in std_logic; -- Data clock should be less than clk / 4
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
tx_enable : in Boolean; -- Enable TX
tx_ack : out std_logic; -- Request new Slot Data
tx_stb : in std_logic; -- Request new Slot Data
tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
rx_enable : in Boolean; -- Enable RX
rx_ack : in std_logic;
rx_stb : out std_logic; -- Valid Slot Data
rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameter
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255
);
end i2s_controller;
architecture Behavioral of i2s_controller is
constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
signal enable : Boolean;
signal tick : std_logic;
signal tick_d1 : std_logic;
signal tick_d2 : std_logic;
signal BCLK_O_int : std_logic;
signal LRCLK_O_int : std_logic;
signal tx_bclk : std_logic;
signal tx_lrclk : std_logic;
signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
signal tx_tick : std_logic;
signal tx_channel_sync : std_logic;
signal tx_frame_sync : std_logic;
signal bclk_tick : std_logic;
signal rx_bclk : std_logic;
signal rx_lrclk : std_logic;
signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
signal rx_channel_sync : std_logic;
signal rx_frame_sync : std_logic;
signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
begin
enable <= rx_enable or tx_enable;
-- Generate tick signal in the DATA_CLK_I domain
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
tick <= '0';
else
tick <= not tick;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if resetn = '0' then
tick_d1 <= '0';
tick_d2 <= '0';
else
tick_d1 <= tick;
tick_d2 <= tick_d1;
end if;
end if;
end process;
tx_tick <= tick_d2 xor tick_d1;
tx_sync_fifo_in(0) <= tx_channel_sync;
tx_sync_fifo_in(1) <= tx_frame_sync;
tx_sync_fifo_in(2) <= tx_bclk;
tx_sync_fifo_in(3) <= tx_lrclk;
tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
BCLK_O <= (others => '1');
LRCLK_O <= (others => '1');
SDATA_O <= (others => '0');
else
if C_BCLK_POL = 0 then
BCLK_O <= (others => tx_sync_fifo_out(2));
else
BCLK_O <= (others => not tx_sync_fifo_out(2));
end if;
if C_LRCLK_POL = 0 then
LRCLK_O <= (others => tx_sync_fifo_out(3));
else
LRCLK_O <= (others => not tx_sync_fifo_out(3));
end if;
if C_HAS_TX = 1 then
SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4);
end if;
if C_HAS_RX = 1 then
rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I;
end if;
end if;
end if;
end process;
tx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_TX + 4
)
port map (
resetn => resetn,
in_clk => clk,
in_data => tx_sync_fifo_in,
in_tick => tx_tick,
out_clk => data_clk,
out_data => tx_sync_fifo_out
);
clkgen: entity i2s_clkgen
port map(
clk => clk,
resetn => resetn,
enable => enable,
tick => tx_tick,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
lrclk => tx_lrclk
);
tx_gen: if C_HAS_TX = 1 generate
tx: entity i2s_tx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_TX
)
port map (
clk => clk,
resetn => resetn,
enable => tx_enable,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
sdata => tx_sdata,
ack => tx_ack,
stb => tx_stb,
data => tx_data
);
end generate;
rx_gen: if C_HAS_RX = 1 generate
rx: entity i2s_rx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_RX
)
port map (
clk => clk,
resetn => resetn,
enable => rx_enable,
channel_sync => rx_channel_sync,
frame_sync => rx_frame_sync,
bclk => rx_bclk,
sdata => rx_sdata,
ack => rx_ack,
stb => rx_stb,
data => rx_data
);
rx_channel_sync <= rx_sync_fifo_out(0);
rx_frame_sync <= rx_sync_fifo_out(1);
rx_bclk <= rx_sync_fifo_out(2);
rx_lrclk <= rx_sync_fifo_out(3);
rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
rx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_RX + 4
)
port map (
resetn => resetn,
in_clk => data_clk,
in_data => rx_sync_fifo_in,
in_tick => '1',
out_clk => clk,
out_data => rx_sync_fifo_out
);
end generate;
end Behavioral;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_s2mm_axis_dwidth_converter.vhd | 4 | 22216 | -------------------------------------------------------------------------------
-- axi_vdma_s2mm_axis_dwidth_converter
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_s2mm_axis_dwidth_converter.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
entity axi_vdma_s2mm_axis_dwidth_converter is
generic ( C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED : integer := 32;
C_S_AXIS_S2MM_TDATA_WIDTH : integer := 32;
C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 : integer := 4;
C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 : integer := 4;
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0;
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
--C_AXIS_SIGNAL_SET : integer := 255;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
s2mm_fsize_less_err_internal_tvalid_gating : in std_logic ;
fsync_out : in std_logic ;
crnt_vsize_d2 : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ;
chnl_ready_dwidth : out std_logic;
strm_not_finished_dwidth : out std_logic;
strm_all_lines_rcvd_dwidth : out std_logic;
all_vount_rcvd_dwidth : out std_logic;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
);
end axi_vdma_s2mm_axis_dwidth_converter;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_s2mm_axis_dwidth_converter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE : std_logic_vector(255 downto 0)
:= (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Verilog module component declarations
-------------------------------------------------------------------------------
component axi_vdma_v6_2_8_axis_dwidth_converter_v1_0_axis_dwidth_converter is
generic ( C_S_AXIS_TDATA_WIDTH : integer := 32;
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_S_AXIS_TUSER_WIDTH : integer := 4;
C_M_AXIS_TUSER_WIDTH : integer := 4;
--C_AXIS_SIGNAL_SET : integer := 255;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal decr_vcount_dwidth : std_logic := '0';
signal S_AXIS_TREADY_OUT : std_logic := '0';
signal vsize_counter_dwidth : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_DWIDTH_NO_FLUSH_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 or C_S2MM_SOF_ENABLE = 0 generate
begin
chnl_ready_dwidth <= '0' ;
strm_not_finished_dwidth <= '0' ;
strm_all_lines_rcvd_dwidth <= '0' ;
all_vount_rcvd_dwidth <= '0' ;
S2MM_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_8_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_M_AXIS_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY ,
S_AXIS_TDATA => S_AXIS_TDATA(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
);
end generate GEN_DWIDTH_NO_FLUSH_SOF;
GEN_DWIDTH_FLUSH_SOF : if ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 1 generate
begin
S2MM_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_8_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_M_AXIS_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY_OUT ,
S_AXIS_TDATA => S_AXIS_TDATA(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
);
S_AXIS_TREADY <= S_AXIS_TREADY_OUT;
-- Decrement vertical count with each accept tlast
decr_vcount_dwidth <= '1' when S_AXIS_TLAST = '1'
and S_AXIS_TVALID = '1'
and S_AXIS_TREADY_OUT = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER_DWIDTH : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if((ARESETN = '0' and fsync_out = '0') or s2mm_fsize_less_err_internal_tvalid_gating = '1')then
vsize_counter_dwidth <= (others => '0');
chnl_ready_dwidth <= '0';
strm_not_finished_dwidth <= '0';
strm_all_lines_rcvd_dwidth <= '1';
all_vount_rcvd_dwidth <= '0';
elsif(fsync_out = '1')then
vsize_counter_dwidth <= crnt_vsize_d2;
chnl_ready_dwidth <= '1';
strm_not_finished_dwidth <= '1';
strm_all_lines_rcvd_dwidth <= '0';
all_vount_rcvd_dwidth <= '0';
elsif(decr_vcount_dwidth = '1' and vsize_counter_dwidth = VSIZE_ONE_VALUE)then
vsize_counter_dwidth <= (others => '0');
chnl_ready_dwidth <= '0';
strm_not_finished_dwidth <= '0';
strm_all_lines_rcvd_dwidth <= '1';
all_vount_rcvd_dwidth <= '1';
elsif(decr_vcount_dwidth = '1' and vsize_counter_dwidth /= VSIZE_ZERO_VALUE)then
vsize_counter_dwidth <= std_logic_vector(unsigned(vsize_counter_dwidth) - 1);
chnl_ready_dwidth <= '1';
strm_not_finished_dwidth <= '1';
strm_all_lines_rcvd_dwidth <= '0';
all_vount_rcvd_dwidth <= '0';
else
all_vount_rcvd_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER_DWIDTH;
end generate GEN_DWIDTH_FLUSH_SOF;
end implementation;
| gpl-3.0 |
rad-/65C816_SoftCore | 65816_Interface_System.ipdefs/Vivado_Custom_IP_Repo/AXIinterfacefor65816_1.0/hdl/AXIinterfacefor65816_v1_0.vhd | 2 | 4173 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIinterfacefor65816_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk : in std_logic;
tru_clk: in std_logic;
reset_65816_module : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end AXIinterfacefor65816_v1_0;
architecture arch_imp of AXIinterfacefor65816_v1_0 is
-- component declaration
component AXIinterfacefor65816_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
clk : in std_logic;
tru_clk: in std_logic;
reset_65816_module : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component AXIinterfacefor65816_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
AXIinterfacefor65816_v1_0_S00_AXI_inst : AXIinterfacefor65816_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
clk => clk,
tru_clk => tru_clk,
reset_65816_module => reset_65816_module,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_afifo_autord.vhd | 5 | 17241 | -------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
-- ored_ack_ff_reset <= fifo_read_enable or
-- AFIFO_Ainit_Rd_clk or
-- AFIFO_Clr_Rd_Data_Valid;
--
-- sig_rddata_valid <= hold_ff_q or
-- sig_wrfifo_rdack;
--
ored_ack_ff_reset <= '1'
when (fifo_read_enable = '1' or
AFIFO_Ainit_Rd_clk = '1' or
AFIFO_Clr_Rd_Data_Valid = '1')
Else '0';
sig_rddata_valid <= '1'
when (hold_ff_q = '1' or
sig_wrfifo_rdack = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_vaddrreg_mux.vhd | 4 | 10810 | -------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd | 5 | 59969 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_s2mm_dre;
use axi_datamover_v5_1_11.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_11.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ip/block_design_axi_vdma_0_0/sim/block_design_axi_vdma_0_0.vhd | 4 | 21746 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_afifo_autord.vhd | 4 | 21693 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_vdma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_vdma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_vdma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
signal AFIFO_Ainit_reg : std_logic ;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_SYNCHRONIZER_STAGE => MTBF_STAGES,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_EN_SAFETY_CKT => 1,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
---------------------------------------------------------------------------
-- AFIFO_Ainit synchronization in AFIFO_Rd_clk domain
---------------------------------------------------------------------------
---- AFIFO_Ainit_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => AFIFO_Wr_clk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => AFIFO_Rd_clk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => AFIFO_Ainit ,
---- scndry_out => AFIFO_Ainit_reg ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
----
AFIFO_Ainit_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => AFIFO_Wr_clk,
prmry_resetn => '1',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '1',
scndry_out => AFIFO_Ainit_reg,
scndry_vect_out => open
);
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_reg or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_reg_mux.vhd | 4 | 592541 | -------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/digilent/axi_dispctrl_v1_0/hdl/axi_dispctrl_v1_0.vhd | 7 | 18671 | --------------------------------------------------------------------------------
--
-- File:
-- axi_dispctrl_v1_0.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author:
-- Tinghui Wang (Steve)
-- Sam Bobrowicz
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dispctrl_v1_0 is
generic (
-- Users to add parameters here
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
-- Clock Signals
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
-- Display Signals
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
-- Debug Signals
DEBUG_O : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXIS_MM2S
s_axis_mm2s_aclk : in std_logic;
s_axis_mm2s_aresetn : in std_logic;
s_axis_mm2s_tready : out std_logic;
s_axis_mm2s_tdata : in std_logic_vector(C_S_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
s_axis_mm2s_tstrb : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
s_axis_mm2s_tlast : in std_logic;
s_axis_mm2s_tvalid : in std_logic
);
end axi_dispctrl_v1_0;
architecture arch_imp of axi_dispctrl_v1_0 is
-- component declaration
component axi_dispctrl_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
FRAME_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dispctrl_v1_0_S_AXI;
component mmcme2_drp
generic (
DIV_F : integer
);
port(
SEN : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
S1_CLKOUT0 : in std_logic_vector(35 downto 0);
S1_CLKFBOUT : in std_logic_vector(35 downto 0);
S1_DIVCLK : in std_logic_vector(13 downto 0);
S1_LOCK : in std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : in std_logic_vector(9 downto 0);
REF_CLK : in std_logic;
CLKFBOUT_I : in std_logic;
CLKFBOUT_O : out std_logic;
SRDY : out std_logic;
PXL_CLK : out std_logic;
LOCKED_O : out std_logic
);
end component;
component vdma_to_vga
generic (
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port(
LOCKED_I : in std_logic;
ENABLE_I : in std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
USR_WIDTH_I : in std_logic_vector(11 downto 0);
USR_HEIGHT_I : in std_logic_vector(11 downto 0);
USR_HPS_I : in std_logic_vector(11 downto 0);
USR_HPE_I : in std_logic_vector(11 downto 0);
USR_HPOL_I : in std_logic;
USR_HMAX_I : in std_logic_vector(11 downto 0);
USR_VPS_I : in std_logic_vector(11 downto 0);
USR_VPE_I : in std_logic_vector(11 downto 0);
USR_VPOL_I : in std_logic;
USR_VMAX_I : in std_logic_vector(11 downto 0);
RUNNING_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0)
);
end component;
signal CTRL_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal STAT_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal FRAME_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_O_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FB_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FRAC_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_DIV_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_LOCK_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FLTR_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal clk_state : CLK_STATE_TYPE := RESET;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal pxl_clk : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal vga_running : std_logic;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_dispctrl_v1_0_S_AXI_inst : axi_dispctrl_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
CTRL_REG => CTRL_REG,
STAT_REG => STAT_REG,
FRAME_REG => FRAME_REG,
HPARAM1_REG => HPARAM1_REG,
HPARAM2_REG => HPARAM2_REG,
VPARAM1_REG => VPARAM1_REG,
VPARAM2_REG => VPARAM2_REG,
CLK_O_REG => CLK_O_REG,
CLK_FB_REG => CLK_FB_REG,
CLK_FRAC_REG => CLK_FRAC_REG,
CLK_DIV_REG => CLK_DIV_REG,
CLK_LOCK_REG => CLK_LOCK_REG,
CLK_FLTR_REG => CLK_FLTR_REG,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
PXL_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED =>
-- This state ensures that the initial SRDY pulse
-- doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
generic map (
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => s_axis_mm2s_aclk,
S_AXIS_ARESETN => s_axis_mm2s_aresetn,
S_AXIS_TREADY => s_axis_mm2s_tready,
S_AXIS_TDATA => s_axis_mm2s_tdata,
S_AXIS_TSTRB => s_axis_mm2s_tstrb,
S_AXIS_TLAST => s_axis_mm2s_tlast,
S_AXIS_TVALID => s_axis_mm2s_tvalid,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DEBUG_O => DEBUG_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
STAT_REG(C_S_AXI_DATA_WIDTH-1 downto 1) <= (others => '0');
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| gpl-3.0 |
rad-/65C816_SoftCore | 65816_Interface_System.ipdefs/Vivado_Custom_IP_Repo/AXIinterfacefor65816_1.0/src/65C816.vhd | 3 | 66825 | ----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- This is a soft-core implementation of a 65C816. There will be initally 92
--of the 256 OpCodes useable. Please refer to DOC 1A for reference.
--
-- Dependencies:
-- For testing purposes there will be an AXI interface into this module.
--This should be provided with all the source HDL.
--If this module is being used in conjunction with another module and there is no need
--to access or view the inner workings of this module, no other dependancies occour.
--
-- Revision: V .1 -- 26 Jan 2016 STS
--
-- Revision 0.01 - File Created
-- Additional Comments:
-- The SNES CPU (65c816) uses little endian.
-- Revision 0.5 - Decode Table and Addressing Modes
-- The decode process and addressing mode assigning table
-- processes have been crated.
-- NOTE : Memory accesses will be passed from this
-- module to a C_FLAG program for reading/writing.
-- Revision 1.0 - 18 Feb 2016
-- Main Modules finished.
-- Revision 1.1 - 3 March 2016
-- Tests passed. Main is now implemented.
--
----------------------------------------------------------------------------------
-- ██████ ███████ ███████ ████████
-- ██░░░░██ ██░░░░░██ ░██░░░░██ ░██░░░░░
-- ██ ░░ ██ ░░██░██ ░██ ░██
--░██ ░██ ░██░███████ ░███████
--░██ ░██ ░██░██░░░██ ░██░░░░
--░░██ ██░░██ ██ ░██ ░░██ ░██
-- ░░██████ ░░███████ ░██ ░░██░████████
-- ░░░░░░ ░░░░░░░ ░░ ░░ ░░░░░░░░
-- ████ ████ ███████ ███████ ██ ██ ██ ████████
--░██░██ ██░██ ██░░░░░██ ░██░░░░██ ░██ ░██░██ ░██░░░░░
--░██░░██ ██ ░██ ██ ░░██░██ ░██░██ ░██░██ ░██
--░██ ░░███ ░██░██ ░██░██ ░██░██ ░██░██ ░███████
--░██ ░░█ ░██░██ ░██░██ ░██░██ ░██░██ ░██░░░░
--░██ ░ ░██░░██ ██ ░██ ██ ░██ ░██░██ ░██
--░██ ░██ ░░███████ ░███████ ░░███████ ░████████░████████
--░░ ░░ ░░░░░░░ ░░░░░░░ ░░░░░░░ ░░░░░░░░ ░░░░░░░░
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.SNES65816func.all;
entity Soft_65C816 is
Port ( clk :in STD_LOGIC; -- Main CLK for system
tru_clk :in std_logic; -- True clk for system
reset :in std_logic; -- Reset Signal
Addr_Bus :out STD_LOGIC_VECTOR (23 downto 0);-- Address Bus
D_BUS :in STD_LOGIC_VECTOR (31 downto 0);-- Data Bus IN
D_BUS_out :out STD_LOGIC_VECTOR (23 downto 0);-- Data Bus OUT
EMULATION_SELECT :out STD_LOGIC; -- Emulation Bit
RDY :out STD_LOGIC;
DATA_RDY :in STD_LOGIC;
REG_A :out std_logic_vector(15 downto 0);
REG_X :out std_logic_vector(15 downto 0);
REG_Y :out std_logic_vector(15 downto 0);
REG_SP :out std_logic_vector(15 downto 0);
REG_PC :out std_logic_vector(15 downto 0);
REG_Proc :out std_logic_vector(7 downto 0);
REG_DBR :out std_logic_vector(7 downto 0);
state_machine :out std_logic_vector(15 downto 0);
RW :out std_logic ; -- Read or write bit
VPB :out STD_LOGIC);
end Soft_65C816;
architecture Behavioral of Soft_65C816 is
--state machine states
type state_machine_states is (s0, s1, s2, s3, s4, s5 , sc, sa, sm, sp, sf, ss, sn, se, si, calculate_memory_pointer, s6);
signal state : state_machine_states;
--One hot sounter for state machine location/control
signal state_machine_onehot : std_logic_vector (15 downto 0);
--chunk pull vector
signal chunk_pull : std_logic_vector (31 downto 0);
--vector with info about the opcode
signal instruction_info : std_logic_vector (11 downto 0);
signal op_code : std_logic_vector (7 downto 0);
-- This will have the instructions arguments assigned to it.
signal instrction_args : std_logic_vector (31 downto 0);
-- This signal must be run with a 3.58 MHz CLK.
-- It is just a counter, but it must count at 3.58 MHz.
signal tru_cpu : std_logic_vector (3 downto 0);
-- This is essentially a latch enable,
-- it will count for as many cycles as the
-- operation would take on a true 65816
signal tru_clk_cntr : std_logic_vector(3 downto 0);
-- This will hold the instruction size, so the PC can correctly
-- be incrimented.
signal instruction_size : std_logic_vector (3 downto 0);
-- Memory pointer for pulling and pushing values
signal memory_pointer : std_logic_vector ( 23 downto 0);
-- This signal holds the values from the memory locations
-- requested.
signal requested_values : std_logic_vector (31 downto 0);
-- This will hold type info so the correct
-- execution state can be determined.
signal type_info : std_logic_vector (3 downto 0);
--
-- Process Control Signals
--
signal addressing_done, addressing_on, decode_on, decode_done, memory_calculate_done, memory_calculate_on : STD_LOGIC;
signal memory_done:std_logic;
signal math_done : std_logic;
signal pc_done : std_logic;
signal flag_done : std_logic;
signal store_back: std_logic;
signal push_to_stack : std_logic;
signal ready_up : std_logic;
signal stack_done: std_logic;
signal exchange_done: std_logic;
signal data_enable : std_logic;
--
-- REGISTER DECLARATIONS
--
-- Program Counter : PC
-- PC Bank Register : PBR
signal PC : std_logic_vector (23 downto 0);
alias PBR : std_logic_vector (7 downto 0) is PC (23 downto 16);
alias ProgramCntr : std_logic_vector (15 downto 0) is PC (15 downto 0);
-- Accumulator : A_REG
-- Direct Page Register: DP
-- Stack Pointer : SP
-- X & Y_REG Are Index Registers
signal A_REG, DP, StackPointer, X_REG, Y_REG : std_logic_vector ( 15 downto 0);
-- StackPointer is vaid from 00:0000 to 00:FFFF
-- Processor Status : P
-- Data Bank Register : DBR
signal P : std_logic_vector ( 7 downto 0);
signal DBR : std_logic_vector ( 7 downto 0);
alias N : STD_LOGIC is P(7); -- Negative Flag
alias V : STD_LOGIC is P(6); -- Overflow Flag
alias M : STD_LOGIC is P(5); -- Memory Select
alias X_FLAG : STD_LOGIC is P(4); -- Index Register
alias D_FLAG : STD_LOGIC is P(3); -- Decimal Mode
alias I : STD_LOGIC is P(2); -- IRQ Disable
alias Z : STD_LOGIC is P(1); -- Zero Result
alias C_FLAG : STD_LOGIC is P(0); -- Carry Flag / Emulation Mode
--
-- END REGISTER DECLARATIONS
--
--
-- Memory signals
--
signal effective_memory_pointer : std_logic_vector (23 downto 0);
signal write_back_location : std_logic_vector (23 downto 0);
signal write_back_value : std_logic_vector(15 downto 0);
signal write_back_bank : std_logic_vector(7 downto 0);
signal adr_type : integer range 0 to 25;
signal push_val : std_logic_vector(23 downto 0);
signal read_out : std_logic_vector(15 downto 0);
signal read_out_bank : std_logic_vector(7 downto 0);
signal address_out : std_logic_vector(23 downto 0);
--
--
-- Constant Signals
--
--
constant zeros : std_logic_vector (15 downto 1) := ( B"0000_0000_0000_000");
begin
state_machine <= state_machine_onehot;
D_BUS_out <= read_out_bank & read_out;
Addr_Bus<= address_out;
REG_A <= A_REG;
REG_X <= X_REG;
REG_Y <= Y_REG;
REG_SP <= StackPointer;
REG_PC <= ProgramCntr;
REG_Proc <= P;
REG_DBR <= DBR;
--
-- This is the true CPU clock for the processor
-- It runs at a multiple of 3.58 MHz and allows s6 to continue
-- to s1.
slow_clock:
process(tru_clk, clk, reset) is
begin
if reset = '1' then
tru_clk_cntr <= (others => '0');
ready_up <= '0';
elsif rising_edge(clk) then
if (tru_clk_cntr = tru_cpu) and (tru_clk = '1') then
ready_up <= '1' ;
end if;
end if;
if falling_edge(clk) then
if ready_up ='1' then
tru_clk_cntr <= (others => '0');
end if;
end if;
if rising_edge(tru_clk) then
tru_clk_cntr <= std_logic_vector(unsigned(tru_clk_cntr) + 1);
end if;
end process;
--
-- This is a 16 bit microprocessor with variable length instructions, the PC will
-- depend on the current instruction size.
-- Thus the PC will get
--
--
state_machine_process:
process (clk, reset) is
variable effective_memeory_pointer_temp : std_logic_vector (23 downto 0);
variable pointer_calculation_done : std_logic;
variable math_temp : std_logic_vector (16 downto 0);
variable stack_temp : std_logic_vector (16 downto 0);
variable xfr_temp : std_logic_vector (16 downto 0);
variable mem_temp : std_logic_vector (16 downto 0);
variable flag_temp : std_logic_vector (16 downto 0);
variable check_done : std_logic;
begin
if reset = '1' then
--TODO: RESET
state <= s0; -- reset to s0
chunk_pull <= (others => 'Z'); -- clear chunk pull
op_code <= (others => 'Z'); -- set opcode hi-Z
StackPointer <= X"0100"; -- Initialize Stack pointer
A_REG <= (others => '0');
X_REG <= (others => '0');
Y_REG <= (others => '0');
PC <= (others => '0');
DBR <= X"00";
DP <= X"0000";
N <= '0';
V <= '0';
M <= '1';
X_FLAG <= '1';
D_FLAG <= '0';
I <= '1';
Z <= '0';
C_FLAG <= '1'; -- This is the emulation flag on reset.
elsif rising_edge(clk) then
case state is
when s0 =>
if state_machine_onehot = "0000000000000001" then
state <= s1;
else
state <= s0;
end if;
state_machine_onehot <= "0000000000000001";
write_back_value <=X"0000";
write_back_bank <=X"00";
address_out <=PC;
check_done := '0';
rdy <= '1';
RW <= '0';
when s1 =>
if state_machine_onehot = "0000000000000010" then
state <= s2;
else
state <= s1;
end if;
data_enable <= '1';
if data_rdy ='0' and chunk_pull /= "ZZZZZZZZZZZZZZZZZ" then
chunk_pull <= D_BUS;
state_machine_onehot <= "0000000000000010";
rdy <= '0';
end if;
when s2 =>
if ((addressing_done = '1') and (decode_done = '1') and (state_machine_onehot = "0000000000000100")) then
state <= s3;
else
state <= s2;
end if;
addressing_on <= '1';
decode_on <= '1';
-- This should send the OPCode from chunkpull
-- to the opcode_info process, which inturn
-- will give us everything we need to know about how
-- to execute the instruction.
if data_enable = '1' then
op_code <= chunk_pull(31 downto 24);
state_machine_onehot <= "0000000000000100";
data_enable <= '0';
end if;
when s3 =>
if state_machine_onehot = "0000000000001000" then
state <= s4;
else
state <= s3;
end if;
data_enable <= '1';
addressing_on <= '0';
decode_on <= '0';
instruction_size <= instruction_info(11 downto 8);
tru_cpu <= instruction_info(7 downto 4);
type_info <= instruction_info( 3 downto 0);
state_machine_onehot <= "0000000000001000";
when s4 =>
if ((state_machine_onehot = "0000000000010000") and (memory_calculate_done = '1'))then
state <= calculate_memory_pointer;
else
state <= s4;
end if;
PC <= std_logic_vector(unsigned(PC) + unsigned(instruction_size));
state_machine_onehot <= "0000000000010000";
memory_calculate_on <= '1';
when calculate_memory_pointer =>
if pointer_calculation_done = '1' then
state <= s5;
end if;
memory_calculate_on <= '0';
case adr_type is
when 0 =>
if ((op_code = X"20") or (op_code = X"4c")) then
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
else
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
end if;
pointer_calculation_done := '1';
when 1 =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 2 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(X_REG));
pointer_calculation_done := '1';
when 3 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(Y_REG));
pointer_calculation_done := '1';
when 4 =>
effective_memory_pointer <= memory_pointer;
pointer_calculation_done := '1';
when 5 =>
effective_memory_pointer <= std_logic_vector(unsigned(memory_pointer) + unsigned(X_REG));
pointer_calculation_done := '1';
when 6 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
pointer_calculation_done := '1';
when 7 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0) + X_REG;
pointer_calculation_done := '1';
when 8 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 9 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 10=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + X_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 11=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + Y_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 12=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 13=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 14=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 15=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= X_REG + DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 16=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 17=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 18=>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 19=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 20=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 21=>
-- Stack Operations are handled in the stack state or where neccicary
effective_memory_pointer <= X"00" & StackPointer;
pointer_calculation_done := '1';
when 22=>
-- Block operations are not implemented yet
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 23 =>
requested_values <= X"00" & memory_pointer;
pointer_calculation_done := '1';
when others =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
end case;
when s5 =>
pointer_calculation_done := '0';
state_machine_onehot <= "0000000000100000";
if state_machine_onehot = "0000000000100000" then
-- Go to fan out based on type info,
-- if type info is not 0 - 8, then count it
-- as a NOP
--
if type_info = X"0" then
state <= sa;
elsif type_info = X"1" then
state <= sp;
elsif type_info = X"2" then
state <= sm;
elsif type_info = X"3" then
state <= sc;
elsif type_info = X"4" then
state <= sf;
elsif type_info = X"5" then
state <= ss;
elsif type_info = X"6" then
state <= sn;
elsif type_info = X"7" then
state <= se;
elsif type_info = X"8" then
state <= si;
-- if state can not be defined treat it as a NOP
else
state <= sn;
end if;
end if;
when sc =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sc;
end if;
state_machine_onehot <= "0000000001000000";
--
-- Arithmatic State Start
--
when sa =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sa;
end if;
-- ADC
if op_code = X"6D" or
op_code = X"7D" or
op_code = X"79" or
op_code = X"6F" or
op_code = X"7F" or
op_code = X"17" or
op_code = X"65" or
op_code = X"63" or
op_code = X"75" or
op_code = X"72" or
op_code = X"67" or
op_code = X"73" or
op_code = X"61" or
op_code = X"71" or
op_code = X"77" or
op_code = X"69" then
math_temp := ('0' & requested_values(15 downto 0)) + A_REG + ( zeros & C_FLAG);
if ((math_temp = "00000000000000000" ) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
elsif math_temp /= "ZZZZZZZZZZZZZZZZZ" then
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
-- AND
elsif op_code = X"2D" or
op_code = X"3E" or
op_code = X"39" or
op_code = X"2F" or
op_code = X"3F" or
op_code = X"25" or
op_code = X"23" or
op_code = X"36" or
op_code = X"32" or
op_code = X"27" or
op_code = X"33" or
op_code = X"91" or
op_code = X"31" or
op_code = X"37" or
op_code = X"29" then
math_temp := '0' & ( A_REG and requested_values(15 downto 0));
if math_temp = "00000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0 );
math_done <= '1';
-- ASL
elsif
op_code = X"0E" or
op_code = X"1E" or
op_code = X"06" or
op_code = X"16" then
math_temp := requested_values(15 downto 0) & '0';
C_FLAG <= requested_values(15);
store_back <= '1';
if math_temp(15 downto 0) = "0000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
elsif op_code = X"0A" then
math_temp := A_REG( 15 downto 0) & '0';
C_FLAG <= A_REG(15);
if math_temp(15 downto 0) = ("0000000000000000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
-- CMP
elsif
op_code = X"CD" or
op_code = X"DD" or
op_code = X"D9" or
op_code = X"CF" or
op_code = X"DF" or
op_code = X"C5" or
op_code = X"C3" or
op_code = X"D5" or
op_code = X"D2" or
op_code = X"C7" or
op_code = X"D3" or
op_code = X"C1" or
op_code = X"D1" or
op_code = X"D7" or
op_code = X"C9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0));
if (A_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPX
elsif
op_code = X"EC" or
op_code = X"E4" or
op_code = X"E0" then
math_temp := X_REG - ('0' & requested_values(15 downto 0));
if (X_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPY
elsif
op_code = X"CC" or
op_code = X"C4" or
op_code = X"C0" then
math_temp := Y_REG - ('0' & requested_values(15 downto 0));
if (Y_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- DEX
elsif
op_code = X"CA" then
math_temp := '0' & X_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- DEY
elsif
op_code = X"88" then
math_temp := '0' & Y_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- EOR
elsif
op_code = X"4D" or
op_code = X"5D" or
op_code = X"59" or
op_code = X"4F" or
op_code = X"5F" or
op_code = X"5D" or
op_code = X"45" or
op_code = X"43" or
op_code = X"55" or
op_code = X"52" or
op_code = X"47" or
op_code = X"53" or
op_code = X"41" or
op_code = X"51" or
op_code = X"57" or
op_code = X"49" then
math_temp := '0' & (requested_values(15 downto 0) xor A_REG);
if math_temp = ('0'&(X"0000")) then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- INX
elsif
op_code = X"E8" then
math_temp := '0' & X_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- INY
elsif
op_code = X"C8" then
math_temp := '0' & Y_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- LSR
elsif
op_code = X"4A" then
math_temp := '0' & A_REG;
N <= '0';
C_FLAG <= A_REG(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"4E" or
op_code = X"5E" or
op_code = X"46" or
op_code = X"56" then
math_temp := '0' & requested_values(15 downto 0);
store_back <= '1';
N <= '0';
C_FLAG <= requested_values(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
math_done <= '1';
-- ORA
elsif
op_code = X"0D" or
op_code = X"1D" or
op_code = X"19" or
op_code = X"0F" or
op_code = X"1F" or
op_code = X"05" or
op_code = X"03" or
op_code = X"15" or
op_code = X"12" or
op_code = X"07" or
op_code = X"13" or
op_code = X"01" or
op_code = X"11" or
op_code = X"17" or
op_code = X"09" then
math_temp := '0' & (requested_values(15 downto 0) or A_REG);
A_REG <= math_temp(15 downto 0);
if math_temp = ('0' & X"0000") then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- ROL
elsif
op_code = X"2A" then
math_temp := A_REG & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
if math_temp(16 downto 1) = X"0000" then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (15 downto 0);
math_done <= '1';
elsif
op_code = X"2E" or
op_code = X"3E" or
op_code = X"26" or
op_code = X"36" then
math_temp := requested_values(15 downto 0) & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- ROR
elsif
op_code = X"6A" then
math_temp := C_FLAG & A_REG;
C_FLAG <= A_REG (0);
N <= math_temp(15);
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"6E" or
op_code = X"7E" or
op_code = X"66" or
op_code = X"76" then
math_temp := C_FLAG & requested_values(15 downto 0) ;
C_FLAG <= requested_values (0);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- SBC
elsif
op_code = X"ED" or
op_code = X"FD" or
op_code = X"F9" or
op_code = X"FF" or
op_code = X"E5" or
op_code = X"E3" or
op_code = X"F5" or
op_code = X"F2" or
op_code = X"E7" or
op_code = X"F3" or
op_code = X"E1" or
op_code = X"F1" or
op_code = X"F7" or
op_code = X"E9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0)) - ( ('0' & zeros) & C_FLAG);
if ((math_temp = ('0' & X"0000")) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
else
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
if (store_back = '1') and (math_done = '1') then
write_back_value <= math_temp (15 downto 0);
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif math_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END OF ARITHMATIC STATE
--
--
-- START MEMORY MANIPULATION STATE
--
when sm =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sm;
end if;
-- DEC
if op_code = X"CE" or
op_code= X"DE" or
op_code= X"C6" or
op_code= X"D6" then
mem_temp := '0' & requested_values(15 downto 0) - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
elsif op_code = X"3A" then
mem_temp := '0' & A_REG - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- INC
elsif op_code= X"1A" then
mem_temp := '0' & A_REG + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"EE" or
op_code= X"FE" or
op_code= X"E6" or
op_code= X"F6" then
mem_temp := '0' & requested_values(15 downto 0) + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
-- LDA
elsif op_code = X"AD" or
op_code= X"BD" or
op_code = X"B9" or
op_code = X"AF" or
op_code = X"BF" or
op_code = X"A5" or
op_code = X"A3" or
op_code = X"B5" or
op_code = X"B2" or
op_code = X"A7" or
op_code = X"B3" or
op_code = X"A1" or
op_code = X"B1" or
op_code = X"B7" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"A9" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDX
elsif op_code = X"AE" or
op_code= X"BE" or
op_code= X"A6" or
op_code= X"B6" or
op_code= X"A2" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
X_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDY
elsif op_code = X"AC" or
op_code= X"BC" or
op_code= X"A4" or
op_code= X"B4" or
op_code= X"A0" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
Y_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- STA
elsif op_code = X"8D" or
op_code= X"9D" or
op_code= X"8F" or
op_code= X"9F" or
op_code= X"85" or
op_code= X"83" or
op_code= X"95" or
op_code= X"92" or
op_code= X"87" or
op_code= X"93" or
op_code= X"81" or
op_code= X"91" or
op_code= X"97" then
mem_temp := '0' & A_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STX
elsif op_code = X"8E" or
op_code= X"86" or
op_code= X"96" then
mem_temp := '0' & X_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STY
elsif op_code = X"8C" or
op_code= X"84" or
op_code= X"94" then
mem_temp :='0' & Y_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
end if;
if (memory_done = '1') and (store_back = '1') then
state_machine_onehot <= "0000000001000000";
write_back_location <= effective_memory_pointer;
elsif (memory_done = '1') and (store_back = '0') then
state_machine_onehot <= "0000000001000000";
store_back <= '0';
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END MEMORY MANIPULATION STATE
--
--
-- START PC MANIPULATION STATE
--
when sp =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sp;
end if;
-- BCC
if op_code = X"90" then
if C_FLAG = '0' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BEQ
elsif op_code = X"F0" then
if Z = '1' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BMI
elsif op_code = X"30" then
if N = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BNE
elsif op_code = X"D0" then
if Z = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BPL
elsif op_code = X"10" then
if N = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVC
elsif op_code = X"50" then
if V = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVS
elsif op_code = X"70" then
if V = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- JMP
elsif
op_code = X"4C" then
PC <= effective_memory_pointer;
pc_done <= '1';
elsif
op_code = X"5C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
elsif
op_code = X"6C" or
op_code = X"7C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
-- JSR
elsif op_code = X"20" or
op_code = X"FC" then
write_back_value <= ProgramCntr;
write_back_bank <= PBR;
PC <= requested_values(23 downto 0);
push_to_stack <= '1';
pc_done <= '1';
-- RTS
elsif op_code = X"60" then
ProgramCntr <= requested_values(15 downto 0);
StackPointer <= StackPointer - 2;
pc_done <= '1';
end if;
if (pc_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END PC MANIPULATION STATE
--
--
-- START FLAGC MANIPULATION STATE
--
when sf =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sf;
end if;
-- BIT
if op_code = X"2C" or
op_code = X"3C" or
op_code = X"24" or
op_code = X"34" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= flag_temp(15);
V <= flag_temp(14);
else
V <= flag_temp(14);
N <= flag_temp(15);
Z <= '0';
end if;
flag_done <= '1';
elsif op_code = X"89" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
flag_done <= '1';
-- CLC
elsif op_code = X"18" then
C_FLAG <= '0';
flag_done <= '1';
-- CLD
elsif op_code = X"D8" then
D_FLAG <= '0';
flag_done <= '1';
-- CLI
elsif op_code = X"58" then
I <= '0';
flag_done <= '1';
-- CLV
elsif op_code = X"B8" then
V <= '0';
flag_done <= '1';
-- SEC
elsif op_code = X"38" then
C_FLAG <= '1';
flag_done <= '1';
-- SED
elsif op_code = X"F8" then
D_FLAG <= '0';
flag_done <= '1';
-- SEI
elsif op_code = X"78" then
I <= '1';
flag_done <= '1';
end if;
if flag_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END FLAG MANIPULATION STATE
--
--
-- STACK MANIPULATION STATE
--
when ss =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= ss;
end if;
-- PHA
if op_code = X"48" then
StackPointer <= StackPointer + 2;
push_to_stack <= '1';
write_back_value <= A_REG;
stack_done <= '1';
-- PHP
elsif op_code = X"08" then
StackPointer <= StackPointer + 1;
push_to_stack <= '1';
write_back_value <= X"00" & P;
stack_done <= '1';
-- PLA
elsif op_code = X"68" then
StackPointer <= StackPointer - 2;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
A_REG <= stack_temp(15 downto 0);
stack_done <= '1';
-- PLP
elsif op_code = X"28" then
StackPointer <= StackPointer - 1;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
P <= stack_temp(7 downto 0);
stack_done <= '1';
end if;
if (stack_done = '1') and (store_back = '1') then
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif (stack_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END STACK MANIPULATION STATE
--
--
-- START NOP STATE
--
when sn =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sn;
end if;
state_machine_onehot <= "0000000001000000";
--
-- END NOP STATE
--
--
-- START EXCHANGE STATE
--
when se =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= se;
end if;
-- TAX
if op_code = X"AA" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TAY
elsif op_code = X"AB" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
Y_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TYA
elsif op_code = X"98" then
xfr_temp := '0' & Y_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TSX
elsif op_code = X"BA" then
xfr_temp := '0' & StackPointer;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXA
elsif
op_code = X"8A" then
xfr_temp := '0' & X_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXS
elsif
op_code = X"9A" then
xfr_temp := '0' & X_REG;
StackPointer <= xfr_temp(15 downto 0);
exchange_done <= '1';
end if;
if (exchange_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END EXCHANGE STATE
--
--
-- START INTERUPT STATE
--
when si =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= si;
end if;
-- RTI
if op_code = X"40" then
ProgramCntr <= requested_values(23 downto 8);
P <= requested_values(7 downto 0);
end if;
state_machine_onehot <= "0000000001000000";
--
-- END INTRRUPT STATE
--
when s6 =>
if (state_machine_onehot = "0000000010000000") and (ready_up = '1') then
state <= s0;
else
state <= state;
end if;
math_done <= '0';
memory_done <= '0';
pc_done <= '0';
flag_done <= '0';
stack_done <= '0';
exchange_done <= '0';
if (store_back = '1') then
READ_OUT <= write_back_value;
ADDRESS_OUT <= write_back_location;
store_back <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
elsif (push_to_stack = '1') then
read_out <= write_back_value;
read_out_bank <= write_back_bank;
address_out <= X"00" & StackPointer;
push_to_stack <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
else
check_done := '1';
state_machine_onehot <= "0000000010000000";
end if;
when others =>
state_machine_onehot <= "0000000000000010";
end case;
end if;
end process;
--
-- This process will look at the opcode
-- and determine the addressing mode of
-- the specific instruction being requested
-- and then pass it onto the adr_type vector.
--
Addressing_Mode:
process (addressing_on) is
begin
addressing_done <= '0';
if (addressing_on = '1') then
-- Refer to 65000 Programmers Manual for explanation
-- of addressing modes.
--
-- Symbol Addressing Mode Symbol Addressing Mode
-- 0 -> a absolute
-- 1 -> A_REG accumulator
-- 2 -> a,x absolute indexed with X
-- 3 -> a,y absolute indexed with Y_REG
-- 4 -> al absolute long
-- 5 -> al,x absolute long indexed
-- 6 -> (a) absolute indirect
-- 7 -> (a,x) absolute indexed indirect
-- 8 -> d direct
-- 9 -> d,s stack relative
-- 10 -> d,x direct indexed with x
-- 11 -> d,y direct indexed with y
-- 12 -> (d) direct indirect
-- 13 -> [d] direct indirect long
-- 14 -> (d,s),y stack relative indirect indexed
-- 15 -> (d,x) direct indexed indirect
-- 16 -> (d),y direct indirect indexed
-- 17 -> [d].y direct indirect long indexed
-- 18 -> i implied
-- 19 -> r program counter relative
-- 20 -> rl program counter relative long
-- 21 -> s stack
-- 22 -> xyc block move
-- 23 -> # immediate
--
--
case op_code is
when X"6d" | X"2d" | X"0e" | X"2c" | X"cd" | X"ec" | X"cc" | X"ce" | X"4d" | X"ee" | X"4c" | X"20" | X"ad" | X"ae" | X"ac" | X"4e" | X"0d" | X"2e" | X"6e" | X"ed" | X"8d" | X"8e" | X"8c" | X"9c" | X"1c" | X"0c" =>
adr_type <= 0;
when X"0a" | X"3A" | X"1a" | X"4a" | X"2a" | X"6a" | X"3b" | X"ba" | X"8a" | X"9a" | X"9b" | X"98" | X"bb" | X"cb" | X"42" | X"eb" | X"fb" =>
adr_type <= 1;
when X"7d" | X"3e" | X"1e" | X"3c" | X"dd" | X"de" | X"5d" | X"fe" | X"bd" | X"bc" | X"5e" | X"1d" | X"7e" | X"fd" | X"9d" | X"9e" =>
adr_type <= 2;
when X"6f" | X"2f" | X"cf" | X"4f" | X"5c" | X"22" | X"af" | X"0f" | X"8f" =>
adr_type <= 3;
when X"79" | X"39" | X"d9" | X"59" | X"b9" | X"be" | X"19" | X"f9" =>
adr_type <= 4;
when X"7f" | X"3f" | X"df" | X"5f" | X"bf" | X"1f" | X"ff" | X"9f" =>
adr_type <= 5;
when X"dc" | X"6c" =>
adr_type <= 6;
when X"7c" | X"fc" =>
adr_type <= 7;
when X"65" | X"25" | X"06" | X"24" | X"c5" | X"e4" | X"c4" | X"c6" | X"45" | X"e6" | X"a5" | X"a6" | X"a4" | X"46" | X"05" | X"26" | X"66" | X"e5" | X"85" | X"86" | X"84" | X"64" | X"14" | X"04" =>
adr_type <= 8;
when X"63" | X"23" | X"c3" | X"43" | X"a3" | X"03" | X"e3" | X"83" =>
adr_type <= 9;
when X"75" | X"36" | X"16" | X"34" | X"d5" | X"d6" | X"55" | X"f6" | X"b5" | X"b4" | X"56" | X"15" | X"76" | X"f5" | X"95" | X"94" | X"74" =>
adr_type <= 10;
when X"b6" | X"96" =>
adr_type <= 11;
when X"72" | X"32" | X"d2" | X"52" | X"b2" | X"12" | X"f2" | X"92" =>
adr_type <= 12;
when X"67" | X"27" | X"c7" | X"47" | X"a7" | X"07" | X"e7" | X"87" =>
adr_type <= 13;
when X"73" | X"33" | X"d3" | X"53" | X"b3" | X"13" | X"f3" | X"93" =>
adr_type <= 14;
when X"61" | X"c1" | X"41" | X"a1" | X"01" | X"e1" | X"81" =>
adr_type <= 15;
when X"71" | X"31" | X"d1" | X"51" | X"b1" | X"11" | X"f1" | X"91" =>
adr_type <= 16;
when X"77" | X"37" | X"d7" | X"57" | X"b7" | X"17" | X"f7" | X"97" =>
adr_type <= 17;
when X"18" | X"d8" | X"58" | X"b8" | X"ca" | X"88" | X"e8" | X"c8" | X"ea" | X"38" | X"f8" | X"78" | X"db" | X"aa" | X"5b" | X"1b" | X"7b" =>
adr_type <= 18;
when X"b0" | X"f0" | X"90" | X"d0" | X"10" | X"80" | X"50" | X"70" =>
adr_type <= 19;
when X"82" =>
adr_type <= 20;
when X"00" | X"02" | X"f4" | X"d4" | X"62" | X"48" | X"8b" | X"0b" | X"4b" | X"08" | X"da" | X"5a" | X"68" | X"ab" | X"2b" | X"28" | X"fa" | X"7a" | X"40" | X"6b" | X"60" =>
adr_type <= 21;
when X"54" | X"44" =>
adr_type <= 22;
when X"69" | X"29" | X"89" | X"c9" | X"e0" | X"c0" | X"49" | X"a9" | X"a2" | X"a0" | X"09" | X"c2" | X"e9" | X"e2" =>
adr_type <= 23;
when others =>
adr_type <= 0;
end case;
addressing_done <= '1';
end if;
end process;
--
-- This process reverses the byte order
-- of instruction arguments so that
-- a memory pointer or argument can
-- be precisely used
--
memory_pointer_calculation:
process (memory_calculate_on) is
begin
memory_calculate_done <= '0';
if memory_calculate_on = '1' then
case instruction_size is
when X"2" =>
memory_pointer <= X"0000" & chunk_pull (23 downto 16);
when X"3" =>
memory_pointer <= X"00" & chunk_pull (23 downto 16) & chunk_pull(15 downto 8);
when X"4" =>
memory_pointer <= chunk_pull (23 downto 16) & chunk_pull(15 downto 8) & chunk_pull (7 downto 0);
when others =>
memory_pointer <= (others => '0');
end case;
memory_calculate_done <= '1';
end if;
end process;
--
-- This process will decode the OPcode byte.
-- It will then assign instruction_info all relevent data.
--
opcode_info:
process (decode_on) is
begin
decode_done <= '0';
if reset = '1' then
instruction_info <= (others => '0');-- clear instruction info
elsif (decode_on = '1') then
--
--
-- intstruction_info syntax is
-- bytes + cycles + type
--
-- Flags (on reset) :
-- N V M X D I Z C_FLAG/E
-- P = * * 1 1 0 1 * */1
-- * = Not Initialized
-- STP and WAI instructions are cleared.
-- Type Table:
-- 0 -> Arithmatic
-- 1 -> PC
-- 2 -> Memory
-- 3 -> Coprocessor
-- 4 -> Flag
-- 5 -> Stack
-- 6 -> NOP (and non used)
-- 7 -> Exchange
-- 8 -> Interrupt
--
--
--
--
case op_code is
--
-- BRK (break)
-- pc+2 onto stack, processor status onto stack
-- Also set I flag = 1
--
-- !!!!!!!!!!!!! TODO: Implemented as a NOP for now due to issues with interrupts
-- !!!!!!!!!!!!!!!!!!!!!!!!!!! X"270" is now X"126"
when X"00" =>
instruction_info <= X"126";
-- ADC
-- The following are Add memory to accumulator with cary
-- A_REG + M + C_FLAG -> A_REG, C_FLAG
--
when X"69" =>
instruction_info <= X"220";
when X"65" =>
instruction_info <= X"230";
when X"75" =>
instruction_info <= X"240";
when X"6D" =>
instruction_info <= X"340";
when X"7D" =>
instruction_info <= X"340";
when X"79" =>
instruction_info <= X"340";
when X"61" =>
instruction_info <= X"260";
when X"71" =>
instruction_info <= X"250";
-- AND
-- The follwing are logical AND's with accumulator
-- A_REG and M -> A_REG
--
--
when X"29" =>
instruction_info <= X"220";
when X"25" =>
instruction_info <= X"230";
when X"35" =>
instruction_info <= X"240";
when X"2D" =>
instruction_info <= X"340";
when X"3D" =>
instruction_info <= X"340";
when X"39" =>
instruction_info <= X"340";
when X"21" =>
instruction_info <= X"260";
when X"31" =>
instruction_info <= X"250";
--
-- The following are ASL
-- left shift by one
-- memory or accumulator
--
when X"0A" =>
instruction_info <= X"120";
when X"06" =>
instruction_info <= X"250";
when X"16" =>
instruction_info <= X"260";
when X"0E" =>
instruction_info <= X"360";
when X"1E" =>
instruction_info <= X"370";
-- BCC
-- Branch on carry clear
-- when carry flag = 0, branch
-- * + 1 cycle if branch happens
when X"90" =>
instruction_info <= X"221";
-- BEQ
-- branch on zero flag set
-- * + 1 cycle if branch happens
when X"F0" =>
instruction_info <= X"221";
-- BIT
-- Accumulator AND'd with memory,
-- bit 7 of memory goes to Negative flag
-- bit 6 of memoyr goes to overflow flag
-- If A_REG and M = 0 then Z = 1 , else 0
when X"24" =>
instruction_info <= X"234";
when X"2C" =>
instruction_info <= X"344";
-- BMI
-- Branch On Negative Flag Set
-- * + 1 Cycle If Can Branch
when X"30" =>
instruction_info <= X"221";
-- BNE
-- Branch on zero flag not set
-- * + 1 cycle if can do
--
when X"D0" =>
instruction_info <= X"221";
-- BPL
-- Brnach when N flag not set.
-- * + 1 cycle if can do
--
when X"10" =>
instruction_info <= X"221";
-- BVC
-- Branch on V flag = 0
-- * +1 cycle if can do
when X"50" =>
instruction_info <= X"221";
-- BVS
-- Branch when V flag set
-- * + 1 cycle if can do
when X"70" =>
instruction_info <= X"221";
-- CLC
-- Clear the carry flag
--
when X"18" =>
instruction_info <= X"124";
-- CLD
-- Clear the decimal flag
--
when X"D8" =>
instruction_info <= X"124";
-- CLI
-- Clear interupt bit
--
when X"58" =>
instruction_info <= X"124";
-- CLV
-- Clear the overflow flag
--
when X"B8" =>
instruction_info <= X"124";
-- CMP
-- Compar memory and accumulator
-- Set N, Z, or C_FLAG flag accordingly
-- A_REG - M
--
when X"c9" =>
instruction_info <= X"220";
when X"c5" =>
instruction_info <= X"230";
when X"D5" =>
instruction_info <= X"240";
when X"DD" =>
instruction_info <= X"340";
when X"d9" =>
instruction_info <= X"340";
when X"c1" =>
instruction_info <= X"260";
when X"d1" =>
instruction_info <= X"250";
-- CPX
-- Compary memory and X reg
-- X - M and set N, Z, C_FLAG flags as needed
--
when X"E0" =>
instruction_info <= X"220";
when X"E4" =>
instruction_info <= X"230";
when X"EC" =>
instruction_info <= X"340";
-- CPY
-- Compary memory and Y_REG reg
-- Y_REG - M
-- Set N, Z, and C_FLAG flags as needed.
--
when X"C0" =>
instruction_info <= X"220";
when X"C4" =>
instruction_info <= X"230";
when X"cc" =>
instruction_info <= X"340";
-- DEC
-- Decrimeent memory by 1
-- M - 1 -> M
-- Use N & Z flags
when X"C6" =>
instruction_info <= X"252";
when X"D6" =>
instruction_info <= X"262";
when X"ce" =>
instruction_info <= X"362";
when X"de" =>
instruction_info <= X"372";
-- DEX
-- Decriment X reg by 1
-- X - 1 -> X
-- use N & Z flags
when X"CA" =>
instruction_info <= X"120";
-- DEY
-- Decriment Y_REG reg by 1
-- Y_REG - 1 -> Y_REG
-- N & Z flags
--
when X"88" =>
instruction_info <= X"120";
-- EOR
-- Acc XOR Mem -> Acc
-- N and Z flags
--
when X"49" =>
instruction_info <= X"220";
when X"45" =>
instruction_info <= X"230";
when X"55" =>
instruction_info <= X"240";
when X"4d" =>
instruction_info <= X"340";
when X"5d" =>
instruction_info <= X"340";
when X"59" =>
instruction_info <= X"340";
when X"41" =>
instruction_info <= X"260";
when X"51" =>
instruction_info <= X"250";
-- INC
-- Incriment memory by one
-- M + 1 -> M
-- N & Z flags
--
when X"E6" =>
instruction_info <= X"252";
when X"F6" =>
instruction_info <= X"262";
when X"ee" =>
instruction_info <= X"362";
when X"fe" =>
instruction_info <= X"372";
-- INX
-- Incriment X by one
-- X + 1 -> X
-- N & Z flags
--
when X"e8" =>
instruction_info <= X"120";
-- INY
-- Incriment Y_REG by one
-- Y_REG + 1 -> Y_REG
-- N & Z flags
--
when X"c8" =>
instruction_info <= X"120";
--
--
-- JMP
-- JUMP INSTRUCTIONS
--=======================================================================
-- JMP
-- Jump to location
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--JMP absolute
--take contents of memory location
--1 byte from opcode and store into
--PC LOW, then take the very next byte
--and store into PC HIGH
-- REVERSE BYTE ORDER AND MAKE NEW PC
when X"4c" =>
instruction_info <= X"331";
--JMP indirect
-- starts out the same as above, but
-- instead of getting the opcode at the new PC,
-- a new PC is again fetched in the same way.
-- making this a jump to a jump.
when X"6c" =>
instruction_info <= X"351";
--=======================================================================
--
--
--
--
-- JSR
-- Jump to subroutine
-- PC + 2 -> stack
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--
when X"20" =>
instruction_info <= X"361";
-- LDA
-- Load accumulator with memory
-- M -> A_REG
-- N & Z flags
when X"a9" =>
instruction_info <= X"222";
when X"a5" =>
instruction_info <= X"232";
when X"b5" =>
instruction_info <= X"242";
when X"ad" =>
instruction_info <= X"342";
when X"bd" =>
instruction_info <= X"342";
when X"b9" =>
instruction_info <= X"342";
when X"a1" =>
instruction_info <= X"262";
when X"b1" =>
instruction_info <= X"252";
-- LDX
-- Load X with memory
-- M -> X
-- N & Z flags
--
when X"a2" =>
instruction_info <= X"222";
when X"a6" =>
instruction_info <= X"232";
when X"b6" =>
instruction_info <= X"242";
when X"ae" =>
instruction_info <= X"342";
when X"be" =>
instruction_info <= X"342";
-- LDY
-- Load Y_REG with memory
-- M -> Y_REG
-- N & Z Flags
--
when X"a0" =>
instruction_info <= X"222";
when X"a4" =>
instruction_info <= X"232";
when X"b4" =>
instruction_info <= X"242";
when X"ac" =>
instruction_info <= X"342";
when X"bc" =>
instruction_info <= X"342";
-- LSR
-- Right shift one bit
-- 0 -> [bits] -> C_FLAG
-- C_FLAG & Z flag, N flag zerod
--
when X"4a" =>
instruction_info <= X"120";
when X"46" =>
instruction_info <= X"250";
when X"56" =>
instruction_info <= X"260";
when X"4e" =>
instruction_info <= X"360";
when X"5e" =>
instruction_info <= X"370";
-- NOP
-- No operation
--
when X"ea" =>
instruction_info <= X"126";
-- ORA
-- Or with accumulator
-- A_REG (or) M -> A_REG
-- N & Z flags
--
when X"09" =>
instruction_info <= X"220";
when X"05" =>
instruction_info <= X"230";
when X"15" =>
instruction_info <= X"240";
when X"0d" =>
instruction_info <= X"340";
when X"1d" =>
instruction_info <= X"340";
when X"19" =>
instruction_info <= X"340";
when X"01" =>
instruction_info <= X"260";
when X"11" =>
instruction_info <= X"250";
-- PHA
-- Push accumuator to stack
-- A_REG -> STACK
-- NO FLAGS
when X"48" =>
instruction_info <= X"135";
-- PHP
-- Push processor status on stack
-- P -> STACK
when X"08" =>
instruction_info <= X"135";
-- PLA
-- Pull accumulator from stack
-- STACK -> A_REG
-- N & Z flags
--
when X"68" =>
instruction_info <= X"145";
-- PLP
-- Pull processor status from stack
-- STACK -> P
-- ALL FLAGS CAN CHANGE
when X"28" =>
instruction_info <= X"145";
-- ROL
-- Rotate one bit left
-- [bit 7] -> C_FLAG FLAG
-- [ <- bits 6 - 0] [C_FLAG FLAG (becomes 0 bit)]
-- N & Z & C_FLAG FLAGS
--
when X"2a" =>
instruction_info <= X"120";
when X"26" =>
instruction_info <= X"250";
when X"36" =>
instruction_info <= X"260";
when X"2e" =>
instruction_info <= X"360";
when X"3e" =>
instruction_info <= X"270";
-- ROR
-- Rotate right one
-- [C_FLAG FLAG -> bit 7] [bits 7 - 1 ] [bit 0 becomes C_FLAG flag]
-- N & Z & C_FLAG
--
when X"6a" =>
instruction_info <= X"120";
when X"66" =>
instruction_info <= X"250";
when X"76" =>
instruction_info <= X"260";
when X"6e" =>
instruction_info <= X"360";
when X"7e" =>
instruction_info <= X"370";
-- RTI
-- Return from Interrupt
-- STACK -> P
-- STACK -> PC
-- FLAGS FROM STACK
--
when X"40" =>
instruction_info <= X"168";
-- RTS
-- Reutrn from subroutine
-- STACK -> PC
-- PC + 1 -> PC
-- NO FLAGS
--
when X"60" =>
instruction_info <= X"161";
-- SBC
-- Subtract memory from accumulator w/ borrow
-- A_REG - M - (not) C_FLAG -> Accumulator
-- N & Z & C_FLAG & V Flags
--
when X"e9" =>
instruction_info <= X"220";
when X"e5" =>
instruction_info <= X"230";
when X"f5" =>
instruction_info <= X"240";
when X"ed" =>
instruction_info <= X"340";
when X"fd" =>
instruction_info <= X"340";
when X"f9" =>
instruction_info <= X"340";
when X"e1" =>
instruction_info <= X"260";
when X"f1" =>
instruction_info <= X"250";
-- SEC
-- Set carry flag
-- 1 -> C_FLAG
-- C_FLAG Flag
--
when X"38" =>
instruction_info <= X"124";
-- SED
-- Set decimal flag
-- 1 -> D
-- D flag
--
when X"f8" =>
instruction_info <= X"124";
-- SEI
-- Set interrupt disable flag
-- 1 -> I
-- I FLAG
when X"78" =>
instruction_info <= X"124";
-- STA
-- Store accumulator in memory
-- A_REG -> M
-- no flags
--
when X"85" =>
instruction_info <= X"232";
when X"95" =>
instruction_info <= X"242";
when X"8d" =>
instruction_info <= X"342";
when X"9d" =>
instruction_info <= X"352";
when X"99" =>
instruction_info <= X"352";
when X"81" =>
instruction_info <= X"262";
when X"91" =>
instruction_info <= X"262";
-- STX
-- Store X in memory
-- X -> M
--
when X"86" =>
instruction_info <= X"232";
when X"96" =>
instruction_info <= X"242";
when X"8e" =>
instruction_info <= X"342";
-- STY
-- Store y in memory
-- Y_REG -> M
--
when X"84" =>
instruction_info <= X"232";
when X"94" =>
instruction_info <= X"242";
when X"8c" =>
instruction_info <= X"342";
-- TAX
-- Transfer A_REG to X
-- A_REG -> X
-- N & Z
--
when X"AA" =>
instruction_info <= X"127";
-- TAY
-- X-fer A_REG to Y_REG
-- A_REG -> Y_REG
-- N & Z
--
when X"a8" =>
instruction_info <= X"127";
-- TYA
-- X-fer Y_REG to A_REG
-- Y_REG -> A_REG
-- N & Z
--
when X"98" =>
instruction_info <= X"127";
-- TSX
-- X-fer stack pointer to X
-- S -> X
-- N & Z
--
when X"ba" =>
instruction_info <= X"127";
-- TXA
-- X-fer X to Accumulator
-- X -> A_REG
-- N & Z
--
when X"8A" =>
instruction_info <= X"127";
-- TXS
-- X-fer X to stack pointer
-- X -> S
--
when X"9a" =>
instruction_info <= X"127";
-- XBA
-- Exchange B & A_REG Accumulators
-- A_REG <-> B
-- Remeber that A_REG is the lower 8 bits of C_FLAG
-- and that B is the upper 8 bits of C_FLAG
--
when X"EB" =>
instruction_info <= X"137";
-- XCE
-- Exchange Carry and Emulation flags
-- E Flag <-> C_FLAG Flag
-- Even though this manipulates
-- flag bits, note that it is
-- EXCHANGE type instruction for
-- this implementation.
--
when X"FB" =>
instruction_info <= X"127";
--
-- All other instructions are NOP's
--
when others =>
instruction_info <= X"126";
end case;
decode_done <= '1';
end if;
end process;
end architecture;
| gpl-3.0 |
rad-/65C816_SoftCore | 65816_Interface_System.srcs/sources_1/bd/Interface_Master_BD/hdl/Interface_Master_BD_wrapper.vhd | 1 | 3918 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Mon Apr 11 02:53:44 2016
--Host : Daedalus running 64-bit Ubuntu 14.04.4 LTS
--Command : generate_target Interface_Master_BD_wrapper.bd
--Design : Interface_Master_BD_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Interface_Master_BD_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
clk_test : out STD_LOGIC;
locked : out STD_LOGIC;
reset_65816_module : in STD_LOGIC;
resetn : in STD_LOGIC
);
end Interface_Master_BD_wrapper;
architecture STRUCTURE of Interface_Master_BD_wrapper is
component Interface_Master_BD is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
clk_test : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
reset_65816_module : in STD_LOGIC
);
end component Interface_Master_BD;
begin
Interface_Master_BD_i: component Interface_Master_BD
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
clk_test => clk_test,
locked => locked,
reset_65816_module => reset_65816_module,
resetn => resetn
);
end STRUCTURE;
| gpl-3.0 |
mfrechtling/vhdl_fsm | src/fsm.vhd | 1 | 6592 | library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(
-- GLOBAL SIGNALS:
clk : in std_logic;
reset : in std_logic;
-- COMMAND INTERFACE:
data_in_vld : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out_vld : out std_logic;
data_out : out std_logic_vector(7 downto 0);
--REGISTER ACCESS INTERFACE:
rd_ack : in std_logic;
rd_data : in std_logic_vector(31 downto 0);
wr_en : out std_logic;
rd_en : out std_logic;
addr : out std_logic_vector(15 downto 0);
wr_data : out std_logic_vector(31 downto 0));
end entity;
architecture behaviour of fsm is
type state is (IDLE, CMD, RD, WR, RSP, BRK, ADDR_0, ADDR_1, ADDR_2, ADDR_3, DATA_0, DATA_1, DATA_2, DATA_3, READ_DATA, READ_ACK, RSP_SPC, RSP_CMD);
signal fsm_state : state := IDLE;
signal prev_fsm_state : state := IDLE;
signal current_state : state := IDLE;
signal next_state : state := IDLE;
signal state_buffer : state := IDLE;
signal addr_reg : std_logic_vector(31 downto 0) := (others => '0');
signal data_reg : std_logic_vector(31 downto 0) := (others => '0');
signal fsm_sig : std_logic_vector(7 downto 0);
signal prev_fsm_sig : std_logic_vector(7 downto 0);
signal current_sig : std_logic_vector(7 downto 0);
signal next_sig : std_logic_vector(7 downto 0);
signal rd_cntr : integer := 0;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
fsm_state <= IDLE;
current_state <= IDLE;
prev_fsm_state <= IDLE;
else
case fsm_state is
when IDLE =>
if (data_in_vld = '1' and data_in = x"e7") then
fsm_state <= CMD;
end if;
current_state <= IDLE;
when CMD =>
if (data_in_vld = '1') then
case data_in is
when x"13" =>
fsm_state <= RD;
current_state <= ADDR_3;
when x"23" =>
fsm_state <= WR;
current_state <= ADDR_3;
when x"e7" =>
fsm_state <= prev_fsm_state;
current_state <= next_state;
when others =>
fsm_state <= IDLE;
current_state <= IDLE;
end case;
end if;
when others =>
if (data_in_vld = '1' and data_in = x"e7") then
prev_fsm_state <= fsm_state;
fsm_state <= CMD;
current_state <= CMD;
elsif (next_state = BRK) then
if (fsm_state = BRK) then
fsm_state <= IDLE;
current_state <= IDLE;
else
fsm_state <= BRK;
current_state <= RSP_SPC;
end if;
elsif (next_state = READ_DATA) then
if (rd_ack = '1') then
fsm_state <= RSP;
current_state <= READ_ACK;
rd_cntr <= 0;
elsif (rd_cntr >= 3) then
fsm_state <= BRK;
current_state <= RSP_SPC;
rd_cntr <= 0;
else
current_state <= next_state;
rd_cntr <= rd_cntr + 1;
end if;
elsif (next_state = fsm_state) then
fsm_state <= IDLE;
current_state <= next_state;
else
current_state <= next_state;
end if;
end case;
end if;
end if;
end process;
process(current_state)
begin
rd_en <= '0';
wr_en <= '0';
addr <= (others => '0');
wr_data <= (others => '0');
data_out_vld <= '0';
data_out <= (others => '0');
case current_state is
when IDLE =>
next_state <= IDLE;
when ADDR_3 =>
if (data_in_vld = '1') then
addr_reg(31 downto 24) <= data_in;
next_state <= ADDR_2;
end if;
when ADDR_2 =>
if (data_in_vld = '1') then
addr_reg(23 downto 16) <= data_in;
next_state <= ADDR_1;
end if;
when ADDR_1 =>
if (data_in_vld = '1') then
addr_reg(15 downto 8) <= data_in;
next_state <= ADDR_0;
end if;
when ADDR_0 =>
if (data_in_vld = '1') then
addr_reg(7 downto 0) <= data_in;
case fsm_state is
when RD =>
next_state <= READ_DATA;
when WR =>
next_state <= DATA_3;
when others => null;
end case;
end if;
when DATA_3 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(31 downto 24) <= data_in;
next_state <= DATA_2;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(31 downto 24);
if (data_reg(31 downto 24) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_2;
else
next_state <= DATA_2;
end if;
when others => null;
end case;
when DATA_2 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(23 downto 16) <= data_in;
next_state <= DATA_1;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(23 downto 16);
if (data_reg(23 downto 16) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_1;
else
next_state <= DATA_1;
end if;
when others => null;
end case;
when DATA_1 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(15 downto 8) <= data_in;
next_state <= DATA_0;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(15 downto 8);
if (data_reg(15 downto 8) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_0;
else
next_state <= DATA_0;
end if;
when others => null;
end case;
when DATA_0 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(7 downto 0) <= data_in;
next_state <= WR;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(7 downto 0);
if (data_reg(7 downto 0) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= RSP;
else
next_state <= RSP;
end if;
when others => null;
end case;
when READ_DATA =>
rd_en <= '1';
addr <= addr_reg(15 downto 0);
when READ_ACK =>
data_reg <= rd_data;
next_state <= RSP_SPC;
when WR =>
wr_en <= '1';
addr <= addr_reg(15 downto 0);
wr_data <= data_reg;
next_state <= IDLE;
when RSP_SPC =>
data_out_vld <= '1';
data_out <= x"e7";
if (state_buffer = IDLE) then
next_state <= RSP_CMD;
else
next_state <= state_buffer;
end if;
state_buffer <= IDLE;
when RSP_CMD =>
data_out_vld <= '1';
case fsm_state is
when RSP =>
data_out <= x"03";
next_state <= DATA_3;
when BRK =>
data_out <= x"55";
next_state <= BRK;
when others => null;
end case;
when others => null;
end case;
end process;
end architecture; | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/axi_lite_ipif.vhd | 4 | 14526 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_basic_wrap.vhd | 5 | 50383 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ip/block_design_proc_sys_reset_0_0/synth/block_design_proc_sys_reset_0_0.vhd | 1 | 6661 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY block_design_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END block_design_proc_sys_reset_0_0;
ARCHITECTURE block_design_proc_sys_reset_0_0_arch OF block_design_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_proc_sys_reset_0_0_arch : ARCHITECTURE IS "block_design_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "block_design_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END block_design_proc_sys_reset_0_0_arch;
| gpl-3.0 |
marcoep/MusicBoxNano | ip/WaveformROM.vhd | 1 | 5897 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: WaveformROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY WaveformROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END WaveformROM;
ARCHITECTURE SYN OF waveformrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 12,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/ps2_keyboard.vhd | 2 | 5116 | --------------------------------------------------------------------------------
--
-- FileName: ps2_keyboard.vhd
-- Dependencies: debounce.vhd
-- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/25/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_keyboard IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
debounce_counter_size : INTEGER := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
ps2_clk : IN STD_LOGIC; --clock signal from PS/2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS/2 keyboard
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2
END ps2_keyboard;
ARCHITECTURE logic OF ps2_keyboard IS
SIGNAL sync_ffs : STD_LOGIC_VECTOR(1 DOWNTO 0); --synchronizer flip-flops for PS/2 signals
SIGNAL ps2_clk_int : STD_LOGIC; --debounced clock signal from PS/2 keyboard
SIGNAL ps2_data_int : STD_LOGIC; --debounced data signal from PS/2 keyboard
SIGNAL ps2_word : STD_LOGIC_VECTOR(10 DOWNTO 0); --stores the ps2 data word
SIGNAL error : STD_LOGIC; --validate parity, start, and stop bits
SIGNAL count_idle : INTEGER RANGE 0 TO clk_freq/18_000; --counter to determine PS/2 is idle
--declare debounce component for debouncing PS2 input signals
COMPONENT debounce IS
GENERIC(
counter_size : INTEGER); --debounce period (in seconds) = 2^counter_size/(clk freq in Hz)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END COMPONENT;
BEGIN
--synchronizer flip-flops
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
sync_ffs(0) <= ps2_clk; --synchronize PS/2 clock signal
sync_ffs(1) <= ps2_data; --synchronize PS/2 data signal
END IF;
END PROCESS;
--debounce PS2 input signals
debounce_ps2_clk: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(0), result => ps2_clk_int);
debounce_ps2_data: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(1), result => ps2_data_int);
--input PS2 data
PROCESS(ps2_clk_int)
BEGIN
IF(ps2_clk_int'EVENT AND ps2_clk_int = '0') THEN --falling edge of PS2 clock
ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift in PS2 data bit
END IF;
END PROCESS;
--verify that parity, start, and stop bits are all correct
error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR
ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR
ps2_word(2) XOR ps2_word(1)));
--determine if PS2 port is idle (i.e. last transaction is finished) and output result
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
IF(ps2_clk_int = '0') THEN --low PS2 clock, PS/2 is active
count_idle <= 0; --reset idle counter
ELSIF(count_idle /= clk_freq/18_000) THEN --PS2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
END IF;
IF(count_idle = clk_freq/18_000 AND error = '0') THEN --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new PS/2 code is available
ps2_code <= ps2_word(8 DOWNTO 1); --output new PS/2 code
ELSE --PS/2 port active or error detected
ps2_code_new <= '0'; --set flag that PS/2 transaction is in progress
END IF;
END IF;
END PROCESS;
END logic;
| gpl-3.0 |
stefanct/aua | hw/io/sc_de2_switches/src/sc_de2_switches.vhd | 1 | 1192 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity sc_de2_switches is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t;
-- pins
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0)
);
end sc_de2_switches;
architecture sat1 of sc_de2_switches is
signal switch_reg : std_logic_vector(15 downto 0);
signal led_reg : std_logic_vector(15 downto 0);
begin
rdy_cnt <= (others => '0'); -- no wait states
rd_data <= ((rd_data'length-1 downto switch_reg'length => '0')&switch_reg);
led_pins <= led_reg;
process(clk, reset)
begin
if (reset='1') then
switch_reg <= (others => '0');
led_reg <= (others => '0'); -- high active LEDs
elsif rising_edge(clk) then
if rd = '1' then
switch_reg <= switch_pins;
end if;
if wr = '1' then
led_reg <= not wr_data(15 downto 0);
end if;
end if;
end process;
end sat1;
| gpl-3.0 |
viniciussmello/SistemasDigitais | Trabalho 1/AND_BitABit.vhd | 1 | 721 | ----------------------------------------------------------------------------------
-- Create Date: 21:44:50 04/10/2017
-- Module Name: AND_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end AND_BitABit;
architecture Behavioral of AND_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) AND B(0);
Zout(1) <= A(1) AND B(1);
Zout(2) <= A(2) AND B(2);
Zout(3) <= A(3) AND B(3);
Z <= Zout;
end Behavioral;
| gpl-3.0 |
stefanct/aua | hw/io/sc_dummy/src/sc_dummy.vhd | 1 | 2062 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity sc_test_slave is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t
);
end sc_test_slave;
architecture rtl of sc_test_slave is
signal cycle_cnt, cycle_cnt_nxt : unsigned(3 downto 0);
signal ready, ready_nxt : unsigned(3 downto 0);
signal reg, reg_nxt : sc_data_t;
signal sc_out, sc_out_nxt : sc_data_t;
type state_type is (st_done, st_wait);
signal state : state_type;
signal state_nxt : state_type;
begin
rd_data <= sc_out;
nxt: process(reset, state, cycle_cnt, reg, wr_data, address, wr, rd, ready, sc_out)
begin
cycle_cnt_nxt <= cycle_cnt;
reg_nxt <= reg;
sc_out_nxt <= sc_out;
rdy_cnt <= (others => '0');
ready_nxt <= ready;
state_nxt <= st_done;
if state=st_done then
if address(0)='0' then
if(wr='1') then
cycle_cnt_nxt <= unsigned(wr_data(3 downto 0));
end if;
if rd='1' then
sc_out_nxt <= (sc_out_nxt'length-1 downto cycle_cnt'length => '0')&std_logic_vector(cycle_cnt);
end if;
else
if(wr='1') then
reg_nxt <= wr_data;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
if(rd='1') then
sc_out_nxt <= reg;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
end if;
else
ready_nxt <= ready-1;
sc_out_nxt <= reg;
if ready > 3 then
rdy_cnt <= "11";
else
rdy_cnt <= ready(1 downto 0);
end if;
if ready /= 0 then
state_nxt <= st_wait;
end if;
end if;
end process;
sync: process(clk, reset)
begin
if (reset='1') then
sc_out <= (others => '0');
cycle_cnt <= (others => '0');
reg <= (others => '0');
ready <= (others => '0');
state <= st_done;
elsif rising_edge(clk) then
sc_out <= sc_out_nxt;
cycle_cnt <= cycle_cnt_nxt;
reg <= reg_nxt;
ready <= ready_nxt;
state <= state_nxt;
end if;
end process;
end rtl;
| gpl-3.0 |
viniciussmello/SistemasDigitais | Trabalho 1/ULA/OR.vhd | 1 | 719 | ----------------------------------------------------------------------------------
-- Create Date: 21:40:57 04/10/2017
-- Module Name: OR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)); -- Saida
end OR_BitABit;
architecture Behavioral of OR_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) OR B(0);
Zout(1) <= A(1) OR B(1);
Zout(2) <= A(2) OR B(2);
Zout(3) <= A(3) OR B(3);
Z <= Zout;
end Behavioral;
| gpl-3.0 |
stefanct/aua | hw/alu/src/alu_opt.vhd | 1 | 10502 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
architecture opt of alu is
component Mux32to1 is
port(
i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 downto 0);
i07: in std_logic_vector(15 downto 0);
i08: in std_logic_vector(15 downto 0);
i09: in std_logic_vector(15 downto 0);
i10: in std_logic_vector(15 downto 0);
i11: in std_logic_vector(15 downto 0);
i12: in std_logic_vector(15 downto 0);
i13: in std_logic_vector(15 downto 0);
i14: in std_logic_vector(15 downto 0);
i15: in std_logic_vector(15 downto 0);
i16: in std_logic_vector(15 downto 0);
i17: in std_logic_vector(15 downto 0);
i18: in std_logic_vector(15 downto 0);
i19: in std_logic_vector(15 downto 0);
i20: in std_logic_vector(15 downto 0);
i21: in std_logic_vector(15 downto 0);
i22: in std_logic_vector(15 downto 0);
i23: in std_logic_vector(15 downto 0);
i24: in std_logic_vector(15 downto 0);
i25: in std_logic_vector(15 downto 0);
i26: in std_logic_vector(15 downto 0);
i27: in std_logic_vector(15 downto 0);
i28: in std_logic_vector(15 downto 0);
i29: in std_logic_vector(15 downto 0);
i30: in std_logic_vector(15 downto 0);
i31: in std_logic_vector(15 downto 0);
i32: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(4 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end component;
signal carry: std_logic;
signal carry_nxt: std_logic;
signal mux_sel: std_logic_vector(4 downto 0);
signal mux1_o: word_t;
signal res_ldi: word_t;
signal res_addi: word_t;
signal res_muli: word_t;
signal res_add: word_t;
signal res_addc: word_t;
signal res_sub: word_t;
signal res_subc: word_t;
signal res_mul: word_t;
signal res_mulu: word_t;
signal res_mulh: word_t;
signal res_mulhu: word_t;
signal res_or: word_t;
signal res_and: word_t;
signal res_xor: word_t;
signal res_not: word_t;
signal res_neg: word_t;
signal res_asr: word_t;
signal res_lsl: word_t;
signal res_lsr: word_t;
signal res_lsli: word_t;
signal res_lsri: word_t;
signal res_scb: word_t;
signal res_roti: word_t;
signal res_cmplt: word_t;
signal res_cmpltu: word_t;
signal res_cmplte: word_t;
signal res_cmplteu: word_t;
signal res_cmpe: word_t;
signal res_cmpei: word_t;
signal res_mov: word_t;
signal res_ignore: word_t;
begin
mux1: Mux32to1 port map
( res_ldi,
res_add,
res_mul,
res_add,
res_addc,
res_sub,
res_subc,
res_mul,
res_mulu,
res_mulh,
res_mulhu,
res_or,
res_and,
res_xor,
res_not,
res_neg,
res_asr,
res_lsl,
res_lsr,
res_lsli,
res_lsri,
res_scb,
res_roti,
res_cmplt,
res_cmpltu,
res_cmplte,
res_cmplteu,
res_cmpe,
res_cmpei,
res_mov,
res_ignore,
res_ignore,
mux_sel,
mux1_o
);
sync_carry: process (clk, reset)
begin
if reset = '1' then
carry <= '0';
elsif rising_edge(clk) then
carry <= carry_nxt;
end if;
end process;
process(opcode, opa, opb, carry, mux1_o)
variable tmp_sel: std_logic_vector(4 downto 0);
variable tmp_opa: std_logic_vector(16 downto 0);
variable tmp_opb: std_logic_vector(16 downto 0);
variable tmp_addc: std_logic_vector(16 downto 0);
variable tmp_subc: std_logic_vector(16 downto 0);
variable tmp_carry: std_logic_vector(16 downto 0);
variable carry_addc:std_logic;
variable carry_subc:std_logic;
variable tmp_muls: std_logic_vector(31 downto 0);
variable tmp_mulu: std_logic_vector(31 downto 0);
variable tmp_scb: word_t;
variable tmp_sll: word_t;
variable tmp_srl: word_t;
begin
res_ldi <= opa(15 downto 8) & opb(7 downto 0);
--------------------------------------------------------------------------------------------------
tmp_opa := std_logic_vector(('0' & opa));
tmp_opb := std_logic_vector(('0' & opb));
if (opcode = "100001") or (opcode = "100011") then
tmp_carry := (x"0000"&carry);
else
tmp_carry := (16 downto 0 => '0');
end if;
tmp_addc := std_logic_vector(unsigned(tmp_opa) + unsigned(tmp_opb) + unsigned(tmp_carry));
tmp_subc := std_logic_vector(unsigned(tmp_opa) - unsigned(tmp_opb) - unsigned(tmp_carry));
carry_addc := tmp_addc(16);
carry_subc := tmp_subc(16);
res_add <= tmp_addc(15 downto 0);
res_addc <= tmp_addc(15 downto 0);
res_sub <= tmp_subc(15 downto 0);
res_subc <= tmp_subc(15 downto 0);
if opcode = "100001" or opcode = "011000" or opcode = "100000" then
carry_nxt <= carry_addc;
elsif opcode = "100011" or opcode = "100010" then
carry_nxt <= carry_subc;
else
carry_nxt <= '0';
end if;
--------------------------------------------------------------------------------------------------
-- tmp_add := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)));
-- tmp_addc := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)) + (x"0000"&carry));
-- carry_add := tmp_add(16);
-- carry_addc := tmp_addc(16);
--
-- res_add <= tmp_add(15 downto 0);
-- res_addc <= tmp_addc(15 downto 0);
--
-- tmp_sub := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)));
-- tmp_subc := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)) - (x"0000"&carry));
-- carry_sub := tmp_sub(16);
-- carry_subc := tmp_subc(16);
--
-- res_sub <= tmp_sub(15 downto 0);
-- res_subc <= tmp_subc(15 downto 0);
--------------------------------------------------------------------------------------------------
tmp_muls := std_logic_vector(signed(opa) * signed(opb));
tmp_mulu := std_logic_vector(unsigned(opa) * unsigned(opb));
res_mul <= tmp_muls(15 downto 0);
res_mulu <= tmp_mulu(15 downto 0);
res_mulh <= tmp_muls(31 downto 16);
res_mulhu <= tmp_mulu(31 downto 16);
res_or <= opa or opb;
res_and <= opa and opb;
res_xor <= opa xor opb;
res_not <= not opb;
res_neg <= std_logic_vector(unsigned(not opb) + 1);
res_asr <= to_stdlogicvector(to_bitvector(opb) sra 1);
res_lsl <= std_logic_vector(unsigned(opb) sll 1);
res_lsr <= std_logic_vector(unsigned(opb) srl 1);
res_lsli <= std_logic_vector(unsigned(opa) sll to_integer(unsigned(opb(3 downto 0))));
res_lsri <= std_logic_vector(unsigned(opa) srl to_integer(unsigned(opb(3 downto 0))));
tmp_scb := opa;
tmp_scb(to_integer(unsigned(opb(3 downto 0)))) := opb(4);
res_scb <= tmp_scb;
if opb(4) = '0' then -- rotl
res_roti <= std_logic_vector(unsigned(opa) rol to_integer(unsigned(opb(3 downto 0))));
else -- rotr
res_roti <= std_logic_vector(unsigned(opa) ror to_integer(unsigned(opb(3 downto 0))));
end if;
if signed(opa) < signed(opb) then
res_cmplt <= x"0001";
else
res_cmplt <= x"0000";
end if;
if unsigned(opa) < unsigned(opb) then
res_cmpltu <= x"0001";
else
res_cmpltu <= x"0000";
end if;
if signed(opa) <= signed(opb) then
res_cmplte <= x"0001";
else
res_cmplte <= x"0000";
end if;
if unsigned(opa) <= unsigned(opb) then
res_cmplteu <= x"0001";
else
res_cmplteu <= x"0000";
end if;
if opa = opb then
res_cmpe <= x"0001";
else
res_cmpe <= x"0000";
end if;
if opa = ((15 downto 5 => '0')&opb(4 downto 0)) then
res_cmpei <= x"0001";
else
res_cmpei <= x"0000";
end if;
res_mov <= opb;
res_ignore <= x"0000";
case opcode(5 downto 3) is
when "000" => tmp_sel := "00000"; --ldi
--when "001" => tmp_sel := "11110"; branches--ignore
--when "010" => tmp_sel := "11110"; --ignore
when "011" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "00001"; --addi
when "001" => tmp_sel := "00001"; --addi
when "010" => tmp_sel := "00001"; --addi
when "011" => tmp_sel := "00001"; --addi
when "100" => tmp_sel := "00010"; --muli
when "101" => tmp_sel := "00010"; --muli
when "110" => tmp_sel := "00010"; --muli
when "111" => tmp_sel := "00010"; --muli
when others => tmp_sel := "11110"; --ignore
end case;
when "100" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "00011"; --add
when "001" => tmp_sel := "00100"; --addc
when "010" => tmp_sel := "00101"; --sub
when "011" => tmp_sel := "00110"; --subc
when "100" => tmp_sel := "00111"; --mul
when "101" => tmp_sel := "01000"; --mulu
when "110" => tmp_sel := "01001"; --mulh
when "111" => tmp_sel := "01010"; --mulhu
when others => tmp_sel := "11110"; --ignore
end case;
when "101" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "01011"; --or
when "001" => tmp_sel := "01100"; --and
when "010" => tmp_sel := "01101"; --xor
when "011" => tmp_sel := "01110"; --not
when "100" => tmp_sel := "01111"; --neg
when "101" => tmp_sel := "10000"; --asr
when "110" => tmp_sel := "10001"; --lsl
when "111" => tmp_sel := "10010"; --lsr
when others => tmp_sel := "11110"; --ignore
end case;
when "110" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "10011"; --lsli
when "001" => tmp_sel := "10100"; --lsri
when "010" => tmp_sel := "10101"; --scb
when "011" => tmp_sel := "10110"; --roti
when "100" => tmp_sel := "10111"; --cmplt
when "101" => tmp_sel := "11000"; --cmpltu
when "110" => tmp_sel := "11001"; --cmplte
when "111" => tmp_sel := "11010"; --cmplteu
when others => tmp_sel := "11110"; --ignore
end case;
when "111" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "11011"; --cmpe
when "001" => tmp_sel := "11100"; --cmpei
when "010" => tmp_sel := "11110"; --ignore
when "011" => tmp_sel := "11101"; --mov
when "100" => tmp_sel := "11110"; --ld, ignore
when "101" => tmp_sel := "11110"; --ldb, ignore
when "110" => tmp_sel := "11110"; --st, ignore
when "111" => tmp_sel := "11110"; --stb, ignore
when others => tmp_sel := "11110"; --ignore
end case;
when others => tmp_sel := "11110"; --ignore
end case;
mux_sel <= tmp_sel;
result <= mux1_o;
end process;
end opt;
| gpl-3.0 |
stefanct/aua | hw/if/sim/tb.vhd | 1 | 1933 | library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity if_tb is
end if_tb;
architecture if_test of if_tb is
component ent_if is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register outputs
opcode : out opcode_t;
dest : out reg_t;
pc_out : out word_t;
rega : out reg_t;
regb : out reg_t;
imm : out std_logic_vector(7 downto 0);
-- asynchron register outputs
async_rega : out reg_t;
async_regb : out reg_t;
-- branches (from ID)
pc_in : in word_t;
branch : in std_logic;
-- mmu
instr_addr : out word_t;
instr_data : in word_t
);
end component;
signal clk : std_logic;
signal reset : std_logic;
-- pipeline register outputs
signal opcode : opcode_t;
signal dest : reg_t;
signal pc_out : word_t;
signal rega : reg_t;
signal regb : reg_t;
signal imm : std_logic_vector(7 downto 0);
signal async_rega : reg_t;
signal async_regb : reg_t;
-- branches (from ID)
signal pc_in : word_t;
signal branch : std_logic;
-- mmu
signal instr_addr : word_t;
signal instr_data : word_t;
begin
if1: ent_if
port map(clk, reset, opcode, dest, pc_out, rega, regb, imm, async_rega, async_regb, pc_in, branch, instr_addr, instr_data);
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset <= '1';
pc_in <= "1111111111111111";
branch <= '0';
instr_data <= "1100110010101010";
icwait(2);
--
reset <= '0';
icwait(1);
--
branch <= '1';
icwait(1);
--
branch <= '0';
instr_data <= "0000110010101010";
icwait(100);
--
end process TEST;
end if_test; | gpl-3.0 |
viniciussmello/SistemasDigitais | Trabalho 1/ULA/incrementador.vhd | 1 | 845 | ----------------------------------------------------------------------------------
-- Create Date: 15:31:16 04/11/2017
-- Module Name: incrementador - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity incrementador is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end incrementador;
architecture Behavioral of incrementador is
component Somador4bits
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Ov : out STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
O: Somador4bits port map( A, "0000", '1');
end Behavioral;
| gpl-3.0 |
David-Estevez/spaceinvaders | src/screenFormat.vhd | 1 | 12453 | ----------------------------------------------------------------------------------
--
-- Lab session #4: screenFormat
--
-- Send the screen elements to the VGA controller
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity screenFormat is
port (
VGAx : in std_logic_vector (9 downto 0);
VGAy : in std_logic_vector (9 downto 0);
test : in std_logic;
invArray: in std_logic_vector (39 downto 0);
invLine : in std_logic_vector (3 downto 0);
shipX1 : in std_logic_vector (4 downto 0);
bullX1 : in std_logic_vector (4 downto 0);
bullY1 : in std_logic_vector (3 downto 0);
bulletFlying1: in std_logic;
player2shown : in std_logic;
shipX2 : in std_logic_vector (4 downto 0);
bullX2 : in std_logic_vector (4 downto 0);
bullY2 : in std_logic_vector (3 downto 0);
bulletFlying2: in std_logic;
specialScreen: in std_logic_vector( 2 downto 0);
p1Score: in std_logic_vector(7 downto 0);
p2Score: in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(2 downto 0)
);
end screenFormat;
architecture behavioral of screenFormat is
-- macropixels
signal x : std_logic_vector (4 downto 0); -- 0 to 19
signal y : std_logic_vector (3 downto 0); -- 0 to 14
-- game sprites:
type sprite is array( 0 to 31, 0 to 31) of std_logic;
CONSTANT alien1: sprite := (
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000011000000000011000000000",
"00000000011000000000011000000000",
"00000000000110000001100000000000",
"00000000000110000001100000000000",
"00000000011111111111111000000000",
"00000000011111111111111000000000",
"00000001111001111110011110000000",
"00000001111001111110011110000000",
"00000111111111111111111111100000",
"00000111111111111111111111100000",
"00000110011111111111111001100000",
"00000110011111111111111001100000",
"00000110011000000000011001100000",
"00000110011000000000011001100000",
"00000000000111100111100000000000",
"00000000000111100111100000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"
);
CONSTANT ship_sprite: sprite := (
"00000000000000011000000000000000",
"00000000000000011000000000000000",
"00000000000000011000000000000000",
"00000000000000011000000000000000",
"00000000000001111110000000000000",
"00000000000001111110000000000000",
"00000000000001111110000000000000",
"00000000000001111110000000000000",
"00000001100001111110000110000000",
"00000001100001111110000110000000",
"00000001100001111110000110000000",
"00000001100001111110000110000000",
"00000001100111111111100110000000",
"00000001100111111111100110000000",
"00000001111111100111111110000000",
"00000001111111100111111110000000",
"01100001111110000001111110000110",
"01100001111110000001111110000110",
"01100001111110011001111110000110",
"01100001111110011001111110000110",
"01100001111111111111111110000110",
"01100001111111111111111110000110",
"01100111111111111111111111100110",
"01100111111111111111111111100110",
"01111111111111111111111111111110",
"01111111111111111111111111111110",
"01111110011111111111111001111110",
"01111110011111111111111001111110",
"01111000011110011001111000011110",
"01111000011110011001111000011110",
"01100000000000011000000000000110",
"01100000000000011000000000000110"
);
CONSTANT funny_bullet: sprite := (
"00000000000000111100000000000000",
"00000000000001011110000000000000",
"00000000000010101111000000000000",
"00000000000110001111100000000000",
"00000000001111111111110000000000",
"00000000001111110011110000000000",
"00000000011111110001111000000000",
"00000000011111100001111000000000",
"00000000011111110001111000000000",
"00000000011111100001111000000000",
"00000000011111100011111000000000",
"00000000011111110011111000000000",
"00000000011111111111111000000000",
"00000000000000000000000000000000",
"00000000010111111111111000000000",
"00000000010111111111111000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"
);
-- Define colors as constants:
CONSTANT BLACK : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "000";
CONSTANT BLUE : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "001";
CONSTANT GREEN : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "010";
CONSTANT CYAN : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "011";
CONSTANT RED : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "100";
CONSTANT MAGENTA : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "101";
CONSTANT YELLOW : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "110";
CONSTANT WHITE : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "111";
begin
-- Conversion to macropixels (32x32 blocks)
x <= VGAx(9 downto 5);
y <= VGAy(8 downto 5);
-- Process to draw the screen
process (x,y,test,specialScreen,invArray,bulletFlying1,bullX1,bullY1,player2shown,bulletFlying2,bullX2,bullY2,shipX1,shipX2,invLine)
variable currentPixel: std_logic; -- Stores temporarily the current pixel of the sprite
variable currentInvader: std_logic_vector( 1 downto 0); -- Stores the type of the current invader
variable indX, indY: integer range 0 to 31; -- Indices inside the 32x32 block
variable indInv: integer range 0 to 39; -- Index inside the invaders array
begin
if test = '1' then
-- Show test checkerboard pattern
----------------------------------------
if (x(0) xor y(0)) = '1' then
rgb <= BLACK;
else
rgb <= WHITE;
end if;
else
-- Select screen
case specialScreen is
when "000" =>
-- No special screen (show game)
------------------------------------
-- Get coordinates inside de 32x32 macropixel
indX := to_integer(unsigned(VGAx(4 downto 0)));
indY := to_integer(unsigned(VGAy(4 downto 0)));
-- Convert the 'macropixel' x coordinate to the invArray coordinates (2*x+1, 2*x)
indInv := to_integer(unsigned(x)) * 2;
currentInvader := invArray( indInv+1 downto indInv);
-- Show player 1 bullet in red
if bulletFlying1 = '1' and (x = bullX1) and (y = bullY1) then
if funny_bullet( indY, indX) = '1' then
rgb <= CYAN;
else
rgb <= BLACK;
end if;
-- Show player 2 bullet in magenta
elsif player2shown = '1' and bulletFlying2 = '1' and (x = bullX2) and (y = bullY2) then
if funny_bullet( indY, indX) = '1' then
rgb <= MAGENTA;
else
rgb <= BLACK;
end if;
-- Show ship 1 in blue
elsif (x = shipX1) and (y = std_logic_vector(to_unsigned(14,4))) then
if ship_sprite( indY, indX) = '1' then
rgb <= BLUE;
else
rgb <= BLACK;
end if;
-- Show ship 2 in cyan
elsif player2shown = '1' and (x = shipX2) and (y = std_logic_vector(to_unsigned(14,4))) then
if ship_sprite( indY, indX) = '1' then
rgb <= RED;
else
rgb <= BLACK;
end if;
-- Show invaders in green
elsif ( currentInvader /= "00") and (y = invLine) then
currentPixel := alien1( indY, indX);
if currentPixel = '1' then
case currentInvader is
when "01" => -- Easy alien
rgb <= GREEN;
when "10" => -- Medium alien
rgb <= YELLOW;
when "11" => -- Hard alien
rgb <= WHITE;
when others =>
rgb <= "XXX";
end case;
else
rgb <= BLACK;
end if;
else
-- Pixel is black otherwise:
rgb <= BLACK;
end if ;
when "001" =>
-- You win screen
-------------------------------------
-- Get coordinates inside de 32x32 macropixel
indX := to_integer(unsigned(VGAx(4 downto 0)));
indY := to_integer(unsigned(VGAy(4 downto 0)));
-- Convert the 'macropixel' x coordinate to the invArray coordinates (2*x+1, 2*x)
indInv := to_integer(unsigned(x)) * 2;
currentInvader := invArray( indInv+1 downto indInv);
if (y = std_logic_vector(to_unsigned(5,4))) then
-- We are in the correct line
if ((x > std_logic_vector(to_unsigned(0,5))) and (x < std_logic_vector(to_unsigned(9,5)))) then
-- We are in the correct box
if (p1Score(7-to_integer(unsigned(x))) = '1') then
-- Show an alien
currentPixel := alien1( indY, indX);
if currentPixel = '1' then
rgb <= BLACK;
else
rgb <= BLUE;
end if;
else
rgb <= BLUE;
end if;
else
rgb <= BLACK;
end if;
elsif (y = std_logic_vector(to_unsigned(7,4))) then
-- We are in the correct line
if ((x > std_logic_vector(to_unsigned(0,5))) and (x < std_logic_vector(to_unsigned(9,5)))) then
-- We are in the correct box
if (p2Score(7-to_integer(unsigned(x))) = '1') then
-- Show an alien
currentPixel := alien1( indY, indX);
if currentPixel = '1' then
rgb <= BLACK;
else
rgb <= RED;
end if;
else
rgb <= RED;
end if;
else
rgb <= BLACK;
end if;
else
rgb <= BLACK;
end if;
when "010" =>
-- You lose screen
-------------------------------------
if (x(0) xor y(0)) = '1' then
rgb <= BLACK;
else
rgb <= BLUE;
end if;
-- Temporarily blue checkerboard pattern
when "011" =>
-- Game won screen
-------------------------------------
if (x(0) xor y(0)) = '1' then
rgb <= BLACK;
else
rgb <= YELLOW;
end if;
-- Temporarily blue checkerboard pattern
when others =>
rgb <= "XXX"; -- Indicate error
end case;
end if ;
end process;
end behavioral;
| gpl-3.0 |
stefanct/aua | hw/id/src/id.vhd | 1 | 5648 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity id is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register inputs
opcode_in : in opcode_t;
dest_in : in reg_t;
pc_in : in pc_t;
pcnxt_in : in pc_t;
rega_in : in reg_t;
regb_in : in reg_t;
imm_in : in std_logic_vector(7 downto 0);
-- asynchron register inputs
async_rega : in reg_t;
async_regb : in reg_t;
-- results from wb to reg file
regr : in reg_t;
valr : in word_t;
-- pipeline register outputs
opcode_out : out opcode_t;
dest_out : out reg_t;
opa_out : out word_t;
opb_out : out word_t;
-- needed for EX forwarding
rega_out : out reg_t;
regb_out : out reg_t;
opb_isfrom_regb : out boolean;
-- branch decision
pc_out : out pc_t;
branch_out : out std_logic;
-- interlock
lock : in std_logic;
id_locks : out std_logic
);
end id;
architecture sat1 of id is
component reg is
port (
clk : in std_logic;
reset : in std_logic;
async_rega : in reg_t;
async_regb : in reg_t;
rega : in reg_t;
regb : in reg_t;
async_regr : in reg_t;
async_valr : in word_t;
vala : out word_t;
valb : out word_t
);
end component;
signal opcode_nxt : opcode_t;
signal dest_nxt : reg_t;
signal opa_nxt : word_t;
signal opb_nxt : word_t;
signal dest : reg_t;
signal opa : word_t;
signal opb : word_t;
signal vala : word_t;
signal valb : word_t;
signal rega_nxt : reg_t;
signal regb_nxt : reg_t;
signal opb_isfrom_regb_nxt : boolean;
signal jmpl_op : std_logic; -- set if instr is jmpl. used to propagate $ra to EX
signal opa_to_nop : std_logic; -- set if we need opa to be all 0s for idle EX
signal br_data_hz_nxt : std_logic;
signal br_data_hz : std_logic;
begin
cmp_reg : reg
port map(clk, reset, async_rega, async_regb, rega_in, regb_in, regr, valr, vala, valb);
dest_out <= dest;
rega_nxt <= rega_in;
regb_nxt <= regb_in;
id_locks <= br_data_hz_nxt;
branch: process (opcode_in, pc_in, vala, valb, dest_in, dest, opb_nxt, rega_in, regb_in, br_data_hz)
variable inv : std_logic; -- set if op is a "not branch"
variable brinstr : std_logic; -- set if op changes PC
begin
inv := '0';
brinstr := '0';
br_data_hz_nxt <= '0';
opa_to_nop <= '0';
jmpl_op <= '0';
pc_out <= resize(unsigned(to_integer(pc_in) + signed(resize(unsigned(opb_nxt(ADDR_SIZE-1 downto 1)&'0'), ADDR_SIZE+1))), ADDR_SIZE);
--~ pc_out <= unsigned(resize(unsigned(opb_nxt(ADDR_SIZE-1 downto 1)&'0'), ADDR_SIZE+1)); -- numeric_std warnings in modelsim
opcode_nxt <= opcode_in;
if opcode_in(5 downto 3)="010" then -- branch imm
inv := opcode_in(2);
brinstr := '1';
-- schedule nop
opcode_nxt <= (others => '0');
opa_to_nop <= '1';
dest_nxt <= (others => '0');
elsif opcode_in(5 downto 1) ="00111" then
inv := opcode_in(0);
brinstr := '1';
pc_out <= pc_t(opb_nxt); -- absolute branch
-- schedule nop
opcode_nxt <= (others => '0');
opa_to_nop <= '1';
dest_nxt <= (others => '0');
elsif opcode_in = "001101" then
inv := '0';
brinstr := '1';
-- jmpl, schedule mov r31, pc!
opcode_nxt <= "111011";
dest_nxt <= "11111";
jmpl_op <= '1';
pc_out <= pc_t(valb); -- jump is absolute, and we need to take the reg value directly!
elsif opcode_in(5 downto 2) = "1101" or opcode_in(5 downto 1) = "11100" then
dest_nxt <= "11011";
else
dest_nxt <= dest_in;
end if;
branch_out <= '0';
if brinstr='1' then
if (dest=rega_in or dest=regb_in) and br_data_hz='0' then
br_data_hz_nxt <= '1';
elsif (x"0000"=vala xor inv='1') then
branch_out <= '1';
end if;
end if;
end process;
-- inserts a nop (for branches etc.)
insert_nop: process (vala, opa_to_nop)
begin
if opa_to_nop = '1' then
opa_nxt <= (others => '0');
else
opa_nxt <= vala;
end if;
end process;
-- sign extend, expand and mux with regb
extend_n_mux: process (opcode_in, imm_in, valb, jmpl_op, pcnxt_in)
begin
opb_isfrom_regb_nxt <= false;
if opcode_in(5 downto 3)="000" then
opb_nxt <= (15 downto 8 => '0') & imm_in(7 downto 0);
elsif opcode_in(5 downto 2) ="1100" or opcode_in(5 downto 0) ="111010" then
--expand whole imm (alu has to take care if thats "too much")
opb_nxt <= (15 downto 7 => '0') & imm_in(6 downto 0);
elsif opcode_in(5 downto 4)="01" then
--sign extend imm(6 downto 0)
if opcode_in(3) = '0' then -- imm branch; word addressing -> shift
opb_nxt <= (15 downto 8 => imm_in(6)) & imm_in(6 downto 0) & '0';
else
opb_nxt <= (15 downto 7 => imm_in(6)) & imm_in(6 downto 0);
end if;
elsif jmpl_op='1' then
opb_nxt <= word_t(pcnxt_in); -- EX needs the return address
--~ opb_nxt <= valb;
else
opb_isfrom_regb_nxt <= true;
opb_nxt <= valb;
end if;
end process;
sync: process (clk, reset)
begin
if reset = '1' then
opcode_out <= (others => '0');
--~ dest_out <= (others => '0');
dest <= (others => '0');
opa_out <= (others => '0');
opb_out <= (others => '0');
rega_out <= (others => '0');
regb_out <= (others => '0');
br_data_hz <= '0';
opb_isfrom_regb <= false;
elsif rising_edge(clk) then
if lock/='1' then
opcode_out <= opcode_nxt;
--~ dest_out <= dest_nxt;
dest <= dest_nxt;
opa_out <= opa_nxt;
opb_out <= opb_nxt;
--~ else
--~ opcode <= opcode;
--~ dest <= dest;
--~ opa <= opa;
--~ opb <= opb;
rega_out <= rega_nxt;
regb_out <= regb_nxt;
opb_isfrom_regb <= opb_isfrom_regb_nxt;
br_data_hz <= br_data_hz_nxt;
end if;
end if;
end process;
end sat1;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@m@i@s@c_@r@d@m@u@x/_primary.vhd | 3 | 2273 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDMUX is
port(
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
COMPARATOR : in vl_logic_vector(11 downto 0);
SSE_IRQ_EN : in vl_logic_vector(20 downto 0);
SSE_IRQ : in vl_logic_vector(20 downto 0);
COMP_IRQ_EN : in vl_logic_vector(23 downto 0);
COMP_IRQ : in vl_logic_vector(23 downto 0);
PPE_FIFO_IRQ : in vl_logic_vector(8 downto 0);
PPE_FIFO_IRQ_EN : in vl_logic_vector(8 downto 0);
PPE_FLAGS0_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS0_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS1_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS1_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS2_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS2_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS3_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS3_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_SFFLAGS_IRQ : in vl_logic_vector(31 downto 0);
PPE_SFFLAGS_IRQ_EN: in vl_logic_vector(31 downto 0);
FPGA_FLAGS_SEL : in vl_logic_vector(9 downto 0);
PPE_PDMA_CTRL : in vl_logic_vector(31 downto 0);
PDMA_STATUS : in vl_logic_vector(31 downto 0);
PPE_PDMA_DATAOUT: in vl_logic_vector(31 downto 0);
PADDR : in vl_logic_vector(12 downto 0);
PRDATA_MISC : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_MISC_RDMUX;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/read_analog_input/_primary.vhd | 3 | 259 | library verilog;
use verilog.vl_types.all;
entity read_analog_input is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_input;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@s@s@e_@e@n@g@i@n@e/_primary.vhd | 3 | 3833 | library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_ENGINE is
generic(
RAM_DEBUG : integer := 0
);
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
SSE_TS_CTRL0 : out vl_logic;
SSE_RWB : in vl_logic;
SSE_ADDR : in vl_logic_vector(9 downto 0);
SSE_WDATA : in vl_logic_vector(15 downto 0);
SSE_RDATA_o : out vl_logic_vector(15 downto 0);
PPE_FIFO_FULL : in vl_logic;
PC0_FLAGS_o : out vl_logic_vector(3 downto 0);
PC1_FLAGS_o : out vl_logic_vector(3 downto 0);
PC2_FLAGS_o : out vl_logic_vector(3 downto 0);
ADC0_CALIBRATE_rise: out vl_logic;
ADC1_CALIBRATE_rise: out vl_logic;
ADC2_CALIBRATE_rise: out vl_logic;
ADC0_CALIBRATE_fall: out vl_logic;
ADC1_CALIBRATE_fall: out vl_logic;
ADC2_CALIBRATE_fall: out vl_logic;
ADC0_DATAVALID_rise: out vl_logic;
ADC1_DATAVALID_rise: out vl_logic;
ADC2_DATAVALID_rise: out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_TVC_o : out vl_logic_vector(7 downto 0);
ADC1_TVC_o : out vl_logic_vector(7 downto 0);
ADC2_TVC_o : out vl_logic_vector(7 downto 0);
ADC0_STC_o : out vl_logic_vector(7 downto 0);
ADC1_STC_o : out vl_logic_vector(7 downto 0);
ADC2_STC_o : out vl_logic_vector(7 downto 0);
ADC0_MODE_o : out vl_logic_vector(3 downto 0);
ADC1_MODE_o : out vl_logic_vector(3 downto 0);
ADC2_MODE_o : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL_o : out vl_logic;
ABPOWERON_o : out vl_logic;
ADC0_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART_o : out vl_logic;
ADC1_ADCSTART_o : out vl_logic;
ADC2_ADCSTART_o : out vl_logic;
ADC0_PWRDWN_o : out vl_logic;
ADC1_PWRDWN_o : out vl_logic;
ADC2_PWRDWN_o : out vl_logic;
ADC0_ADCRESET_o : out vl_logic;
ADC1_ADCRESET_o : out vl_logic;
ADC2_ADCRESET_o : out vl_logic;
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
DAC0_DATA_o : out vl_logic_vector(23 downto 0);
DAC1_DATA_o : out vl_logic_vector(23 downto 0);
DAC2_DATA_o : out vl_logic_vector(23 downto 0);
DAC0_CTRL_o : out vl_logic_vector(7 downto 0);
DAC1_CTRL_o : out vl_logic_vector(7 downto 0);
DAC2_CTRL_o : out vl_logic_vector(7 downto 0);
PDMA_decode : in vl_logic;
INREADY_o : out vl_logic;
SSE_ADC0_RESULTS_o: out vl_logic;
SSE_ADC1_RESULTS_o: out vl_logic;
SSE_ADC2_RESULTS_o: out vl_logic
);
end F2DSS_SSE_ENGINE;
| gpl-3.0 |
kristofferkoch/ethersound | tb_timer.vhd | 1 | 1551 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_timer IS
END tb_timer;
ARCHITECTURE behavior OF tb_timer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT timer
PORT(
reset : IN std_logic;
sysclk : IN std_logic;
load : IN unsigned(63 downto 0);
load_en : IN std_logic;
time_o : OUT unsigned(63 downto 0);
ppm : IN signed(9 downto 0)
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal sysclk : std_logic := '0';
signal load : unsigned(63 downto 0) := (others => '0');
signal load_en : std_logic := '0';
signal ppm : signed(9 downto 0) := (others => '0');
--Outputs
signal time_o : unsigned(63 downto 0);
-- Clock period definitions
constant sysclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: timer PORT MAP (
reset => reset,
sysclk => sysclk,
load => load,
load_en => load_en,
time_o => time_o,
ppm => ppm
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
ppm <= to_signed(-1, 10);
load_en <= '0';
wait for 100 ns;
reset <= '0';
wait for sysclk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@r@d@m@u@x/_primary.vhd | 3 | 2940 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_RDMUX is
port(
RAM_RD_B_apbrd_pre: in vl_logic;
RAM_DO_B : in vl_logic_vector(31 downto 0);
ADC0_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_SCRATCH : in vl_logic_vector(31 downto 0);
PPE_SF : in vl_logic_vector(31 downto 0);
ALU_CTRL : in vl_logic_vector(31 downto 0);
ALU_STATUS : in vl_logic_vector(31 downto 0);
ALU_A : in vl_logic_vector(31 downto 0);
ALU_B : in vl_logic_vector(31 downto 0);
ALU_C : in vl_logic_vector(31 downto 0);
ALU_D : in vl_logic_vector(15 downto 0);
ALU_E : in vl_logic_vector(15 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
PPE_FLAGS0 : in vl_logic_vector(31 downto 0);
PPE_FLAGS1 : in vl_logic_vector(31 downto 0);
PPE_FLAGS2 : in vl_logic_vector(31 downto 0);
PPE_FLAGS3 : in vl_logic_vector(31 downto 0);
PPE_SFFLAGS : in vl_logic_vector(31 downto 0);
PADDR : in vl_logic_vector(12 downto 0);
PRDATA_PPE : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_RDMUX;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_differential_inputs/_primary.vhd | 3 | 338 | library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_differential_inputs;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@m@i@s@c_@f@d@e@t/_primary.vhd | 3 | 286 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_FDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
FALL : out vl_logic
);
end F2DSS_ACE_MISC_FDET;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@a@b_@f060/_primary.vhd | 3 | 4185 | library verilog;
use verilog.vl_types.all;
entity F2AB_F060 is
generic(
WIDTH : integer := 32;
DAC_RESOLUTION : vl_logic_vector(5 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
ANALOG_QUAD_NUM : integer := 6;
ADC_NUM : integer := 1;
NUM_ADC_IN : integer := 5;
VAREF_INT : real := 2.560000
);
port(
AV1 : in vl_logic_vector(5 downto 0);
AV2 : in vl_logic_vector(5 downto 0);
AC : in vl_logic_vector(5 downto 0);
AT : in vl_logic_vector(5 downto 0);
ATGND_01 : in vl_logic;
ATGND_23 : in vl_logic;
ATGND_45 : in vl_logic;
VAREF : in vl_logic_vector(2 downto 0);
ADCGNDREF : in vl_logic;
ADC_VAREFSEL : in vl_logic;
ADC0 : in vl_logic_vector(3 downto 0);
ADC1 : in vl_logic_vector(3 downto 0);
ADC2 : in vl_logic_vector(3 downto 0);
ADC_F060 : in vl_logic_vector(13 downto 0);
DEN_ADC : in vl_logic_vector(11 downto 0);
ADC0_PWRDWN : in vl_logic;
ADC0_ADCRESET : in vl_logic;
ADC0_SYSCLK : in vl_logic;
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC0_MODE : in vl_logic_vector(3 downto 0);
ADC0_TVC : in vl_logic_vector(7 downto 0);
ADC0_STC : in vl_logic_vector(7 downto 0);
ADC0_ADCSTART : in vl_logic;
ADC1_PWRDWN : in vl_logic;
ADC1_ADCRESET : in vl_logic;
ADC1_SYSCLK : in vl_logic;
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_MODE : in vl_logic_vector(3 downto 0);
ADC1_TVC : in vl_logic_vector(7 downto 0);
ADC1_STC : in vl_logic_vector(7 downto 0);
ADC1_ADCSTART : in vl_logic;
ADC2_PWRDWN : in vl_logic;
ADC2_ADCRESET : in vl_logic;
ADC2_SYSCLK : in vl_logic;
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_MODE : in vl_logic_vector(3 downto 0);
ADC2_TVC : in vl_logic_vector(7 downto 0);
ADC2_STC : in vl_logic_vector(7 downto 0);
ADC2_ADCSTART : in vl_logic;
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ADC_VAREFOUT : out vl_logic;
ACB_RDATA : out vl_logic_vector(7 downto 0);
ADC0_BUSY : out vl_logic;
ADC0_CALIBRATE : out vl_logic;
ADC0_DATAVALID : out vl_logic;
ADC0_SAMPLE : out vl_logic;
ADC0_RESULT : out vl_logic_vector(11 downto 0);
ADC1_BUSY : out vl_logic;
ADC1_CALIBRATE : out vl_logic;
ADC1_DATAVALID : out vl_logic;
ADC1_SAMPLE : out vl_logic;
ADC1_RESULT : out vl_logic_vector(11 downto 0);
ADC2_BUSY : out vl_logic;
ADC2_CALIBRATE : out vl_logic;
ADC2_DATAVALID : out vl_logic;
ADC2_SAMPLE : out vl_logic;
ADC2_RESULT : out vl_logic_vector(11 downto 0);
DACOUT0 : out vl_logic;
DACOUT1 : out vl_logic;
DACOUT2 : out vl_logic;
DIG_ADC : out vl_logic_vector(11 downto 0);
OBD_DIN : in vl_logic_vector(2 downto 0);
OBD_CLKIN : in vl_logic_vector(2 downto 0);
OBD_ENABLE : in vl_logic_vector(2 downto 0);
COMPARATOR : out vl_logic_vector(11 downto 0)
);
attribute DAC_RESOLUTION_mti_vect_attrib : integer;
attribute DAC_RESOLUTION_mti_vect_attrib of DAC_RESOLUTION : constant is 0;
end F2AB_F060;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@apb@client_@h@m/_primary.vhd | 3 | 745 | library verilog;
use verilog.vl_types.all;
entity ApbClient_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
pError : out vl_logic;
pAddrPhAck : out vl_logic;
pDataPhAck : out vl_logic;
mergedReq : in vl_logic;
mergedWrite : in vl_logic;
invalidXfer : in vl_logic;
pDataClkEn : out vl_logic;
F_HM_PSEL : out vl_logic;
F_HM_PENABLE : out vl_logic;
F_HM_PREADY : in vl_logic;
F_HM_PSLVERR : in vl_logic
);
end ApbClient_HM;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@client_@f@m/_primary.vhd | 3 | 868 | library verilog;
use verilog.vl_types.all;
entity Client_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
DS_FM_HTRANS1 : out vl_logic;
DS_FM_HREADY : in vl_logic;
DS_FM_HRESP : in vl_logic;
addrClkEn : out vl_logic;
dataClkEn : out vl_logic;
hRegReq : in vl_logic;
hRegWrite : in vl_logic;
hFMInvalidXfer : in vl_logic;
pRegReq : in vl_logic;
pRegWrite : in vl_logic;
pFMInvalidXfer : in vl_logic;
clientReady : out vl_logic;
clientError : out vl_logic;
dataPhAck : out vl_logic
);
end Client_FM;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@apb@wrapper_@f@m/_primary.vhd | 3 | 1211 | library verilog;
use verilog.vl_types.all;
entity ApbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
pRegReq : out vl_logic;
pRegWrite : out vl_logic;
pFMInvalidXfer : out vl_logic;
wrapperWData : out vl_logic_vector(31 downto 0);
wrapperRData : in vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
APB16_XHOLD : out vl_logic_vector(15 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic;
F_FM_HREADYOUT : in vl_logic
);
end ApbWrapper_FM;
| gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@x@f@e@r_@d@i@n@m@u@x/_primary.vhd | 3 | 3657 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_XFER_DINMUX is
port(
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_SCRATCH : in vl_logic_vector(31 downto 0);
PPE_SF : in vl_logic_vector(31 downto 0);
ALU_CTRL : in vl_logic_vector(31 downto 0);
ALU_STATUS : in vl_logic_vector(31 downto 0);
ALU_A : in vl_logic_vector(31 downto 0);
ALU_B : in vl_logic_vector(31 downto 0);
ALU_C : in vl_logic_vector(31 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
PPE_FLAGS0 : in vl_logic_vector(31 downto 0);
PPE_FLAGS1 : in vl_logic_vector(31 downto 0);
PPE_FLAGS2 : in vl_logic_vector(31 downto 0);
PPE_FLAGS3 : in vl_logic_vector(31 downto 0);
PPE_SFFLAGS : in vl_logic_vector(31 downto 0);
ADC0_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : in vl_logic_vector(31 downto 0);
CURRENT_ADC_RESULT: in vl_logic_vector(11 downto 0);
PPE2SSE_PRDATA_rdhold: in vl_logic_vector(15 downto 0);
RAM_DO_A : in vl_logic_vector(31 downto 0);
RAM_DO_B : in vl_logic_vector(31 downto 0);
move_from_PPE_CTRL: in vl_logic;
move_from_PC_ETC: in vl_logic;
move_from_SF : in vl_logic;
move_from_SCRATCH: in vl_logic;
move_from_ALU_CTRL: in vl_logic;
move_from_ALU_STATUS: in vl_logic;
move_from_A : in vl_logic;
move_from_B : in vl_logic;
move_from_C : in vl_logic;
move_from_PPE_FPTR: in vl_logic;
move_from_PPE_FLAGS0: in vl_logic;
move_from_PPE_FLAGS1: in vl_logic;
move_from_PPE_FLAGS2: in vl_logic;
move_from_PPE_FLAGS3: in vl_logic;
move_from_PPE_SFFLAGS: in vl_logic;
move_from_ADC0_FIFO_CTRL: in vl_logic;
move_from_ADC0_FIFO_STATUS: in vl_logic;
move_from_ADC0_FIFO_DATA: in vl_logic;
move_from_ADC1_FIFO_CTRL: in vl_logic;
move_from_ADC1_FIFO_STATUS: in vl_logic;
move_from_ADC1_FIFO_DATA: in vl_logic;
move_from_ADC2_FIFO_CTRL: in vl_logic;
move_from_ADC2_FIFO_STATUS: in vl_logic;
move_from_ADC2_FIFO_DATA: in vl_logic;
move_from_ADC_RESULT_LSB: in vl_logic;
move_from_ADC_RESULT_MSB: in vl_logic;
move_from_PPE2SSE_PRDATA: in vl_logic;
move_from_RAM_DO_A_31_0: in vl_logic;
move_from_RAM_DO_A_23_0_LSB: in vl_logic;
move_from_RAM_DO_A_23_0_MSB: in vl_logic;
move_from_RAM_DO_A_15_0_MSB: in vl_logic;
move_from_RAM_DO_B_31_0: in vl_logic;
xfer_din_mux : out vl_logic_vector(31 downto 0);
xfer_din_mux_not_from_RAM: out vl_logic_vector(31 downto 0);
xfer_din_mux_from_RAM: out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_XFER_DINMUX;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_export/src/DCT1D.vhd | 8 | 11974 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_export/src/DCT1D.vhd | 8 | 11974 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.srcs/sources_1/dct_source/DCT1D.vhd | 8 | 11974 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_export/src/MDCT_PKG.vhd | 9 | 2517 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCT_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCT_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for MDCT core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package MDCT_PKG is
constant IP_W : INTEGER := 8;
constant OP_W : INTEGER := 12;
constant N : INTEGER := 8;
constant COE_W : INTEGER := 12;
constant ROMDATA_W : INTEGER := COE_W+2;
constant ROMADDR_W : INTEGER := 6;
constant RAMDATA_W : INTEGER := 10;
constant RAMADRR_W : INTEGER := 6;
constant COL_MAX : INTEGER := N-1;
constant ROW_MAX : INTEGER := N-1;
constant LEVEL_SHIFT : INTEGER := 128;
constant DA_W : INTEGER := ROMDATA_W+IP_W;
constant DA2_W : INTEGER := DA_W+2;
-- 2's complement numbers
constant AP : INTEGER := 1448;
constant BP : INTEGER := 1892;
constant CP : INTEGER := 784;
constant DP : INTEGER := 2009;
constant EP : INTEGER := 1703;
constant FP : INTEGER := 1138;
constant GP : INTEGER := 400;
constant AM : INTEGER := -1448;
constant BM : INTEGER := -1892;
constant CM : INTEGER := -784;
constant DM : INTEGER := -2009;
constant EM : INTEGER := -1703;
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
end MDCT_PKG; | gpl-3.0 |
tirfil/vhdI2CMaster | test/tb_i2cmaster.vhd | 1 | 3190 | --###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
---- 2016/06/06 Add STOP
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_I2CMASTER is
end tb_I2CMASTER;
architecture stimulus of tb_I2CMASTER is
-- COMPONENTS --
component I2CMASTER
port(
MCLK : in std_logic;
nRST : in std_logic;
SRST : in std_logic;
TIC : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RD : in std_logic;
WE : in std_logic;
NACK : out std_logic;
QUEUED : out std_logic;
DATA_VALID : out std_logic;
STATUS : out std_logic_vector(2 downto 0);
STOP : out std_logic;
SCL_IN : in std_logic;
SCL_OUT : out std_logic;
SDA_IN : in std_logic;
SDA_OUT : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SRST : std_logic;
signal TIC : std_logic;
signal DIN : std_logic_vector(7 downto 0);
signal DOUT : std_logic_vector(7 downto 0);
signal RD : std_logic;
signal WE : std_logic;
signal NACK : std_logic;
signal QUEUED : std_logic;
signal DATA_VALID : std_logic;
signal STATUS : std_logic_vector(2 downto 0);
signal STOP : std_logic;
signal SCL_IN : std_logic;
signal SCL_OUT : std_logic;
signal SDA_IN : std_logic;
signal SDA_OUT : std_logic;
--
signal RUNNING : std_logic := '1';
signal counter : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_I2CMASTER_0 : I2CMASTER
port map (
MCLK => MCLK,
nRST => nRST,
SRST => SRST,
TIC => TIC,
DIN => DIN,
DOUT => DOUT,
RD => RD,
WE => WE,
NACK => NACK,
QUEUED => QUEUED,
DATA_VALID => DATA_VALID,
STOP => STOP,
STATUS => STATUS,
SCL_IN => SCL_IN,
SCL_OUT => SCL_OUT,
SDA_IN => SDA_IN,
SDA_OUT => SDA_OUT
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit
GEN: process(MCLK, nRST)
begin
if (nRST = '0') then
counter <= (others=>'0');
elsif (MCLK'event and MCLK='1') then
if (TIC = '1') then
counter <= (others=>'0');
else
counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8));
end if;
end if;
end process GEN;
GO: process
begin
nRST <= '0';
SRST <= '0';
--DIN <= (others=>'0');
DIN <= x"EE";
RD <= '0';
WE <= '1';
SDA_IN <= '0';
SCL_IN <= '0';
wait for 1000 ns;
nRST <= '1';
wait until QUEUED'event and QUEUED = '0';
WE <= '1';
DIN <= x"AA";
wait until QUEUED'event and QUEUED = '0';
WE <= '0';
RD <= '1';
wait until QUEUED'event and QUEUED = '0';
WE <= '0';
RD <= '1';
wait until DATA_VALID'event and DATA_VALID = '0';
SDA_IN <= '1';
wait until QUEUED'event and QUEUED = '0';
WE <= '0';
RD <= '0';
wait until DATA_VALID'event and DATA_VALID = '0';
wait for 100 uS;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ip/mult_gen_0/mult_gen_0_sim_netlist.vhdl | 2 | 32697 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:50:02 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_0_synth_1/mult_gen_0_sim_netlist.vhdl
-- Design : mult_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_0_mult_gen_v12_0_9 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 32 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 53 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult_gen_0_mult_gen_v12_0_9 : entity is 33;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult_gen_0_mult_gen_v12_0_9 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult_gen_0_mult_gen_v12_0_9 : entity is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult_gen_0_mult_gen_v12_0_9 : entity is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult_gen_0_mult_gen_v12_0_9 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult_gen_0_mult_gen_v12_0_9 : entity is 53;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult_gen_0_mult_gen_v12_0_9 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult_gen_0_mult_gen_v12_0_9 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult_gen_0_mult_gen_v12_0_9 : entity is "mult_gen_v12_0_9";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_0_mult_gen_v12_0_9 : entity is "yes";
end mult_gen_0_mult_gen_v12_0_9;
architecture STRUCTURE of mult_gen_0_mult_gen_v12_0_9 is
attribute C_A_TYPE of i_mult : label is 0;
attribute C_A_WIDTH of i_mult : label is 33;
attribute C_B_TYPE of i_mult : label is 0;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 14;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 0;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 1;
attribute C_OPTIMIZE_GOAL of i_mult : label is 1;
attribute C_OUT_HIGH of i_mult : label is 53;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "artix7";
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
i_mult: entity work.mult_gen_0_mult_gen_v12_0_9_viv
port map (
A(32 downto 0) => A(32 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => CE,
CLK => CLK,
P(53 downto 0) => P(53 downto 0),
PCASC(47 downto 0) => PCASC(47 downto 0),
SCLR => SCLR,
ZERO_DETECT(1 downto 0) => ZERO_DETECT(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_0 is
port (
A : in STD_LOGIC_VECTOR ( 32 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
P : out STD_LOGIC_VECTOR ( 53 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult_gen_0 : entity is "mult_gen_0,mult_gen_v12_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of mult_gen_0 : entity is "mult_gen_0,mult_gen_v12_0_9,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=33,C_A_TYPE=0,C_B_WIDTH=14,C_B_TYPE=0,C_OUT_HIGH=53,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult_gen_0 : entity is "mult_gen_v12_0_9,Vivado 2015.3";
end mult_gen_0;
architecture STRUCTURE of mult_gen_0 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 33;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of U0 : label is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 53;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:signal:data:1.0 p_intf DATA";
begin
U0: entity work.mult_gen_0_mult_gen_v12_0_9
port map (
A(32 downto 0) => A(32 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => '1',
CLK => '1',
P(53 downto 0) => P(53 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/xbip_pipe_v3_0_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 1 | 24644 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 18 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 18 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 18 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 18 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qTTbr9Do0UAuG3/q84c3fgjPsKvyBqSCFwf/1bHmT6ZC/IAZmQ+0OTY1kBHuCPfj5H/Pvqcy1Bsu
DXDNRZkE/g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/digilent_repo/local/ip/dvi2rgb_v1_5/src/ChannelBond.vhd | 15 | 6809 | -------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/xbip_bram18k_v3_0_0/hdl/xbip_bram18k_v3_0.vhd | 1 | 9340 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/mult_gen_1/mult_gen_1_stub.vhdl | 2 | 1340 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 09:23:31 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/mult_gen_1/mult_gen_1_stub.vhdl
-- Design : mult_gen_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult_gen_1 is
Port (
A : in STD_LOGIC_VECTOR ( 11 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
P : out STD_LOGIC_VECTOR ( 32 downto 0 )
);
end mult_gen_1;
architecture stub of mult_gen_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[11:0],B[13:0],P[32:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0,Vivado 2015.1";
begin
end;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 3 | 18538 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=1,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=1,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=DEADBEEF,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.96515 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RREADY";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 1,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "DEADBEEF",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.96515 mW"
)
PORT MAP (
clka => '0',
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/mult_gen_v12_0_9/hdl/mult_gen_v12_0.vhd | 1 | 10054 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/synth/dcfifo_32in_32out_8kb_cnt.vhd | 2 | 38925 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY dcfifo_32in_32out_8kb_cnt IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dcfifo_32in_32out_8kb_cnt;
ARCHITECTURE dcfifo_32in_32out_8kb_cnt_arch OF dcfifo_32in_32out_8kb_cnt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dcfifo_32in_32out_8kb_cnt_arch : ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=1,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=8,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 8,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 253,
C_PROG_FULL_THRESH_NEGATE_VAL => 252,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 1,
C_RD_DEPTH => 256,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 8,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 8,
C_WR_DEPTH => 256,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 8,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END dcfifo_32in_32out_8kb_cnt_arch;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/mult_gen_1/synth/mult_gen_1.vhd | 2 | 5547 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY mult_gen_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(32 DOWNTO 0)
);
END mult_gen_1;
ARCHITECTURE mult_gen_1_arch OF mult_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(32 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mult_gen_1_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mult_gen_1_arch : ARCHITECTURE IS "mult_gen_1,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mult_gen_1_arch: ARCHITECTURE IS "mult_gen_1,mult_gen_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=12,C_A_TYPE=0,C_B_WIDTH=14,C_B_TYPE=0,C_OUT_HIGH=32,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "artix7",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 0,
C_A_WIDTH => 12,
C_A_TYPE => 0,
C_B_WIDTH => 14,
C_B_TYPE => 0,
C_OUT_HIGH => 32,
C_OUT_LOW => 0,
C_MULT_TYPE => 1,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => '1',
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_gen_1_arch;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 15 | 90319 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
ASacanell/University-Projects | VHDL/bubble sort ASM/uc.vhd | 1 | 4001 | ----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: TOC&TC
--
-- Create Date:
-- Design Name: sort
-- Module Name: uc - rtl
-- Project Name: Practica 5
-- Target Devices: Spartan-3
-- Tool versions: ISE 14.1
-- Description: Unidad control de ASM ordenamiento burbuja
-- Dependencies:
-- Revision:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uc is
port (
clk : in std_logic; -- clock
rst_n : in std_logic; -- reset
ini : in std_logic; -- External control signal
fin : out std_logic; -- External control signal
ctrl : out std_logic_vector(6 downto 0); -- Control vector
status : in std_logic_vector(2 downto 0)); -- Status vector
end entity uc;
architecture rtl of uc is
type t_st is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
signal current_state, next_state : t_st;
-- signal cmp_i, cmp_j, cmp_mem : std_logic;
begin
p_next_state : process (current_state, status, ini) is
variable cmp_i : std_logic; -- Senal de estado del comparador cntri
variable cmp_j : std_logic; -- Senal de estado del comparador cntrj
variable cmp_mem : std_logic; -- Senal de estado del comparador mem
begin
(cmp_i,
cmp_j,
cmp_mem) := status;
case current_state is
when s0 =>
if ini = '1' then
next_state <= s1;
else
next_state <= current_state;
end if;
when s1 =>
next_state <= s2;
when s2 =>
if cmp_i = '1' then
next_state <= s3;
else
next_state <= s0;
end if;
when s3 =>
next_state <= s4;
when s4 =>
if cmp_j = '1' then
next_state <= s5;
else
next_state <= s9;
end if;
when s5 =>
next_state <= s6;
when s6 =>
if cmp_mem = '1' then
next_state <= s7;
else
next_state <= s8;
end if;
when s7 =>
next_state <= s8;
when s8 =>
next_state <= s4;
when s9 =>
next_state <= s2;
when others => null;
end case;
end process p_next_state;
p_outputs : process (current_state)
constant c_cntri_ld : std_logic_vector(6 downto 0) := "0000001";
constant c_cntri_cu : std_logic_vector(6 downto 0) := "0000010";
constant c_cntrj_ld : std_logic_vector(6 downto 0) := "0000100";
constant c_cntrj_cu : std_logic_vector(6 downto 0) := "0001000";
constant c_wea : std_logic_vector(6 downto 0) := "0010000";
constant c_web : std_logic_vector(6 downto 0) := "0100000";
constant c_debug_mode : std_logic_vector(6 downto 0) := "1000000";
constant c_zero : std_logic_vector(6 downto 0) := (others => '0');
begin
ctrl <= (others => '0');
case current_state is
when s0 =>
ctrl <= c_debug_mode;
fin <= '1';
when s1 =>
ctrl <= c_cntri_ld;
fin <= '0';
when s2 =>
ctrl <= c_zero;
fin <= '0';
when s3 =>
ctrl <= c_cntrj_ld;
fin <= '0';
when s4 =>
ctrl <= c_zero;
fin <= '0';
when s5 =>
ctrl <=c_zero;
fin <= '0';
when s6 =>
ctrl <= c_zero;
fin <= '0';
when s7 =>
ctrl <= c_web OR c_wea;
fin <= '0';
when s8 =>
ctrl <= c_cntrj_cu;
fin <= '0';
when s9 =>
ctrl <= c_cntri_cu;
fin <= '0';
when others => null;
end case;
end process p_outputs;
p_status_reg : process (clk, rst_n) is
begin
if rst_n = '0' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process p_status_reg;
end architecture rtl;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/synth/scfifo_32in_32out_1kb.vhd | 3 | 38647 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY scfifo_32in_32out_1kb IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END scfifo_32in_32out_1kb;
ARCHITECTURE scfifo_32in_32out_1kb_arch OF scfifo_32in_32out_1kb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF scfifo_32in_32out_1kb_arch : ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END scfifo_32in_32out_1kb_arch;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_funcsim.vhdl | 1 | 238366 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 29 14:16:28 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_funcsim.vhdl
-- Design : dcfifo_32in_32out_16kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 5) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 5) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 0) => din(15 downto 0),
DIBDI(15 downto 0) => din(31 downto 16),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => dout(15 downto 0),
DOBDO(15 downto 0) => dout(31 downto 16),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_compare : entity is "compare";
end dcfifo_32in_32out_16kb_compare;
architecture STRUCTURE of dcfifo_32in_32out_16kb_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_compare_0 is
port (
comp2 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_compare_0 : entity is "compare";
end dcfifo_32in_32out_16kb_compare_0;
architecture STRUCTURE of dcfifo_32in_32out_16kb_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \rd_pntr_bin_reg[8]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_compare_1 : entity is "compare";
end dcfifo_32in_32out_16kb_compare_1;
architecture STRUCTURE of dcfifo_32in_32out_16kb_compare_1 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \wr_pntr_bin_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_compare_2 : entity is "compare";
end dcfifo_32in_32out_16kb_compare_2;
architecture STRUCTURE of dcfifo_32in_32out_16kb_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_bin_cntr : entity is "rd_bin_cntr";
end dcfifo_32in_32out_16kb_rd_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair11";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => WR_PNTR_RD(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => WR_PNTR_RD(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => WR_PNTR_RD(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => WR_PNTR_RD(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => WR_PNTR_RD(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => WR_PNTR_RD(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => WR_PNTR_RD(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => WR_PNTR_RD(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => WR_PNTR_RD(8),
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end dcfifo_32in_32out_16kb_reset_blk_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_16kb_reset_blk_ramfifo is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
rst_full_ff_i <= rst_d2;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^q\(0),
I1 => p_18_out,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_synchronizer_ff : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_synchronizer_ff;
architecture STRUCTURE of dcfifo_32in_32out_16kb_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_synchronizer_ff_3 is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_synchronizer_ff_3 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_synchronizer_ff_3;
architecture STRUCTURE of dcfifo_32in_32out_16kb_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_synchronizer_ff_4 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_synchronizer_ff_4 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_synchronizer_ff_4;
architecture STRUCTURE of dcfifo_32in_32out_16kb_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^wr_pntr_bin_reg[7]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
\out\(0) <= Q_reg(8);
\wr_pntr_bin_reg[7]\(7 downto 0) <= \^wr_pntr_bin_reg[7]\(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^wr_pntr_bin_reg[7]\(3),
O => \^wr_pntr_bin_reg[7]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^wr_pntr_bin_reg[7]\(3),
O => \^wr_pntr_bin_reg[7]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^wr_pntr_bin_reg[7]\(3),
I1 => Q_reg(2),
O => \^wr_pntr_bin_reg[7]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(8),
I2 => Q_reg(6),
I3 => Q_reg(7),
I4 => Q_reg(5),
I5 => Q_reg(3),
O => \^wr_pntr_bin_reg[7]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(8),
I4 => Q_reg(4),
O => \^wr_pntr_bin_reg[7]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(6),
I2 => Q_reg(7),
I3 => Q_reg(5),
O => \^wr_pntr_bin_reg[7]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \^wr_pntr_bin_reg[7]\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \^wr_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_synchronizer_ff_5 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_synchronizer_ff_5 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_synchronizer_ff_5;
architecture STRUCTURE of dcfifo_32in_32out_16kb_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^rd_pntr_bin_reg[7]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
\out\(0) <= Q_reg(8);
\rd_pntr_bin_reg[7]\(7 downto 0) <= \^rd_pntr_bin_reg[7]\(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(8),
Q => Q_reg(8)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^rd_pntr_bin_reg[7]\(3),
O => \^rd_pntr_bin_reg[7]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^rd_pntr_bin_reg[7]\(3),
O => \^rd_pntr_bin_reg[7]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_bin_reg[7]\(3),
I1 => Q_reg(2),
O => \^rd_pntr_bin_reg[7]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(8),
I2 => Q_reg(6),
I3 => Q_reg(7),
I4 => Q_reg(5),
I5 => Q_reg(3),
O => \^rd_pntr_bin_reg[7]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(8),
I4 => Q_reg(4),
O => \^rd_pntr_bin_reg[7]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(6),
I2 => Q_reg(7),
I3 => Q_reg(5),
O => \^rd_pntr_bin_reg[7]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \^rd_pntr_bin_reg[7]\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \^rd_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_wr_bin_cntr is
port (
\wr_data_count_i_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\wr_data_count_i_reg[8]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[8]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_wr_bin_cntr : entity is "wr_bin_cntr";
end dcfifo_32in_32out_16kb_wr_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d1_reg[8]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
\gic0.gc0.count_d1_reg[8]_0\(0) <= \^gic0.gc0.count_d1_reg[8]_0\(0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
I4 => wr_pntr_plus2(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
I5 => wr_pntr_plus2(5),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[8]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[8]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[8]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
I3 => \^gic0.gc0.count_d1_reg[8]_0\(0),
O => \plusOp__0\(8)
);
\gic0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => wr_pntr_plus2(3),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => wr_pntr_plus2(2),
I5 => wr_pntr_plus2(4),
O => \gic0.gc0.count[8]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => Q(0),
Q => p_8_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(1),
Q => p_8_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(2),
Q => p_8_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(4),
Q => p_8_out(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(5),
Q => p_8_out(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(6),
Q => p_8_out(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => wr_pntr_plus2(7),
Q => p_8_out(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \^gic0.gc0.count_d1_reg[8]_0\(0),
Q => p_8_out(8)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => p_8_out(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => Q(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => Q(0),
D => \plusOp__0\(8),
Q => \^gic0.gc0.count_d1_reg[8]_0\(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(0),
I1 => RD_PNTR_WR(0),
I2 => p_8_out(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(2),
I1 => RD_PNTR_WR(2),
I2 => p_8_out(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus2(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(4),
I1 => RD_PNTR_WR(4),
I2 => p_8_out(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus2(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(6),
I1 => RD_PNTR_WR(6),
I2 => p_8_out(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus2(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_8_out(8),
I1 => RD_PNTR_WR(8),
O => v1_reg(4)
);
\wr_data_count_i[8]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
\wr_data_count_i[8]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
\wr_data_count_i[8]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
\wr_data_count_i[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[8]\(0)
);
\wr_data_count_i[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[8]_0\(3)
);
\wr_data_count_i[8]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[8]_0\(2)
);
\wr_data_count_i[8]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[8]_0\(1)
);
\wr_data_count_i[8]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[8]_0\(0)
);
\wr_data_count_i[8]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_wr_dc_as : entity is "wr_dc_as";
end dcfifo_32in_32out_16kb_wr_dc_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_wr_dc_as is
signal minusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \wr_data_count_i_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_4_n_0\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_4_n_1\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_4_n_2\ : STD_LOGIC;
signal \wr_data_count_i_reg[8]_i_4_n_3\ : STD_LOGIC;
signal \NLW_wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => Q(0),
D => minusOp(8),
Q => wr_data_count(0)
);
\wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \wr_data_count_i_reg[8]_i_2_n_0\,
CO(3 downto 0) => \NLW_wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 1) => \NLW_wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => minusOp(8),
S(3) => '0',
S(2) => '0',
S(1) => '0',
S(0) => \gic0.gc0.count_d2_reg[8]\(0)
);
\wr_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \wr_data_count_i_reg[8]_i_4_n_0\,
CO(3) => \wr_data_count_i_reg[8]_i_2_n_0\,
CO(2) => \wr_data_count_i_reg[8]_i_2_n_1\,
CO(1) => \wr_data_count_i_reg[8]_i_2_n_2\,
CO(0) => \wr_data_count_i_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 4),
O(3 downto 0) => minusOp(7 downto 4),
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]_0\(3 downto 0)
);
\wr_data_count_i_reg[8]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \wr_data_count_i_reg[8]_i_4_n_0\,
CO(2) => \wr_data_count_i_reg[8]_i_4_n_1\,
CO(1) => \wr_data_count_i_reg[8]_i_4_n_2\,
CO(0) => \wr_data_count_i_reg[8]_i_4_n_3\,
CYINIT => '1',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0),
O(3 downto 0) => minusOp(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dcfifo_32in_32out_16kb_blk_mem_gen_prim_width;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_clk_x_pntrs is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_clk_x_pntrs : entity is "clk_x_pntrs";
end dcfifo_32in_32out_16kb_clk_x_pntrs;
architecture STRUCTURE of dcfifo_32in_32out_16kb_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_in7_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_1_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_2_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
RD_PNTR_WR(8 downto 0) <= \^rd_pntr_wr\(8 downto 0);
WR_PNTR_RD(8 downto 0) <= \^wr_pntr_rd\(8 downto 0);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => \gc0.count_reg[7]\(1),
I2 => \^wr_pntr_rd\(0),
I3 => \gc0.count_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => \gc0.count_reg[7]\(3),
I2 => \^wr_pntr_rd\(2),
I3 => \gc0.count_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => \gc0.count_reg[7]\(5),
I2 => \^wr_pntr_rd\(4),
I3 => \gc0.count_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => \gc0.count_reg[7]\(7),
I2 => \^wr_pntr_rd\(6),
I3 => \gc0.count_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^rd_pntr_wr\(8),
I1 => \gic0.gc0.count_reg[8]\(0),
O => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(8),
I1 => Q(8),
O => ram_empty_fb_i_reg
);
\gsync_stage[1].rd_stg_inst\: entity work.dcfifo_32in_32out_16kb_synchronizer_ff
port map (
D(8 downto 0) => p_3_out(8 downto 0),
Q(8 downto 0) => wr_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.dcfifo_32in_32out_16kb_synchronizer_ff_3
port map (
D(8 downto 0) => p_2_out(8 downto 0),
Q(8 downto 0) => rd_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.dcfifo_32in_32out_16kb_synchronizer_ff_4
port map (
D(8 downto 0) => p_3_out(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(8),
rd_clk => rd_clk,
\wr_pntr_bin_reg[7]\(7 downto 0) => p_0_in(7 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.dcfifo_32in_32out_16kb_synchronizer_ff_5
port map (
D(8 downto 0) => p_2_out(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(8),
\rd_pntr_bin_reg[7]\(7) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[7]\(6) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[7]\(5) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[7]\(4) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[7]\(3) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[7]\(2) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[7]\(1) => \gsync_stage[2].wr_stg_inst_n_7\,
\rd_pntr_bin_reg[7]\(0) => \gsync_stage[2].wr_stg_inst_n_8\,
wr_clk => wr_clk
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_8\,
Q => \^rd_pntr_wr\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => \^rd_pntr_wr\(8)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \rd_pntr_gc[7]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => rd_pntr_gc(8)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(8),
Q => \^wr_pntr_rd\(8)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(0),
I1 => \gic0.gc0.count_d2_reg[8]\(1),
O => p_0_in7_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(1),
I1 => \gic0.gc0.count_d2_reg[8]\(2),
O => p_0_in7_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(2),
I1 => \gic0.gc0.count_d2_reg[8]\(3),
O => p_0_in7_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(3),
I1 => \gic0.gc0.count_d2_reg[8]\(4),
O => p_0_in7_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(4),
I1 => \gic0.gc0.count_d2_reg[8]\(5),
O => p_0_in7_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(5),
I1 => \gic0.gc0.count_d2_reg[8]\(6),
O => p_0_in7_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(6),
I1 => \gic0.gc0.count_d2_reg[8]\(7),
O => p_0_in7_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(7),
I1 => \gic0.gc0.count_d2_reg[8]\(8),
O => p_0_in7_out(7)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[8]\(8),
Q => wr_pntr_gc(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_status_flags_as : entity is "rd_status_flags_as";
end dcfifo_32in_32out_16kb_rd_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_status_flags_as is
signal comp0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
signal ram_empty_i_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair8";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_empty_i_i_1 : label is "soft_lutpair8";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
c0: entity work.dcfifo_32in_32out_16kb_compare_1
port map (
comp0 => comp0,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
c1: entity work.dcfifo_32in_32out_16kb_compare_2
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i_i_1_n_0,
PRE => Q(0),
Q => \^p_18_out\
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \^p_18_out\,
I3 => comp1,
O => ram_empty_i_i_1_n_0
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i_i_1_n_0,
PRE => Q(0),
Q => empty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_wr_status_flags_as : entity is "wr_status_flags_as";
end dcfifo_32in_32out_16kb_wr_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_1_out,
O => E(0)
);
c1: entity work.dcfifo_32in_32out_16kb_compare
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.dcfifo_32in_32out_16kb_compare_0
port map (
comp2 => comp2,
\rd_pntr_bin_reg[8]\(0) => \rd_pntr_bin_reg[8]\(0),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => p_1_out
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => rst_full_gen_i,
I1 => comp2,
I2 => p_1_out,
I3 => wr_en,
I4 => comp1,
O => ram_full_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_prim_width
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_logic : entity is "rd_logic";
end dcfifo_32in_32out_16kb_rd_logic;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_14_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
begin
\gras.rsts\: entity work.dcfifo_32in_32out_16kb_rd_status_flags_as
port map (
E(0) => p_14_out,
Q(0) => Q(0),
empty => empty,
\gc0.count_reg[8]\ => rpntr_n_0,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
rpntr: entity work.dcfifo_32in_32out_16kb_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => p_14_out,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
WR_PNTR_RD(8 downto 0) => WR_PNTR_RD(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(0),
ram_empty_fb_i_reg => rpntr_n_0,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_wr_logic is
port (
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d1_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 8 downto 0 );
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_wr_logic : entity is "wr_logic";
end dcfifo_32in_32out_16kb_wr_logic;
architecture STRUCTURE of dcfifo_32in_32out_16kb_wr_logic is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_10 : STD_LOGIC;
signal wpntr_n_11 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_14 : STD_LOGIC;
signal wpntr_n_15 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_17 : STD_LOGIC;
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
WEBWE(0) <= \^webwe\(0);
\gwas.gwdc0.wdc\: entity work.dcfifo_32in_32out_16kb_wr_dc_as
port map (
Q(0) => Q(0),
S(3) => wpntr_n_14,
S(2) => wpntr_n_15,
S(1) => wpntr_n_16,
S(0) => wpntr_n_17,
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0),
\gic0.gc0.count_d2_reg[7]_0\(3) => wpntr_n_10,
\gic0.gc0.count_d2_reg[7]_0\(2) => wpntr_n_11,
\gic0.gc0.count_d2_reg[7]_0\(1) => wpntr_n_12,
\gic0.gc0.count_d2_reg[7]_0\(0) => wpntr_n_13,
\gic0.gc0.count_d2_reg[8]\(0) => wpntr_n_0,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0)
);
\gwas.wsts\: entity work.dcfifo_32in_32out_16kb_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
\rd_pntr_bin_reg[8]\(0) => \rd_pntr_bin_reg[8]\(0),
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \c2/v1_reg\(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.dcfifo_32in_32out_16kb_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0),
E(0) => \^webwe\(0),
Q(0) => Q(0),
RD_PNTR_WR(8 downto 0) => RD_PNTR_WR(8 downto 0),
S(3) => wpntr_n_14,
S(2) => wpntr_n_15,
S(1) => wpntr_n_16,
S(0) => wpntr_n_17,
\gic0.gc0.count_d1_reg[8]_0\(0) => \gic0.gc0.count_d1_reg[8]\(0),
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \c2/v1_reg\(3 downto 0),
wr_clk => wr_clk,
\wr_data_count_i_reg[8]\(0) => wpntr_n_0,
\wr_data_count_i_reg[8]_0\(3) => wpntr_n_10,
\wr_data_count_i_reg[8]_0\(2) => wpntr_n_11,
\wr_data_count_i_reg[8]_0\(1) => wpntr_n_12,
\wr_data_count_i_reg[8]_0\(0) => wpntr_n_13
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dcfifo_32in_32out_16kb_blk_mem_gen_top;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_top
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_blk_mem_gen_v8_2 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
end dcfifo_32in_32out_16kb_blk_mem_gen_v8_2;
architecture STRUCTURE of dcfifo_32in_32out_16kb_blk_mem_gen_v8_2 is
begin
inst_blk_mem_gen: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_memory : entity is "memory";
end dcfifo_32in_32out_16kb_memory;
architecture STRUCTURE of dcfifo_32in_32out_16kb_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.dcfifo_32in_32out_16kb_blk_mem_gen_v8_2
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end dcfifo_32in_32out_16kb_fifo_generator_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_16kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 8 to 8 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.dcfifo_32in_32out_16kb_clk_x_pntrs
port map (
Q(8 downto 0) => p_20_out(8 downto 0),
RD_PNTR_WR(8 downto 0) => p_0_out(8 downto 0),
WR_PNTR_RD(8 downto 0) => p_1_out(8 downto 0),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
\gic0.gc0.count_reg[8]\(0) => wr_pntr_plus2(8),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(0) => \gwas.wsts/c2/v1_reg\(4),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.dcfifo_32in_32out_16kb_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_20_out(8 downto 0),
Q(0) => RD_RST,
WR_PNTR_RD(8 downto 0) => p_1_out(8 downto 0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.dcfifo_32in_32out_16kb_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_9_out(8 downto 0),
Q(0) => WR_RST,
RD_PNTR_WR(8 downto 0) => p_0_out(8 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
full => full,
\gic0.gc0.count_d1_reg[8]\(0) => wr_pntr_plus2(8),
\rd_pntr_bin_reg[8]\(0) => \gwas.wsts/c2/v1_reg\(4),
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.dcfifo_32in_32out_16kb_memory
port map (
Q(0) => rd_rst_i(0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_20_out(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.dcfifo_32in_32out_16kb_reset_blk_ramfifo
port map (
Q(2) => RD_RST,
Q(1 downto 0) => rd_rst_i(1 downto 0),
\gic0.gc0.count_reg[0]\(1) => WR_RST,
\gic0.gc0.count_reg[0]\(0) => wr_rst_i(0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_fifo_generator_top : entity is "fifo_generator_top";
end dcfifo_32in_32out_16kb_fifo_generator_top;
architecture STRUCTURE of dcfifo_32in_32out_16kb_fifo_generator_top is
begin
\grf.rf\: entity work.dcfifo_32in_32out_16kb_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.dcfifo_32in_32out_16kb_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 509;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 508;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end dcfifo_32in_32out_16kb_fifo_generator_v12_0;
architecture STRUCTURE of dcfifo_32in_32out_16kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dcfifo_32in_32out_16kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dcfifo_32in_32out_16kb : entity is "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dcfifo_32in_32out_16kb : entity is "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=509,C_PROG_FULL_THRESH_NEGATE_VAL=508,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=1,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dcfifo_32in_32out_16kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dcfifo_32in_32out_16kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end dcfifo_32in_32out_16kb;
architecture STRUCTURE of dcfifo_32in_32out_16kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 509;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 508;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 1;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.dcfifo_32in_32out_16kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8) => '0',
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(8) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(8) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8) => '0',
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(8) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(8) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(0) => wr_data_count(0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_funcsim.vhdl | 2 | 220711 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sat Mar 19 19:16:24 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/repo/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_funcsim.vhdl
-- Design : dcfifo_32in_32out_8kb_cnt
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => \gc0.count_d1_reg[7]\(7 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 0) => din(15 downto 0),
DIBDI(15 downto 0) => din(31 downto 16),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => dout(15 downto 0),
DOBDO(15 downto 0) => dout(31 downto 16),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_bin_cntr is
port (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_bin_cntr : entity is "rd_bin_cntr";
end dcfifo_32in_32out_8kb_cnt_rd_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_i_i_6_n_0 : STD_LOGIC;
signal ram_empty_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[7]_i_2\ : label is "soft_lutpair7";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(4),
I1 => rd_pntr_plus1(2),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(0),
I4 => rd_pntr_plus1(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => rd_pntr_plus1(3),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(1),
I4 => rd_pntr_plus1(2),
I5 => rd_pntr_plus1(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => rd_pntr_plus1(4),
I2 => \gc0.count[7]_i_2_n_0\,
I3 => rd_pntr_plus1(3),
I4 => rd_pntr_plus1(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(7),
I1 => rd_pntr_plus1(5),
I2 => rd_pntr_plus1(3),
I3 => \gc0.count[7]_i_2_n_0\,
I4 => rd_pntr_plus1(4),
I5 => rd_pntr_plus1(6),
O => plusOp(7)
);
\gc0.count[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
O => \gc0.count[7]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(5),
Q => rd_pntr_plus1(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(6),
Q => rd_pntr_plus1(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(7),
Q => rd_pntr_plus1(7)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \wr_pntr_bin_reg[6]\,
I1 => \wr_pntr_bin_reg[4]\,
I2 => ram_empty_i_i_4_n_0,
I3 => ram_empty_i_i_5_n_0,
I4 => ram_empty_i_i_6_n_0,
I5 => ram_empty_i_i_7_n_0,
O => ram_empty_i_reg
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => WR_PNTR_RD(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => WR_PNTR_RD(3),
O => ram_empty_i_i_4_n_0
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => WR_PNTR_RD(5),
I2 => rd_pntr_plus1(4),
I3 => WR_PNTR_RD(4),
I4 => WR_PNTR_RD(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_i_i_5_n_0
);
ram_empty_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => WR_PNTR_RD(6),
I2 => rd_en,
I3 => p_18_out,
I4 => WR_PNTR_RD(7),
I5 => rd_pntr_plus1(7),
O => ram_empty_i_i_6_n_0
);
ram_empty_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => WR_PNTR_RD(3),
I2 => rd_pntr_plus1(1),
I3 => WR_PNTR_RD(1),
I4 => WR_PNTR_RD(0),
I5 => rd_pntr_plus1(0),
O => ram_empty_i_i_7_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 6 downto 0 );
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_dc_as : entity is "rd_dc_as";
end dcfifo_32in_32out_8kb_cnt_rd_dc_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_dc_as is
signal minusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \NLW_rd_dc_i_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => minusOp(7),
Q => rd_data_count(0)
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_2_n_0\,
CO(3) => \NLW_rd_dc_i_reg[7]_i_1_CO_UNCONNECTED\(3),
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => WR_PNTR_RD(6 downto 4),
O(3 downto 0) => minusOp(7 downto 4),
S(3 downto 0) => S(3 downto 0)
);
\rd_dc_i_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[7]_i_2_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_2_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_2_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_2_n_3\,
CYINIT => '1',
DI(3 downto 0) => WR_PNTR_RD(3 downto 0),
O(3 downto 0) => minusOp(3 downto 0),
S(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_status_flags_as : entity is "rd_status_flags_as";
end dcfifo_32in_32out_8kb_cnt_rd_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_status_flags_as is
signal \^p_18_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
\gc0.count_d1[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => empty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
rst_full_ff_i <= rst_d2;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^q\(0),
I1 => p_18_out,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^wr_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\wr_pntr_bin_reg[6]\(6 downto 0) <= \^wr_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^wr_pntr_bin_reg[6]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^wr_pntr_bin_reg[6]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^wr_pntr_bin_reg[6]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^rd_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\rd_pntr_bin_reg[6]\(6 downto 0) <= \^rd_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^rd_pntr_bin_reg[6]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^rd_pntr_bin_reg[6]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^rd_pntr_bin_reg[6]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_bin_cntr is
port (
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_bin_cntr : entity is "wr_bin_cntr";
end dcfifo_32in_32out_8kb_cnt_wr_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gic0.gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair10";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) <= \^gic0.gc0.count_d2_reg[7]_0\(7 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => \^q\(0),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => \^q\(0),
I3 => \^q\(1),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(0),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => \^q\(1),
I4 => \^q\(2),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(1),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(3),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
I2 => \^q\(5),
O => \plusOp__0\(7)
);
\gic0.gc0.count[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => \^q\(0),
I5 => \^q\(2),
O => \gic0.gc0.count[7]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[7]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[7]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[7]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[7]_0\(7)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(0)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(1)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(2)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(3)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(4)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(5)
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => RD_PNTR_WR(0),
I1 => wr_pntr_plus2(0),
I2 => wr_en,
I3 => p_0_out,
I4 => wr_pntr_plus2(1),
I5 => RD_PNTR_WR(1),
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_status_flags_as : entity is "wr_status_flags_as";
end dcfifo_32in_32out_8kb_cnt_wr_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_status_flags_as is
signal \^p_0_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_0_out <= \^p_0_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_0_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => \^p_0_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_clk_x_pntrs is
port (
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg_0 : out STD_LOGIC;
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_dc_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_i : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_full_gen_i : in STD_LOGIC;
\rd_pntr_bin_reg[0]_0\ : in STD_LOGIC;
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_clk_x_pntrs : entity is "clk_x_pntrs";
end dcfifo_32in_32out_8kb_cnt_clk_x_pntrs;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_in6_out : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 2 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_1_out : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_2_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal ram_full_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
begin
RD_PNTR_WR(1 downto 0) <= \^rd_pntr_wr\(1 downto 0);
WR_PNTR_RD(7 downto 0) <= \^wr_pntr_rd\(7 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff
port map (
D(7 downto 0) => p_3_out(7 downto 0),
Q(7 downto 0) => wr_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0
port map (
D(7 downto 0) => p_2_out(7 downto 0),
Q(7 downto 0) => rd_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1
port map (
D(7 downto 0) => p_3_out(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(7),
rd_clk => rd_clk,
\wr_pntr_bin_reg[6]\(6 downto 0) => p_0_in(6 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2
port map (
D(7 downto 0) => p_2_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out_0(7),
\rd_pntr_bin_reg[6]\(6) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[6]\(5) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[6]\(4) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[6]\(3) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[6]\(2) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[6]\(1) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[6]\(0) => \gsync_stage[2].wr_stg_inst_n_7\,
wr_clk => wr_clk
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
I2 => \^wr_pntr_rd\(1),
I3 => Q(1),
I4 => Q(0),
I5 => \^wr_pntr_rd\(0),
O => ram_empty_i_reg_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(4),
I1 => Q(4),
I2 => \^wr_pntr_rd\(5),
I3 => Q(5),
I4 => Q(7),
I5 => \^wr_pntr_rd\(7),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55554000"
)
port map (
I0 => rst_full_gen_i,
I1 => ram_full_i_i_2_n_0,
I2 => \rd_pntr_bin_reg[0]_0\,
I3 => ram_full_i_i_4_n_0,
I4 => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(5),
I1 => \gic0.gc0.count_reg[7]\(3),
I2 => p_0_out(7),
I3 => \gic0.gc0.count_reg[7]\(5),
I4 => \gic0.gc0.count_reg[7]\(4),
I5 => p_0_out(6),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(2),
I1 => \gic0.gc0.count_reg[7]\(0),
I2 => p_0_out(3),
I3 => \gic0.gc0.count_reg[7]\(1),
I4 => \gic0.gc0.count_reg[7]\(2),
I5 => p_0_out(4),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => p_0_out(7),
I1 => \gic0.gc0.count_d1_reg[7]\(7),
I2 => p_0_out(6),
I3 => \gic0.gc0.count_d1_reg[7]\(6),
I4 => ram_full_i_i_6_n_0,
I5 => ram_full_i_i_7_n_0,
O => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
I4 => \gic0.gc0.count_d1_reg[7]\(2),
I5 => p_0_out(2),
O => ram_full_i_i_6_n_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(3),
I1 => \gic0.gc0.count_d1_reg[7]\(3),
I2 => p_0_out(4),
I3 => \gic0.gc0.count_d1_reg[7]\(4),
I4 => \gic0.gc0.count_d1_reg[7]\(5),
I5 => p_0_out(5),
O => ram_full_i_i_7_n_0
);
\rd_dc_i[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(0),
I1 => Q(0),
O => \rd_dc_i_reg[7]\(0)
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => Q(7),
O => S(3)
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
O => S(2)
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => Q(5),
O => S(1)
);
\rd_dc_i[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(4),
I1 => Q(4),
O => S(0)
);
\rd_dc_i[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => Q(3),
O => \rd_dc_i_reg[7]\(3)
);
\rd_dc_i[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(2),
I1 => Q(2),
O => \rd_dc_i_reg[7]\(2)
);
\rd_dc_i[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => Q(1),
O => \rd_dc_i_reg[7]\(1)
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => p_0_out(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => p_0_out(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => p_0_out(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => p_0_out(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => p_0_out(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out_0(7),
Q => p_0_out(7)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => rd_pntr_gc(7)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(0),
I1 => \gic0.gc0.count_d2_reg[7]\(1),
O => p_0_in6_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(1),
I1 => \gic0.gc0.count_d2_reg[7]\(2),
O => p_0_in6_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(2),
I1 => \gic0.gc0.count_d2_reg[7]\(3),
O => p_0_in6_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(3),
I1 => \gic0.gc0.count_d2_reg[7]\(4),
O => p_0_in6_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(4),
I1 => \gic0.gc0.count_d2_reg[7]\(5),
O => p_0_in6_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(5),
I1 => \gic0.gc0.count_d2_reg[7]\(6),
O => p_0_in6_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(6),
I1 => \gic0.gc0.count_d2_reg[7]\(7),
O => p_0_in6_out(6)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[7]\(7),
Q => wr_pntr_gc(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC;
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_logic : entity is "rd_logic";
end dcfifo_32in_32out_8kb_cnt_rd_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_logic is
signal p_14_out : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
signal rpntr_n_8 : STD_LOGIC;
begin
p_18_out <= \^p_18_out\;
\gras.grdc1.rdc\: entity work.dcfifo_32in_32out_8kb_cnt_rd_dc_as
port map (
Q(0) => Q(0),
S(3 downto 0) => S(3 downto 0),
WR_PNTR_RD(6 downto 0) => WR_PNTR_RD(6 downto 0),
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
\wr_pntr_bin_reg[3]\(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0)
);
\gras.rsts\: entity work.dcfifo_32in_32out_8kb_cnt_rd_status_flags_as
port map (
E(0) => p_14_out,
Q(0) => Q(0),
empty => empty,
p_18_out => \^p_18_out\,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[6]\ => rpntr_n_8
);
rpntr: entity work.dcfifo_32in_32out_8kb_cnt_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0),
E(0) => p_14_out,
Q(0) => Q(0),
WR_PNTR_RD(7 downto 0) => WR_PNTR_RD(7 downto 0),
p_18_out => \^p_18_out\,
ram_empty_i_reg => rpntr_n_8,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[4]\ => \wr_pntr_bin_reg[4]\,
\wr_pntr_bin_reg[6]\ => \wr_pntr_bin_reg[6]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_logic is
port (
full : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_logic : entity is "wr_logic";
end dcfifo_32in_32out_8kb_cnt_wr_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
begin
WEBWE(0) <= \^webwe\(0);
\gwas.wsts\: entity work.dcfifo_32in_32out_8kb_cnt_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.dcfifo_32in_32out_8kb_cnt_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0),
E(0) => \^webwe\(0),
Q(5 downto 0) => Q(5 downto 0),
RD_PNTR_WR(1 downto 0) => RD_PNTR_WR(1 downto 0),
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
p_0_out => p_0_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 is
begin
inst_blk_mem_gen: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_memory : entity is "memory";
end dcfifo_32in_32out_8kb_cnt_memory;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_15\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_16\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_17\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwas.wsts/ram_full_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 2 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.dcfifo_32in_32out_8kb_cnt_clk_x_pntrs
port map (
Q(7 downto 0) => p_20_out(7 downto 0),
RD_PNTR_WR(1 downto 0) => p_0_out(1 downto 0),
S(3) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
S(2) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
S(1) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
\gic0.gc0.count_reg[7]\(5 downto 0) => wr_pntr_plus2(7 downto 2),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_i => \gwas.wsts/ram_full_i\,
rd_clk => rd_clk,
\rd_dc_i_reg[7]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\rd_dc_i_reg[7]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\rd_dc_i_reg[7]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
\rd_dc_i_reg[7]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_19\,
\rd_pntr_bin_reg[0]_0\ => \gntv_or_sync_fifo.gl0.wr_n_1\,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.dcfifo_32in_32out_8kb_cnt_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_20_out(7 downto 0),
Q(0) => RD_RST,
S(3) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
S(2) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
S(1) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
\wr_pntr_bin_reg[3]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\wr_pntr_bin_reg[3]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\wr_pntr_bin_reg[3]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
\wr_pntr_bin_reg[3]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_19\,
\wr_pntr_bin_reg[4]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\,
\wr_pntr_bin_reg[6]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.dcfifo_32in_32out_8kb_cnt_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_9_out(7 downto 0),
Q(5 downto 0) => wr_pntr_plus2(7 downto 2),
RD_PNTR_WR(1 downto 0) => p_0_out(1 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
full => full,
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\,
ram_full_i => \gwas.wsts/ram_full_i\,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.dcfifo_32in_32out_8kb_cnt_memory
port map (
Q(0) => rd_rst_i(0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => p_20_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo
port map (
Q(2) => RD_RST,
Q(1 downto 0) => rd_rst_i(1 downto 0),
\gic0.gc0.count_reg[0]\(1) => \^rst\,
\gic0.gc0.count_reg[0]\(0) => wr_rst_i(0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_top : entity is "fifo_generator_top";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_top is
begin
\grf.rf\: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dcfifo_32in_32out_8kb_cnt : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dcfifo_32in_32out_8kb_cnt : entity is "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dcfifo_32in_32out_8kb_cnt : entity is "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=1,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=8,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dcfifo_32in_32out_8kb_cnt : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dcfifo_32in_32out_8kb_cnt : entity is "fifo_generator_v12_0,Vivado 2015.1";
end dcfifo_32in_32out_8kb_cnt;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 1;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(7 downto 0) => NLW_U0_data_count_UNCONNECTED(7 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(7 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(7 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 |
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