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tnsrb93/G1_RealTimeDCTSteganography | src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_stub.vhdl | 3 | 1553 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_stub.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scfifo_32in_32out_1kb is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end scfifo_32in_32out_1kb;
architecture stub of scfifo_32in_32out_1kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[31:0],wr_en,rd_en,dout[31:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
| gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/xbip_pipe_v3_0_0/hdl/xbip_pipe_v3_0.vhd | 1 | 8323 | `protect begin_protected
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| gpl-3.0 |
trsk/etip | Projekt1/Implementierung/Test_Versions/implementierung1c.vhd | 1 | 3297 | ----
-- This file is part of etip-ss11-g07.
--
-- Copyright (C) 2011 Lukas Märdian <[email protected]>
-- Copyright (C) 2011 M. S.
-- Copyright (C) 2011 Orest Tarasiuk <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY BINBCD IS
PORT(
clk : IN std_logic;
bin_input : IN std_logic_vector (16 DOWNTO 0);
einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0);
overflow : OUT std_logic
);
END BINBCD;
ARCHITECTURE DoubleDabbleV3 OF BINBCD IS
SIGNAL int_input : integer := 0;
BEGIN
int_input <= to_integer(unsigned(bin_input));
IF (int_input <= 99999) THEN
overflow := '0';
ELSE
overflow := '1';
einer := "0000";
zehner := "0000";
hunderter := "0000";
tausender := "0000";
zehntausender := "0000";
END IF;
PROCESS(clk)
VARIABLE vector: std_logic_vector(36 DOWNTO 0) := "00000000000000000000" & bin_input;
VARIABLE int_bcd_seg : integer := 0;
BEGIN
IF (rising_edge(clk)) AND (overflow = '0') THEN
FOR i IN 0 TO 17 LOOP
-- Prüfen, ob größergleich 5; falls ja, dann 3 addieren für:
-- Zehntausender
int_bcd_seg <= to_integer(unsigned(vector(3 DOWNTO 0)));
IF (int_bcd_seg >= 5) THEN
vector(3 DOWNTO 0) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Tausender
int_bcd_seg <= to_integer(unsigned(vector(7 DOWNTO 4)));
IF (int_bcd_seg >= 5) THEN
vector(7 DOWNTO 4) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Hunderter
int_bcd_seg <= to_integer(unsigned(vector(11 DOWNTO 8)));
IF (int_bcd_seg >= 5) THEN
vector(11 DOWNTO 8) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Zehner
int_bcd_seg <= to_integer(unsigned(vector(15 DOWNTO 12)));
IF (int_bcd_seg >= 5) THEN
vector(15 DOWNTO 12) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Einer
int_bcd_seg <= to_integer(unsigned(vector(19 DOWNTO 16)));
IF (int_bcd_seg >= 5) THEN
vector(19 DOWNTO 16) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Shiften:
vector := vector(35 DOWNTO 0) & '0';
END LOOP;
-- Ergebnisse in die jeweiligen Stellen schreiben
zehntausender <= vector(3 DOWNTO 0);
tausender <= vector(7 DOWNTO 4);
hunderter <= vector(11 DOWNTO 8);
zehner <= vector(15 DOWNTO 12);
einer <= vector(19 DOWNTO 16);
END IF;
END PROCESS;
END DoubleDabbleV3;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/bin_cntr.vhd | 9 | 8423 | `protect begin_protected
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| gpl-3.0 |
Project-Bonfire/EHA | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_routing_part_pseudo_checkers.vhd | 3 | 15472 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
else
err_header_not_empty_faulty_drop_packet_in <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
else
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
else
err_header_not_empty_faulty_Req_in_all_zero <= '0';
end if;
end process;
-- Added (according to new design)!
--process (flit_type, empty, Req_L_in, N1_out, E1_out, W1_out, S1_out)
--begin
-- if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
-- err_header_not_empty_Req_L_in <= '1';
-- else
-- err_header_not_empty_Req_L_in <= '0';
-- end if;
--end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; | gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Arbiter_out_one_hot_checkers/RTL/Arbiter_out_one_hot_pseudo.vhd | 3 | 4663 | --Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end Arbiter_out_one_hot_pseudo;
architecture behavior of Arbiter_out_one_hot_pseudo is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
--process (clk, reset)begin
-- if reset = '0' then
-- state <= IDLE;
-- elsif clk'event and clk ='1'then
-- state <= state_in;
-- end if;
--end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, credit)
begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
-- Arbiter_out's prioritization is N,E,W,S and L (N: highest priority)
case state is
when IDLE =>
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and req_X_N = '1' then
grant_Y_N <= '1';
end if;
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and req_X_E = '1' then
grant_Y_E <= '1';
end if;
if req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and req_X_W = '1' then
grant_Y_W <= '1';
end if;
if req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and req_X_S = '1' then
grant_Y_S <= '1';
end if;
if req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others => -- Includes Local state and invalid state(s)
if credit /= "00" and req_X_L = '1' then
grant_Y_L <= '1';
end if;
if req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b_@f060/_primary.vhd | 3 | 9695 | library verilog;
use verilog.vl_types.all;
entity MSS_AHB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHADDR : out vl_logic_vector(19 downto 0);
MSSHWDATA : out vl_logic_vector(31 downto 0);
MSSHTRANS : out vl_logic_vector(1 downto 0);
MSSHSIZE : out vl_logic_vector(1 downto 0);
MSSHLOCK : out vl_logic;
MSSHWRITE : out vl_logic;
MSSHRDATA : in vl_logic_vector(31 downto 0);
MSSHREADY : in vl_logic;
MSSHRESP : in vl_logic;
FABHADDR : in vl_logic_vector(31 downto 0);
FABHWDATA : in vl_logic_vector(31 downto 0);
FABHTRANS : in vl_logic_vector(1 downto 0);
FABHSIZE : in vl_logic_vector(1 downto 0);
FABHMASTLOCK : in vl_logic;
FABHWRITE : in vl_logic;
FABHSEL : in vl_logic;
FABHREADY : in vl_logic;
FABHRDATA : out vl_logic_vector(31 downto 0);
FABHREADYOUT : out vl_logic;
FABHRESP : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
ADC12 : in vl_logic;
ADC13 : in vl_logic;
ADC14 : in vl_logic;
ADC15 : in vl_logic;
ADC16 : in vl_logic;
ADC17 : in vl_logic;
ADC18 : in vl_logic;
ADC19 : in vl_logic;
ADC20 : in vl_logic;
ADC21 : in vl_logic;
ADC22 : in vl_logic;
ADC23 : in vl_logic;
ADC24 : in vl_logic;
ADC25 : in vl_logic;
SDD0 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
TM0 : in vl_logic;
CM0 : in vl_logic;
GNDTM0 : in vl_logic;
VAREF0 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_AHB_F060;
| gpl-3.0 |
bremathx/AoC_VHDL | Mand.vhd | 1 | 216 | --- Entity MAnd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Mand IS
PORT (
A, B: IN STD_LOGIC;
R: OUT STD_LOGIC
);
END Mand;
ARCHITECTURE pure_logic OF Mand IS
BEGIN
R <= (A AND B);
END pure_logic;
| gpl-3.0 |
meaepeppe/FIR_ISA | VHDL/Reg_n.vhd | 1 | 521 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_reg OF Reg_n IS
BEGIN
PROCESS(CLK, RST_n)
BEGIN
IF RST_n = '0' THEN
DOUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
IF EN = '1' THEN
DOUT <= DIN;
END IF;
END IF;
END PROCESS;
END beh_reg;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/Rxy_Reconf_pseudo_checkers.vhd | 9 | 5107 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_tmp)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_tmp) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp <= '0';
end if;
end process;
-- Checked (changed)!
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in /= '0') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '1' and ReConf_FF_in /= '1') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in <= '0';
end if;
end process;
-- Checked (changed)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, Rxy_tmp_in, Rxy_reconf_PE)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '1' and Rxy_tmp_in /= Rxy_reconf_PE) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (Added)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, Rxy_tmp_in, Rxy_tmp)
begin
if ( (((ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '0') or
(ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1')) and Rxy_tmp_in /= Rxy_tmp) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal <= '0';
end if;
end process;
-- Checked (Added)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
-- Checked (updated)!
end; | gpl-3.0 |
meaepeppe/FIR_ISA | VHDL/data_maker_new.vhd | 1 | 2631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity data_maker is
port (
CLK : in std_logic;
RST_n : in std_logic;
VOUT : out std_logic;
DOUT : out std_logic_vector(8 downto 0);
coeffs : out std_logic_vector(80 downto 0);
END_SIM : out std_logic);
end data_maker;
architecture beh of data_maker is
constant tco : time := 1 ns;
signal sEndSim : std_logic;
signal END_SIM_i : std_logic_vector(0 to 10);
signal H0 : std_logic_vector(8 downto 0);
signal H1 : std_logic_vector(8 downto 0);
signal H2 : std_logic_vector(8 downto 0);
signal H3 : std_logic_vector(8 downto 0);
signal H4 : std_logic_vector(8 downto 0);
signal H5 : std_logic_vector(8 downto 0);
signal H6 : std_logic_vector(8 downto 0);
signal H7 : std_logic_vector(8 downto 0);
signal H8 : std_logic_vector(8 downto 0);
begin -- beh
H0 <= conv_std_logic_vector(-2,9);
H1 <= conv_std_logic_vector(-4,9);
H2 <= conv_std_logic_vector(13,9);
H3 <= conv_std_logic_vector(68,9);
H4 <= conv_std_logic_vector(103,9);
H5 <= conv_std_logic_vector(68,9);
H6 <= conv_std_logic_vector(13,9);
H7 <= conv_std_logic_vector(-4,9);
H8 <= conv_std_logic_vector(-2,9);
coeffs <= H8 & H7 & H6 & H5 & H4 & H3 & H2 & H1 & H0;
process (CLK, RST_n)
file fp_in : text open READ_MODE is "./samples.txt";
variable line_in : line;
variable x : integer;
begin -- process
if RST_n = '0' then -- asynchronous reset (active low)
DOUT <= (others => '0') after tco;
VOUT <= '0' after tco;
sEndSim <= '0' after tco;
elsif CLK'event and CLK = '1' then -- rising clock edge
if not endfile(fp_in) then
readline(fp_in, line_in);
read(line_in, x);
DOUT <= conv_std_logic_vector(x, 9) after tco;
VOUT <= '1' after tco;
sEndSim <= '0' after tco;
else
VOUT <= '0' after tco;
sEndSim <= '1' after tco;
end if;
end if;
end process;
process (CLK, RST_n)
begin -- process
if RST_n = '0' then -- asynchronous reset (active low)
END_SIM_i <= (others => '0') after tco;
elsif CLK'event and CLK = '1' then -- rising clock edge
END_SIM_i(0) <= sEndSim after tco;
END_SIM_i(1 to 10) <= END_SIM_i(0 to 9) after tco;
end if;
end process;
END_SIM <= END_SIM_i(10);
end beh;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/delay.vhd | 9 | 9914 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/xilinx_image.vhd | 3 | 181451 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"3c000c243c000c343c343caf24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"0004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c34",
INIT_07 => X"8fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c24",
INIT_08 => X"000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af2400",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"0200004402000044024502c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"00400042020000400243630302020000040510000044024300c34202c2004242",
INIT_07 => X"c20200000405100000040000400500c200004402006202c3c20000c4c2004202",
INIT_08 => X"0000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c24200",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"200000320000007801c20000000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"00000000800000007f00ff0f7f00000700007f00003200000000002000000000",
INIT_07 => X"0000000700007f0000000001200030000000320000000000000008000000007f",
INIT_08 => X"00000000000000000000e810000100ff0300000000007f000008000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"0000ae6c000080407d000110013c38252c3034c80000080804254224feff0808",
INIT_06 => X"002e000000003300fc00fffffc0000f90103fc00aea800000014300014000050",
INIT_07 => X"100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000fc",
INIT_08 => X"0b0705030008382c30342525006000cae90010000020fc20009d180009100100",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/sha256_s1.vhd | 4 | 1178 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:56 06/02/2011
-- Design Name:
-- Module Name: sha256_s1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_s1 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_s1;
architecture Behavioral of sha256_s1 is
begin
q(31 downto 22) <= d(16 downto 7) xor d(18 downto 9);
q(21 downto 0) <= (d(6 downto 0) & d(31 downto 17)) xor (d(8 downto 0) & d(31 downto 19)) xor d(31 downto 10);
end Behavioral;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd | 9 | 10044 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5696)
`protect data_block
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`protect end_protected
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/counter_threshold.vhd | 9 | 3773 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/xbar.vhd | 20 | 1004 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end; | gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/allocator.vhd | 11 | 12730 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end allocator;
architecture behavior of allocator is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
component arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
grant_N_N <= grant_N_N_sig and not empty_N;
grant_N_E <= grant_N_E_sig and not empty_E;
grant_N_W <= grant_N_W_sig and not empty_W;
grant_N_S <= grant_N_S_sig and not empty_S;
grant_N_L <= grant_N_L_sig and not empty_L;
grant_E_N <= grant_E_N_sig and not empty_N;
grant_E_E <= grant_E_E_sig and not empty_E;
grant_E_W <= grant_E_W_sig and not empty_W;
grant_E_S <= grant_E_S_sig and not empty_S;
grant_E_L <= grant_E_L_sig and not empty_L;
grant_W_N <= grant_W_N_sig and not empty_N;
grant_W_E <= grant_W_E_sig and not empty_E;
grant_W_W <= grant_W_W_sig and not empty_W;
grant_W_S <= grant_W_S_sig and not empty_S;
grant_W_L <= grant_W_L_sig and not empty_L;
grant_S_N <= grant_S_N_sig and not empty_N;
grant_S_E <= grant_S_E_sig and not empty_E;
grant_S_W <= grant_S_W_sig and not empty_W;
grant_S_S <= grant_S_S_sig and not empty_S;
grant_S_L <= grant_S_L_sig and not empty_L;
grant_L_N <= grant_L_N_sig and not empty_N;
grant_L_E <= grant_L_E_sig and not empty_E;
grant_L_W <= grant_L_W_sig and not empty_W;
grant_L_S <= grant_L_S_sig and not empty_S;
grant_L_L <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
arb_N_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L);
arb_E_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L);
arb_W_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L);
arb_S_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L);
arb_L_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L);
-- Y is N now
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig);
-- Y is E now
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig);
-- Y is W now
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig);
-- Y is S now
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig);
-- Y is L now
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig);
valid_N <= grant_N;
valid_E <= grant_E;
valid_W <= grant_W;
valid_S <= grant_S;
valid_L <= grant_L;
END;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/LBDR_packet_drop.vhd | 3 | 6278 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
Rxy_tmp <= (others => '0');
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Rxy_tmp <= Rxy_tmp_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_tmp;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig_command = '1'then
Rxy_tmp_in <= Rxy_reconf_PE;
ReConf_FF_in <= '1';
else
Rxy_tmp_in <= Rxy_tmp;
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
elsif Reconfig_command = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= Cx_reconf_PE;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order <= packet_drop;
END; | gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@s@s@e/_primary.vhd | 3 | 4539 | library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
HCLK : in vl_logic;
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
PPE_FIFO_FULL : in vl_logic;
PC0_FLAGS : out vl_logic_vector(3 downto 0);
PC1_FLAGS : out vl_logic_vector(3 downto 0);
PC2_FLAGS : out vl_logic_vector(3 downto 0);
ADC0_CALIBRATE_rise: out vl_logic;
ADC1_CALIBRATE_rise: out vl_logic;
ADC2_CALIBRATE_rise: out vl_logic;
ADC0_CALIBRATE_fall: out vl_logic;
ADC1_CALIBRATE_fall: out vl_logic;
ADC2_CALIBRATE_fall: out vl_logic;
ADC0_DATAVALID_rise: out vl_logic;
ADC1_DATAVALID_rise: out vl_logic;
ADC2_DATAVALID_rise: out vl_logic;
FPGA_TRIGGER : in vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
OBD_FPGA0_CLKOUT: in vl_logic;
OBD_FPGA1_CLKOUT: in vl_logic;
OBD_FPGA2_CLKOUT: in vl_logic;
OBD_FPGA0_DOUT : in vl_logic;
OBD_FPGA1_DOUT : in vl_logic;
OBD_FPGA2_DOUT : in vl_logic;
OBD_DOUT0 : out vl_logic;
OBD_DOUT1 : out vl_logic;
OBD_DOUT2 : out vl_logic;
OBD_CLKOUT0 : out vl_logic;
OBD_CLKOUT1 : out vl_logic;
OBD_CLKOUT2 : out vl_logic;
OBD_ENABLE0 : out vl_logic;
OBD_ENABLE1 : out vl_logic;
OBD_ENABLE2 : out vl_logic;
INREADY : out vl_logic;
SSE_ADC0_RESULTS: out vl_logic;
SSE_ADC1_RESULTS: out vl_logic;
SSE_ADC2_RESULTS: out vl_logic
);
end F2DSS_SSE;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Processor_NI/TB_Package_32_bit_credit_based.vhd | 9 | 15781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_pe_sshft.vhd | 9 | 17501 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
`protect data_block
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`protect end_protected
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@s@s@e_@e@n@g@i@n@e/_primary.vhd | 3 | 3833 | library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_ENGINE is
generic(
RAM_DEBUG : integer := 0
);
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
SSE_TS_CTRL0 : out vl_logic;
SSE_RWB : in vl_logic;
SSE_ADDR : in vl_logic_vector(9 downto 0);
SSE_WDATA : in vl_logic_vector(15 downto 0);
SSE_RDATA_o : out vl_logic_vector(15 downto 0);
PPE_FIFO_FULL : in vl_logic;
PC0_FLAGS_o : out vl_logic_vector(3 downto 0);
PC1_FLAGS_o : out vl_logic_vector(3 downto 0);
PC2_FLAGS_o : out vl_logic_vector(3 downto 0);
ADC0_CALIBRATE_rise: out vl_logic;
ADC1_CALIBRATE_rise: out vl_logic;
ADC2_CALIBRATE_rise: out vl_logic;
ADC0_CALIBRATE_fall: out vl_logic;
ADC1_CALIBRATE_fall: out vl_logic;
ADC2_CALIBRATE_fall: out vl_logic;
ADC0_DATAVALID_rise: out vl_logic;
ADC1_DATAVALID_rise: out vl_logic;
ADC2_DATAVALID_rise: out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_TVC_o : out vl_logic_vector(7 downto 0);
ADC1_TVC_o : out vl_logic_vector(7 downto 0);
ADC2_TVC_o : out vl_logic_vector(7 downto 0);
ADC0_STC_o : out vl_logic_vector(7 downto 0);
ADC1_STC_o : out vl_logic_vector(7 downto 0);
ADC2_STC_o : out vl_logic_vector(7 downto 0);
ADC0_MODE_o : out vl_logic_vector(3 downto 0);
ADC1_MODE_o : out vl_logic_vector(3 downto 0);
ADC2_MODE_o : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL_o : out vl_logic;
ABPOWERON_o : out vl_logic;
ADC0_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER_o : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART_o : out vl_logic;
ADC1_ADCSTART_o : out vl_logic;
ADC2_ADCSTART_o : out vl_logic;
ADC0_PWRDWN_o : out vl_logic;
ADC1_PWRDWN_o : out vl_logic;
ADC2_PWRDWN_o : out vl_logic;
ADC0_ADCRESET_o : out vl_logic;
ADC1_ADCRESET_o : out vl_logic;
ADC2_ADCRESET_o : out vl_logic;
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
DAC0_DATA_o : out vl_logic_vector(23 downto 0);
DAC1_DATA_o : out vl_logic_vector(23 downto 0);
DAC2_DATA_o : out vl_logic_vector(23 downto 0);
DAC0_CTRL_o : out vl_logic_vector(7 downto 0);
DAC1_CTRL_o : out vl_logic_vector(7 downto 0);
DAC2_CTRL_o : out vl_logic_vector(7 downto 0);
PDMA_decode : in vl_logic;
INREADY_o : out vl_logic;
SSE_ADC0_RESULTS_o: out vl_logic;
SSE_ADC1_RESULTS_o: out vl_logic;
SSE_ADC2_RESULTS_o: out vl_logic
);
end F2DSS_SSE_ENGINE;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@r@d@m@u@x/_primary.vhd | 3 | 2940 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_RDMUX is
port(
RAM_RD_B_apbrd_pre: in vl_logic;
RAM_DO_B : in vl_logic_vector(31 downto 0);
ADC0_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : in vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA_PEEK: in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA0 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA1 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA2 : in vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA3 : in vl_logic_vector(31 downto 0);
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_SCRATCH : in vl_logic_vector(31 downto 0);
PPE_SF : in vl_logic_vector(31 downto 0);
ALU_CTRL : in vl_logic_vector(31 downto 0);
ALU_STATUS : in vl_logic_vector(31 downto 0);
ALU_A : in vl_logic_vector(31 downto 0);
ALU_B : in vl_logic_vector(31 downto 0);
ALU_C : in vl_logic_vector(31 downto 0);
ALU_D : in vl_logic_vector(15 downto 0);
ALU_E : in vl_logic_vector(15 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
PPE_FLAGS0 : in vl_logic_vector(31 downto 0);
PPE_FLAGS1 : in vl_logic_vector(31 downto 0);
PPE_FLAGS2 : in vl_logic_vector(31 downto 0);
PPE_FLAGS3 : in vl_logic_vector(31 downto 0);
PPE_SFFLAGS : in vl_logic_vector(31 downto 0);
PADDR : in vl_logic_vector(12 downto 0);
PRDATA_PPE : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_RDMUX;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_differential_inputs/_primary.vhd | 3 | 338 | library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_differential_inputs;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@addr@dec@m3/_primary.vhd | 3 | 324 | library verilog;
use verilog.vl_types.all;
entity AddrDecM3 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDecM3;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_synth.vhd | 9 | 160200 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 116848)
`protect data_block
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`protect end_protected
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_synth.vhd | 9 | 160200 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 116848)
`protect data_block
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| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/eth_dma.vhd | 12 | 6966 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
| gpl-3.0 |
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| gpl-3.0 |
HectorGPala/DAS | Practica6/pong.vhd | 1 | 12274 | --Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Fichero Principal.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pong is
port(
rst: in std_logic;
clk: in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
hsync: out std_logic;
vsync: out std_logic;
disp1 : out std_logic_vector (6 downto 0);--puntos jugador1
disp2 : out std_logic_vector (6 downto 0);--puntos jugador2
sound : out std_logic;
rgb: out std_logic_vector(8 downto 0)
);
end pong;
architecture rtl of pong is
--señales vga:
signal pixelcntout : std_logic_vector (10 downto 0);
signal linecntout : std_logic_vector (9 downto 0);
signal blanking, valor : std_logic;
signal hsync_int,vsync_int,valor_int : std_logic;
signal line : std_logic_vector (7 downto 0);
signal pixel : std_logic_vector (7 downto 0);
signal color : std_logic_vector(8 downto 0);
--registros:
signal raqueta1,raqueta2 : std_logic_vector (6 downto 0);--posicion raquetas
signal pelotax : std_logic_vector (7 downto 0);--posicion pelota eje_x
signal pelotay : std_logic_vector (6 downto 0);--posicion pelota eje_y
--señales de control:
signal addr1,addr2,addx,addy : std_logic;--suma/resta en los registros de raqueta1,raqueta2 y pelota
signal mvr1,mvr2 : std_logic;--movimiento de raquetas y pelota
signal choque,choque_pared,choque_raqueta : std_logic;--señales de deteccion de choque
signal fin1,fin2,fin : std_logic;--señales fin de juego
signal flag : std_logic_vector (4 downto 0);--indica que tecla esta pulsada
--señales PS2:
signal ps2_reg : std_logic_vector (7 downto 0);
signal new_data_s,ack :std_logic;
type states_ps2 is(wait_press,state_f0,wait_depress);
signal current_state_ps2,next_state_ps2 : states_ps2;
signal state_ps2 : std_logic;
--deteccion de eventos:
signal flag_rise : std_logic;
signal fin1_rise,fin2_rise : std_logic;
signal start : std_logic;
--estados de la pelota
type states_ball is (izq_arriba,izq_abajo,der_abajo,der_arriba);
signal current_state,next_state : states_ball;
--marcadores:
signal puntos1,puntos2 : std_logic_vector (3 downto 0);
--timer:
signal timer : std_logic_vector (19 downto 0);
signal fin_timer,fin_juego : std_logic;
--sonido choque:
signal choque_nota : std_logic_vector (17 downto 0);
signal sound_s : std_logic;
--instancias:
component edgedetector is
Port(
rst : in STD_LOGIC;
x : in STD_LOGIC;
clk : in STD_LOGIC;
x_falling_edge : out STD_LOGIC;
x_rising_edge : out STD_LOGIC
);
end component;
component ps2_interface is
port(
clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
new_data_ack : in std_logic;
data : out std_logic_vector(7 downto 0);
new_data : out std_logic
);
end component;
component switch2display7seg is
port(
a : in std_logic_vector(3 downto 0);
b : out std_logic_vector(6 downto 0)
);
end component;
component gen_onda is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector(17 downto 0);
clear : in std_logic;
onda_out : out std_logic
);
end component;
begin
choque_nota <= "010111010101001101";--do en 50MHz
u_gen_onda : gen_onda port map(clk=>clk,rst=>rst,note_in=>choque_nota,clear=>'0',onda_out=>sound_s);
u_ps2 : ps2_interface port map(clk=>clk,rst=>rst,ps2_clk=>ps2_clk,ps2_data=>ps2_data,new_data_ack=>ack,data=>ps2_reg,new_data=>new_data_s);
u_display1 : switch2display7seg port map (a=>puntos1,b=>disp1);
u_display2 : switch2display7seg port map (a=>puntos2,b=>disp2);
u_edge_start : edgedetector port map(rst=>rst,x=>flag(0),clk=>clk,x_falling_edge=>open,x_rising_edge=>flag_rise);
u_edge_fin1 : edgedetector port map(rst=>rst,x=>fin1,clk=>clk,x_falling_edge=>open,x_rising_edge=>fin1_rise);
u_edge_fin2 : edgedetector port map(rst=>rst,x=>fin2,clk=>clk,x_falling_edge=>open,x_rising_edge=>fin2_rise);
--process VGA:
pixelcnt : process(rst,clk)
begin
if(rst='0') then
pixelcntout <= (others=>'0');
elsif(rising_edge(clk)) then
if(pixelcntout = 1588) then
pixelcntout <= (others=>'0');
else
pixelcntout <= pixelcntout+1;
end if;
end if;
end process pixelcnt;
linecnt : process(rst,clk)
begin
if (rst='0') then
linecntout <= (others=>'0');
elsif (rising_edge(clk)) then
if (pixelcntout=1588) then
if (linecntout=527) then
linecntout <= (others=>'0');
else
linecntout <= linecntout+1;
end if;
end if;
end if;
end process linecnt;
signals_out : process(clk,rst)
begin
if(rst = '0') then
hsync <= '0';
vsync <= '0';
valor <= '0';
elsif(rising_edge(clk)) then
hsync <= hsync_int;
vsync <= vsync_int;
valor <= valor_int;
end if;
end process;
hsync_int <= '0' when (pixelcntout > 1304) and (pixelcntout <= 1493) else '1';
vsync_int <= '0' when (linecntout > 493) and (linecntout <= 495) else '1';
blanking <= '1' when (pixelcntout > 1223) or (linecntout > 479) else '0';
valor_int <= not blanking;
rgb <= color when valor = '1' else "000000000";
line <= linecntout(9 downto 2);
pixel <= pixelcntout(10 downto 3);
color <= "111000000" when ((line >= raqueta1) and (line <= raqueta1 +16)) and pixel = 8 else
"000000111" when ((line >= raqueta2) and (line<=raqueta2 +16 )) and pixel = 145 else
"111111111" when (line = 8) or (line = 112) or (pixel = 76 and line(3) = '1') else
"111111000" when (pelotax = pixel) and pelotay = line else
"010100010";
--Movimiento raquetas:
p_raqueta1 : process(clk,rst,addr1,mvr1,fin_timer)
begin
if(rst = '0') then
raqueta1 <= "0110000";--52
elsif(rising_edge(clk)) then
if(mvr1 = '1' and fin_timer = '1') then
if(addr1 = '1' and raqueta1 < 96) then
raqueta1 <= raqueta1 + 1;
elsif(addr1 = '0' and raqueta1 > 8) then
raqueta1 <= raqueta1 - 1;
end if;
end if;
end if;
end process;
mvr1 <= '1' when flag(4) = '1' or flag(3) = '1' else '0';
addr1 <= '1' when flag(3) = '1' else '0';
p_raqueta2 : process(clk,rst,addr2,mvr2,fin_timer)
begin
if(rst = '0') then
raqueta2 <= "0110100";--52
elsif(rising_edge(clk)) then
if(mvr2 = '1' and fin_timer = '1') then
if(addr2 = '1' and raqueta2 < 96) then
raqueta2 <= raqueta2 + 1;
elsif(addr2 = '0' and raqueta2 > 8) then
raqueta2 <= raqueta2 - 1;
end if;
end if;
end if;
end process;
mvr2 <= '1' when flag(2) = '1' or flag(1) = '1' else '0';
addr2 <= '1' when flag(1) = '1' else '0';
--Movimiento pelota:
p_pelotax : process(clk,rst,addx,start,fin_timer)
begin
if(rst = '0') then
pelotax <= "01001100";--76
elsif(rising_edge(clk)) then
if(start = '1' and fin_timer = '1') then
if(addx = '1') then
pelotax <= pelotax + 1;
else
pelotax <= pelotax - 1;
end if;
elsif(flag_rise = '1') then
pelotax <= "01001100";--76
end if;
end if;
end process;
p_pelotay : process(clk,rst,addy,start,fin_timer)
begin
if(rst = '0') then
pelotay <= "0111100";--60
elsif(rising_edge(clk)) then
if(start = '1' and fin_timer = '1') then
if(addy = '1') then
pelotay <= pelotay + 1;
else
pelotay <= pelotay - 1;
end if;
elsif(flag_rise = '1') then
pelotay <= "0111100";--60
end if;
end if;
end process;
--Control Teclado PS2:
state_keyboard : process(clk,rst)
begin
if(rst = '0') then
current_state_ps2 <= wait_press;
elsif(rising_edge(clk)) then
current_state_ps2 <= next_state_ps2;
end if;
end process;
gen_state_ps2 : process(current_state_ps2,ps2_reg,new_data_s)
begin
next_state_ps2 <= current_state_ps2;
case current_state_ps2 is
when wait_press =>
if(ps2_reg = x"f0") then
next_state_ps2 <= state_f0;
end if;
when state_f0 =>
if(new_data_s = '1') then
next_state_ps2 <= wait_depress;
end if;
when wait_depress =>
next_state_ps2 <= wait_press;
end case;
end process;
gen_signals_ps2 : process(current_state_ps2)
begin
case current_state_ps2 is
when wait_press =>
state_ps2 <= '0';
when state_f0 =>
state_ps2 <= '1';
when wait_depress =>
state_ps2 <= '1';
end case;
end process;
p_flags : process(clk,rst,ps2_reg)
begin
if(rst = '0') then
flag <= (others=> '0');
elsif(rising_edge(clk)) then
if(new_data_s = '1') then
if (state_ps2 = '0') then
if(ps2_reg = x"15") then
flag(4) <= '1';
elsif(ps2_reg = x"1C") then
flag(3) <= '1';
elsif(ps2_reg = x"4D") then
flag(2) <= '1';
elsif(ps2_reg = x"4B") then
flag(1) <= '1';
elsif(ps2_reg = x"29") then
flag(0) <= '1';
end if;
else
if(ps2_reg = x"15") then
flag(4) <= '0';
elsif(ps2_reg = x"1C") then
flag(3) <= '0';
elsif(ps2_reg = x"4D") then
flag(2) <= '0';
elsif(ps2_reg = x"4B") then
flag(1) <= '0';
elsif(ps2_reg = x"29") then
flag(0) <= '0';
end if;
end if;
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
--FSM control movimiento pelota:
state_ball : process(clk,rst)
begin
if(rst = '0') then
current_state <= izq_arriba;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
gen_state : process(choque_pared,choque_raqueta,current_state,fin_timer)
begin
next_state <= current_state;
if(choque_raqueta = '1' and fin_timer = '1') then
case current_state is
when izq_arriba =>
next_state <= der_arriba;
when izq_abajo =>
next_state <= der_abajo;
when der_abajo =>
next_state <= izq_abajo;
when der_arriba =>
next_state <= izq_arriba;
end case;
elsif(choque_pared = '1' and fin_timer = '1') then
case current_state is
when izq_arriba =>
next_state <= izq_abajo;
when izq_abajo =>
next_state <= izq_arriba;
when der_abajo =>
next_state <= der_arriba;
when der_arriba =>
next_state <= der_abajo;
end case;
end if;
end process;
gen_signals : process(next_state)
begin
case next_state is
when izq_arriba =>
addx <= '0';
addy <= '0';
when izq_abajo =>
addx <= '0';
addy <= '1';
when der_abajo =>
addx <= '1';
addy <= '1';
when der_arriba =>
addx <= '1';
addy <= '0';
end case;
end process;
--Control arranque/parada/puntos de Juego:
p_fin1 : process(clk,rst,pelotax)
begin
if(rst = '0') then
fin1 <= '0';
elsif(rising_edge(clk)) then
if(pelotax < 8) then
fin1 <= '1';
else
fin1 <= '0';
end if;
end if;
end process;
p_fin2 : process(clk,rst,pelotax)
begin
if(rst = '0') then
fin2 <= '0';
elsif(rising_edge(clk)) then
if(pelotax > 145) then
fin2 <= '1';
else
fin2 <= '0';
end if;
end if;
end process;
p_puntos : process(clk,rst,fin1_rise,fin2_rise)
begin
if(rst = '0') then
puntos1 <= (others=>'0');
puntos2 <= (others=>'0');
elsif(rising_edge(clk)) then
if(fin1_rise = '1') then
puntos2 <= puntos2 + 1;
elsif(fin2_rise = '1') then
puntos1 <= puntos1 + 1;
end if;
end if;
end process;
p_start : process(clk,rst,flag_rise,fin)
begin
if(rst = '0') then
start <= '0';
elsif(rising_edge(clk)) then
if(flag_rise = '1') then
start <= '1';
elsif(fin = '1') then
start <= '0';
end if;
end if;
end process;
fin <= fin1_rise or fin2_rise or fin_juego;
fin_juego <= '1' when puntos1 = "1010" or puntos2 = "1010" else '0';
--temporizacion 50px/s
p_timer : process(clk,rst)
begin
if(rst = '0') then
timer <= (others=>'0');
fin_timer <= '0';
elsif(rising_edge(clk)) then
if(timer = "11110100001000111111") then
fin_timer <= '1';
timer <= (others=>'0');
else
timer <= timer + 1;
fin_timer <= '0';
end if;
end if;
end process;
--Condiciones de choque:
choque <= choque_pared or choque_raqueta;
choque_pared <= '1' when pelotay = 8 or pelotay = 112 else '0';
choque_raqueta <= '1' when (pelotax = 8 and (pelotay >= raqueta1 and pelotay < raqueta1+16)) or (pelotax = 145 and (pelotay >= raqueta2 and pelotay < raqueta2+16)) else '0';
--Activacion sonido:
sound <= choque and sound_s;
end rtl; | gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_cmdsts_if.vhd | 2 | 27844 | -------------------------------------------------------------------------------
-- axi_vdma_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cmdsts_if is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_DM_STATUS_WIDTH : integer := 8;
-- CR608521
-- DataMover status width - is based on mode of operation
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 -- CR591965
-- Specifies VDMA Flush on Frame sync enabled
-- 0 = Disabled
-- 1 = Enabled
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
cmnd_wr : in std_logic ; --
cmnd_data : in std_logic_vector --
((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
cmnd_pending : out std_logic ; --
sts_received : out std_logic ; --
halt : in std_logic ; -- CR613214
stop : in std_logic ; --
crnt_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
dmasr_halt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_cmd_tvalid : out std_logic ; --
s_axis_cmd_tready : in std_logic ; --
s_axis_cmd_tdata : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_sts_tvalid : in std_logic ; --
m_axis_sts_tready : out std_logic ; --
m_axis_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH-1 downto 0) ; -- CR608521
m_axis_sts_tkeep : in std_logic_vector --
((C_DM_STATUS_WIDTH/8)-1 downto 0) ; -- CR608521
s2mm_fsize_more_or_sof_late : in std_logic ; --
s2mm_dmasr_lsize_less_err : in std_logic ; --
--
-- Zero Hsize and/or Vsize. mapped here to combine with interr --
zero_size_err : in std_logic ; -- CR579593/CR579597
-- Frame Mismatch. mapped here to combine with interr --
fsize_mismatch_err : in std_logic ; -- CR591965
lsize_mismatch_err : out std_logic ; -- CR591965
lsize_more_mismatch_err : out std_logic ; -- CR591965
capture_hsize_at_uf_err : out std_logic_vector(15 downto 0) ;
--
-- Datamover status --
err : in std_logic ; --
done : out std_logic ; --
err_o : out std_logic ; --
interr_minus_frame_errors : out std_logic ; --
interr : out std_logic ; --
slverr : out std_logic ; --
decerr : out std_logic ; --
tag : out std_logic_vector(3 downto 0) --
);
end axi_vdma_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
constant PAD_HSIZE : std_logic_vector(22 - HSIZE_DWIDTH downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal slverr_i : std_logic := '0';
signal decerr_i : std_logic := '0';
signal interr_i : std_logic := '0';
signal err_i : std_logic := '0';
signal err_or : std_logic := '0';
signal uf_err : std_logic := '0';
signal of_err : std_logic := '0';
signal undrflo_err : std_logic := '0';
signal ovrflo_err : std_logic := '0';
signal ext_crnt_hsize : std_logic_vector(22 downto 0) := (others => '0');
signal s2mm_dmasr_lsize_less_err_d1 : std_logic := '0';
signal s2mm_dmasr_lsize_less_err_fe : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
slverr <= slverr_i;
decerr <= decerr_i;
interr_minus_frame_errors <= interr_i or zero_size_err;
interr <= interr_i or zero_size_err
or fsize_mismatch_err
or s2mm_fsize_more_or_sof_late ; -- CR591965
-- Asserted with each valid status
sts_received <= m_axis_sts_tvalid and sts_tready;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
s_axis_cmd_tvalid <= '0';
s_axis_cmd_tdata <= (others => '0');
cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(cmnd_wr = '1')then
s_axis_cmd_tvalid <= '1';
s_axis_cmd_tdata <= cmnd_data;
cmnd_pending <= '1';
-- Clear flags when command excepted by datamover or halt issued to datamover and command is pending (CR 671208 ("white line-shift" issue))
elsif(s_axis_cmd_tready = '1'or halt = '1')then
s_axis_cmd_tvalid <= '0';
s_axis_cmd_tdata <= (others => '0');
cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sts_tready <= '0';
else
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
done <= '0';
slverr_i <= '0';
decerr_i <= '0';
interr_i <= '0';
tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_sts_tvalid = '1')then
done <= m_axis_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
slverr_i <= m_axis_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
decerr_i <= m_axis_sts_tdata(DATAMOVER_STS_DECERR_BIT);
interr_i <= m_axis_sts_tdata(DATAMOVER_STS_INTERR_BIT);
tag <= m_axis_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
else
done <= '0';
slverr_i <= '0';
decerr_i <= '0';
interr_i <= '0';
tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Line MisMatch Detection (Datamover underflow or overflow)
-------------------------------------------------------------------------------
-- Status is for MM2S or S2MM with Store and Forward turned OFF
-- therefore Datamover detects overflow and underflow
GEN_STS_EQL_TO_8 : if C_DM_STATUS_WIDTH = 8 generate
begin
of_err <= '0';
uf_err <= '0';
undrflo_err <= '0';
ovrflo_err <= '0';
lsize_mismatch_err <= '0';
lsize_more_mismatch_err <= '0';
capture_hsize_at_uf_err <= (others => '0');
end generate GEN_STS_EQL_TO_8;
-- Status is for S2MM with Store and Forward turned OON (i.e. Indeterimate BTT mode)
-- therefore need to detect overflow and underflow here
GEN_STS_GRTR_THAN_8 : if C_DM_STATUS_WIDTH > 8 generate
begin
-- Pad current hsize up to the full 23 bit BTT
ext_crnt_hsize <= PAD_HSIZE & crnt_hsize;
-- CR608521 - Under Flow or Over Flow error detected
uf_err <= '1' when m_axis_sts_tvalid = '1'
and (ext_crnt_hsize /= m_axis_sts_tdata(BRCVD_MSB_BIT -- Underflow
downto BRCVD_LSB_BIT))
else '0';
of_err <= '1' when m_axis_sts_tvalid = '1'
and (ext_crnt_hsize = m_axis_sts_tdata(BRCVD_MSB_BIT
downto BRCVD_LSB_BIT))
and (m_axis_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0') -- Overflow
else '0';
GEN_CAPTURE_HSIZE_AT_LSIZE_LESS_ERR : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_12 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
S2MM_DMASR_BIT8_D1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_dmasr_lsize_less_err_d1 <= '0';
else
s2mm_dmasr_lsize_less_err_d1 <= s2mm_dmasr_lsize_less_err;
end if;
end if;
end process S2MM_DMASR_BIT8_D1;
s2mm_dmasr_lsize_less_err_fe <= s2mm_dmasr_lsize_less_err_d1 and not s2mm_dmasr_lsize_less_err;
REG_HSIZE_AT_LSIZE_LESS_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or s2mm_dmasr_lsize_less_err_fe = '1')then
capture_hsize_at_uf_err <= (others => '0');
elsif (( m_axis_sts_tvalid = '1' and (ext_crnt_hsize /= m_axis_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT))) and s2mm_dmasr_lsize_less_err = '0')then
capture_hsize_at_uf_err <= m_axis_sts_tdata(23 downto 8);
end if;
end if;
end process REG_HSIZE_AT_LSIZE_LESS_ERR;
end generate GEN_CAPTURE_HSIZE_AT_LSIZE_LESS_ERR;
GEN_NO_CAPTURE_HSIZE_AT_LSIZE_LESS_ERR : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_12 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
capture_hsize_at_uf_err <= (others => '0');
end generate GEN_NO_CAPTURE_HSIZE_AT_LSIZE_LESS_ERR;
-- CR608521- Under Flow or Over Flow error detected
-- Register and hold error
-- CR613214 - need to qualify overflow with datamover halt
REG_UF_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
undrflo_err <= '0';
-- set on underflow or overflow
-- CR609038 qualify with error already being set because on
-- datamover shut down the byte count in the rcved status is
-- invalid.
-- CR613214 - need to qualify overflow with datamover halt
elsif(uf_err = '1' and err_i = '0' and stop = '0' and halt = '0')then
undrflo_err <= '1';
else -- CR591965
undrflo_err <= '0'; -- CR591965
end if;
end if;
end process REG_UF_ERR;
REG_OF_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ovrflo_err <= '0';
-- set on underflow or overflow
-- CR609038 qualify with error already being set because on
-- datamover shut down the byte count in the rcved status is
-- invalid.
-- CR613214 - need to qualify overflow with datamover halt
elsif(of_err = '1' and err_i = '0' and stop = '0' and halt = '0')then
ovrflo_err <= '1';
else -- CR591965
ovrflo_err <= '0'; -- CR591965
end if;
end if;
end process REG_OF_ERR;
-- CR591965
-- pass underflow/overflow to line size mismatch for use
-- in genlock repeat frame logic
lsize_mismatch_err <= undrflo_err;
lsize_more_mismatch_err <= ovrflo_err;
end generate GEN_STS_GRTR_THAN_8;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
-- Flush On Frame Sync disabled therefore...
-- Halt channel on all errors. Done by OR'ing all errors and using
-- to set err_i which is used in axi_vdma_mngr to assert stop. Stop
-- will shut down channel. (CR591965)
GEN_ERR_FOR_NO_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
err_or <= slverr_i -- From DataMover
or decerr_i -- From DataMover
or interr_i -- From DataMover
or zero_size_err -- From axi_vdma_sm
or fsize_mismatch_err; -- From axi_vdma_sm (CR591965)
end generate GEN_ERR_FOR_NO_FLUSH;
-- Flush On Frame Sync enabled therefore...
-- Halt channel on all errors except underflow and overflow (line size mismatch)
-- and frame size mismatch errors. Shutdown is accomplished by OR'ing select errors
-- and using to set err_i which is used in axi_vdma_mngr to assert stop. Stop
-- will shut down channel. (CR591965)
GEN_ERR_FOR_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 1 generate
begin
err_or <= slverr_i -- From DataMover
or decerr_i -- From DataMover
or interr_i -- From DataMover
or zero_size_err; -- From axi_vdma_sm
end generate GEN_ERR_FOR_FLUSH;
-- Log errors into a global error output
ERR_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_i <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif(err_or = '1')then
err_i <= '1';
end if;
end if;
end process ERR_PROCESS;
---- CR609038
err_o <= err_i;
end implementation;
| gpl-3.0 |
fmadotto/DS_sha256 | src/hdl/old_design/full_adder.vhd | 1 | 1278 | -- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- full_adder.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (
x : in std_ulogic;
y : in std_ulogic;
cin : in std_ulogic; -- carry in
sum : out std_ulogic;
cout : out std_ulogic -- carry out
);
end entity full_adder;
architecture behav of full_adder is
begin
sum <= x xor y xor cin;
cout <= (x and y) or (cin and (x xor y));
end architecture behav;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd | 6 | 17324 | -------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/lib_pkg_v1_0/cd7baeb2/hdl/src/vhdl/lib_pkg.vhd | 28 | 16351 | -- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_logic_pkt_fifo.vhd | 6 | 31831 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_as.vhd | 6 | 20484 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424)
`protect data_block
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`protect end_protected
| gpl-3.0 |
HectorGPala/DAS | Practica3/synchronizer.vhd | 1 | 646 | --Practica3 de Diseño Automatico de Sistemas
--Cerrojo Electronico.
--Sincronizador de señal de entrada con clk.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xsync : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal xp : std_logic;
begin
clock : process(clk,rst)
begin
if(rst = '0') then
xp <= '1';
xsync <= '1';
elsif(rising_edge(clk)) then
xp <= x;
xsync <= xp;
end if;
end process;
end rtl;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_reg_mux.vhd | 2 | 592416 | -------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 8 | 24873 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/sim/shd_fifo.vhd | 1 | 33639 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY shd_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END shd_fifo;
ARCHITECTURE shd_fifo_arch OF shd_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF shd_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 9,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 128,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 128,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 511,
C_PROG_FULL_THRESH_NEGATE_VAL => 510,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 9,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 9,
C_WR_DEPTH => 512,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 9,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END shd_fifo_arch;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_ms_strb_set.vhd | 18 | 62690 | -------------------------------------------------------------------------------
-- axi_datamover_ms_strb_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ms_strb_set.vhd
--
-- Description:
-- This module implements a function to detect the most significant strobe
-- bit asserted and outputs the index value of that strobe bit. It can only
-- be used in applications where the asserted strobe bits are contiguous and
-- always asserted from LS to MS bit positions,
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ms_strb_set is
generic (
C_STRB_WIDTH : Integer := 8;
-- Sets the width of the input strobe port
C_INDEX_WIDTH : Integer := 3
-- Sets the width of the ms_strb_index output port
-- Should be log2(C_STRB_WIDTH)
);
port (
-- Input strobe value ------------------------------------------------
strbs_in : in std_logic_vector(C_STRB_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Specifies the index of the most significant strobe set ------------
ms_strb_index : out std_logic_vector(C_INDEX_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Invalid strobe input Indcation ------------------------------------
strb_error : Out std_logic --
-- Indicates an error with the strobe input, either a hole in the --
-- asserted strobes or not asserted from LS bits upwards. --
----------------------------------------------------------------------
);
end entity axi_datamover_ms_strb_set;
architecture implementation of axi_datamover_ms_strb_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_2
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 2-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_2 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(1 downto 0);
begin
var_strb_value := input_strobe(1 downto 0);
case var_strb_value is
when "01" =>
var_ms_strb_index := 0;
when "11" | "10" =>
var_ms_strb_index := 1;
when others =>
var_ms_strb_index := 2;
end case;
Return (var_ms_strb_index);
end function get_ms_index_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_4
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 4-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_4 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(3 downto 0);
begin
var_strb_value := input_strobe(3 downto 0);
case var_strb_value is
when "0001" =>
var_ms_strb_index := 0;
when "0011" | "0010" =>
var_ms_strb_index := 1;
when "0111" | "0110" | "0100" =>
var_ms_strb_index := 2;
when "1111" | "1110" | "1100" | "1000"=>
var_ms_strb_index := 3;
when others =>
var_ms_strb_index := 4;
end case;
Return (var_ms_strb_index);
end function get_ms_index_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_8
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 8-bit wide strobe value.
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_8 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(7 downto 0);
begin
var_strb_value := input_strobe(7 downto 0);
case var_strb_value is
when "00000001" =>
var_ms_strb_index := 0;
when "00000010" =>
var_ms_strb_index := 1;
when "00000100" =>
var_ms_strb_index := 2;
when "00001000" =>
var_ms_strb_index := 3;
when "00010000" =>
var_ms_strb_index := 4;
when "00100000" =>
var_ms_strb_index := 5;
when "01000000" =>
var_ms_strb_index := 6;
when "10000000" =>
var_ms_strb_index := 7;
when others =>
var_ms_strb_index := 8;
end case;
Return (var_ms_strb_index);
end function get_ms_index_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_16
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 16-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_16 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(15 downto 0);
begin
var_strb_value := input_strobe(15 downto 0);
case var_strb_value is
when "0000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000100" =>
var_ms_strb_index := 2;
when "0000000000001000" =>
var_ms_strb_index := 3;
when "0000000000010000" =>
var_ms_strb_index := 4;
when "0000000000100000" =>
var_ms_strb_index := 5;
when "0000000001000000" =>
var_ms_strb_index := 6;
when "0000000010000000" =>
var_ms_strb_index := 7;
when "0000000100000000" =>
var_ms_strb_index := 8;
when "0000001000000000" =>
var_ms_strb_index := 9;
when "0000010000000000" =>
var_ms_strb_index := 10;
when "0000100000000000" =>
var_ms_strb_index := 11;
when "0001000000000000" =>
var_ms_strb_index := 12;
when "0010000000000000" =>
var_ms_strb_index := 13;
when "0100000000000000" =>
var_ms_strb_index := 14;
when "1000000000000000" =>
var_ms_strb_index := 15;
when others =>
var_ms_strb_index := 16;
end case;
Return (var_ms_strb_index);
end function get_ms_index_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_32
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 32-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_32 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(31 downto 0);
begin
var_strb_value := input_strobe(31 downto 0);
case var_strb_value is
when "00000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "01000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "10000000000000000000000000000000" =>
var_ms_strb_index := 31;
when others =>
var_ms_strb_index := 32;
end case;
Return (var_ms_strb_index);
end function get_ms_index_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_64
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_64 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(63 downto 0);
begin
var_strb_value := input_strobe(63 downto 0);
case var_strb_value is
when "0000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "0000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "0000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "0000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "0000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "0000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "0000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "0000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "0000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "0000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "0000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "0000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "0000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "0000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "0000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "0000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "0000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "0000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "0000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "0000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "0000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "0000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "0000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "0000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "0000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "0000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "0000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "0000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "0000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "0000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "0000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "0000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "0000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "0000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "0000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "0000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "0000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "0000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "0000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "0000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "0000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "0000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "0000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "0000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "0000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "0000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "0000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "0000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "0000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "0000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "0000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "0000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "0000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "0000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "0000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "0000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "0000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "0000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "0001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "0010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "0100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "1000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when others =>
var_ms_strb_index := 64;
end case;
Return (var_ms_strb_index);
end function get_ms_index_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_128
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_128 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(127 downto 0);
begin
var_strb_value := input_strobe(127 downto 0);
case var_strb_value is
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 64;
when "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 65;
when "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 66;
when "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 67;
when "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 68;
when "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 69;
when "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 70;
when "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 71;
when "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 72;
when "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 73;
when "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 74;
when "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 75;
when "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 76;
when "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 77;
when "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 78;
when "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 79;
when "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 80;
when "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 81;
when "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 82;
when "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 83;
when "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 84;
when "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 85;
when "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 86;
when "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 87;
when "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 88;
when "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 89;
when "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 90;
when "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 91;
when "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 92;
when "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 93;
when "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 94;
when "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 95;
when "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 96;
when "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 97;
when "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 98;
when "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 99;
when "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 100;
when "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 101;
when "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 102;
when "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 103;
when "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 104;
when "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 105;
when "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 106;
when "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 107;
when "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 108;
when "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 109;
when "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 110;
when "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 111;
when "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 112;
when "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 113;
when "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 114;
when "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 115;
when "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 116;
when "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 117;
when "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 118;
when "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 119;
when "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 120;
when "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 121;
when "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 122;
when "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 123;
when "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 124;
when "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 125;
when "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 126;
when "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 127;
when others =>
var_ms_strb_index := 128;
end case;
Return (var_ms_strb_index);
end function get_ms_index_128;
-- Constants
Constant ERROR_INDEX : natural := C_STRB_WIDTH;
Constant TEMP_NAT_MAX : natural := 255; -- allows for a 0 to 255 strobe index value
Constant TEMP_UN_WIDTH : natural := 8; -- 8 bits allows for a 0 to 255 index value
-- Signals
signal sig_input_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_ms_asserted_index_un : unsigned(C_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_error : std_logic := '0';
signal sig_temp_ms_index_un : unsigned(TEMP_UN_WIDTH-1 downto 0) := (others => '0');
signal sig_temp_ms_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin --(architecture implementation)
-- Assign the ms asserted strobe value
ms_strb_index <= STD_LOGIC_VECTOR(sig_ms_asserted_index_un);
-- Assign the input strobe
sig_input_stbs <= strbs_in ; -- assign input strobes
-- Assign the strobe eror output
strb_error <= sig_strb_error ; -- assign the strobe error output
-- Rip the valid index bits
sig_ms_asserted_index_un <= sig_temp_ms_index_un(C_INDEX_WIDTH-1 downto 0);
-- Assert the Strobe Error output if an out of range index is returned
sig_temp_ms_index_nat <= TO_INTEGER(sig_ms_asserted_index_un) ;
sig_strb_error <= '1'
When (sig_temp_ms_index_nat >= ERROR_INDEX)
else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_temp_ms_index_un <= TO_UNSIGNED( 0, TEMP_UN_WIDTH);
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_2(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 4-bit strobe width case.
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_4(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 8-bit strobe width case.
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_8(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_16(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 32-bit strobe width case.
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_32(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 64-bit strobe width case.
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_64(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 128-bit strobe width case.
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_128(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_128BIT_CASE;
end implementation;
| gpl-3.0 |
fmadotto/DS_sha256 | src/hdl/old_design/reg_H_minus_1.vhd | 1 | 3308 | -- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- reg_H_minus_1.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.std_logic_arith.all; -- signed/unsigned, conv_integer(), conv_std_logic_vector(signal, no. bit)
use ieee.numeric_std.all; -- to_integer()
entity reg_H_minus_1 is
port (
clk : in std_ulogic; -- clock
rstn : in std_ulogic; -- asynchronous active low reset
reg_H_minus_1_en : in std_ulogic; -- enable signal for the H(i-1) registers
reg_H_minus_1_sel : in std_ulogic; -- select signal for the H(i-1) registers
H_i_A,
H_i_B,
H_i_C,
H_i_D,
H_i_E,
H_i_F,
H_i_G,
H_i_H : in std_ulogic_vector(31 downto 0); -- resulting hash value H_(i) from datapath (to be stored)
H_iminus1_A,
H_iminus1_B,
H_iminus1_C,
H_iminus1_D,
H_iminus1_E,
H_iminus1_F,
H_iminus1_G,
H_iminus1_H : out std_ulogic_vector(31 downto 0) -- intermediate hash value H_(i-1)
);
end entity reg_H_minus_1;
architecture behav of reg_H_minus_1 is
type H_array_type is array(0 to 7) of std_ulogic_vector(31 downto 0);
constant H0 : H_array_type := (
x"6a09e667", x"bb67ae85", x"3c6ef372", x"a54ff53a",
x"510e527f", x"9b05688c", x"1f83d9ab", x"5be0cd19"
);
signal H_iminus1 : H_array_type;
begin
process (clk, rstn) -- asynchronous reset
begin
if rstn = '0' then
H_iminus1 <= (others => x"00000000");
elsif clk'event and clk = '1' then
if reg_H_minus_1_en = '1' then
if reg_H_minus_1_sel = '0' then
H_iminus1(0) <= H0(0);
H_iminus1(1) <= H0(1);
H_iminus1(2) <= H0(2);
H_iminus1(3) <= H0(3);
H_iminus1(4) <= H0(4);
H_iminus1(5) <= H0(5);
H_iminus1(6) <= H0(6);
H_iminus1(7) <= H0(7);
elsif reg_H_minus_1_sel = '1' then
H_iminus1(0) <= H_i_A;
H_iminus1(1) <= H_i_B;
H_iminus1(2) <= H_i_C;
H_iminus1(3) <= H_i_D;
H_iminus1(4) <= H_i_E;
H_iminus1(5) <= H_i_F;
H_iminus1(6) <= H_i_G;
H_iminus1(7) <= H_i_H;
end if;
end if;
end if;
end process;
H_iminus1_A <= H_iminus1(0);
H_iminus1_B <= H_iminus1(1);
H_iminus1_C <= H_iminus1(2);
H_iminus1_D <= H_iminus1(3);
H_iminus1_E <= H_iminus1(4);
H_iminus1_F <= H_iminus1(5);
H_iminus1_G <= H_iminus1(6);
H_iminus1_H <= H_iminus1(7);
end architecture behav;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd | 8 | 20893 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
HectorGPala/DAS | Practica4/edgedetector.vhd | 1 | 721 | --Practica4 de Diseño Automatico de Sistemas
--Cronometro.
--Detector de Flancos.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity edgedetector is
port(
rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic
);
end edgedetector;
architecture rtl of edgedetector is
signal q1,q2 : std_logic;
begin
edge : process(clk,rst)
begin
if(rst = '0') then
q1 <= '1';
q2 <= '1';
elsif(rising_edge(clk)) then
q2 <= q1;
q1 <= x;
end if;
end process;
x_falling_edge <= q2 and not(q1);
x_rising_edge <= q1 and not(q2);
end rtl;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_rd_status_cntl.vhd | 18 | 19292 | -------------------------------------------------------------------------------
-- axi_datamover_rd_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_rd_status_cntl is
generic (
C_STS_WIDTH : Integer := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the Status reply
);
port (
-- Clock and Reset input --------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Calculator Status Interface ---------------------------
--
calc2rsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------
-- Address Controller Status Interface ----------------------------
--
addr2rsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- is empty (no commands pending) --
--
addr2rsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
-------------------------------------------------------------------
-- Data Controller Status Interface ---------------------------------------------
--
data2rsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2rsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- is empty (no commands pending) --
--
data2rsc_okay : In std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : In std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : In std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : In std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : Out std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : in std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
----------------------------------------------------------------------------------
-- Command/Status Module Interface ----------------------------------------------
--
rsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2rsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is ready to accept a transfer --
--
rsc2stat_status_valid : Out std_logic ; --
-- Control Signal to the Status Reg/FIFO indicating a new status --
-- output value is valid and ready for transfer --
---------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt ----------------------------------
--
rsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
---------------------------------------------------------------------------
);
end entity axi_datamover_rd_status_cntl;
architecture implementation of axi_datamover_rd_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
-- Signal Declarations --------------------------------------------
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_rsc2status_valid : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_rd_sts_okay_reg : std_logic := '0';
signal sig_rd_sts_interr_reg : std_logic := '0';
signal sig_rd_sts_decerr_reg : std_logic := '0';
signal sig_rd_sts_slverr_reg : std_logic := '0';
signal sig_rd_sts_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_rd_sts_reg : std_logic := '0';
signal sig_push_rd_sts_reg : std_logic := '0';
Signal sig_rd_sts_push_ok : std_logic := '0';
signal sig_rd_sts_reg_empty : std_logic := '0';
signal sig_rd_sts_reg_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the status write output control
rsc2stat_status_valid <= sig_rsc2status_valid ;
sig_rsc2status_valid <= sig_rd_sts_reg_full;
-- Formulate the status outout value (assumes an 8-bit status width)
rsc2stat_status <= sig_rd_sts_okay_reg &
sig_rd_sts_slverr_reg &
sig_rd_sts_decerr_reg &
sig_rd_sts_interr_reg &
sig_tag2status;
-- Detect that a push of a new status word is completing
sig_rd_sts_push_ok <= sig_rsc2status_valid and
stat2rsc_status_ready;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it
rsc2mstr_halt_pipe <= sig_rsc2status_valid and
(not(stat2rsc_status_ready) );
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_rd_sts_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0);
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_rd_sts_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
------- Read Status Collection Logic --------------------------------
rsc2data_ready <= sig_rsc2data_ready ;
sig_rsc2data_ready <= sig_rd_sts_reg_empty;
sig_push_rd_sts_reg <= data2rsc_valid and
sig_rsc2data_ready;
sig_pop_rd_sts_reg <= sig_rd_sts_push_ok;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_STATUS_FIFO_REG
--
-- Process Description:
-- Implement Read status FIFO register.
-- This register holds the Read status from the Data Controller
-- until it is transfered to the Status FIFO.
--
-------------------------------------------------------------
RD_STATUS_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_rd_sts_reg = '1') then
sig_rd_sts_tag_reg <= (others => '0');
sig_rd_sts_interr_reg <= '0';
sig_rd_sts_decerr_reg <= '0';
sig_rd_sts_slverr_reg <= '0';
sig_rd_sts_okay_reg <= '1'; -- set back to default of "OKAY"
sig_rd_sts_reg_full <= '0';
sig_rd_sts_reg_empty <= '1';
Elsif (sig_push_rd_sts_reg = '1') Then
sig_rd_sts_tag_reg <= data2rsc_tag;
sig_rd_sts_interr_reg <= data2rsc_calc_error or
sig_rd_sts_interr_reg;
sig_rd_sts_decerr_reg <= data2rsc_decerr or sig_rd_sts_decerr_reg;
sig_rd_sts_slverr_reg <= data2rsc_slverr or sig_rd_sts_slverr_reg;
sig_rd_sts_okay_reg <= data2rsc_okay and
not(data2rsc_decerr or
sig_rd_sts_decerr_reg or
data2rsc_slverr or
sig_rd_sts_slverr_reg or
data2rsc_calc_error or
sig_rd_sts_interr_reg
);
sig_rd_sts_reg_full <= data2rsc_cmd_cmplt or
data2rsc_calc_error;
sig_rd_sts_reg_empty <= not(data2rsc_cmd_cmplt or
data2rsc_calc_error);
else
null; -- hold current state
end if;
end if;
end process RD_STATUS_FIFO_REG;
end implementation;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd | 6 | 17522 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_lite_if.vhd | 2 | 64732 | -------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_vdma_lite_if is
generic(
C_MM2S_IS : integer range 0 to 1 := 1;
-- Include or exclude MM2S channel
-- 0 = exclude mm2s channel
-- 1 = include mm2s channel
C_S2MM_IS : integer range 0 to 1 := 1;
-- Include or exclude S2MM channel
-- 0 = exclude s2mm channel
-- 1 = include s2mm channel
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1;
-- Specifies the AXI Lite clock is asynchronous
-- 0 = AXI Clocks are Synchronous
-- 1 = AXI Clocks are Asynchronous
C_NUM_CE : integer := 8 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
mm2s_hrd_resetn : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
s2mm_hrd_resetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
axi2ip_lite_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- MM2S Reg Interface signals --
mm2s_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
mm2s_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
mm2s_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- S2MM Reg Interface signals --
s2mm_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
s2mm_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
s2mm_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
axi2ip_common_region_1_rden : out std_logic ; --
axi2ip_common_region_2_rden : out std_logic ; --
--
--
ip2axi_rddata_common_region : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_vdma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal wvalid : std_logic := '0';
signal arvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal s2mm_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal write_response_accepted : std_logic := '0';
signal write_has_started : std_logic := '0';
signal awready_out_i : std_logic := '0';
signal wready_out_i : std_logic := '0';
signal wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal bvalid_out_i : std_logic := '0';
signal read_data_res_accepted : std_logic := '0';
signal read_has_started_i : std_logic := '0';
signal sig_arvalid_arrived : std_logic := '0';
signal sig_arvalid_arrived_d1 : std_logic := '0';
signal sig_arvalid_arrived_d2 : std_logic := '0';
signal sig_arvalid_arrived_d3 : std_logic := '0';
signal sig_arvalid_arrived_d4 : std_logic := '0';
signal sig_arvalid_detected : std_logic := '0';
signal arready_out_i_cmb : std_logic := '0';
signal arready_out_i : std_logic := '0';
signal arready_out_i_mm2s : std_logic := '0';
signal arready_out_i_s2mm : std_logic := '0';
signal arready_out_i_common : std_logic := '0';
signal rvalid_out_i : std_logic := '0';
----Async_mode
signal wready_out_to_bvalid : std_logic := '0';
signal mm2s_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal s2mm_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal addr_region_mm2s_rden_cmb : std_logic := '0';
signal addr_region_s2mm_rden_cmb : std_logic := '0';
signal addr_region_1_common_rden_cmb : std_logic := '0';
signal addr_region_2_common_rden_cmb : std_logic := '0';
signal ip2axi_rddata_captured : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal arready_out_i_d1 : std_logic := '0';
signal sig_awvalid_arrived_d1 : std_logic := '0';
signal sig_awvalid_arrived : std_logic := '0';
signal sig_awvalid_detected : std_logic := '0';
signal sig_wvalid_arrived : std_logic := '0';
signal lite_wr_addr_phase_finished_data_phase_started : std_logic := '0';
signal prepare_wrce : std_logic := '0';
signal prepare_wrce_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite : std_logic := '0';
signal prepare_wrce_pulse_lite_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite_d2 : std_logic := '0';
signal prepare_wrce_pulse_lite_d3 : std_logic := '0';
signal prepare_wrce_pulse_lite_d4 : std_logic := '0';
signal prepare_wrce_pulse_lite_d5 : std_logic := '0';
signal prepare_wrce_pulse_lite_d6 : std_logic := '0';
signal prepare_wrce_pulse_mm2s : std_logic := '0';
signal prepare_wrce_pulse_s2mm : std_logic := '0';
signal wready_mm2s : std_logic := '0';
signal wready_s2mm : std_logic := '0';
signal lite_mm2s_wr_done : std_logic := '0';
signal lite_s2mm_wr_done : std_logic := '0';
signal lite_wr_done : std_logic := '0';
signal lite_wr_done_d1 : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm : std_logic := '0';
signal mm2s_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal s2mm_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ip2axi_rddata_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF ip2axi_rddata_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF mm2s_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF s2mm_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s_axi_lite_awready <= awready_out_i;
s_axi_lite_wready <= wready_out_i;
s_axi_lite_bvalid <= bvalid_out_i;
s_axi_lite_arready <= arready_out_i;
s_axi_lite_rvalid <= rvalid_out_i;
axi2ip_lite_rdaddr(8) <= '0';
axi2ip_lite_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
axi2ip_lite_rdaddr(1) <= '0';
axi2ip_lite_rdaddr(0) <= '0';
mm2s_axi2ip_rdaddr(8) <= '0';
mm2s_axi2ip_rdaddr(1) <= '0';
mm2s_axi2ip_rdaddr(0) <= '0';
s2mm_axi2ip_rdaddr(8) <= '0';
s2mm_axi2ip_rdaddr(1) <= '0';
s2mm_axi2ip_rdaddr(0) <= '0';
s_axi_lite_bresp <= OKAY_RESP;
s_axi_lite_rresp <= OKAY_RESP;
-------------------------------------------------------------------------------------------------
--------------------------- Register AXI4-LITE Control signals ----------------------------------
-------------------------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
wvalid <= '0' ;
arvalid <= '0' ;
awaddr <= (others => '0') ;
wdata <= (others => '0') ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
wvalid <= s_axi_lite_wvalid ;
arvalid <= s_axi_lite_arvalid ;
awaddr <= s_axi_lite_awaddr ;
wdata <= s_axi_lite_wdata ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE WRITE---------------------------------
-------------------------------------------------------------------------------
sig_awvalid_arrived <= awvalid;
sig_wvalid_arrived <= wvalid;
D1_LITE_WR_ADDR_PHASE_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_has_started = '1')then
sig_awvalid_arrived_d1 <= '0';
else
sig_awvalid_arrived_d1 <= sig_awvalid_arrived;
end if;
end if;
end process D1_LITE_WR_ADDR_PHASE_DETECT;
AXI4_LITE_WR_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_response_accepted = '1')then
write_has_started <= '0';
elsif(sig_awvalid_detected = '1')then
write_has_started <= '1';
end if;
end if;
end process AXI4_LITE_WR_STARTED;
sig_awvalid_detected <= sig_awvalid_arrived and not (sig_awvalid_arrived_d1) and not (write_has_started);
--axi2ip_wraddr_captured <= awaddr when sig_awvalid_detected = '1';
CAPTURE_AWADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wraddr_captured(7 downto 2) <= (others => '0');
elsif(sig_awvalid_detected = '1')then
axi2ip_wraddr_captured(7 downto 2) <= awaddr(7 downto 2);
end if;
end if;
end process CAPTURE_AWADDR;
GEN_LITE_AWREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awready_out_i <= '0';
else
awready_out_i <= sig_awvalid_detected;
end if;
end if;
end process GEN_LITE_AWREADY;
GEN_WR_ADDR_PHASE_TO_DATA_PHASE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or wready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '0';
elsif(awready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '1';
end if;
end if;
end process GEN_WR_ADDR_PHASE_TO_DATA_PHASE;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce_gen(j) <= (prepare_wrce and not prepare_wrce_d1) when axi2ip_wraddr_captured
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_GEN;
mm2s_axi2ip_wrce <= wrce_gen;
s2mm_axi2ip_wrce <= wrce_gen;
GEN_LITE_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= (prepare_wrce and not prepare_wrce_d1);
end if;
end if;
end process GEN_LITE_WREADY;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
GEN_LITE_ARREADY_SYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d1;
end if;
end if;
end process GEN_LITE_ARREADY_SYNC;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
AXI4_LITE_RRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_PROCESS;
-------------------------
--*READ
-------------------------
mm2s_axi2ip_wrdata <= wdata;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end generate GEN_LITE_IS_SYNC;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE READ----------------------------------
-------------------------------------------------------------------------------
sig_arvalid_arrived <= arvalid;
D1_LITE_RD_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_has_started_i = '1')then
sig_arvalid_arrived_d1 <= '0';
else
sig_arvalid_arrived_d1 <= sig_arvalid_arrived;
end if;
end if;
end process D1_LITE_RD_DETECT;
AXI4_LITE_RD_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_data_res_accepted = '1')then
read_has_started_i <= '0';
elsif(sig_arvalid_detected = '1')then
read_has_started_i <= '1';
end if;
end if;
end process AXI4_LITE_RD_STARTED;
sig_arvalid_detected <= sig_arvalid_arrived and not (sig_arvalid_arrived_d1) and not (read_has_started_i);
read_data_res_accepted <= rvalid_out_i and s_axi_lite_rready;
CAPTURE_ARADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_captured(7 downto 2) <= (others => '0');
elsif(sig_arvalid_detected = '1')then
axi2ip_rdaddr_captured(7 downto 2) <= araddr(7 downto 2);
end if;
end if;
end process CAPTURE_ARADDR;
-------------------------------------------------------------------------------
-- Decode read_lite_addr MSB to get the region of read access
-------------------------------------------------------------------------------
--*****************************************************************************
-- MM2S_Region_1 (0x00 to 0x1C)
-- MM2S_Region_2 (0x50 to 0x9C)
-- S2MM_Region_1 (0x30 to 0x3C)
-- S2MM_Region_2 (0xA0 to 0xEC)
-- Common_Region_1 (0x20 to 0x2C) (common read only register)
-- Common_Region_2 (0xF0 to 0xFC) (s2mm read-only registers)
--*****************************************************************************
addr_region_1_common_rden_cmb <= ((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)));
addr_region_2_common_rden_cmb <= (axi2ip_rdaddr_captured(7) and axi2ip_rdaddr_captured(6) and axi2ip_rdaddr_captured(5) and axi2ip_rdaddr_captured(4));
--MM2S Region read
addr_region_mm2s_rden_cmb <= (((not axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)))
or
((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5))))
;
--S2MM Region read
addr_region_s2mm_rden_cmb <= (((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5))));
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
AXI4_LITE_WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_out_i <= '0';
elsif(bvalid_out_i = '1' and s_axi_lite_bready = '1')then
bvalid_out_i <= '0';
elsif(wready_out_to_bvalid = '1')then
bvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_WRESP_PROCESS;
write_response_accepted <= bvalid_out_i and s_axi_lite_bready;
axi2ip_common_region_1_rden <= addr_region_1_common_rden_cmb;
GEN_S2MM_COM_REG2_READ : if C_S2MM_IS = 1 generate
axi2ip_common_region_2_rden <= addr_region_2_common_rden_cmb;
end generate GEN_S2MM_COM_REG2_READ;
GEN_NO_S2MM_COM_REG2_READ : if C_S2MM_IS = 0 generate
axi2ip_common_region_2_rden <= '0';
end generate GEN_NO_S2MM_COM_REG2_READ;
--------------------------------------------------------------------------------------------------
--***** ASYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
--Both channels exist and async mode
GEN_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 1 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
----
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
end generate GEN_ASYNC_LITE_ACCESS;
--------------------------------------------
--ASYNC_MODE but only single channel enabled
--------------------------------------------
GEN_S2MM_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 0 and C_S2MM_IS = 1 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--S2MM
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
mm2s_axi2ip_wrdata <= wdata;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
mm2s_axi2ip_wrce <= (others => '0');
end generate GEN_S2MM_ONLY_ASYNC_LITE_ACCESS;
GEN_MM2S_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 0 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
s2mm_axi2ip_wrce <= (others => '0');
end generate GEN_MM2S_ONLY_ASYNC_LITE_ACCESS;
end generate GEN_LITE_IS_ASYNC;
end implementation;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/fifo_generator_v12_0/hdl/fifo_generator_top.vhd | 6 | 36480 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25264)
`protect data_block
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`protect end_protected
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover.vhd | 5 | 73317 | -------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
| gpl-3.0 |
HectorGPala/DAS | Practica5/speaker.vhd | 1 | 3295 | --Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Altavoz.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity speaker is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector (7 downto 0);
new_data : in std_logic;
sound : out std_logic;
ack : out std_logic;
sound_active : out std_logic_vector (7 downto 0)
);
end speaker;
architecture rtl of speaker is
component gen_onda is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector(17 downto 0);
clear : in std_logic;
onda_out : out std_logic
);
end component;
type states_piano is (wait_press,state_f0,wait_depress);
signal current_state,next_state : states_piano;
signal n : std_logic_vector(18 downto 0);
signal silence : std_logic;
signal note_out :std_logic;
signal clear_s,load_note,clear_note : std_logic;
signal reg_note : std_logic_vector (7 downto 0);
begin
--rom memory
n <= "0101110101010011010" when reg_note = x"1c" else--a
"0101100000010010110" when reg_note = x"1d" else--w
"0101001000110011110" when reg_note = x"1b" else--s
"0100111001111001111" when reg_note = x"24" else--e
"0100101000010010010" when reg_note = x"23" else--d
"0100010111101001111" when reg_note = x"2b" else--f
"0100000111111011110" when reg_note = x"2c" else--t
"0011111001000111110" when reg_note = x"34" else--g
"0011101011001001010" when reg_note = x"35" else--y
"0011011101111100011" when reg_note = x"33" else--h
"0011010001011110001" when reg_note = x"3c" else--u
"0011000101101110010" when reg_note = x"3b" else--j
"0010111010100111010" when reg_note = x"42" else--k
"1000000000000000000";
p_state : process(clk,rst)
begin
if (rst = '0') then
current_state <= wait_press;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
gen_state : process(current_state,reg_note,new_data)
begin
next_state <= current_state;
case current_state is
when wait_press =>
if(reg_note = x"f0") then
next_state <= state_f0;
end if;
when state_f0 =>
if(new_data = '1') then
next_state <= wait_depress;
end if;
when wait_depress =>
next_state <= wait_press;
end case;
end process;
gen_signals : process(current_state)
begin
case current_state is
when wait_press =>
load_note <= '1';
clear_note <= '0';
when state_f0 =>
load_note <= '0';
clear_note <= '1';
when wait_depress =>
load_note <= '0';
clear_note <= '0';
end case;
end process;
reg_note_p : process(clk,rst,clear_note)
begin
if(rst = '0') then
reg_note <= x"00";
ack <= '0';
elsif(rising_edge(clk)) then
if(new_data = '1') then
if(clear_note = '1') then
reg_note <= x"00";
elsif(load_note = '1') then
reg_note <= note_in;
end if;
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
silence <= n(18);
sound_active <= reg_note;
clear_s <= '1' when reg_note /= note_in else '0';
sound <= note_out and not(silence);
u_gen_onda : gen_onda port map(clk =>clk,rst=>rst,note_in=>n(17 downto 0),clear=>clear_s,onda_out=>note_out);
end rtl;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/ramfifo/rd_status_flags_as.vhd | 6 | 15251 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9552)
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/fifo_generator_top_bi_sim.vhd | 6 | 28804 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19584)
`protect data_block
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| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd | 6 | 88906 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd | 6 | 75237 | -------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 |
HectorGPala/DAS | Practica6/edgedetector.vhd | 1 | 736 | --Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Detector de Flancos.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity edgedetector is
port(
rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic
);
end edgedetector;
architecture rtl of edgedetector is
signal q1,q2 : std_logic;
begin
edge : process(clk,rst)
begin
if(rst = '0') then
q1 <= '1';
q2 <= '1';
elsif(rising_edge(clk)) then
q2 <= q1;
q1 <= x;
end if;
end process;
x_falling_edge <= q2 and not(q1);
x_rising_edge <= q1 and not(q2);
end rtl;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_sim_netlist.vhdl | 1 | 295785 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jul 8 09:16:27 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_sim_netlist.vhdl}
-- Design : shd_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end shd_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of shd_fifo_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 24) => din(70 downto 63),
DIBDI(23 downto 16) => din(61 downto 54),
DIBDI(15 downto 8) => din(52 downto 45),
DIBDI(7 downto 0) => din(43 downto 36),
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => din(71),
DIPBDIP(2) => din(62),
DIPBDIP(1) => din(53),
DIPBDIP(0) => din(44),
DOADO(31 downto 24) => D(34 downto 27),
DOADO(23 downto 16) => D(25 downto 18),
DOADO(15 downto 8) => D(16 downto 9),
DOADO(7 downto 0) => D(7 downto 0),
DOBDO(31 downto 24) => D(70 downto 63),
DOBDO(23 downto 16) => D(61 downto 54),
DOBDO(15 downto 8) => D(52 downto 45),
DOBDO(7 downto 0) => D(43 downto 36),
DOPADOP(3) => D(35),
DOPADOP(2) => D(26),
DOPADOP(1) => D(17),
DOPADOP(0) => D(8),
DOPBDOP(3) => D(71),
DOPBDOP(2) => D(62),
DOPBDOP(1) => D(53),
DOPBDOP(0) => D(44),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31) => '0',
DIBDI(30 downto 24) => din(55 downto 49),
DIBDI(23) => '0',
DIBDI(22 downto 16) => din(48 downto 42),
DIBDI(15) => '0',
DIBDI(14 downto 8) => din(41 downto 35),
DIBDI(7) => '0',
DIBDI(6 downto 0) => din(34 downto 28),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\,
DOADO(30 downto 24) => D(27 downto 21),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\,
DOADO(22 downto 16) => D(20 downto 14),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\,
DOADO(14 downto 8) => D(13 downto 7),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\,
DOADO(6 downto 0) => D(6 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\,
DOBDO(30 downto 24) => D(55 downto 49),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\,
DOBDO(22 downto 16) => D(48 downto 42),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\,
DOBDO(14 downto 8) => D(41 downto 35),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\,
DOBDO(6 downto 0) => D(34 downto 28),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare : entity is "compare";
end shd_fifo_compare;
architecture STRUCTURE of shd_fifo_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_0 is
port (
ram_full_i : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
comp1 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_0 : entity is "compare";
end shd_fifo_compare_0;
architecture STRUCTURE of shd_fifo_compare_0 is
signal comp2 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_reg[8]\
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF08"
)
port map (
I0 => comp2,
I1 => wr_en,
I2 => p_0_out,
I3 => comp1,
I4 => rst_full_gen_i,
O => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_1 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
p_2_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_1 : entity is "compare";
end shd_fifo_compare_1;
architecture STRUCTURE of shd_fifo_compare_1 is
signal comp0 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \wr_pntr_bin_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBBAAAAAAAA"
)
port map (
I0 => comp0,
I1 => p_2_out,
I2 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => rd_en,
I5 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_2 : entity is "compare";
end shd_fifo_compare_2;
architecture STRUCTURE of shd_fifo_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end shd_fifo_rd_bin_cntr;
architecture STRUCTURE of shd_fifo_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => WR_PNTR_RD(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I3 => WR_PNTR_RD(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I1 => WR_PNTR_RD(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I3 => WR_PNTR_RD(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I1 => WR_PNTR_RD(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I3 => WR_PNTR_RD(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I1 => WR_PNTR_RD(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I3 => WR_PNTR_RD(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => WR_PNTR_RD(8),
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\goreg_bm.dout_i_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_2_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_fwft : entity is "rd_fwft";
end shd_fifo_rd_fwft;
architecture STRUCTURE of shd_fifo_rd_fwft is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[0]_i_1_n_0\ : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair9";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair8";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAEFFF"
)
port map (
I0 => Q(0),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I4 => p_2_out,
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA22"
)
port map (
I0 => empty_fwft_fb,
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I2 => rd_en,
I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => p_2_out,
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => rd_en,
O => E(0)
);
\goreg_bm.dout_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => \goreg_bm.dout_i_reg[127]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => \gpregsm1.curr_fwft_state[0]_i_1_n_0\
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I2 => rd_en,
I3 => p_2_out,
O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[0]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end shd_fifo_reset_blk_ramfifo;
architecture STRUCTURE of shd_fifo_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \shd_fifo_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \shd_fifo_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff;
architecture STRUCTURE of shd_fifo_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_3 is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_3 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_3;
architecture STRUCTURE of shd_fifo_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_4 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_4 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_4;
architecture STRUCTURE of shd_fifo_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
\out\(0) <= Q_reg(8);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => \wr_pntr_bin[2]_i_2_n_0\,
I3 => Q_reg(3),
I4 => Q_reg(2),
I5 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(3),
I2 => Q_reg(2),
I3 => Q_reg(8),
I4 => Q_reg(1),
O => \wr_pntr_bin_reg[7]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(2),
I2 => Q_reg(3),
I3 => \wr_pntr_bin[2]_i_2_n_0\,
O => \wr_pntr_bin_reg[7]\(2)
);
\wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(4),
O => \wr_pntr_bin[2]_i_2_n_0\
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => Q_reg(8),
I4 => Q_reg(6),
I5 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(8),
I4 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(8),
I3 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_5 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_5 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_5;
architecture STRUCTURE of shd_fifo_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
\out\(0) <= Q_reg(8);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(8),
Q => Q_reg(8)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => \rd_pntr_bin[2]_i_2_n_0\,
I3 => Q_reg(3),
I4 => Q_reg(2),
I5 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(3),
I2 => Q_reg(2),
I3 => Q_reg(8),
I4 => Q_reg(1),
O => \rd_pntr_bin_reg[7]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(2),
I2 => Q_reg(3),
I3 => \rd_pntr_bin[2]_i_2_n_0\,
O => \rd_pntr_bin_reg[7]\(2)
);
\rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(4),
O => \rd_pntr_bin[2]_i_2_n_0\
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => Q_reg(8),
I4 => Q_reg(6),
I5 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(8),
I4 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(8),
I3 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_bin_cntr is
port (
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end shd_fifo_wr_bin_cntr;
architecture STRUCTURE of shd_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gic0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_2\ : label is "soft_lutpair15";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) <= \^gic0.gc0.count_d2_reg[7]_0\(7 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gic0.gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gic0.gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gic0.gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => \plusOp__0\(8)
);
\gic0.gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gic0.gc0.count[8]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^q\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[7]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[7]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[7]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[7]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(6),
Q => \^gic0.gc0.count_d2_reg[7]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(7),
Q => \^gic0.gc0.count_d2_reg[7]_0\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(8),
Q => p_12_out(8)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(8),
Q => wr_pntr_plus2(8)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_12_out(8),
I1 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end shd_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of shd_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.shd_fifo_blk_mem_gen_prim_wrapper
port map (
D(71 downto 0) => D(71 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_blk_mem_gen_prim_width__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \shd_fifo_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \shd_fifo_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\
port map (
D(55 downto 0) => D(55 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(55 downto 0) => din(55 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_clk_x_pntrs is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_clk_x_pntrs : entity is "clk_x_pntrs";
end shd_fifo_clk_x_pntrs;
architecture STRUCTURE of shd_fifo_clk_x_pntrs is
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_in7_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_1_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_22_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
WR_PNTR_RD(8 downto 0) <= \^wr_pntr_rd\(8 downto 0);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => \gc0.count_reg[7]\(1),
I2 => \^wr_pntr_rd\(0),
I3 => \gc0.count_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_d1_reg[7]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_d1_reg[7]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_reg[7]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_reg[7]\(0),
O => v1_reg_1(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => \gc0.count_reg[7]\(3),
I2 => \^wr_pntr_rd\(2),
I3 => \gc0.count_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_d1_reg[7]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_d1_reg[7]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_reg[7]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_reg[7]\(2),
O => v1_reg_1(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => \gc0.count_reg[7]\(5),
I2 => \^wr_pntr_rd\(4),
I3 => \gc0.count_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_d1_reg[7]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_d1_reg[7]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_reg[7]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_reg[7]\(4),
O => v1_reg_1(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => \gc0.count_reg[7]\(7),
I2 => \^wr_pntr_rd\(6),
I3 => \gc0.count_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_d1_reg[7]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_d1_reg[7]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_reg[7]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_reg[7]\(6),
O => v1_reg_1(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(8),
I1 => Q(8),
O => ram_empty_fb_i_reg
);
\gsync_stage[1].rd_stg_inst\: entity work.shd_fifo_synchronizer_ff
port map (
D(8 downto 0) => p_3_out(8 downto 0),
Q(8 downto 0) => wr_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.shd_fifo_synchronizer_ff_3
port map (
D(8 downto 0) => p_2_out(8 downto 0),
Q(8 downto 0) => rd_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.shd_fifo_synchronizer_ff_4
port map (
D(8 downto 0) => p_3_out(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(8),
rd_clk => rd_clk,
\wr_pntr_bin_reg[7]\(7 downto 0) => p_0_in(7 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.shd_fifo_synchronizer_ff_5
port map (
D(8 downto 0) => p_2_out(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(8),
\rd_pntr_bin_reg[7]\(7) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[7]\(6) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[7]\(5) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[7]\(4) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[7]\(3) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[7]\(2) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[7]\(1) => \gsync_stage[2].wr_stg_inst_n_7\,
\rd_pntr_bin_reg[7]\(0) => \gsync_stage[2].wr_stg_inst_n_8\,
wr_clk => wr_clk
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_8\,
Q => p_22_out(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => p_22_out(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => p_22_out(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => p_22_out(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => p_22_out(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => p_22_out(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => p_22_out(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => p_22_out(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => RD_PNTR_WR(0)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \rd_pntr_gc[7]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => rd_pntr_gc(8)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(8),
Q => \^wr_pntr_rd\(8)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(0),
I1 => \gic0.gc0.count_d2_reg[8]\(1),
O => p_0_in7_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(1),
I1 => \gic0.gc0.count_d2_reg[8]\(2),
O => p_0_in7_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(2),
I1 => \gic0.gc0.count_d2_reg[8]\(3),
O => p_0_in7_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(3),
I1 => \gic0.gc0.count_d2_reg[8]\(4),
O => p_0_in7_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(4),
I1 => \gic0.gc0.count_d2_reg[8]\(5),
O => p_0_in7_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(5),
I1 => \gic0.gc0.count_d2_reg[8]\(6),
O => p_0_in7_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(6),
I1 => \gic0.gc0.count_d2_reg[8]\(7),
O => p_0_in7_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(7),
I1 => \gic0.gc0.count_d2_reg[8]\(8),
O => p_0_in7_out(7)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[8]\(8),
Q => wr_pntr_gc(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_status_flags_as is
port (
p_2_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_status_flags_as : entity is "rd_status_flags_as";
end shd_fifo_rd_status_flags_as;
architecture STRUCTURE of shd_fifo_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \^p_2_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
p_2_out <= \^p_2_out\;
c0: entity work.shd_fifo_compare_1
port map (
comp1 => comp1,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
p_2_out => \^p_2_out\,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
c1: entity work.shd_fifo_compare_2
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => Q(0),
Q => \^p_2_out\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_status_flags_as : entity is "wr_status_flags_as";
end shd_fifo_wr_status_flags_as;
architecture STRUCTURE of shd_fifo_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_0_out,
O => E(0)
);
c1: entity work.shd_fifo_compare
port map (
comp1 => comp1,
\gic0.gc0.count_d1_reg[8]\ => \gic0.gc0.count_d1_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
c2: entity work.shd_fifo_compare_0
port map (
comp1 => comp1,
\gic0.gc0.count_reg[8]\ => \gic0.gc0.count_reg[8]\,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
wr_en => wr_en
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => p_0_out
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end shd_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of shd_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.shd_fifo_blk_mem_gen_prim_width
port map (
D(71 downto 0) => D(71 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\shd_fifo_blk_mem_gen_prim_width__parameterized0\
port map (
D(55 downto 0) => D(127 downto 72),
E(0) => E(0),
Q(0) => Q(0),
din(55 downto 0) => din(127 downto 72),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_logic is
port (
empty : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_logic : entity is "rd_logic";
end shd_fifo_rd_logic;
architecture STRUCTURE of shd_fifo_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.shd_fifo_rd_fwft
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1) => \gr1.rfwft_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0) => curr_fwft_state(0),
E(0) => \gr1.rfwft_n_1\,
Q(1 downto 0) => Q(1 downto 0),
empty => empty,
\goreg_bm.dout_i_reg[127]\(0) => E(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.shd_fifo_rd_status_flags_as
port map (
Q(0) => Q(1),
\gc0.count_reg[8]\ => rpntr_n_0,
\gpregsm1.curr_fwft_state_reg[1]\(1) => \gr1.rfwft_n_2\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => curr_fwft_state(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
rpntr: entity work.shd_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \gr1.rfwft_n_1\,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
WR_PNTR_RD(8 downto 0) => WR_PNTR_RD(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
ram_empty_fb_i_reg => rpntr_n_0,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_logic is
port (
full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_logic : entity is "wr_logic";
end shd_fifo_wr_logic;
architecture STRUCTURE of shd_fifo_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.shd_fifo_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gic0.gc0.count_d1_reg[8]\ => wpntr_n_0,
\gic0.gc0.count_reg[8]\ => wpntr_n_1,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.shd_fifo_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^e\(0),
Q(7 downto 0) => \gic0.gc0.count_d1_reg[7]\(7 downto 0),
RD_PNTR_WR(0) => RD_PNTR_WR(0),
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) => Q(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_full_fb_i_reg => wpntr_n_0,
ram_full_fb_i_reg_0 => wpntr_n_1,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end shd_fifo_blk_mem_gen_top;
architecture STRUCTURE of shd_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.shd_fifo_blk_mem_gen_generic_cstr
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_v8_3_1_synth is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end shd_fifo_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of shd_fifo_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.shd_fifo_blk_mem_gen_top
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_v8_3_1 is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
end shd_fifo_blk_mem_gen_v8_3_1;
architecture STRUCTURE of shd_fifo_blk_mem_gen_v8_3_1 is
begin
inst_blk_mem_gen: entity work.shd_fifo_blk_mem_gen_v8_3_1_synth
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_memory : entity is "memory";
end shd_fifo_memory;
architecture STRUCTURE of shd_fifo_memory is
signal doutb : STD_LOGIC_VECTOR ( 127 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.shd_fifo_blk_mem_gen_v8_3_1
port map (
D(127 downto 0) => doutb(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(100),
Q => dout(100),
R => Q(0)
);
\goreg_bm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(101),
Q => dout(101),
R => Q(0)
);
\goreg_bm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(102),
Q => dout(102),
R => Q(0)
);
\goreg_bm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(103),
Q => dout(103),
R => Q(0)
);
\goreg_bm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(104),
Q => dout(104),
R => Q(0)
);
\goreg_bm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(105),
Q => dout(105),
R => Q(0)
);
\goreg_bm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(106),
Q => dout(106),
R => Q(0)
);
\goreg_bm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(107),
Q => dout(107),
R => Q(0)
);
\goreg_bm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(108),
Q => dout(108),
R => Q(0)
);
\goreg_bm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(109),
Q => dout(109),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(110),
Q => dout(110),
R => Q(0)
);
\goreg_bm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(111),
Q => dout(111),
R => Q(0)
);
\goreg_bm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(112),
Q => dout(112),
R => Q(0)
);
\goreg_bm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(113),
Q => dout(113),
R => Q(0)
);
\goreg_bm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(114),
Q => dout(114),
R => Q(0)
);
\goreg_bm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(115),
Q => dout(115),
R => Q(0)
);
\goreg_bm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(116),
Q => dout(116),
R => Q(0)
);
\goreg_bm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(117),
Q => dout(117),
R => Q(0)
);
\goreg_bm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(118),
Q => dout(118),
R => Q(0)
);
\goreg_bm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(119),
Q => dout(119),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(120),
Q => dout(120),
R => Q(0)
);
\goreg_bm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(121),
Q => dout(121),
R => Q(0)
);
\goreg_bm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(122),
Q => dout(122),
R => Q(0)
);
\goreg_bm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(123),
Q => dout(123),
R => Q(0)
);
\goreg_bm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(124),
Q => dout(124),
R => Q(0)
);
\goreg_bm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(125),
Q => dout(125),
R => Q(0)
);
\goreg_bm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(126),
Q => dout(126),
R => Q(0)
);
\goreg_bm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(127),
Q => dout(127),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(24),
Q => dout(24),
R => Q(0)
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(25),
Q => dout(25),
R => Q(0)
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(26),
Q => dout(26),
R => Q(0)
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(27),
Q => dout(27),
R => Q(0)
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(28),
Q => dout(28),
R => Q(0)
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(29),
Q => dout(29),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(30),
Q => dout(30),
R => Q(0)
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(31),
Q => dout(31),
R => Q(0)
);
\goreg_bm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(32),
Q => dout(32),
R => Q(0)
);
\goreg_bm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(33),
Q => dout(33),
R => Q(0)
);
\goreg_bm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(34),
Q => dout(34),
R => Q(0)
);
\goreg_bm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(35),
Q => dout(35),
R => Q(0)
);
\goreg_bm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(36),
Q => dout(36),
R => Q(0)
);
\goreg_bm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(37),
Q => dout(37),
R => Q(0)
);
\goreg_bm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(38),
Q => dout(38),
R => Q(0)
);
\goreg_bm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(39),
Q => dout(39),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(40),
Q => dout(40),
R => Q(0)
);
\goreg_bm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(41),
Q => dout(41),
R => Q(0)
);
\goreg_bm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(42),
Q => dout(42),
R => Q(0)
);
\goreg_bm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(43),
Q => dout(43),
R => Q(0)
);
\goreg_bm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(44),
Q => dout(44),
R => Q(0)
);
\goreg_bm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(45),
Q => dout(45),
R => Q(0)
);
\goreg_bm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(46),
Q => dout(46),
R => Q(0)
);
\goreg_bm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(47),
Q => dout(47),
R => Q(0)
);
\goreg_bm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(48),
Q => dout(48),
R => Q(0)
);
\goreg_bm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(49),
Q => dout(49),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(50),
Q => dout(50),
R => Q(0)
);
\goreg_bm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(51),
Q => dout(51),
R => Q(0)
);
\goreg_bm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(52),
Q => dout(52),
R => Q(0)
);
\goreg_bm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(53),
Q => dout(53),
R => Q(0)
);
\goreg_bm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(54),
Q => dout(54),
R => Q(0)
);
\goreg_bm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(55),
Q => dout(55),
R => Q(0)
);
\goreg_bm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(56),
Q => dout(56),
R => Q(0)
);
\goreg_bm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(57),
Q => dout(57),
R => Q(0)
);
\goreg_bm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(58),
Q => dout(58),
R => Q(0)
);
\goreg_bm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(59),
Q => dout(59),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(60),
Q => dout(60),
R => Q(0)
);
\goreg_bm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(61),
Q => dout(61),
R => Q(0)
);
\goreg_bm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(62),
Q => dout(62),
R => Q(0)
);
\goreg_bm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(63),
Q => dout(63),
R => Q(0)
);
\goreg_bm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(64),
Q => dout(64),
R => Q(0)
);
\goreg_bm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(65),
Q => dout(65),
R => Q(0)
);
\goreg_bm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(66),
Q => dout(66),
R => Q(0)
);
\goreg_bm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(67),
Q => dout(67),
R => Q(0)
);
\goreg_bm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(68),
Q => dout(68),
R => Q(0)
);
\goreg_bm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(69),
Q => dout(69),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(70),
Q => dout(70),
R => Q(0)
);
\goreg_bm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(71),
Q => dout(71),
R => Q(0)
);
\goreg_bm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(72),
Q => dout(72),
R => Q(0)
);
\goreg_bm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(73),
Q => dout(73),
R => Q(0)
);
\goreg_bm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(74),
Q => dout(74),
R => Q(0)
);
\goreg_bm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(75),
Q => dout(75),
R => Q(0)
);
\goreg_bm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(76),
Q => dout(76),
R => Q(0)
);
\goreg_bm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(77),
Q => dout(77),
R => Q(0)
);
\goreg_bm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(78),
Q => dout(78),
R => Q(0)
);
\goreg_bm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(79),
Q => dout(79),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(80),
Q => dout(80),
R => Q(0)
);
\goreg_bm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(81),
Q => dout(81),
R => Q(0)
);
\goreg_bm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(82),
Q => dout(82),
R => Q(0)
);
\goreg_bm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(83),
Q => dout(83),
R => Q(0)
);
\goreg_bm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(84),
Q => dout(84),
R => Q(0)
);
\goreg_bm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(85),
Q => dout(85),
R => Q(0)
);
\goreg_bm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(86),
Q => dout(86),
R => Q(0)
);
\goreg_bm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(87),
Q => dout(87),
R => Q(0)
);
\goreg_bm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(88),
Q => dout(88),
R => Q(0)
);
\goreg_bm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(89),
Q => dout(89),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(90),
Q => dout(90),
R => Q(0)
);
\goreg_bm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(91),
Q => dout(91),
R => Q(0)
);
\goreg_bm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(92),
Q => dout(92),
R => Q(0)
);
\goreg_bm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(93),
Q => dout(93),
R => Q(0)
);
\goreg_bm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(94),
Q => dout(94),
R => Q(0)
);
\goreg_bm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(95),
Q => dout(95),
R => Q(0)
);
\goreg_bm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(96),
Q => dout(96),
R => Q(0)
);
\goreg_bm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(97),
Q => dout(97),
R => Q(0)
);
\goreg_bm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(98),
Q => dout(98),
R => Q(0)
);
\goreg_bm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(99),
Q => dout(99),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end shd_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of shd_fifo_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_17_out : STD_LOGIC;
signal p_21_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_5_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.shd_fifo_clk_x_pntrs
port map (
Q(8 downto 0) => p_0_out(8 downto 0),
RD_PNTR_WR(0) => p_22_out(8),
WR_PNTR_RD(8 downto 0) => p_21_out(8 downto 0),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_12_out(7 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\gic0.gc0.count_reg[7]\(7 downto 0) => wr_pntr_plus2(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_1(3 downto 0) => \gwas.wsts/c2/v1_reg\(3 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.shd_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_0_out(8 downto 0),
E(0) => p_5_out,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
WR_PNTR_RD(8 downto 0) => p_21_out(8 downto 0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.shd_fifo_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_11_out(8 downto 0),
E(0) => p_17_out,
Q(7 downto 0) => p_12_out(7 downto 0),
RD_PNTR_WR(0) => p_22_out(8),
full => full,
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => wr_pntr_plus2(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \gwas.wsts/c2/v1_reg\(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.shd_fifo_memory
port map (
E(0) => p_17_out,
Q(0) => rd_rst_i(0),
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_0_out(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out,
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.\shd_fifo_reset_blk_ramfifo__parameterized0\
port map (
Q(1) => \^rst\,
Q(0) => wr_rst_i(0),
\gc0.count_reg[1]\(2) => RD_RST,
\gc0.count_reg[1]\(1 downto 0) => rd_rst_i(1 downto 0),
rd_clk => rd_clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_top : entity is "fifo_generator_top";
end shd_fifo_fifo_generator_top;
architecture STRUCTURE of shd_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.shd_fifo_fifo_generator_ramfifo
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_v13_0_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_v13_0_1_synth : entity is "fifo_generator_v13_0_1_synth";
end shd_fifo_fifo_generator_v13_0_1_synth;
architecture STRUCTURE of shd_fifo_fifo_generator_v13_0_1_synth is
begin
\gconvfifo.rf\: entity work.shd_fifo_fifo_generator_top
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
\reset_gen_ic.rstblk_cc\: entity work.shd_fifo_reset_blk_ramfifo
port map (
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_v13_0_1 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of shd_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of shd_fifo_fifo_generator_v13_0_1 : entity is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of shd_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of shd_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of shd_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_v13_0_1 : entity is "fifo_generator_v13_0_1";
end shd_fifo_fifo_generator_v13_0_1;
architecture STRUCTURE of shd_fifo_fifo_generator_v13_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.shd_fifo_fifo_generator_v13_0_1_synth
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
m_aclk => m_aclk,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of shd_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of shd_fifo : entity is "shd_fifo,fifo_generator_v13_0_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of shd_fifo : entity is "shd_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=128,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=128,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shd_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of shd_fifo : entity is "fifo_generator_v13_0_1,Vivado 2015.4";
end shd_fifo;
architecture STRUCTURE of shd_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.shd_fifo_fifo_generator_v13_0_1
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => rd_clk,
rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd | 6 | 12657 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd | 6 | 12657 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632)
`protect data_block
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`protect end_protected
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_sfifo_autord.vhd | 2 | 22492 | -------------------------------------------------------------------------------
-- axi_vdma_sfifo_autord.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_vdma_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_vdma_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_SYNCHRONIZER_STAGE => MTBF_STAGES,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
--C_WRITE_DEPTH => C_DEPTH,
--C_PRELOAD_REGS => 1, -- 1 = first word fall through
--C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
--C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_mngr.vhd | 1 | 21150 | -------------------------------------------------------------------------------
-- axi_sg_updt_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_mngr.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
ch2_updt_curdesc_wren : in std_logic ; --
ch2_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
s2mm_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_cmnd_wr : std_logic := '0';
signal updt_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH
+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal updt_done : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal updt_interr : std_logic := '0';
signal updt_slverr : std_logic := '0';
signal updt_decerr : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_UPDT_SG : entity axi_vdma_v6_2.axi_sg_updt_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ftch_error => ftch_error ,
-- Channel 1 Control and Status
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set ,
ch1_dma_slverr_set => ch1_dma_slverr_set ,
ch1_dma_decerr_set => ch1_dma_decerr_set ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set ,
ch2_dma_slverr_set => ch2_dma_slverr_set ,
ch2_dma_decerr_set => ch2_dma_decerr_set ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- DataMover Command
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- DataMover Status
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_UPDT_CMDSTS_IF : entity axi_vdma_v6_2.axi_sg_updt_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
-- Scatter Gather Fetch Status
s2mm_err => s2mm_err ,
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr
);
end implementation;
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/fifo_generator_v12_0/hdl/common/shft_wrapper.vhd | 6 | 13889 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8544)
`protect data_block
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/builtin/delay.vhd | 6 | 10088 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/fifo_generator_v12_0/hdl/ramfifo/rd_status_flags_sshft.vhd | 6 | 19232 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12496)
`protect data_block
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`protect end_protected
| gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/sim/design_1_axi_uartlite_0_0.vhd | 1 | 8182 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 4800,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/ramfifo/fifo_generator_ramfifo.vhd | 6 | 89326 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64384)
`protect data_block
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_dc_fwft_ext_as.vhd | 6 | 13630 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fmadotto/DS_sha256 | src/hdl/old_design/sigma_1.vhd | 1 | 1367 | -- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- sigma_1.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity sigma_1 is
port (
x : in std_ulogic_vector(31 downto 0); -- first binary input
o : out std_ulogic_vector(31 downto 0) -- output
);
end entity sigma_1;
architecture behav of sigma_1 is
begin
process(x) -- the process is woken up whenever the input change
begin
o <= to_stdulogicvector((to_bitvector(x) ror 17) xor (to_bitvector(x) ror 19) xor (to_bitvector(x) srl 10));
end process;
end architecture behav; | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/fifo_generator_v12_0/hdl/common/wr_pf_ss.vhd | 6 | 44605 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/builtin/bin_cntr.vhd | 6 | 8597 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4624)
`protect data_block
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1+J/9gfbB4zRIlq3PSTfrnFg49ARnP7hfUbA+G/K59gxltG28JOvyDlK/CnrVAyKW3zDNxd6CGk6
NUohERzUlw==
`protect end_protected
| gpl-3.0 |
terpstra/opa | syn/jtag.vhd | 1 | 5277 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity jtag is
port(
addr_o : out std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
data_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector( 3 downto 0);
we_xor_o : out std_logic;
rstn_o : out std_logic);
end jtag;
architecture rtl of jtag is
constant c_ir_wide : natural := 2;
constant c_IR_GPIO : std_logic_vector := "00";
constant c_IR_ADDR : std_logic_vector := "10";
constant c_IR_DATA : std_logic_vector := "11";
-- Virtual JTAG pins
signal s_tck : std_logic;
signal s_tdi : std_logic;
signal s_tdo : std_logic;
signal s_virtual_state_cdr : std_logic;
signal s_virtual_state_sdr : std_logic;
signal s_virtual_state_udr : std_logic;
signal s_virtual_state_uir : std_logic;
signal s_ir : std_logic_vector(c_ir_wide-1 downto 0);
signal r_ir : std_logic_vector(c_ir_wide-1 downto 0);
signal r_rstn : std_logic := '0';
signal r_xor : std_logic := '0';
signal r_gpio : std_logic_vector( 5 downto 0) := (others => '0');
signal r_addr : std_logic_vector(31 downto 0);
signal r_data : std_logic_vector(31 downto 0);
begin
vjtag : sld_virtual_jtag
generic map(
sld_instance_index => 99,
sld_ir_width => c_ir_wide)
port map(
ir_in => s_ir,
ir_out => r_ir,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => s_tck,
tdi => s_tdi,
tdo => s_tdo,
tms => open,
virtual_state_cdr => s_virtual_state_cdr,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => s_virtual_state_sdr,
virtual_state_udr => s_virtual_state_udr,
virtual_state_uir => s_virtual_state_uir);
jtag : process(s_tck) is
begin
if rising_edge(s_tck) then
if s_virtual_state_uir = '1' then
r_ir <= s_ir;
end if;
if s_virtual_state_cdr = '1' then
case r_ir is
when c_IR_DATA => r_data <= data_i;
when others => null;
end case;
end if;
if s_virtual_state_sdr = '1' then
case r_ir is
when c_IR_GPIO => r_gpio <= s_tdi & r_gpio(r_gpio'high downto r_gpio'low+1);
when c_IR_ADDR => r_addr <= s_tdi & r_addr(r_addr'high downto r_addr'low+1);
when c_IR_DATA => r_data <= s_tdi & r_data(r_data'high downto r_data'low+1);
when others => null;
end case;
end if;
if s_virtual_state_udr = '1' then
case r_ir is
when c_IR_GPIO => r_rstn <= r_gpio(5); r_xor <= r_xor xor r_gpio(4);
when others => null;
end case;
end if;
end if;
end process;
with r_ir select
s_tdo <=
r_gpio(r_gpio'low) when c_IR_GPIO,
r_addr(r_addr'low) when c_IR_ADDR,
r_data(r_data'low) when c_IR_DATA,
'-' when others;
addr_o <= r_addr;
data_o <= r_data;
gpio_o <= r_gpio(gpio_o'range);
we_xor_o <= r_xor;
rstn_o <= r_rstn;
end rtl;
| gpl-3.0 |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/ArithmeticalRightShifter_x16.vhd | 1 | 443 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ArithmeticalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end ArithmeticalRightShifter_x16;
architecture skeleton of ArithmeticalRightShifter_x16 is
begin
process(input) is
begin
for i in 14 downto 0 loop
output(i) <= input(i + 1);
end loop;
output(15) <= input(15);
end process;
end skeleton; | gpl-3.0 |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/ALU_x16.vhd | 1 | 4845 | library ieee;
use ieee.std_logic_1164.all;
entity ALU_x16 is
port (
opcode : IN STD_LOGIC_VECTOR(3 downto 0);
negate : IN STD_LOGIC;
input_A, input_B : IN STD_LOGIC_VECTOR(15 downto 0);
output, overflowMultDiv : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end ALU_x16;
architecture skeleton of ALU_x16 is
component Multiplexer_4x16 is
Port ( Selector : in STD_LOGIC_VECTOR (3 downto 0);
input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0);
input_I, input_J, input_K, input_L, input_M, input_N, input_O, input_P: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Adder_2x16 is
port (
isSubtraction: in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR(15 DOWNTO 0);
carry_out: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end component;
component ArithmeticalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ArithmeticalLogicalLeftShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ArithmeticalComparator_x16 is
Port (
opcodeComp : STD_LOGIC_VECTOR(2 downto 0);
input_A, input_B : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Multiplier_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end component;
component Divider_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end component;
component LogicalAND_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalOR_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalXOR_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal output1, output2, output3, output4, output5, output6 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal output7, outputComparator : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal output14, output15, output0, outputand, outputor, outputxor : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal carryoutMul, carryoutDiv, carryoutAddSub : STD_LOGIC;
signal overMult, overDiv : STD_LOGIC_VECTOR(15 downto 0);
begin
-- 0000
-- 12
-- Soma e Subtração
P0: Adder_2x16 port map(negate, input_A, input_B, carryoutAddSub, output0);
-- 0001
-- Retorna o segundo valor
output1 <= input_B;
P2: LogicalAND_2x16 port map(input_A, input_B, outputand);
P3: LogicalOR_2x16 port map(input_A, input_B, outputor);
P4: LogicalXOR_2x16 port map(input_A, input_B, outputxor);
process(input_A, input_B) begin
if(negate = '0')
then
-- 0010
-- 1
-- And
output2 <= outputand;
-- 0011
-- 1
-- Or
output3 <= outputor;
-- 0100
-- 1
-- Xor
output4 <= outputxor;
else
-- 0010
-- 1
-- Nand
output2 <= not outputand;
-- 0011
-- 1
-- Nor
output3 <= not outputor;
-- 0100
-- 1
-- Xnor
output4 <= not outputxor;
end if;
if(opcode(0) = '0') then
overflowMultDiv <= overMult;
else
overflowMultDiv <= overDiv;
end if;
end process;
-- 0101
-- Shift aritmetico para direita
P5: ArithmeticalRightShifter_x16 port map(input_A, output5);
-- 0110
-- Shift logico para direita
P6: LogicalRightShifter_x16 port map(input_A, output6);
-- 0111
-- Shift aritmetico e logico para esquerda
P7: ArithmeticalLogicalLeftShifter_x16 port map(input_A, output7);
-- 1000
-- Comparadores
P8: ArithmeticalComparator_x16 port map(opcode(2 downto 0), input_A, input_B, outputComparator);
-- 1110
-- 12
-- Multiplicação
p14: Multiplier_2x16 port map(input_A, input_B, output14, overMult, carryoutMul);
-- 1111
-- 12
-- Divisão
p15: Divider_2x16 port map(input_A, input_B, output15, overDiv, carryoutDiv);
Poutput: Multiplexer_4x16 port map (opcode, output0, output1, output2, output3, output4, output5, output6,
output7, outputComparator, outputComparator, outputComparator,
outputComparator, outputComparator,
outputComparator, output14, output15, output);
end skeleton; | gpl-3.0 |
terpstra/opa | opa_tdpram.vhd | 1 | 6339 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
-- Inputs are registered
-- Read output from a port during a write is undefined
-- Simultaneous write to the same address writes 'X's
-- Data read from one port while written by another outputs 'X'
entity opa_tdpram is
generic(
g_width : natural;
g_size : natural;
g_hunks : natural := 1);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
a_wen_i : in std_logic;
a_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
a_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
a_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
a_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0);
b_wen_i : in std_logic;
b_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
b_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
b_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
b_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0));
end opa_tdpram;
architecture rtl of opa_tdpram is
begin
nobe : if g_hunks = 1 generate
simple : block is
type t_memory is array(g_size-1 downto 0) of std_logic_vector(g_width-1 downto 0);
shared variable v_memory : t_memory;
signal a_idx : integer;
signal b_idx : integer;
begin
a_idx <= to_integer(unsigned(a_addr_i));
b_idx <= to_integer(unsigned(b_addr_i));
a : process(clk_i) is
begin
if rising_edge(clk_i) then
if (a_wen_i and a_sel_i(0)) = '1' then
v_memory(a_idx) := a_data_i;
end if;
a_data_o <= v_memory(a_idx);
-- Output undefined during write
if a_wen_i = '1' or (b_wen_i = '1' and a_idx = b_idx) then
a_data_o <= (others => 'X');
end if;
end if;
end process;
b : process(clk_i) is
begin
if rising_edge(clk_i) then
if (b_wen_i and b_sel_i(0)) = '1' then
v_memory(b_idx) := b_data_i;
end if;
b_data_o <= v_memory(b_idx);
-- Output undefined during write
if b_wen_i = '1' or (a_wen_i = '1' and a_idx = b_idx) then
b_data_o <= (others => 'X');
end if;
end if;
end process;
fatal : process(clk_i) is
begin
if rising_edge(clk_i) then
assert (a_idx /= b_idx or a_wen_i = '0' or b_wen_i = '0')
report "Two writes to the same address in opa_tdpram"
severity failure;
end if;
end process;
end block;
end generate;
-- Reduce the dpram to multiple dprams per byte enable
be : if g_hunks > 1 generate
recurse : block is
signal s_clk_i : std_logic;
signal s_rst_n_i : std_logic;
signal s_a_wen_i : std_logic;
signal s_a_sel_i : std_logic_vector(g_hunks-1 downto 0) := (others => '1');
signal s_a_addr_i : std_logic_vector(f_opa_log2(g_size)-1 downto 0);
signal s_a_data_i : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_a_data_o : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_b_wen_i : std_logic;
signal s_b_sel_i : std_logic_vector(g_hunks-1 downto 0) := (others => '1');
signal s_b_addr_i : std_logic_vector(f_opa_log2(g_size)-1 downto 0);
signal s_b_data_i : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_b_data_o : std_logic_vector(g_hunks*g_width-1 downto 0);
begin
-- We have to rename so they don't conflict in recursive component
s_clk_i <= clk_i;
s_rst_n_i <= rst_n_i;
s_a_wen_i <= a_wen_i;
s_a_sel_i <= a_sel_i;
s_a_addr_i <= a_addr_i;
s_a_data_i <= a_data_i;
a_data_o <= s_a_data_o;
s_b_wen_i <= b_wen_i;
s_b_sel_i <= b_sel_i;
s_b_addr_i <= b_addr_i;
s_b_data_i <= b_data_i;
b_data_o <= s_b_data_o;
bex : for i in 0 to g_hunks-1 generate
ram : entity opa_tdpram
generic map(
g_width => g_width,
g_size => g_size)
port map(
clk_i => s_clk_i,
rst_n_i => s_rst_n_i,
a_wen_i => s_a_wen_i,
a_sel_i => s_a_sel_i(i downto i),
a_addr_i => s_a_addr_i,
a_data_i => s_a_data_i((i+1)*g_width-1 downto i*g_width),
a_data_o => s_a_data_o((i+1)*g_width-1 downto i*g_width),
b_wen_i => s_b_wen_i,
b_sel_i => s_b_sel_i(i downto i),
b_addr_i => s_b_addr_i,
b_data_i => s_b_data_i((i+1)*g_width-1 downto i*g_width),
b_data_o => s_b_data_o((i+1)*g_width-1 downto i*g_width));
end generate;
end block;
end generate;
end rtl;
| gpl-3.0 |
terpstra/opa | opa_components_pkg.vhd | 1 | 31295 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
package opa_components_pkg is
type t_dpram_equal is (OPA_OLD, OPA_NEW, OPA_UNDEF);
component opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end component;
-- Inputs are registered
-- Read output from a port during a write is undefined
-- Simultaneous write to the same address writes 'X's
-- Data read from one port while written by another outputs 'X'
component opa_tdpram is
generic(
g_width : natural;
g_size : natural;
g_hunks : natural := 1);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
a_wen_i : in std_logic;
a_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
a_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
a_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
a_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0);
b_wen_i : in std_logic;
b_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
b_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
b_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
b_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0));
end component;
-- Inhibit optimization between these points
component opa_lcell is
port(
a_i : in std_logic;
b_o : out std_logic);
end component;
component opa_prim_ternary is
generic(
g_wide : natural);
port(
a_i : in unsigned(g_wide-1 downto 0);
b_i : in unsigned(g_wide-1 downto 0);
c_i : in unsigned(g_wide-1 downto 0);
x_o : out unsigned(g_wide-1 downto 0));
end component;
component opa_prim_mul is
generic(
g_wide : natural;
g_regout : boolean;
g_regwal : boolean;
g_target : t_opa_target);
port(
clk_i : in std_logic;
a_i : in std_logic_vector( g_wide-1 downto 0);
b_i : in std_logic_vector( g_wide-1 downto 0);
x_o : out std_logic_vector(2*g_wide-1 downto 0));
end component;
component opa_prefixsum is
generic(
g_target : t_opa_target;
g_width : natural;
g_count : natural);
port(
bits_i : in std_logic_vector(g_width-1 downto 0);
count_o : out t_opa_matrix(g_count-1 downto 0, g_width-1 downto 0);
total_o : out std_logic_vector(g_width-1 downto 0));
end component;
component opa_lfsr is
generic(
g_entropy : natural := 0;
g_bits : natural);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
random_o : out std_logic_vector(g_bits-1 downto 0));
end component;
component opa_predict is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Deliver our prediction
icache_stall_i : in std_logic;
icache_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_hit_o : out std_logic;
decode_jump_o : out std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
-- Push a return stack entry
decode_push_i : in std_logic;
decode_ret_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Fixup PC to new target
decode_fault_i : in std_logic;
decode_return_i : in std_logic;
decode_jump_i : in std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
decode_source_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_target_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_return_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_icache is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
predict_stall_o : out std_logic;
predict_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_stb_o : out std_logic;
decode_stall_i : in std_logic;
decode_fault_i : in std_logic;
decode_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_dat_o : out std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
i_cyc_o : out std_logic;
i_stb_o : out std_logic;
i_stall_i : in std_logic;
i_ack_i : in std_logic;
i_err_i : in std_logic;
i_addr_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto 0);
i_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_decode is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Predicted jumps?
predict_hit_i : in std_logic;
predict_jump_i : in std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
-- Push a return stack entry
predict_push_o : out std_logic;
predict_ret_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Fixup PC to new target
predict_fault_o : out std_logic;
predict_return_o : out std_logic;
predict_jump_o : out std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
predict_source_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_target_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_return_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Instructions delivered from icache
icache_stb_i : in std_logic;
icache_stall_o : out std_logic;
icache_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_dat_i : in std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
-- Feed data to the renamer
rename_stb_o : out std_logic;
rename_stall_i : in std_logic;
rename_fast_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_slow_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_order_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_setx_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_geta_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_getb_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
rename_archx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archa_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
-- Accept faults
rename_fault_i : in std_logic;
rename_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
rename_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
rename_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Give the regfile the information EUs will need for these operations
regfile_stb_o : out std_logic;
regfile_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
regfile_arg_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_rename is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Values the decoder needs to provide us
decode_stb_i : in std_logic;
decode_stall_o : out std_logic;
decode_fast_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_slow_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_order_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_setx_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_geta_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_getb_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
decode_archx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
decode_archa_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
decode_archb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
-- Values we provide to the issuer
issue_stb_o : out std_logic;
issue_stall_i : in std_logic;
issue_fast_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_slow_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_order_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_geta_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_getb_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
issue_bakx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_baka_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_bakb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_stata_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
issue_statb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
issue_bakx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Feed faults back up the pipeline
issue_fault_i : in std_logic;
issue_mask_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_fault_o : out std_logic;
decode_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
decode_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_issue is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Values the renamer provides us
rename_stb_i : in std_logic;
rename_stall_o : out std_logic;
rename_fast_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_slow_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_order_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_geta_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_getb_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
rename_bakx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_baka_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_bakb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_stata_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
rename_statb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
rename_bakx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Exceptions from the EUs
eu_oldest_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_retry_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_fault_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_pc_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
eu_pcf_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
eu_pcn_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Selected fault fed back up pipeline
rename_fault_o : out std_logic;
rename_mask_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
rename_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
rename_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Regfile needs to fetch these for EU
regfile_rstb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_geta_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_getb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_aux_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_aux_wide (g_config)-1 downto 0);
regfile_dec_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_ren_wide (g_config)-1 downto 0);
regfile_baka_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
regfile_bakb_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Regfile should capture result from EU
regfile_wstb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_bakx_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Gather information from L1d about aliased loads
l1d_store_i : in std_logic;
l1d_load_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
l1d_addr_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_alias_high(g_isa) downto f_opa_alias_low(g_config));
l1d_mask_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)/8-1 downto 0));
end component;
component opa_regfile is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Record PC + immediate data
decode_stb_i : in std_logic;
decode_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
decode_arg_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
decode_imm_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
decode_pc_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcf_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
decode_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Issue has dispatched these instructions to us
issue_rstb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_geta_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_getb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_aux_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_aux_wide (g_config)-1 downto 0);
issue_dec_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_ren_wide (g_config)-1 downto 0);
issue_baka_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide (g_isa,g_config)-1 downto 0);
issue_bakb_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide (g_isa,g_config)-1 downto 0);
-- Feed the EUs one cycle later (they register this => result is two cycles later)
eu_stb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_rega_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
eu_regb_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
eu_arg_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
eu_imm_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
eu_pc_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
eu_pcf_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
eu_pcn_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Issue has indicated these EUs will write now
issue_wstb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_bakx_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- The results arrive two cycles after the issue said they would
eu_regx_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_fast is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_slow is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_stb_o : out std_logic;
l1d_we_o : out std_logic;
l1d_sext_o : out std_logic;
l1d_size_o : out std_logic_vector(1 downto 0);
l1d_addr_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_oldest_o : out std_logic; -- delivered 1 cycle after stb
l1d_retry_i : in std_logic; -- valid 1 cycle after stb_o
l1d_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0); -- 2 cycles
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
type t_opa_dbus_request is (
OPA_DBUS_WIPE,
OPA_DBUS_IDLE,
OPA_DBUS_WAIT_STORE_LOAD,
OPA_DBUS_STORE_LOAD, -- request forbidden
OPA_DBUS_LOAD_STORE,
OPA_DBUS_WAIT_LOAD,
OPA_DBUS_WAIT_STORE,
OPA_DBUS_LOAD,
OPA_DBUS_STORE); -- request forbidden
component opa_l1d is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- read/writes come from the slow EUs
slow_stb_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_we_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_sext_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_size_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, 1 downto 0);
slow_addr_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
slow_data_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
slow_oldest_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_retry_o : out std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_data_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
-- Share information about the addresses we are loading/storing
issue_store_o : out std_logic;
issue_load_o : out std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
issue_addr_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_alias_high(g_isa) downto f_opa_alias_low(g_config));
issue_mask_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)/8-1 downto 0);
-- L1d requests action
dbus_req_o : out t_opa_dbus_request;
dbus_radr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_way_o : out std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
dbus_wadr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_dirty_o : out std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
dbus_data_o : out std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
dbus_busy_i : in std_logic; -- can accept a req_i
dbus_we_i : in std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
dbus_adr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_valid_i : in std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
dbus_data_i : in std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
pbus_stall_i : in std_logic;
pbus_req_o : out std_logic;
pbus_we_o : out std_logic;
pbus_addr_o : out std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
pbus_sel_o : out std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
pbus_dat_o : out std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
pbus_pop_o : out std_logic;
pbus_full_i : in std_logic;
pbus_err_i : in std_logic;
pbus_dat_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_dbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_cyc_o : out std_logic;
d_stb_o : out std_logic;
d_we_o : out std_logic;
d_stall_i : in std_logic;
d_ack_i : in std_logic;
d_err_i : in std_logic;
d_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
d_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
d_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
d_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_req_i : in t_opa_dbus_request;
l1d_radr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_way_i : in std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_wadr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_dirty_i : in std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_i : in std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
l1d_busy_o : out std_logic; -- can accept a req_i
l1d_we_o : out std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_adr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_valid_o : out std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0));
end component;
component opa_pbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
p_cyc_o : out std_logic;
p_stb_o : out std_logic;
p_we_o : out std_logic;
p_stall_i : in std_logic;
p_ack_i : in std_logic;
p_err_i : in std_logic;
p_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
p_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
p_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
p_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_stall_o : out std_logic; -- stall has an async dep on addr
l1d_req_i : in std_logic;
l1d_we_i : in std_logic;
l1d_addr_i : in std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
l1d_sel_i : in std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
l1d_dat_i : in std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
l1d_pop_i : in std_logic;
l1d_full_o : out std_logic;
l1d_err_o : out std_logic;
l1d_dat_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
end package;
| gpl-3.0 |
terpstra/opa | opa_dpram_altera.vhd | 1 | 6694 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end opa_dpram;
architecture syn of opa_dpram is
constant c_m10k : boolean := g_regin; -- (g_regin and g_size > 32) or (g_equal = OPA_OLD);
constant c_mlab_cin : string := f_opa_choose(g_regin, "OUTCLOCK", "UNREGISTERED");
constant c_mlab_cout : string := f_opa_choose(g_regout, "OUTCLOCK", "UNREGISTERED");
constant c_m10k_cout : string := f_opa_choose(g_regout, "CLOCK0", "UNREGISTERED");
signal s_rdata : std_logic_vector(g_width-1 downto 0);
signal s_bypass : std_logic;
signal r_bypass1 : std_logic;
signal r_bypass2 : std_logic;
signal s_mux_bypass : std_logic;
signal s_wdata : std_logic_vector(g_width-1 downto 0);
signal r_wdata1 : std_logic_vector(g_width-1 downto 0);
signal r_wdata2 : std_logic_vector(g_width-1 downto 0);
signal s_mux_wdata : std_logic_vector(g_width-1 downto 0);
begin
nohw :
assert (g_equal /= OPA_OLD or g_regin)
report "opa_dpram cannot be used in OPA_OLD mode without a registered input"
severity failure;
regout : if not c_m10k generate
ram : altdpram
generic map(
intended_device_family => "Arria V",
indata_aclr => "OFF",
indata_reg => "INCLOCK",
lpm_type => "altdpram",
outdata_aclr => "OFF",
outdata_reg => c_mlab_cout,
ram_block_type => "MLAB",
rdaddress_aclr => "OFF",
rdaddress_reg => c_mlab_cin,
rdcontrol_aclr => "OFF",
rdcontrol_reg => "UNREGISTERED",
read_during_write_mode_mixed_ports => "DONT_CARE",
width => g_width,
widthad => f_opa_log2(g_size),
width_byteena => 1,
wraddress_aclr => "OFF",
wraddress_reg => "INCLOCK",
wrcontrol_aclr => "OFF",
wrcontrol_reg => "INCLOCK")
port map(
outclock => clk_i,
wren => w_en_i,
wraddress => w_addr_i,
data => w_data_i,
inclock => clk_i,
rdaddress => r_addr_i,
q => s_rdata);
end generate;
regin : if c_m10k generate
ram : altsyncram
generic map(
intended_device_family => "Arria V",
address_aclr_b => "NONE",
address_reg_b => "CLOCK0", -- always registered
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => c_m10k_cout,
power_up_uninitialized => "FALSE",
ram_block_type => "M10K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => f_opa_log2(g_size),
widthad_b => f_opa_log2(g_size),
width_a => g_width,
width_b => g_width,
width_byteena_a => 1)
port map(
clock0 => clk_i,
wren_a => w_en_i,
address_a => w_addr_i,
data_a => w_data_i,
address_b => r_addr_i,
q_b => s_rdata);
end generate;
s_wdata <= w_data_i;
s_bypass <= f_opa_bit(r_addr_i = w_addr_i) and w_en_i;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
r_wdata1 <= s_wdata;
r_wdata2 <= r_wdata1;
r_bypass1 <= s_bypass;
r_bypass2 <= r_bypass1;
end if;
end process;
s_mux_bypass <=
s_bypass when (not g_regin and not g_regout) else
r_bypass2 when ( g_regin and g_regout) else
r_bypass1;
s_mux_wdata <=
s_wdata when (not g_regin and not g_regout) else
r_wdata2 when ( g_regin and g_regout) else
r_wdata1;
r_data_o <= s_mux_wdata when (g_equal = OPA_NEW and s_mux_bypass = '1') else s_rdata;
end syn;
| gpl-3.0 |
terpstra/opa | opa_dpram.vhd | 1 | 4182 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end opa_dpram;
architecture rtl of opa_dpram is
type t_memory is array(g_size-1 downto 0) of std_logic_vector(g_width-1 downto 0);
signal r_memory : t_memory := (others => (others => '0'));
signal s_bypass : std_logic;
signal r_bypass : std_logic;
signal sr_bypass : std_logic;
signal s_data_memory : std_logic_vector(g_width-1 downto 0);
signal r_data_memory : std_logic_vector(g_width-1 downto 0);
signal sr_data_memory : std_logic_vector(g_width-1 downto 0);
signal s_data_bypass : std_logic_vector(g_width-1 downto 0);
signal r_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data : std_logic_vector(g_width-1 downto 0);
signal srr_data : std_logic_vector(g_width-1 downto 0);
begin
nohw :
assert (g_equal /= OPA_OLD or g_regin)
report "opa_dpram cannot be used in OPA_OLD mode without a registered input"
severity failure;
s_data_bypass <= w_data_i;
s_data_memory <= r_memory(to_integer(unsigned(r_addr_i))) when f_opa_safe(r_addr_i)='1' else (others => 'X');
s_bypass <= f_opa_eq(r_addr_i, w_addr_i) and w_en_i;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
if w_en_i = '1' then
assert (f_opa_safe(w_addr_i) = '1') report "Attempt to write to a meta-valued address" severity failure;
r_memory(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
r_data_bypass <= s_data_bypass;
r_data_memory <= s_data_memory;
r_bypass <= s_bypass;
srr_data <= sr_data;
end if;
end process;
sr_data_bypass <= r_data_bypass when g_regin else s_data_bypass;
sr_data_memory <= r_data_memory when g_regin else s_data_memory;
sr_bypass <= r_bypass when g_regin else s_bypass;
sr_data <=
sr_data_memory when sr_bypass = '0' or g_equal = OPA_OLD else
sr_data_bypass when g_equal = OPA_NEW else
(others => 'X');
r_data_o <= srr_data when g_regout else sr_data;
end rtl;
| gpl-3.0 |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Divider_2x16.vhd | 1 | 1444 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Divider_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end Divider_2x16;
architecture skeleton of Divider_2x16 is
begin
process(input_A, input_B)
variable inte, rest, howMuch : std_logic_vector (15 downto 0);
variable carry: std_logic;
function shiter (number : std_logic_vector(15 downto 0)) return std_logic_vector is
variable TMP : std_logic_vector(15 downto 0);
begin
for i in 14 downto 0 loop
TMP(i + 1) := number(i);
end loop;
TMP(0) := '0';
return TMP;
end shiter;
begin
carry:='0';
if(input_B = "0000000000000000") then
outputHigh <= "0000000000000000";
outputLow <= "0000000000000000";
howMuch := "0000000000000001";
else
rest := "0000000000000000";
inte := "0000000000000000";
for i in 15 downto 0 loop
rest := shiter(rest);
rest(0) := input_A(i);
if(rest >= input_B) then
rest := rest - input_B;
inte(i) := '1';
end if;
end loop;
outputHigh <= rest;
outputLow <= inte;
end if;
carryOut <= '0';
end process;
end skeleton;
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_defaults.vhd | 9 | 30146 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_logic.vhd | 9 | 47892 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33712)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/delay.vhd | 9 | 9914 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/clk_x_pntrs_builtin.vhd | 9 | 43244 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30272)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/shft_wrapper.vhd | 9 | 13719 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8416)
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd | 9 | 10044 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5696)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_generic_cstr.vhd | 9 | 120061 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 87136)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_pe_sshft.vhd | 9 | 17501 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/axi_reg_slice.vhd | 9 | 17112 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10928)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/wr_pf_ss.vhd | 9 | 30210 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20624)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_logic.vhd | 9 | 37388 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25936)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_bin_cntr.vhd | 9 | 21696 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14320)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_top.vhd | 9 | 71340 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51072)
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_fsm.vhd | 9 | 61290 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43632)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/synchronizer_ff.vhd | 9 | 8467 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4528)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_status_flags_ss.vhd | 9 | 23617 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15744)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_status_flags_sshft.vhd | 9 | 22948 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_synth_comp.vhd | 9 | 18409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_prim_wrapper_v6_init.vhd | 9 | 605511 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 446496)
`protect data_block
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`protect end_protected
| gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/output_blk.vhd | 9 | 27248 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18432)
`protect data_block
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5az8aS6YUIVrISp3Iq6aZ4OMDMXB
`protect end_protected
| gpl-3.0 |
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