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chibby0ne/vhdl-book | Chapter3/tristate_buf_dir/tristate_buf.vhd | 1 | 461 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity tri_state is
--generic declarations
port (
input: in std_logic;
enable: in std_logic;
output: out std_logic;);
end entity;
------------------------------
architecture circuit of tri_state is
--signals and declarations
begin
output <= input when enable = '1' else 'z';
end architecture;
------------------------------
| gpl-3.0 |
makestuff/swled | fifo/vhdl/timer/tb_unit/timer_tb.vhdl | 1 | 2532 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity timer_tb is
end entity;
architecture behavioural of timer_tb is
constant COUNTER_WIDTH : integer := 4;
constant CEILING_WIDTH : integer := 2;
signal sysClk : std_logic;
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
signal ceiling : std_logic_vector(CEILING_WIDTH-1 downto 0);
signal tick : std_logic;
begin
-- Instantiate timer for testing
uut: entity work.timer
generic map(
COUNTER_WIDTH => COUNTER_WIDTH,
CEILING_WIDTH => CEILING_WIDTH
)
port map(
clk_in => sysClk,
ceiling_in => ceiling,
tick_out => tick
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive the timer
process
begin
ceiling <= "00";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "01";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "10";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "11";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "00";
wait;
end process;
end architecture;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/function_13.vhd | 5 | 1336 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_13 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_13 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(13, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/bus_mux.vhd | 1 | 5288 | ---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
function chr_one_zero(int: std_logic) return character is
variable c: character;
begin
case int is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
return c;
end chr_one_zero;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function bin_char(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
variable bitv : std_logic;
begin
r := 1;
for i in slv'range loop
bitv := slv(i);
result(r) := chr_one_zero( bitv );
r := r + 1;
end loop;
return result;
end bin_char;
begin
--
-- Determine value of a_bus
--
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--
-- Determine value of b_bus
--
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
-- BEGIN ENABLE_(BLTZ,BLTZAL)
when BRANCH_LTZ =>
take_branch <= reg_source(31);
-- END ENABLE_(BLTZ,BLTZAL)
-- BEGIN ENABLE_(BLEZ)
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
-- END ENABLE_(BLEZ)
when BRANCH_EQ =>
take_branch <= is_equal;
-- BEGIN ENABLE_(BNE)
when BRANCH_NE =>
take_branch <= not is_equal;
-- END ENABLE_(BNE)
-- BEGIN ENABLE_(BGEZ,BGEZAL)
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
-- END ENABLE_(BGEZ,BGEZAL)
-- DIFFICILE A SUPPRIMER...
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/memory_64k.vhd | 1 | 3719 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:23 07/17/2011
-- Design Name:
-- Module Name: memory_64k - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY memory_64k IS
PORT (
clk : IN STD_LOGIC;
addr_in : IN STD_LOGIC_VECTOR (31 DOWNTO 2);
data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enable : IN STD_LOGIC;
we_select : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END memory_64k;
ARCHITECTURE Behavioral OF memory_64k IS
CONSTANT ADDRESS_WIDTH : NATURAL := 7; -- 2**X = NOMBRE D'OCTETS DE LA MEMOIRE
-- 14 => 16ko of memory
-- 15 => 32ko of memory
-- 16 => 64ko of memory
-- 17 => 128ko of memory
TYPE ptorage_array IS ARRAY(NATURAL RANGE 0 TO (2 ** ADDRESS_WIDTH) / 4 - 1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL memBank1 : ptorage_array;
SIGNAL memBank2 : ptorage_array;
SIGNAL memBank3 : ptorage_array;
SIGNAL memBank4 : ptorage_array;
attribute RAM_STYLE : string;
attribute RAM_STYLE of memBank1: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank2: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank3: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank4: signal is "DISTRIBUTED";
BEGIN
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(0) = '1' then
memBank1(index) <= data_in(7 DOWNTO 0);
end if;
data_out(7 DOWNTO 0) <= memBank1(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(1) = '1' then
memBank2(index) <= data_in(15 DOWNTO 8);
end if;
data_out(15 DOWNTO 8) <= memBank2(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(2) = '1' then
memBank3(index) <= data_in(23 DOWNTO 16);
end if;
data_out(23 DOWNTO 16) <= memBank3(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(3) = '1' then
memBank4(index) <= data_in(31 DOWNTO 24);
end if;
data_out(31 DOWNTO 24) <= memBank4(index);
end if;
end if;
end process;
END Behavioral;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_ROM_iPos.vhd | 1 | 13234 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_ROM_iPos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_ROM_iPos is
type rom_type is array (0 to 576-1) of UNSIGNED(2 downto 0);
constant rom_iPos : rom_type := (
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(2, 3)
);
SIGNAL READ_C : UNSIGNED(11 downto 0);
--SIGNAL WRITE_C : UNSIGNED(11 downto 0);
--SIGNAL ROM_ADR : UNSIGNED(11 downto 0);
--signal IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
--signal WE_BIS : STD_LOGIC;
--signal HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
--WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
--WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
VARIABLE ADR : INTEGER RANGE 0 to 576;
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
OUTPUT_1(2 downto 0) <= "000";
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 12);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
end if;
READ_C <= TEMP;
ADR := to_integer( TEMP );
OUTPUT_1(2 downto 0) <= STD_LOGIC_VECTOR( rom_iPos( ADR ) );
end if;
end process;
OUTPUT_1(31 downto 3) <= "00000000000000000000000000000";
END cRAM; | gpl-3.0 |
chibby0ne/vhdl-book | Chapter10/example10_3_dir/example10_3.vhd | 1 | 709 | library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity testbench is
--generic declarations
end entity testbench;
--------------------------------------
architecture circuit of testbench is
signal clk: std_logic := '0';
signal rst: std_logic := '0';
begin
-- generation of clk with after (concurrent)
clk <= not clk after 10 ns;
-- generation of rst with wait for (sequential)
process
begin
wait for 10 ns;
rst <= '1';
wait for 10 ns;
rst <= '0';
wait;
end process;
-- generation of rst with after (concurrent)
-- rst <= '1' after 10 ns, '0' after 20 ns;
end architecture circuit;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram_xilinx.vhd | 1 | 362811 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 16);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector( 3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(3 downto 0) is address(16 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(15 downto 0);
--Block Data Out
signal block_do: mem32_vector(15 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(3 downto 0);
begin
block_enable<= "0000000000000001" when (enable='1') and (block_sel="0000") else
"0000000000000010" when (enable='1') and (block_sel="0001") else
"0000000000000100" when (enable='1') and (block_sel="0010") else
"0000000000001000" when (enable='1') and (block_sel="0011") else
"0000000000010000" when (enable='1') and (block_sel="0100") else
"0000000000100000" when (enable='1') and (block_sel="0101") else
"0000000001000000" when (enable='1') and (block_sel="0110") else
"0000000010000000" when (enable='1') and (block_sel="0111") else
"0000000100000000" when (enable='1') and (block_sel="1000") else
"0000001000000000" when (enable='1') and (block_sel="1001") else
"0000010000000000" when (enable='1') and (block_sel="1010") else
"0000100000000000" when (enable='1') and (block_sel="1011") else
"0001000000000000" when (enable='1') and (block_sel="1100") else
"0010000000000000" when (enable='1') and (block_sel="1101") else
"0100000000000000" when (enable='1') and (block_sel="1110") else
"1000000000000000" when (enable='1') and (block_sel="1111") else
"0000000000000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-----------------------------------------------------------------------------
--
-- BLOCKS generation
--
-----------------------------------------------------------------------------
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block8: if (block_count > 8) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 9)
--
-----------------------------------------------------------------------------
block9: if (block_count > 9) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 10)
--
-----------------------------------------------------------------------------
block10: if (block_count > 10) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 11)
--
-----------------------------------------------------------------------------
block11: if (block_count > 11) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 12)
--
-----------------------------------------------------------------------------
block12: if (block_count > 12) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block13: if (block_count > 13) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block14: if (block_count > 14) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 15)
--
-----------------------------------------------------------------------------
block15: if (block_count > 15) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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)
port map (
DO => block_do(15)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
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)
port map (
DO => block_do(15)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/function_4.vhd | 4 | 2074 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/uart.vhd | 1 | 7912 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(10 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(10 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(6 downto 0);
signal uart_read2 : std_logic;
signal reg_debug : std_logic_vector(7 downto 0);
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(10 downto 0) :=
-- "01010110110"; -- 80MHz / 11520Hz
-- "01010001011"; -- 75MHz / 11520Hz
-- "01001011111"; -- 70MHz / 11520Hz
-- "01000111100"; -- 66MHz / 11520Hz
-- "01000110100"; -- 65MHz / 11520Hz
-- "01000010010"; -- 60MHz / 11520Hz
-- "00111101110"; -- 57MHz / 11520Hz
-- "00111011101"; -- 55MHz / 11520Hz
"00110110010"; -- 50MHz / 11520Hz
-- "0100011110"; -- 33MHz / 2/57600Hz = 0x11e
-- "10101101101"; -- 80MHz / 57600Hz = 0x56D
-- "1101100100"; -- 50MHz / 57600Hz = 0x364
-- "00110110010"; -- 25MHz / 57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; -- 12.5MHz /57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(10 downto 0);
read_value_reg <= ONES(read_value_reg'length-1 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(10 downto 0);
data_save_reg <= ZERO(17 downto 0);
reg_debug <= ZERO(7 downto 0); -- FOR DEBUGGING PURPOSE ONLY
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(10 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
reg_debug <= data_in; -- FOR DEBUGGING PURPOSE ONLY
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(10 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(10 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(10 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or (enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synopsys synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable hex_output_line : line; -- BLG
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
write(hex_output_line, c); -- BLG
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(output, hex_output_line); -- BLG
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; -- uart_sel
end if; -- rising_edge(clk)
end process; -- uart_proc
end generate; -- uart_logger
-- synopsys synthesis_on
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q8_4_DECISION.vhd | 1 | 720 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q8_4_DECISION is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q8_4_DECISION is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1)
VARIABLE temp : SIGNED(7 downto 0);
begin
temp := SIGNED( INPUT_1(7 downto 0) );
IF temp < TO_SIGNED(0, 8) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( TO_UNSIGNED(0, 32) );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( TO_UNSIGNED(1, 32) );
END IF;
END PROCESS;
-------------------------------------------------------------------------
END; | gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/function_15.vhd | 5 | 1963 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_15 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_15 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(7 downto 0);
variable rTemp2 : SIGNED(7 downto 0);
variable rTemp3 : SIGNED(7 downto 0);
variable rTemp4 : SIGNED(7 downto 0);
variable sTemp1 : STD_LOGIC;
variable sTemp2 : STD_LOGIC;
variable sTemp3 : STD_LOGIC;
variable sTemp4 : STD_LOGIC;
begin
rTemp1 := SIGNED( INPUT_1( 7 downto 0) );
rTemp2 := SIGNED( INPUT_1(15 downto 8) );
rTemp3 := SIGNED( INPUT_1(23 downto 16) );
rTemp4 := SIGNED( INPUT_1(31 downto 24) );
IF rTemp1 <= TO_SIGNED(0, 8) THEN sTemp1 := INPUT_2( 0); ELSE sTemp1 := '0'; END IF;
IF rTemp2 <= TO_SIGNED(0, 8) THEN sTemp2 := INPUT_2( 8); ELSE sTemp2 := '0'; END IF;
IF rTemp3 <= TO_SIGNED(0, 8) THEN sTemp3 := INPUT_2(16); ELSE sTemp3 := '0'; END IF;
IF rTemp4 <= TO_SIGNED(0, 8) THEN sTemp4 := INPUT_2(24); ELSE sTemp4 := '0'; END IF;
OUTPUT_1 <= "0000000" & sTemp4 & "0000000" & sTemp3 & "0000000" & sTemp2 & "0000000" & sTemp1;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/cam/cam_pkg.vhd | 1 | 867 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
PACKAGE cam_pkg IS
FUNCTION divide(a : IN unsigned;
b : IN unsigned) RETURN unsigned;
END; --package cam_pkg declaration
PACKAGE BODY cam_pkg IS
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
END; --package body | gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/fifo_generator_ramfifo.vhd | 9 | 77825 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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KILIssebFQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55872)
`protect data_block
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`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_logic_pkt_fifo.vhd | 9 | 43848 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30720)
`protect data_block
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`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_top.vhd | 9 | 37688 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00442.vhd | 1 | 3069 | -- NEED RESULT: ARCH00442: Lexical elements, separators, and delimiters passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00442
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.2 (1)
-- 13.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00442)
-- ENT00442_Test_Bench(ARCH00442_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00442 of E00000 is
function xory return boolean is
begin
return true ;
end xory ;
begin
P :
process
variable a,b,c,d : integer ; -- this tests , : ;
variable e : WORK.STANDARD_TYPES.t_enum1 ;
variable x,y : boolean := false ;
variable c1, c2 : character := 'w';
type ary is array ( integer range <> ) of boolean ;
subtype s_ary is ary (-1 to 1) ;
subtype string3 is string (1 to 3) ;
variable sa : s_ary ;
variable s1,s2 : string3 ;
begin
a := 15 ;
b := 10 ;
c := 12 ;
d := 4 ;
e := WORK.STANDARD_TYPES.en1 ;
s1 := "abc" ;
s2 := "def" ;
for i in integer (-1) to 1 loop
sa (i) := boolean'val(abs(i)) ;
end loop ;
case c1 is -- this tests | => :=
when 'x' | 'y' =>
c2 := '1' ;
when 'w' | 'z' =>
c2 := '2' ;
when others =>
c2 := '3' ;
end case ;
test_report ( "ARCH00442" ,
"Lexical elements, separators, and delimiters" ,
(c1 = 'w' and c2 = '2') and
-- this tests + - * / = ( ) **
( ((a+b-1)*(c/d))**2 = ((15+10-1)*(12/4))**2 ) and
-- this tests < >
( a > b and d < c ) and
-- this tests /= <= >=
( a >= b and d <= c and b /= c ) and
-- this tests &
( s1 & s2 = "abcdef" ) and
-- this tests . '
( WORK.STANDARD_TYPES.t_enum1'pos(e) = 0 ) and
-- these test <> (from the definition of type ary)
(sa(-1) = true) and
(sa(0) = false) and
(sa(1) = true) and
-- these test 13.2 (2)
( x or y = false ) and
( xory = true )
) ;
wait ;
end process P ;
end ARCH00442 ;
entity ENT00442_Test_Bench is
end ENT00442_Test_Bench ;
architecture ARCH00442_Test_Bench of ENT00442_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00442 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00442_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00267.vhd | 1 | 6783 | -- NEED RESULT: ARCH00267: Parameters are initialized passed
-- NEED RESULT: ARCH00267: Parameters are initialized passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00267
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1.1 (1)
-- 2.1.1.1 (2)
-- 2.1.1.1 (3)
-- 2.1.1.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00267)
-- ENT00267_Test_Bench(ARCH00267_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
-- 08-JUN-1988 - EL - remove tests of out params being initialize
--
-- NOTES:
--
-- ACCESS TYPES ARE FIXED AT NULL VALUES
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00267 of E00000 is
procedure proc1( int_in : in integer ;
real_in : in real ;
bool_in : in boolean ;
bit_in : in bit ;
chr_in : in character ;
lev_in : in severity_level ;
time_in : in time ;
phys_in : in t_phys1 ;
int_inout : inout integer ;
real_inout : inout real ;
bool_inout : inout boolean ;
bit_inout : inout bit ;
chr_inout : inout character ;
lev_inout : inout severity_level ;
time_inout : inout time ;
phys_inout : inout t_phys1 ;
acc_inout : inout a_bit_vector ;
int_out : out integer ;
real_out : out real ;
bool_out : out boolean ;
bit_out : out bit ;
chr_out : out character ;
lev_out : out severity_level ;
time_out : out time ;
phys_out : out t_phys1 ;
acc_out : out a_bit_vector ) is
begin
-- this tests 2.1.1.1 (1) and 2.1.1.1 (2)
test_report ( "ARCH00267" ,
"Parameters are initialized " ,
(int_in = 5) and
(real_in = 3.14159) and
(bool_in = true) and -- note: bool covers enum types
(bit_in = '0') and
(chr_in = 'Z') and
(lev_in = WARNING) and
(time_in = 10ms) and
(phys_in = phys1_2) and
(int_inout = integer'right) and
(real_inout = real'right) and
(bool_inout = boolean'right) and
(bit_inout = bit'right) and
(chr_inout = character'right) and
(lev_inout = severity_level'right) and
(time_inout = time'right) and
(phys_inout = t_phys1'right) and
(acc_inout = null)
) ;
-- now set the inout & out parms
int_inout := 20 ;
real_inout := 25.5 ;
bool_inout := false ;
bit_inout := '0' ;
chr_inout := 'Y' ;
lev_inout := NOTE ;
time_inout := 2 ps;
phys_inout := phys1_3 ;
acc_inout := null ;
int_out := 20 ;
real_out := 25.5 ;
bool_out := true ;
bit_out := '1' ;
chr_out := 'Y' ;
lev_out := NOTE ;
time_out := 2 ps;
phys_out := phys1_3 ;
acc_out := null ;
end proc1 ;
begin
P :
process
variable int_inout : integer := integer'right ;
variable real_inout : real := real'right ;
variable bool_inout : boolean := boolean'right ;
variable bit_inout : bit := bit'right ;
variable chr_inout : character := character'right ;
variable lev_inout : severity_level := severity_level'right ;
variable time_inout : time := time'right ;
variable phys_inout : t_phys1 := t_phys1'right ;
variable acc_inout : a_bit_vector := null ;
variable int_out : integer := integer'right ;
variable real_out : real := real'right ;
variable bool_out : boolean := boolean'right ;
variable bit_out : bit := bit'right ;
variable chr_out : character := character'right ;
variable lev_out : severity_level := severity_level'right ;
variable time_out : time := time'right ;
variable phys_out : t_phys1 := t_phys1'right ;
variable acc_out : a_bit_vector := null ;
begin
proc1( int_in => 5,
real_in => 3.14159,
bool_in => true,
bit_in => '0',
chr_in => 'Z',
lev_in => WARNING,
time_in => 10ms,
phys_in => phys1_2,
int_inout => int_inout,
real_inout => real_inout,
bool_inout => bool_inout,
bit_inout => bit_inout,
chr_inout => chr_inout,
lev_inout => lev_inout,
time_inout => time_inout,
phys_inout => phys_inout,
acc_inout => acc_inout,
int_out => int_out,
real_out => real_out,
bool_out => bool_out,
bit_out => bit_out,
chr_out => chr_out,
lev_out => lev_out,
time_out => time_out,
phys_out => phys_out,
acc_out => acc_out
) ;
-- this tests 2.1.1.1 (3)
test_report ( "ARCH00267" ,
"Parameters are initialized " ,
(int_inout = 20) and
(real_inout = 25.5) and
(bool_inout = false) and
(bit_inout = '0') and
(chr_inout = 'Y') and
(lev_inout = NOTE) and
(time_inout = 2 ps) and
(phys_inout = phys1_3) and
(acc_inout = null) and
(int_out = 20) and
(real_out = 25.5) and
(bool_out = true) and
(bit_out = '1') and
(chr_out = 'Y') and
(lev_out = NOTE) and
(time_out = 2 ps) and
(phys_out = phys1_3) and
(acc_out = null)
) ;
wait ;
end process P ;
end ARCH00267 ;
entity ENT00267_Test_Bench is
end ENT00267_Test_Bench ;
architecture ARCH00267_Test_Bench of ENT00267_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00267 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00267_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl/function1.vhd | 1 | 721 | entity test is
end entity test;
architecture test of test is
constant c : integer := 0;
type arr01 is array (0 to 1) of integer;
procedure p1(constant i:integer) is
begin
end;
procedure p2(constant i:integer) is
begin
return;
end;
function f1(a1 : arr01) return integer is
begin
return a1(c);
end function;
begin
main: process
variable i : arr01 := (others => 33);
variable x : integer := 10;
begin
p1(c);
p2(c);
x := f1( i );
report integer'image(x);
assert false report "end of simulation" severity failure;
end process;
end architecture test;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/pro000026.vhd | 1 | 6192 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, array, for-loop, function, if-then-else, Attributes-of-the-array-type-or-objects-of-the-array-type
entity ENT00026_Test_Bench is
end entity ENT00026_Test_Bench;
architecture ARCH00026_Test_Bench of ENT00026_Test_Bench is
signal rst : bit := '0';
signal clk : bit := '0';
pure function integer_log2(v : in natural) return integer is
variable log2count : integer := 0;
variable x : integer := v;
begin
while x > 1 loop
log2count := log2count + 1;
x := (x + 1) / 2;
end loop;
return log2count;
end function integer_log2;
constant data_width : natural := 32;
constant addr_width : natural := 32;
function bus_width_ctrl (width : natural) return natural is
variable r : natural;
begin
r := width;
assert r mod 8 = 0
report "Check the bus data/addr width. Actual width is not multiple of 8."
severity WARNING;
return r;
end function;
constant bus_data_width : natural := bus_width_ctrl(data_width);
constant bus_addr_width : natural := bus_width_ctrl(addr_width);
constant master_num : natural := 5;
function bus_mst_control (addr_width, mst_num : natural) return natural is
variable max_dev : integer;
variable r : integer;
begin
max_dev := 2**(addr_width-4);
assert mst_num < max_dev
report "Number of masters is bigger then the possible number of devices on the bus. You must correct the number of masters"
severity ERROR;
if mst_num <= max_dev then
r := mst_num;
else
r := max_dev;
end if;
if r < 0 then
r := 0;
end if;
assert r > 0
report "System have no any masters!"
severity WARNING;
return natural(r);
end function;
constant bus_master_num : natural := bus_mst_control(bus_addr_width,master_num);
type device_conf_type is record
addr_mask : bit_vector(bus_addr_width-1 downto 0);
addr_mask_msb : bit_vector(integer_log2(bus_addr_width)-1 downto 0);
addr_mask_lsb : bit_vector(integer_log2(bus_addr_width)-1 downto 0);
registered : bit;
periphery : bit;
end record;
type device_conf_array_type is array (natural range <>) of device_conf_type;
type addr_mask_boardBit_array_type is array (natural range <>) of bit_vector(4 downto 0);
type registered_array_type is array (natural range <>) of bit_vector(3 downto 0);
type addr_mask_array_type is array (natural range <>) of bit_vector(bus_addr_width-1 downto 0);
signal mst_conf : device_conf_array_type(bus_master_num-1 downto 0);
signal mst_registered : registered_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask_msb : addr_mask_boardBit_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask_lsb : addr_mask_boardBit_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask : addr_mask_array_type(bus_master_num-1 downto 0);
constant const_1_4b : bit_vector(3 downto 0) := "0001";
constant const_1_5b : bit_vector(4 downto 0) := "00001";
constant const_30_32b : bit_vector(31 downto 0) := x"0000001E";
constant const_1m_5b : bit_vector(4 downto 0) := "11111";
function add_bit_vector (l,r : bit_vector) return bit_vector is
variable left : bit_vector(l'length-1 downto 0);
variable right : bit_vector(r'length-1 downto 0);
variable res : bit_vector(l'length-1 downto 0);
variable c : bit_vector(l'length downto 0);
begin
left := l;
right := r;
c(0) := '0';
sum_loop: for i in 0 to res'length-1 loop
res(i) := (left(i) xor right(i)) xor c(i);
c(i+1) := ((left(i) xor right(i)) and c(i)) or (left(i) and right(i));
end loop;
return res;
end function add_bit_vector;
begin
clk <= not clk after 1 us;
process
begin
rst <= '0';
wait for 10 us;
rst <= '1';
wait;
end process;
process (rst, mst_addr_mask_msb, mst_addr_mask_lsb, mst_addr_mask, mst_registered)
begin
if rst = '0' then
mst_conf_components_loop: for i in mst_conf'length-1 downto 0 loop
if i = bus_master_num-1 then
mst_registered(i) <= x"7";
mst_addr_mask(i) <= x"FFF00000";
mst_addr_mask_lsb(i) <= "00110";
mst_addr_mask_msb(i) <= "11111";
else
mst_registered(i) <= add_bit_vector((mst_registered(i+1)(2 downto 0) & mst_registered(i+1)(3)), const_1_4b);
mst_addr_mask(i) <= add_bit_vector(mst_addr_mask(i+1), const_30_32b);
if mst_addr_mask_msb(i+1) >= "11100" then
mst_addr_mask_msb(i) <= add_bit_vector(mst_addr_mask_msb(i+1),const_1m_5b);
else
mst_addr_mask_msb(i) <= "11111";
end if;
if mst_addr_mask_lsb(i+1) <= "01100" then
mst_addr_mask_lsb(i) <= add_bit_vector(mst_addr_mask_lsb(i+1),const_1_5b);
else
mst_addr_mask_lsb(i) <= "00110";
end if;
end if;
end loop;
end if;
end process;
process (rst)
begin
if rst = '1' then
assert (mst_registered(0) = x"3" and mst_registered(1) = x"1" and mst_registered(2) = x"0" and mst_registered(3) = x"F" and mst_registered(4) = x"7")
report "Wrong work of a for-loop"
severity FAILURE;
end if;
end process;
end architecture ARCH00026_Test_Bench;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00159.vhd | 1 | 25028 | -- NEED RESULT: ARCH00159.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00159
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00159(ARCH00159)
-- ENT00159_Test_Bench(ARCH00159_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00159 is
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00159 ;
--
architecture ARCH00159 of ENT00159 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 100 ns;
--
when 5 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns;
--
when 7 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_Vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_Vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_Vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2_Vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_Vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_arr2_Vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00159" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3_Vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_Vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_arr3_Vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00159 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00159_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00159_Test_Bench ;
--
architecture ARCH00159_Test_Bench of ENT00159_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00159 ( ARCH00159 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00159_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00153.vhd | 1 | 15553 | -- NEED RESULT: ARCH00153.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P2: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P3: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00153
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00153(ARCH00153)
-- ENT00153_Test_Bench(ARCH00153_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00153 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00153 ;
--
architecture ARCH00153 of ENT00153 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00153 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00153_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00153_Test_Bench ;
--
architecture ARCH00153_Test_Bench of ENT00153_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00153 ( ARCH00153 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00153_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00554.vhd | 1 | 3486 | -- NEED RESULT: ARCH00554: Signal declarations - composite static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00554
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00554)
-- ENT00554_Test_Bench(ARCH00554_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00554 of E00000 is
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal si_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal si_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
signal synch : boolean := false ;
signal s_correct : boolean := true ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and si_st_string_1 = c_st_string_1 ;
correct := correct and si_st_rec1_1 = c_st_rec1_1 ;
correct := correct and si_st_rec2_1 = c_st_rec2_1 ;
correct := correct and si_st_rec3_1 = c_st_rec3_1 ;
correct := correct and si_st_arr1_1 = c_st_arr1_1 ;
correct := correct and si_st_arr2_1 = c_st_arr2_1 ;
correct := correct and si_st_arr3_1 = c_st_arr3_1 ;
si_st_bit_vector_1 <= c_st_bit_vector_2 ;
si_st_string_1 <= c_st_string_2 ;
si_st_rec1_1 <= c_st_rec1_2 ;
si_st_rec2_1 <= c_st_rec2_2 ;
si_st_rec3_1 <= c_st_rec3_2 ;
si_st_arr1_1 <= c_st_arr1_2 ;
si_st_arr2_1 <= c_st_arr2_2 ;
si_st_arr3_1 <= c_st_arr3_2 ;
synch <= true ;
s_correct <= s_correct and correct ;
wait ;
end process ;
process (synch)
variable correct : boolean ;
begin
correct := s_correct ;
if synch = true then
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and si_st_string_1 = c_st_string_2 ;
correct := correct and si_st_rec1_1 = c_st_rec1_2 ;
correct := correct and si_st_rec2_1 = c_st_rec2_2 ;
correct := correct and si_st_rec3_1 = c_st_rec3_2 ;
correct := correct and si_st_arr1_1 = c_st_arr1_2 ;
correct := correct and si_st_arr2_1 = c_st_arr2_2 ;
correct := correct and si_st_arr3_1 = c_st_arr3_2 ;
test_report ( "ARCH00554" ,
"Signal declarations - composite static subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00554 ;
--
entity ENT00554_Test_Bench is
end ENT00554_Test_Bench ;
--
architecture ARCH00554_Test_Bench of ENT00554_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00554 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00554_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00325.vhd | 1 | 1434 | -- NEED RESULT: *** An assertion follows with severity level FAILURE
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00325
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00325)
-- ENT00325_Test_Bench(ARCH00325_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00325 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level FAILURE") ;
end process P1 ;
assert Dummy
report "An assertion with severity FAILURE"
severity Severity_Level'High ;
end ARCH00325 ;
entity ENT00325_Test_Bench is
end ENT00325_Test_Bench ;
architecture ARCH00325_Test_Bench of ENT00325_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00325 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00325_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/shft_wrapper.vhd | 9 | 13719 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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6G/4Dg4C5w==
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/shft_wrapper.vhd | 9 | 13719 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8416)
`protect data_block
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/WORK/arithmetic.vhd | 1 | 2572 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
package ARITHMETIC is
-- integer definitions
type t_int is range -2 ** 20 to 2 ** 20 ;
subtype st_int is t_int range 2 ** 15 downto -2 ** 20 ;
subtype intt is integer range -2 ** 20 to 2 ** 20 ;
subtype intst is integer range 2 ** 15 downto -2 ** 20 ;
constant c_int_1 : integer := 10 ;
constant c_int_2 : integer := -7 ;
constant c_t_int_1 : t_int := 500 ;
constant c_intt_1 : intt := 500 ;
constant c_t_int_2 : t_int := -3 ;
constant c_intt_2 : intt := -3 ;
constant c_st_int_1 : st_int := 5 ;
constant c_intst_1 : intst := 5 ;
constant c_st_int_2 : st_int := -400 ;
constant c_intst_2 : intst := -400 ;
constant ans_int1 : integer := 0 ;
constant ans_int2 : t_int := 7 ;
constant ans_int3 : st_int := -5 ;
-- physical type definitions
type t_phys is range -2 ** 20 to 2 ** 20
units
ones ;
tens = 10 ones ;
hundreds = 10 tens ;
five_hundreds = 50 tens ;
end units ;
subtype st_phys is t_phys range 2 ** 15 * ones downto -2 ** 20 * ones ;
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 10 fs ;
constant c_t_phys_1 : t_phys := 5 hundreds ;
constant c_t_phys_2 : t_phys := (-3) * ones ;
constant c_st_phys_1 : st_phys := 5 ones ;
constant c_st_phys_2 : st_phys := (-4) * 10 ones ;
constant ans_phys1 : time := 999990 fs ;
constant ans_phys2 : t_phys := 7 ones ;
constant ans_phys3 : t_phys := -5 * 1 ones ;
-- real
type t_real is range -2.0E20 to 2.0E20 ;
subtype st_real is t_real range 2.0E15 downto -2.0E20 ;
subtype realt is real range -2.0E20 to 2.0E20 ;
subtype realst is real range 2.0E15 downto -2.0E20 ;
constant c_real_1 : real := 10.5 ;
constant c_real_2 : real := -7.3 ;
constant c_t_real_1 : t_real := 500.0 ;
constant c_realt_1 : realt := 500.0 ;
constant c_t_real_2 : t_real := -3.5 ;
constant c_realt_2 : realt := -3.5 ;
constant c_st_real_1 : st_real := 5.9 ;
constant c_realst_1 : realst := 5.9 ;
constant c_st_real_2 : st_real := -400.1 ;
constant c_realst_2 : realst := -400.1 ;
constant ans_real1 : real := 0.0 ;
constant ans_real2 : t_real := 9.0 ;
constant ans_real3 : t_real := -6.8 ;
constant acceptable_error : real := 0.001 ;
constant t_acceptable_error : t_real := 0.001 ;
end ARITHMETIC ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00427.vhd | 1 | 5795 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00427
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.3 (5)
-- 7.2.3 (6)
-- 7.2.3 (9)
-- 7.2.3 (10)
-- 7.2.3 (11)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00427
-- ENT00427(ARCH00427)
-- ENT00427_Test_Bench(ARCH00427_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
package PKG00427 is
type complex1 is record
fl : integer ;
f2 : integer ;
end record ;
type complex is array ( positive range <> ) of complex1 ;
constant c_bit_vector_1 : bit_vector := B"0011" ;
constant c_bit_1 : bit := '1' ;
constant c_string_1 : string := "abc" ;
constant c_character_1 : character := 'e' ;
constant c_complex1_1 : complex1 := (others => 5) ;
constant c_complex1_2 : complex1 := (others => 57) ;
constant c_complex_1 : complex ( 1 to 2 ) := (others => c_complex1_2) ;
constant c_complex_3 : complex ( 1 to 3 ) := ( 1 to 2 => c_complex1_2,
others => c_complex1_1 ) ;
constant c_complex_4 : complex ( 1 to 3 ) := ( 2 to 3 => c_complex1_2,
others => c_complex1_1 ) ;
subtype st_bit_vector is bit_vector ( 0 to 4 ) ;
subtype st_string is string ( 1 to 4 ) ;
subtype st_complex is complex ( 1 to 3 ) ;
end PKG00427 ;
use WORK.PKG00427.all ;
entity ENT00427 is
generic (
i_bit_vector_1 : bit_vector := B"0011" ;
i_bit_1 : bit := '1' ;
i_string_1 : string := "abc" ;
i_character_1 : character := 'e' ;
i_complex_1 : complex := c_complex_1 ;
i_complex1_1 : complex1 := c_complex1_1
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00427 ;
architecture ARCH00427 of ENT00427 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_bit_vector_1 : bit_vector ( 0 to 3 ):= c_bit_vector_1 ;
variable v_bit_1 : bit := c_bit_1 ;
variable v_string_1 : string ( 1 to 3 ) := c_string_1 ;
variable v_character_1 : character := c_character_1 ;
variable v_complex_1 : complex ( 1 to 2 ) := c_complex_1 ;
variable v_complex1_1 : complex1 := c_complex1_1 ;
constant c2_bit_vector_1 : bit_vector ( 1 to 5 ) :=
st_bit_vector' (i_bit_1 & B"110" & '0') ;
constant c2_bit_vector_2 : bit_vector ( 1 to 5 ) :=
st_bit_vector' (i_bit_1 & i_bit_vector_1) ;
constant c2_bit_vector_3 : bit_vector ( 1 to 5 ) :=
st_bit_vector' (i_bit_vector_1 & i_bit_1) ;
constant c2_string_1 : string ( 1 to 4 ) :=
st_string' (i_character_1 & "efg") ;
constant c2_string_2 : string ( 1 to 4 ) :=
st_string' (i_character_1 & i_string_1) ;
constant c2_string_3 : string ( 1 to 4 ) :=
st_string' (i_string_1 & i_character_1) ;
constant c2_complex_1 : complex ( 1 to 3 ) :=
st_complex' (i_complex_1 & i_complex1_1) ;
constant c2_complex_2 : complex ( 1 to 3 ) :=
st_complex' (i_complex1_1 & i_complex_1) ;
begin
gen_correct := c2_bit_vector_1 = B"11100" and
c2_bit_vector_2 = B"10011" and
c2_bit_vector_3 = B"00111" and
c2_string_1 = "eefg" and
c2_string_2 = "eabc" and
c2_string_3 = "abce" and
c2_complex_1 = c_complex_3 and
c2_complex_2 = c_complex_4 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dyn_correct :=
st_bit_vector' (v_bit_1 & B"110" & '0') = B"11100" and
st_bit_vector' (v_bit_1 & i_bit_vector_1) = B"10011" and
st_bit_vector' (v_bit_vector_1 & v_bit_1) = B"00111" and
st_string' (v_character_1 & "efg") = "eefg" and
st_string' (v_character_1 & i_string_1) = "eabc" and
st_string' (v_string_1 & v_character_1) = "abce" and
st_complex' (v_complex1_1 & v_complex_1) = c_complex_4 and
st_complex' (i_complex_1 & v_complex1_1) = c_complex_3 ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00427 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00427_Test_Bench is
end ENT00427_Test_Bench ;
architecture ARCH00427_Test_Bench of ENT00427_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00427 ( ARCH00427 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00427" ,
"& correctly predefined for array and scalar operand"
,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00427_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00210.vhd | 1 | 3710 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00210
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00210(ARCH00210)
-- ENT00210_Test_Bench(ARCH00210_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00210 is
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00210 ;
--
--
architecture ARCH00210 of ENT00210 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec3 : inout st_rec3
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_rec3.f1 <= transport
c_st_rec3_2.f1 ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ;
wait until s_st_rec3.f2 =
c_st_rec3_2.f2 ;
Test_Report (
"ENT00210",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f2 =
c_st_rec3_2.f2 )) ;
--
when 1
=>
s_st_rec3.f1 <= transport
c_st_rec3_1.f1 ;
s_st_rec3.f3 <= transport
c_st_rec3_2.f3 after 10 ns ;
wait until s_st_rec3.f3 =
c_st_rec3_2.f3 ;
Test_Report (
"ENT00210",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f3 =
c_st_rec3_2.f3 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_rec3
, counter
, correct
, savtime
, chk_st_rec3
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00210 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00210_Test_Bench is
end ENT00210_Test_Bench ;
--
--
architecture ARCH00210_Test_Bench of ENT00210_Test_Bench is
begin
L1:
block
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00210 ( ARCH00210 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00210_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00648.vhd | 1 | 2846 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00648
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (7)
-- 4.3.3 (8)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00648(ARCH00648)
-- ENT00648_Test_Bench(ARCH00648_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00648 is
port ( signal G1 : integer ;
signal G2, G3, G4 : in integer := 3 ) ;
end ENT00648 ;
--
architecture ARCH00648 of ENT00648 is
procedure Proc ( signal P1 : integer ;
signal P2, P3, P4 : in integer := 3) is
begin
test_report ( "ARCH00648" ,
"The defualt expression is optional in a "&
"signal declaration for a formal parameter of "&
"a procedure" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
end Proc ;
begin
process
begin
test_report ( "ARCH00648" ,
"The defualt expression is optional in a "&
"signal declaration for a formal port of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
Proc (P1 => G1, P2 => G2, P4 => G4) ;
wait ;
end process ;
L1 :
block
port ( signal BG1 : integer ;
signal BG2, BG3, BG4 : in integer := 3 ) ;
port map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00648" ,
"The defualt expression is optional in a "&
"signal declaration for a formal port of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00648 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00648_Test_Bench is
end ENT00648_Test_Bench ;
architecture ARCH00648_Test_Bench of ENT00648_Test_Bench is
begin
L1:
block
component UUT
port ( signal CG1 : integer ;
signal CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00648 ( ARCH00648 )
port map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
signal S1 : integer := 1 ;
signal S2 : integer := 2 ;
signal S4 : integer := 4 ;
begin
CIS1 : UUT
port map ( S1, S2, S4 );
end block L1 ;
end ARCH00648_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00370.vhd | 1 | 5608 | -- NEED RESULT: ARCH00370.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00370: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00370: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00370
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00370(ARCH00370)
-- ENT00370_Test_Bench(ARCH00370_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00370 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00370 ;
--
--
architecture ARCH00370 of ENT00370 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00370.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00370" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00370" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00370" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
end ARCH00370 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00370_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00370_Test_Bench ;
--
--
architecture ARCH00370_Test_Bench of ENT00370_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00370 ( ARCH00370 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00370_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00076.vhd | 1 | 60724 | -- NEED RESULT: ARCH00076.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00076
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00076(ARCH00076)
-- ENT00076_Test_Bench(ARCH00076_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00076 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_boolean : inout boolean ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_boolean : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P1" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= transport c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_bit : inout bit ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_bit : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P2" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= transport c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_severity_level : inout severity_level ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_severity_level : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P3" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= transport c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_character : inout character ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_character : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P4" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= transport c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1 : inout st_enum1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P5" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= transport c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_integer : inout integer ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_integer : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P6" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= transport c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1 : inout st_int1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P7" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= transport c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_time : inout time ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_time : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P8" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= transport c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1 : inout st_phys1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P9" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= transport c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_real : inout real ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_real : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P10" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= transport c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1 : inout st_real1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P11" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= transport c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P12" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= transport c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P13" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= transport c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P14" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= transport c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1 : inout st_arr1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P15" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= transport c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2 : inout st_arr2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P16" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= transport c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3 : inout st_arr3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00076.P17" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= transport c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00076" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00076" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00076 ;
--
architecture ARCH00076 of ENT00076 is
begin
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_boolean )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_boolean,
counter,
correct,
savtime,
chk_boolean
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_bit )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_bit,
counter,
correct,
savtime,
chk_bit
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_severity_level )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_severity_level,
counter,
correct,
savtime,
chk_severity_level
) ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_character )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_character,
counter,
correct,
savtime,
chk_character
) ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1,
counter,
correct,
savtime,
chk_st_enum1
) ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_integer )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_integer,
counter,
correct,
savtime,
chk_integer
) ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1,
counter,
correct,
savtime,
chk_st_int1
) ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_time )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_time,
counter,
correct,
savtime,
chk_time
) ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1,
counter,
correct,
savtime,
chk_st_phys1
) ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_real )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_real,
counter,
correct,
savtime,
chk_real
) ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1,
counter,
correct,
savtime,
chk_st_real1
) ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1,
counter,
correct,
savtime,
chk_st_arr1
) ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2,
counter,
correct,
savtime,
chk_st_arr2
) ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3,
counter,
correct,
savtime,
chk_st_arr3
) ;
end process P17 ;
--
--
end ARCH00076 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00076_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00076_Test_Bench ;
--
architecture ARCH00076_Test_Bench of ENT00076_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00076 ( ARCH00076 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00076_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00378.vhd | 1 | 5400 | -- NEED RESULT: ARCH00378.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00378: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00378: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00378
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00378(ARCH00378)
-- ENT00378_Test_Bench(ARCH00378_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00378 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00378 ;
--
--
architecture ARCH00378 of ENT00378 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00378.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00378" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00378" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00378" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f2.f2 <= transport
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2.f2 after 5 ns ;
--
end ARCH00378 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00378_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00378_Test_Bench ;
--
--
architecture ARCH00378_Test_Bench of ENT00378_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00378 ( ARCH00378 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00378_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00132.vhd | 1 | 83180 | -- NEED RESULT: ARCH00132.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00132
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00132)
-- ENT00132_Test_Bench(ARCH00132_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00132 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= -- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_boolean'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_1 after 100 ns ;
--
when 5
=> correct :=
s_bit = c_bit_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 6
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= -- Last transaction above is marked
c_bit_1 after 40 ns ;
--
when 7
=> correct :=
s_bit = c_bit_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_bit'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= -- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_severity_level'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_1 after 100 ns ;
--
when 5
=> correct :=
s_character = c_character_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 6
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= -- Last transaction above is marked
c_character_1 after 40 ns ;
--
when 7
=> correct :=
s_character = c_character_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_character'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= -- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_enum1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_1 after 100 ns ;
--
when 5
=> correct :=
s_integer = c_integer_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 6
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= -- Last transaction above is marked
c_integer_1 after 40 ns ;
--
when 7
=> correct :=
s_integer = c_integer_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_integer'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= -- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_int1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_1 after 100 ns ;
--
when 5
=> correct :=
s_time = c_time_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 6
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= -- Last transaction above is marked
c_time_1 after 40 ns ;
--
when 7
=> correct :=
s_time = c_time_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_time'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= -- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_phys1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_1 after 100 ns ;
--
when 5
=> correct :=
s_real = c_real_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 6
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= -- Last transaction above is marked
c_real_1 after 40 ns ;
--
when 7
=> correct :=
s_real = c_real_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_real'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= -- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= -- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= -- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= -- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= -- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= -- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= -- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00132" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00132 ;
--
entity ENT00132_Test_Bench is
end ENT00132_Test_Bench ;
--
architecture ARCH00132_Test_Bench of ENT00132_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00132 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00132_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00345.vhd | 1 | 42307 | -- NEED RESULT: ARCH00345.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00345
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00345(ARCH00345)
-- ENT00345_Test_Bench(ARCH00345_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00345 is
end ENT00345 ;
--
--
architecture ARCH00345 of ENT00345 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
begin
CHG1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb to highb-1) <= transport
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
CHG2 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb to highb-1) <= transport
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
CHG3 :
process ( s_st_string )
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb-1 to highb-1) <= transport
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
CHG4 :
process ( s_st_enum1_vector )
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb-1 to highb-1) <= transport
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG5 :
process ( s_st_integer_vector )
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb to highb-1) <= transport
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
CHG6 :
process ( s_st_time_vector )
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb to highb-1) <= transport
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
CHG7 :
process ( s_st_real_vector )
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb-1 to highb-1) <= transport
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG8 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb-1 to highb-1) <= transport
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG9 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb to highb-1) <= transport
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
end ARCH00345 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00345_Test_Bench is
end ENT00345_Test_Bench ;
--
--
architecture ARCH00345_Test_Bench of ENT00345_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00345 ( ARCH00345 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00345_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00620.vhd | 1 | 11844 | -- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00620
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00620(ARCH00620)
-- ENT00620_Test_Bench(ARCH00620_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620 is
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00620 ;
--
--
architecture ARCH00620 of ENT00620 is
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
procedure P1
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_arr3_vector : in st_arr3_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr3_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_arr3_vector ,
st_arr3_vector_select ,
s_st_arr3_vector_savt ,
chk_st_arr3_vector ,
s_st_arr3_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00620 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620_Test_Bench is
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00620_Test_Bench ;
--
--
architecture ARCH00620_Test_Bench of ENT00620_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00620 ( ARCH00620 ) ;
begin
CIS1 : UUT
port map (
s_st_arr2_vector
, s_st_arr3_vector
)
;
end block L1 ;
end ARCH00620_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00289.vhd | 1 | 7235 | -- NEED RESULT: ARCH00289: Logical operators are correctly predefined for boolean array types passed
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for bit array types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00289
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (2)
-- 7.2.1 (9)
-- 7.2.1 (10)
-- 7.2.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00289(ARCH00289)
-- ENT00289_Test_Bench(ARCH00289_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00289 is
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 : out boolean ;
dynamic_correct_1, dynamic_correct_2 : out boolean ) ;
end ENT00289 ;
architecture ARCH00289 of ENT00289 is
signal sbit1, sbit2 : st_bit_vector := B"10100" ;
signal sboolean1, sboolean2 : st_boolean_vector ;
constant answer : boolean := true ;
begin
sbit2 <= B"01011" ;
sboolean1 <= (true, false, true, false, false);
sboolean2 <= (false, true, false, true, true);
-- bit vector
g1: if (((bit1 and bit1) = B"10100") and
((bit1 and bit2) = B"00000") and
((bit2 and bit1) = B"00000") and
((bit2 and bit2) = B"01011") and
((bit1 or bit1) = B"10100") and
((bit1 or bit2) = B"11111") and
((bit2 or bit1) = B"11111") and
((bit2 or bit2) = B"01011") and
((bit1 nand bit1) = B"01011") and
((bit1 nand bit2) = B"11111") and
((bit2 nand bit1) = B"11111") and
((bit2 nand bit2) = B"10100") and
((bit1 nor bit1) = B"01011") and
((bit1 nor bit2) = B"00000") and
((bit2 nor bit1) = B"00000") and
((bit2 nor bit2) = B"10100") and
((bit1 xor bit1) = B"00000") and
((bit1 xor bit2) = B"11111") and
((bit2 xor bit1) = B"11111") and
((bit2 xor bit2) = B"00000") and
((not bit1) = bit2) and
((not bit2) = bit1) ) generate
process ( sbit2 )
variable bool : boolean ;
begin
if sbit2 = B"01011" then
locally_static_correct_1 <= true ;
dynamic_correct_1 <=
((sbit1 and sbit1) = B"10100") and
((sbit1 and sbit2) = B"00000") and
((sbit2 and sbit1) = B"00000") and
((sbit2 and sbit2) = B"01011") and
((sbit1 or sbit1) = B"10100") and
((sbit1 or sbit2) = B"11111") and
((sbit2 or sbit1) = B"11111") and
((sbit2 or sbit2) = B"01011") and
((sbit1 nand sbit1) = B"01011") and
((sbit1 nand sbit2) = B"11111") and
((sbit2 nand sbit1) = B"11111") and
((sbit2 nand sbit2) = B"10100") and
((sbit1 nor sbit1) = B"01011") and
((sbit1 nor sbit2) = B"00000") and
((sbit2 nor sbit1) = B"00000") and
((sbit2 nor sbit2) = B"10100") and
((sbit1 xor sbit1) = B"00000") and
((sbit1 xor sbit2) = B"11111") and
((sbit2 xor sbit1) = B"11111") and
((sbit2 xor sbit2) = B"00000") and
((not sbit1) = sbit2) and
((not sbit2) = sbit1) ;
end if ;
end process ;
end generate ;
-- boolean vector
process ( sboolean2 )
variable bool : boolean ;
variable true_vector, false_vector : st_boolean_vector ;
begin
true_vector := (true, true, true, true, true);
false_vector :=(false, false, false, false, false);
if sboolean2 = (false, true, false, true, true) then
locally_static_correct_2 <= true ;
bool := (sboolean1 and sboolean1) = sboolean1 and
(sboolean1 and sboolean2) = false_vector and
(sboolean2 and sboolean1) = false_vector and
(sboolean2 and sboolean2) = sboolean2 and
(sboolean1 or sboolean1) = sboolean1 and
(sboolean1 or sboolean2) = true_vector ;
bool := bool and
(sboolean2 or sboolean1) = true_vector and
(sboolean2 or sboolean2) = sboolean2 and
(sboolean1 nand sboolean1) = sboolean2 and
(sboolean1 nand sboolean2) = true_vector and
(sboolean2 nand sboolean1) = true_vector and
(sboolean2 nand sboolean2) = sboolean1 ;
bool := bool and
(sboolean1 nor sboolean1) = sboolean2 and
(sboolean1 nor sboolean2) = false_vector and
(sboolean2 nor sboolean1) = false_vector and
(sboolean2 nor sboolean2) = sboolean1 and
(sboolean1 xor sboolean1) = false_vector ;
bool := bool and
(sboolean1 xor sboolean2) = true_vector and
(sboolean2 xor sboolean1) = true_vector and
(sboolean2 xor sboolean2) = false_vector and
((not sboolean1) = sboolean2) and
((not sboolean2) = sboolean1) ;
dynamic_correct_2 <= bool ;
end if ;
end process ;
end ARCH00289 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00289_Test_Bench is
end ENT00289_Test_Bench ;
architecture ARCH00289_Test_Bench of ENT00289_Test_Bench is
begin
L1:
block
signal locally_static_correct_1, dynamic_correct_1 : boolean := false ;
signal locally_static_correct_2, dynamic_correct_2 : boolean := false ;
constant local_c_st_bit_vector_1 : st_bit_vector := B"10100";
constant local_c_st_bit_vector_2 : st_bit_vector := B"01011";
component UUT
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 :
out boolean := false ;
dynamic_correct_1, dynamic_correct_2 : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00289 ( ARCH00289 ) ;
begin
CIS1 : UUT
generic map ( local_c_st_bit_vector_1, local_c_st_bit_vector_2,
c_boolean_1, c_boolean_2 )
port map ( locally_static_correct_1,
locally_static_correct_2 ,
dynamic_correct_1 ,
dynamic_correct_2 ) ;
process ( locally_static_correct_1, locally_static_correct_2,
dynamic_correct_1, dynamic_correct_2 )
begin
if locally_static_correct_1 and dynamic_correct_1 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for boolean array types" ,
true ) ;
end if ;
if locally_static_correct_2 and dynamic_correct_2 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for bit array types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00289_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00229.vhd | 1 | 9414 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00229
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00229)
-- ENT00229_Test_Bench(ARCH00229_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00229 of GENERIC_STANDARD_TYPES is
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
begin
L1:
block
port (
toggle : inout switch := down;
i_boolean_1, i_boolean_2 : inout boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : inout bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : inout severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : inout character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : inout t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : inout st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : inout integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : inout t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : inout st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : inout time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : inout t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : inout st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : inout real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : inout t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : inout st_real1
:= c_st_real1_1
) ;
port map (
toggle ,
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
--
test_report ( "ENT00229" ,
"Associated scalar inout ports with generic subtypes" ,
correct) ;
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
wait ;
end process ;
end block L1 ;
P00229 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
end if ;
--
test_report ( "ENT00229.P00229" ,
"Associated scalar inout ports with generic subtypes",
correct) ;
end process P00229 ;
end ARCH00229 ;
--
entity ENT00229_Test_Bench is
end ENT00229_Test_Bench ;
--
architecture ARCH00229_Test_Bench of ENT00229_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00229 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00229_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00573.vhd | 1 | 1524 | -- NEED RESULT: ARCH00573: Library unit is visible passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00573
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (14)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00573)
-- ENT00573_Test_Bench(ARCH00573_Test_Bench)
-- CONF00573
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
architecture ARCH00573 of E00000 is
begin
process
begin
WORK.STANDARD_TYPES.test_report ( "ARCH00573" ,
"Library unit is visible" ,
True ) ;
wait ;
end process ;
end ARCH00573 ;
--
entity ENT00573_Test_Bench is
end ENT00573_Test_Bench ;
architecture ARCH00573_Test_Bench of ENT00573_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00573 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00573_Test_Bench ;
--
configuration CONF00573 of WORK.ENT00573_Test_Bench is
for ARCH00573_Test_Bench
for L1
for CIS2 : UUT
use entity WORK.E00000 ( ARCH00573 );
end for ;
end for ;
end for ;
end CONF00573 ;
--
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_read_fsm.vhd | 9 | 83511 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00086.vhd | 1 | 64610 | -- NEED RESULT: ARCH00086.P1: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P2: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P3: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P4: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P5: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P6: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P7: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P8: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P9: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P10: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P11: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P12: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P13: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P14: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P15: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P16: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P17: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00086
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00086(ARCH00086)
-- ENT00086_Test_Bench(ARCH00086_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00086 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00086 ;
--
architecture ARCH00086 of ENT00086 is
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P17 ;
--
--
end ARCH00086 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00086_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00086_Test_Bench ;
--
architecture ARCH00086_Test_Bench of ENT00086_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00086 ( ARCH00086 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00086_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00539.vhd | 1 | 3597 | -- NEED RESULT: ARCH00539: Local port/generic visibility test passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00539
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (8)
-- 10.3 (9)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00539(ARCH00539)
-- PKG00539
-- ENT00539_Test_Bench(ARCH00539_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00539 is
generic (G : CHARACTER) ;
port (P1 : inout INTEGER; P2 : out BIT; P3 : in BOOLEAN);
end ENT00539 ;
--
architecture ARCH00539 of ENT00539 is
begin
process ( P1 )
begin
P2 <= transport '1' after 0 ns ;
end process ;
end ARCH00539 ;
--
package PKG00539 is
component PkgCOMP generic (DDD : CHARACTER) ;
port (AAA : inout INTEGER;
BBB : out BIT;
CCC : in BOOLEAN) ;
end component;
end PKG00539 ;
--
use WORK.STANDARD_TYPES.all, WORK.PKG00539 ;
entity ENT00539_Test_Bench is
end ENT00539_Test_Bench ;
architecture ARCH00539_Test_Bench of ENT00539_Test_Bench is
component COMP1 generic (D : CHARACTER) ;
port (A : inout INTEGER := 0 ;
B : out BIT := '0' ;
C : in BOOLEAN := false);
end component;
component COMP2 generic (DD : CHARACTER) ;
port (AA : inout INTEGER := 0 ;
BB : out BIT := '0' ;
CC : in BOOLEAN := false) ;
end component;
signal SA : INTEGER := 0 ;
signal SB : BIT := '0' ;
signal SC : BOOLEAN := false ;
constant SD : CHARACTER := 'D';
signal AA : INTEGER := 0 ;
signal BB : BIT := '0' ;
signal CC : BOOLEAN := false ;
constant DD : CHARACTER := 'D';
signal PSA : INTEGER := 0 ;
signal PSB : BIT := '0' ;
signal PSC : BOOLEAN := false ;
constant PSD : CHARACTER := 'D';
for A1 : COMP1 use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => D )
port map ( A, B, C ) ;
-- names denoting local port or generic are permitted
for others : COMP2 use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => DD )
port map ( AA, BB, CC ) ;
-- names denoting local port or generic are permitted
for all : PKG00539.PkgCOMP use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => DDD )
port map ( AAA, BBB, CCC ) ;
-- names denoting local port or generic are permitted
begin
A1 : COMP1 generic map (D => SD)
port map (A => SA, B => SB, C => SC) ;
-- names denoting local port or generic are permitted
A2 : COMP2 generic map (DD => DD)
port map (AA => AA, BB => BB, CC => CC) ;
-- names denoting local port or generic are permitted
A3 : PKG00539.PkgCOMP generic map (DDD => PSD)
port map (AAA => PSA, BBB => PSB, CCC => PSC) ;
-- names denoting local port or generic are permitted
process
begin
wait for 10 ns ;
test_report ( "ARCH00539" ,
"Local port/generic visibility test" ,
(SB = '1') and
(BB = '1') and
(PSB = '1') ) ;
wait;
end process ;
end ARCH00539_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00064.vhd | 1 | 4606 | -- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next statement does not effect outer loop passed
-- NEED RESULT: ARCH00064.P1_2: Next with no label only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_2: Next with no label only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_2: Next statement does not effect outer loop passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00064
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.9 (1)
-- 8.9 (3)
-- 8.9 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00064)
-- ENT00064_Test_Bench(ARCH00064_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00064 of E00000 is
signal Dummy : Boolean := false ;
begin
P1_1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
variable done : boolean := false ;
begin
L1 :
for i in boolean loop
--
correct := true ;
L2 :
for j in 1 to 3 loop
next ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00064.P1_1" ,
"Next with no label or condition only effects " &
"innermost (labeled) loop",
correct ) ;
--
correct := true ;
while not done loop
done := true ;
next ;
correct := false ;
end loop ;
--
test_report ( "ARCH00064.P1_1" ,
"Next with no label or condition only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00064.P1_1" ,
"Next statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_1 ;
--
P1_2 :
process ( Dummy )
variable correct : boolean := true ;
variable counter : integer := 0 ;
variable done : boolean := false ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= boolean'High loop
--
correct := true ;
for j in 1 to 3 loop
next when j = j ;
correct := false ;
end loop ;
--
test_report ( "ARCH00064.P1_2" ,
"Next with no label only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
correct := true ;
L2 :
while not done loop
done := true ;
next when done = done ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00064.P1_2" ,
"Next with no label only effects " &
"innermost (labeled) loop",
correct ) ;
--
v_boolean :=
boolean'Succ (v_boolean) ;
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (c_boolean_1) ) ;
test_report ( "ARCH00064.P1_2" ,
"Next statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_2 ;
--
--
end ARCH00064 ;
--
entity ENT00064_Test_Bench is
end ENT00064_Test_Bench ;
--
architecture ARCH00064_Test_Bench of ENT00064_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00064 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00064_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00665.vhd | 1 | 2344 | -- NEED RESULT: ARCH00665: Reference to array element in alias uses subtype given in alias declaration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00665
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (3)
-- 4.3.4 (4)
-- 4.3.4 (7)
-- 4.3.4 (8)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00665(ARCH00665)
-- ENT00665_Test_Bench(ARCH00665_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-AUG-1987 - initial revision
-- 16-JUN-1988 - (KLM) added wait statement at end of process
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00665 is
generic ( g_integer : integer := 5 ) ;
--
attribute at_scalar : character ;
attribute at_composite : string ;
end ENT00665 ;
--
architecture ARCH00665 of ENT00665 is
attribute at_composite of ARCH00665 : architecture is "abcde" ;
constant str : string := ARCH00665'at_composite ;
subtype str1 is string (1 to 5 ) ;
subtype str2 is string (5 to 9 ) ;
subtype str3 is string (5 + g_integer - 1 downto 5) ;
alias al_att1 : str1 is str ;
alias al_att2 : str2 is str ;
alias al_att3 : str3 is str ;
alias at_scalar1 : character is al_att1(1) ;
alias at_scalar2 : character is al_att2(g_integer) ;
alias at_scalar3 : character is al_att3(g_integer + 4) ;
begin
process
variable correct : boolean := true ;
begin
test_report ( "ARCH00665" ,
"Reference to array element in alias uses subtype"
& " given in alias declaration" ,
correct and at_scalar1 = at_scalar2 and
at_scalar2 = at_scalar3 and at_scalar3 = 'a' ) ;
wait;
end process ;
end ARCH00665 ;
--
entity ENT00665_Test_Bench is
end ENT00665_Test_Bench ;
architecture ARCH00665_Test_Bench of ENT00665_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00665 ( ARCH00665 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00665_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00420.vhd | 1 | 7809 | -- NEED RESULT: ARCH00420.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00420: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00420
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00420(ARCH00420)
-- ENT00420_Test_Bench(ARCH00420_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00420 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00420 ;
--
--
architecture ARCH00420 of ENT00420 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00420" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f2.f2 <=
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2.f2 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f2.f2 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f2.f2 after 40 ns ;
--
end ARCH00420 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00420_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00420_Test_Bench ;
--
--
architecture ARCH00420_Test_Bench of ENT00420_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00420 ( ARCH00420 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00420_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00094.vhd | 1 | 12020 | -- NEED RESULT: ARCH00094.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094.P2: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094.P3: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00094
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00094(ARCH00094)
-- ENT00094_Test_Bench(ARCH00094_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00094 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00094 ;
--
architecture ARCH00094 of ENT00094 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
end process P3 ;
--
--
end ARCH00094 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00094_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00094_Test_Bench ;
--
architecture ARCH00094_Test_Bench of ENT00094_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00094 ( ARCH00094 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00094_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00261.vhd | 1 | 2852 | -- NEED RESULT: ARCH00261_1: Component declaration and configuration spec allowed in architecture statement part passed
-- NEED RESULT: ARCH00261: Subprogram decl and subprogram body and type, subtype constant, signal, initialization spec, alias decl ,attribute decl and attribute spec in architecture statement part passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00261
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.2.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00261)
-- ENT00261_1(ARCH00261_1)
-- ENT00261_Test_Bench(ARCH00261_Test_Bench)
--
-- REVISION HISTORY:
--
-- 16-JUL-1987 - initial revision
-- 16-JUN-1988 - (KLM) changed t1 from range 1 to 5 to range 1 to 11
-- changed type of parameter p1 from st1 to t1
-- added wait statements to ends of processes
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00261 of E00000 is
type t1 is range 1 to 11 ;
subtype st1 is t1 range 5 downto 1 ;
constant c1 : st1 := 1 ;
signal s1 : st1 := 5;
alias a1 : st1 is s1 ;
attribute at1 : boolean ;
attribute at1 of c1 : constant is true ;
function f1 ( p1 : t1 ) return boolean ;
function f1 ( p1 : t1 ) return boolean is
begin
return p1 = 11 ;
end f1 ;
begin
process
begin
test_report ( "ARCH00261" ,
"Subprogram decl and subprogram body and type, subtype"
& " constant, signal, initialization spec, alias decl"
& " ,attribute decl and attribute spec in"
& " architecture statement part" ,
f1(c1 + s1 + a1) and c1'at1) ;
wait;
end process ;
end ARCH00261 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00261_1 is
end ENT00261_1 ;
architecture ARCH00261_1 of ENT00261_1 is
component comp1
end component ;
for CIS : comp1 use entity WORK.E00000 ( ARCH00261 ) ;
begin
CIS : comp1 ;
process
begin
test_report ( "ARCH00261_1" ,
"Component declaration and configuration spec allowed in"
& " architecture statement part" ,
true ) ;
wait;
end process ;
end ARCH00261_1 ;
entity ENT00261_Test_Bench is
end ENT00261_Test_Bench ;
architecture ARCH00261_Test_Bench of ENT00261_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00261_1 ( ARCH00261_1 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00261_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00414.vhd | 1 | 8856 | -- NEED RESULT: ARCH00414.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00414: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00414: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00414: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00414: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00414
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00414(ARCH00414)
-- ENT00414_Test_Bench(ARCH00414_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00414 is
end ENT00414 ;
--
--
architecture ARCH00414 of ENT00414 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00414.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00414" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00414" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00414" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00414" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00414" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)(lowb to highb-1)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
end ARCH00414 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00414_Test_Bench is
end ENT00414_Test_Bench ;
--
--
architecture ARCH00414_Test_Bench of ENT00414_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00414 ( ARCH00414 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00414_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00101.vhd | 1 | 5193 | -- NEED RESULT: ARCH00101.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00101: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00101: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00101
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00101)
-- ENT00101_Test_Bench(ARCH00101_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00101 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00101.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00101" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00101" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00101" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
--
end ARCH00101 ;
--
entity ENT00101_Test_Bench is
end ENT00101_Test_Bench ;
--
architecture ARCH00101_Test_Bench of ENT00101_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00101 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00101_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00044.vhd | 1 | 4481 | -- NEED RESULT: ARCH00044.P1: Target of a variable assignment may be a indexed name prefixed by a selected name passed
-- NEED RESULT: ARCH00044.P2: Target of a variable assignment may be a indexed name prefixed by a selected name passed
-- NEED RESULT: ARCH00044.P3: Target of a variable assignment may be a indexed name prefixed by a selected name passed
-- NEED RESULT: ARCH00044.P4: Target of a variable assignment may be a indexed name prefixed by a selected name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00044
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00044)
-- ENT00044_Test_Bench(ARCH00044_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00044 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
--
correct :=
correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
test_report ( "ARCH00044.P1" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by a selected name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
--
correct :=
correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00044.P2" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by a selected name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
--
end Proc1 ;
begin
Proc1 ;
correct :=
correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
test_report ( "ARCH00044.P3" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by a selected name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec3 : inout st_rec3
)
is
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
--
end Proc1 ;
begin
Proc1 (
v_st_rec3
) ;
correct :=
correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
test_report ( "ARCH00044.P4" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by a selected name" ,
correct) ;
end process P4 ;
--
end ARCH00044 ;
--
entity ENT00044_Test_Bench is
end ENT00044_Test_Bench ;
--
architecture ARCH00044_Test_Bench of ENT00044_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00044 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00044_Test_Bench ;
| gpl-3.0 |
SamuelLBau/Pool-Shot-Tracking-using-FPGA | examples/sparse_mm/solution1/syn/vhdl/sparse_mm_mul_32s_32s_32_3.vhd | 1 | 2705 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity sparse_mm_mul_32s_32s_32_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of sparse_mm_mul_32s_32s_32_3 is
component sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
sparse_mm_mul_32s_32s_32_3_Mul3S_0_U : component sparse_mm_mul_32s_32s_32_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00244.vhd | 1 | 1911 | -- NEED RESULT: ARCH00244: Procedures and functions may be called recursively passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00244
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00244)
-- ENT00244_Test_Bench(ARCH00244_Test_Bench)
--
-- REVISION HISTORY:
--
-- 14-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00244 of E00000 is
begin
P :
process
variable global_int : integer := 0;
procedure Recursive_subr ( x: integer ) is
begin
global_int := global_int + 1;
if x > 1 then
Recursive_subr (x-1);
end if;
end Recursive_subr ;
function Recursive_func ( n: integer ) return integer is -- factorial
begin
if n > 1 then
return n * Recursive_func (n-1);
else
return 1;
end if;
end Recursive_func ;
begin
Recursive_subr ( 10 ) ;
test_report ( "ARCH00244" ,
"Procedures and functions may be called recursively" ,
(global_int = 10) and
(Recursive_func(5) = 5*4*3*2)
) ;
wait ;
end process P ;
end ARCH00244 ;
entity ENT00244_Test_Bench is
end ENT00244_Test_Bench ;
architecture ARCH00244_Test_Bench of ENT00244_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00244 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00244_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/synth/golden_ticket_fifo.vhd | 6 | 37388 | -- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00508.vhd | 1 | 2124 | -- NEED RESULT: ARCH00508: 'All' test in an initialization spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00508
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00508)
-- ENT00508_Test_Bench(ARCH00508_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00508 of E00000 is
signal s1, s2, s3 : boolean := True ;
type rec is record
f1 : boolean ;
f2 : integer ;
end record ;
type TYPE1 is array ( Integer range <> ) of rec ;
subtype ST1 is TYPE1 ( 1 to 10 ) ;
signal sa : ST1 := (others => (true,20)) ;
subtype ST2 is boolean range False to True ;
signal t1, t2 : ST2 := False ;
begin
process
begin
test_report ( "ARCH00508" ,
"'All' test in an initialization spec" ,
s1 and s2 and s3 and
sa(1).f1 and sa(2).f1 and sa(3).f1 and
sa(4).f1 and sa(5).f1 and sa(6).f1 and
sa(7).f1 and sa(8).f1 and sa(9).f1 and sa(10).f1 and
sa(1).f2=20 and sa(2).f2=20 and sa(3).f2=20 and
sa(4).f2=20 and sa(5).f2=20 and sa(6).f2=20 and
sa(7).f2=20 and sa(8).f2=20 and sa(9).f2=20 and
sa(10).f2=20 and
(Not t1) and (Not t2) ) ;
wait ;
end process ;
end ARCH00508 ;
entity ENT00508_Test_Bench is
end ENT00508_Test_Bench ;
architecture ARCH00508_Test_Bench of ENT00508_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00508 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00508_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/pro000027.vhd | 1 | 2896 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Scherbinin.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity test_generate is
generic(N:natural:=8);
port
(
in_bit : in bit;
out_bit : out bit
);
end entity test_generate;
architecture test_generate_arch of test_generate is
function resolve_bit_or(s : bit_vector) return bit is
variable v : bit := '0';
variable i : integer;
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end function resolve_bit_or;
subtype resolved_bit is resolve_bit_or bit;
signal test_resolved_bit : resolved_bit := '0';
type int_vector is array (integer range <>) of integer;
function resolve_integer_sum(s : int_vector) return integer is
variable v : integer := 0;
variable i : integer;
begin
for i in s'range loop
v := v + s(i);
end loop;
return v;
end function resolve_integer_sum;
subtype resolved_integer is resolve_integer_sum integer;
signal test_resolved_integer : resolved_integer := 0;
signal test_vector_signal : bit_vector(0 to 8);
signal tst_signal : resolved_bit := '0';
signal tst_vector : bit_vector(0 to N-1):=('0','0','0','0','0','0','0','0');
signal model_vector : bit_vector(0 to N-1):=('0','0','1','0','1','0','1','0');
begin
g1: for i in 0 to N-1 generate
test_resolved_bit <= '1';
end generate g1;
out_bit <= in_bit xor test_resolved_bit;
g2: for i in 0 to N-1 generate
tst_vector(i) <= model_vector(i);
tst_signal <= '1';
end generate g2;
validate_g1: process (tst_vector) is
variable i : bit;
variable pooh : integer := 0;
begin
for k in 0 to N-1 loop
i := tst_signal;
assert ( ( (tst_vector(k) = model_vector(k)) and i='1' ) or i = '0')
report "PRO000027: failure: wrong value."
severity ERROR;
end loop;
if pooh /= 0 then
report "pooh mismatch!" severity ERROR;
end if;
end process validate_g1;
end architecture test_generate_arch;
entity ENT00027_Test_Bench is
end ENT00027_Test_Bench;
architecture ARCH00027_Test_Bench of ENT00027_Test_Bench is
signal input, output : bit;
begin
input <= not input after 10 ns;
test_entity: entity work.test_generate
port map
(
in_bit => input,
out_bit => output
);
end ARCH00027_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00154.vhd | 1 | 17205 | -- NEED RESULT: ARCH00154.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00154.P2: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154.P3: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00154: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00154: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00154: Inertial semantics check on a signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00154
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00154(ARCH00154)
-- ENT00154_Test_Bench(ARCH00154_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00154 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00154" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00154 ;
--
architecture ARCH00154 of ENT00154 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00154 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00154_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00154_Test_Bench ;
--
architecture ARCH00154_Test_Bench of ENT00154_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00154 ( ARCH00154 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00154_Test_Bench ;
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`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/rd_pe_ss.vhd | 9 | 28156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
`protect data_block
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00113.vhd | 1 | 5648 | -- NEED RESULT: ARCH00113.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00113: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00113: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00113
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00113)
-- ENT00113_Test_Bench(ARCH00113_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00113 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00113.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00113" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00113" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00113" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
--
end ARCH00113 ;
--
entity ENT00113_Test_Bench is
end ENT00113_Test_Bench ;
--
architecture ARCH00113_Test_Bench of ENT00113_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00113 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00113_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00646.vhd | 1 | 2728 | -- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of an entity passed
-- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00646
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00646(ARCH00646)
-- ENT00646_Test_Bench(ARCH00646_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646 is
port ( G1 : in integer := 0 ;
signal G2, G3, G4 : in integer := 3 ) ;
end ENT00646 ;
--
architecture ARCH00646 of ENT00646 is
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
wait ;
end process ;
L1 :
block
port ( BG1 : in integer := 0 ;
signal BG2, BG3, BG4 : in integer := 3 ) ;
port map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00646 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646_Test_Bench is
end ENT00646_Test_Bench ;
architecture ARCH00646_Test_Bench of ENT00646_Test_Bench is
begin
L1:
block
component UUT
port ( CG1 : in integer ;
signal CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00646 ( ARCH00646 )
port map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
signal S1 : integer := 1 ;
signal S2 : integer := 2 ;
signal S4 : integer := 4 ;
begin
CIS1 : UUT
port map ( S1, S2, S4 );
end block L1 ;
end ARCH00646_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00505.vhd | 1 | 1453 | -- NEED RESULT: ARCH00505: One or more signal names may appear in a signal list in an initialization spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00505
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00505)
-- ENT00505_Test_Bench(ARCH00505_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00505 of E00000 is
signal s1, s2 : boolean := True ;
signal s3 : boolean := True ;
begin
process
begin
test_report ( "ARCH00505" ,
"One or more signal names may appear in a signal "&
"list in an initialization spec" ,
s1 and s2 and s3 ) ;
wait ;
end process ;
end ARCH00505 ;
entity ENT00505_Test_Bench is
end ENT00505_Test_Bench ;
architecture ARCH00505_Test_Bench of ENT00505_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00505 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00505_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00593.vhd | 1 | 2950 | -- NEED RESULT: ARCH00593: Resolution functions may appear in subtype indications used in signal and non-signal declaration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00593
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00593)
-- ENT00593_Test_Bench(ARCH00593_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00593 of E00000 is
subtype rst_integer is bf_integer integer ;
signal s_integer : bf_integer integer := c_integer_1;
subtype rst_arr1 is bf_arr1 t_arr1 (lowb to highb) ;
signal s_arr1 : rst_arr1 := c_st_arr1_1;
subtype rst_rec2 is bf_rec2 st_rec2 ;
signal s_rec2 : rst_rec2 := c_t_rec2_1;
signal toggle : boolean := false ;
begin
process
variable v_integer : bf_integer integer := 1 ;
variable v_arr1 : rst_arr1 ;
variable v_rec2 : rst_rec2 ;
begin
v_integer := v_integer + 1 ;
s_integer <= v_integer ;
for i in lowb to highb loop
v_arr1(i) := st_int1 ( i + 10) ;
end loop ;
s_arr1 <= v_arr1(lowb to highb) ;
v_rec2 := (true, (1, 10 ns, false, 1.0), 2 fs) ;
s_rec2 <= v_rec2 ;
toggle <= true ;
wait ;
end process ;
process
variable v_integer : rst_integer := 2 ;
variable v_arr1 : bf_arr1 t_arr1 (highb downto lowb) ;
variable v_rec2 : rst_rec2 ;
begin
v_integer := v_integer + 1 ;
s_integer <= v_integer ;
for i in lowb to highb loop
v_arr1(i) := st_int1 ( i + 10) ;
end loop ;
s_arr1 <= v_arr1(highb downto lowb) ;
v_rec2 := (false, (2, 15 ns, true, 2.0), 3 fs) ;
s_rec2 <= v_rec2 ;
wait ;
end process ;
process ( s_integer, s_arr1, s_rec2 )
begin
if toggle then
test_report ( "ARCH00593" ,
"Resolution functions may appear in subtype indications "
& " used in signal and non-signal declaration" ,
s_integer = 5 and
s_arr1 = st_arr1'(others => st_int1 ( highb+lowb+20)) and
s_rec2 = (true, (3, 25 ns, true, 3.0), 5 fs) ) ;
end if ;
end process ;
end ARCH00593 ;
--
entity ENT00593_Test_Bench is
end ENT00593_Test_Bench ;
architecture ARCH00593_Test_Bench of ENT00593_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00593 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00593_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/pro000028.vhd | 1 | 1711 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Scherbinin.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity test_generate is
generic(N:natural:=8);
port
(
in_bit : in bit;
out_bit : out bit
);
end entity test_generate;
architecture test_generate_arch of test_generate is
signal tst_signal : bit := '0';
signal tst_vector : bit_vector(0 to N-1):=('0','0','0','0','0','0','0','0');
begin
tst_signal <= '1';
G2:
if (N > 5) generate
tst_vector(7) <= '1';
tst_vector(6) <= '1';
end generate G2;
validate_g1: process (tst_vector) is
variable i : bit;
begin
i := tst_signal;
assert ( ( (tst_vector(6) = '1') and (tst_vector(7) = '1') and i='1' ) or i = '0')
report "PRO000028: failure: wrong value."
severity ERROR;
end process validate_g1;
end architecture test_generate_arch;
entity ENT00028_Test_Bench is
end ENT00028_Test_Bench;
architecture ARCH00028_Test_Bench of ENT00028_Test_Bench is
signal input, output : bit;
begin
input <= not input after 10 ns;
test_entity: entity work.test_generate
port map
(
in_bit => input,
out_bit => output
);
end ARCH00028_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00125.vhd | 1 | 11332 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00125
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00125
-- PKG00125/BODY
-- E00000(ARCH00125)
-- ENT00125_Test_Bench(ARCH00125_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00125 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00125 ;
--
package body PKG00125 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00125 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00125.all ;
architecture ARCH00125 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_r_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_r_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_r_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_r_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_r_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_r_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00125 ;
--
entity ENT00125_Test_Bench is
end ENT00125_Test_Bench ;
--
architecture ARCH00125_Test_Bench of ENT00125_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00125 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00125_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00280.vhd | 1 | 1785 | -- NEED RESULT: ARCH00280: Block statement with a guard expression passed
-- NEED RESULT: ARCH00280: Block statement without a guard expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00280
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00280)
-- ENT00280_Test_Bench(ARCH00280_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00280 of E00000 is
signal S : boolean := false ;
begin
B1 :
block ( S )
begin
B1_2 :
block ( Not S )
begin
process
begin
test_report ( "ARCH00280" ,
"Block statement with a guard expression" ,
True ) ;
wait ;
end process ;
end block B1_2 ;
end block B1 ;
B2 :
block ( S )
begin
B2_2 :
block
begin
process
begin
test_report ( "ARCH00280" ,
"Block statement without a guard expression" ,
True ) ;
wait ;
end process ;
end block B2_2 ;
end block B2 ;
end ARCH00280 ;
entity ENT00280_Test_Bench is
end ENT00280_Test_Bench ;
architecture ARCH00280_Test_Bench of ENT00280_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00280 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00280_Test_Bench ;
| gpl-3.0 |
dcliche/mdsynth | rtl/src/ps2_keyboard.vhd | 1 | 33504 | --===========================================================================--
-- --
-- ps2_keyboard.vhd - Synthesizable PS/2 Keyboard Interface --
-- --
--===========================================================================--
--
-- File name : ps2_keyboard.vhd
--
-- Purpose : Implements a PS/2 Keyboard Interface
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Author : Original Verilog version by John Clayton
-- Converted to VHDL by John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description :
--
-- This is a state-machine driven serial-to-parallel and parallel-to-serial
-- interface to the ps2 style keyboard interface. The details of the operation
-- of the keyboard interface were obtained from the following website:
--
-- http://www.beyondlogic.org/keyboard/keybrd.htm
--
-- Some aspects of the keyboard interface are not implemented (e.g, parity
-- checking for the receive side, and recognition of the various commands
-- which the keyboard sends out, such as "power on selt test passed," "Error"
-- and "Resend.") However, if the user wishes to recognize these reply
-- messages, the scan code output can always be used to extend functionality
-- as desired.
--
-- Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
-- The rx interface provides separate indicator flags for these two conditions
-- with every valid character scan code which it provides. The shift keys are
-- also trapped by the interface, in order to provide correct uppercase ASCII
-- characters at the ascii output, although the scan codes for the shift keys
-- are still provided at the scan code output. So, the left/right ALT keys
-- can be differentiated by the presence of the rx_entended signal, while the
-- left/right shift keys are differentiable by the different scan codes
-- received.
--
-- The interface to the ps2 keyboard uses ps2_clk clock rates of
-- 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
-- machine runs should be at least twice the rate of the ps2_clk, so that the
-- states can accurately follow the clock signal itself. Four times
-- oversampling is better. Say 200kHz at least. The upper limit for clocking
-- the state machine will undoubtedly be determined by delays in the logic
-- which decodes the scan codes into ASCII equivalents. The maximum speed
-- will be most likely many megahertz, depending upon target technology.
-- In order to run the state machine extremely fast, synchronizing flip-flops
-- have been added to the ps2_clk and ps2_data inputs of the state machine.
-- This avoids poor performance related to slow transitions of the inputs.
--
-- Because this is a bi-directional interface, while reading from the keyboard
-- the ps2_clk and ps2_data lines are used as inputs. While writing to the
-- keyboard, however (which may be done at any time. If writing interrupts a
-- read from the keyboard, the keyboard will buffer up its data, and send
-- it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
-- and pullup resistors are used to bring the lines high again, by setting
-- the drivers to high impedance state.
--
-- The tx interface, for writing to the keyboard, does not provide any special
-- pre-processing. It simply transmits the 8-bit command value to the
-- keyboard.
--
-- Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
-- whether they be internal to an FPGA I/O pad, or externally placed.
-- If internal pullups are used, they may be fairly weak, causing bounces
-- due to crosstalk, etc. There is a "debounce timer" implemented in order
-- to eliminate erroneous state transitions which would occur based on bounce.
--
-- Parameters are provided in order to configure and appropriately size the
-- counter of a 60 microsecond timer used in the transmitter, depending on
-- the clock frequency used. The 60 microsecond period is guaranteed to be
-- more than one period of the ps2_clk_s signal.
--
-- Also, a smaller 5 microsecond timer has been included for "debounce".
-- This is used because, with internal pullups on the ps2_clk and ps2_data
-- lines, there is some bouncing around which occurs
--
-- A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
-- from producing scan codes (along with their "undefined" ASCII equivalents)
-- at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
-- key status will only be reported by rx_shift_on. No ascii or scan
-- codes will be reported for the shift keys. This is useful for those who
-- wish to use the ASCII data stream, and who don't want to have to "filter
-- out" the shift key codes.
--
-- Copyright (C) 2001 - 2010 John Clayton and John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Author: John Clayton
-- 2001-04-30 copied this file from lcd_2.v (pared down).
-- 2001-05-24 changed the first module from "ps2_keyboard_receiver"
-- to "ps2_keyboard_interface"
-- 2001-05-29 Added input synchronizing flip-flops. Changed state
-- encoding (m1) for good operation after part config.
-- 2001-05-31 Added low drive strength and slow transitions to ps2_clk
-- and ps2_data in the constraints file. Added the signal
-- "tx_shifting_done" as distinguished from "rx_shifting_done."
-- Debugged the transmitter portion in the lab.
-- 2001-06-01 Added horizontal tab to the ascii output.
-- 2001-06-01 Added parameter TRAP_SHIFT_KEYS.
-- 2001-06-05 Debugged the "debounce" timer functionality.
-- Used 60usec timer as a "watchdog" timeout during
-- receive from the keyboard. This means that a keyboard
-- can now be "hot plugged" into the interface, without
-- messing up the bit_count, since the bit_count is reset
-- to zero during periods of inactivity anyway. This was
-- difficult to debug. I ended up using the logic analyzer,
-- and had to scratch my head quite a bit.
-- 2001-06-06 Removed extra comments before the input synchronizing
-- flip-flops. Used the correct parameter to size the
-- 5usec_timer_count. Changed the name of this file from
-- ps2.v to ps2_keyboard.v
-- 2001-06/06 Removed "&& q[7:0]" in output_strobe logic. Removed extra
-- commented out "else" condition in the shift register and
-- bit counter.
-- 2001-06-07 Changed default values for 60usec timer parameters so that
-- they correspond to 60usec for a 49.152MHz clock.
--
-- Author: John Kent
--2001-02-10 Converted to VHDL
-- 2004-09-11 Added ctrl key
-- Changed undefined key codes to x"ff"
-- Reversed clock polarity
-- 2004-10-18 Added ctrl keys to ASCII ROM
-- Added CAPS Lock toggle.
-- 2007-02-06 Added Generic Clock parameter
-- 2010-05-31 Revised header, added GPL
-- 2010-06-17 Change some signal names for consistancy
-- 2010-10-24 Rearranged code to prevent shift key outputting characters
--
--
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
entity ps2_keyboard is
generic (
CLK_FREQ_MHZ : integer
);
port(
clk : in std_logic;
reset : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_read : in std_logic;
rx_data_ready : out std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_on : out std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_data_empty : out std_logic;
tx_error : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end ps2_keyboard;
-------------------------------------------------------------------------------
-- Architecture for ps2 keyboard interface
-------------------------------------------------------------------------------
architecture rtl of ps2_keyboard is
-----------------------------------------------------------------------------
constant TOTAL_BITS : integer := 11;
constant EXTEND_CODE : integer := 16#E0#;
constant RELEASE_CODE : integer := 16#F0#;
constant LEFT_SHIFT : integer := 16#12#;
constant RIGHT_SHIFT : integer := 16#59#;
constant CTRL_CODE : integer := 16#14#;
constant LEFT_ALT : integer := 16#11#;
constant CAPS_CODE : integer := 16#58#;
constant SCROLL_LOCK : integer := 16#7E#;
constant NUM_LOCK : integer := 16#77#;
-- constants
-- The timer value can be up to (2^bits) inclusive.
-- Values for 49.152 MHz clock
--constant TIMER_60USEC_VALUE_PP : integer := 2950; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 186; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
-- Values for 12.5 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 750; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 10; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 62; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 6; -- Number of bits needed for timer
-- Values for 25 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 1500; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 11; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 125; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 7; -- Number of bits needed for timer
-- Values for generic Clock up to 50 MHz
constant TIMER_60USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 60; -- Number of clock cycles for 60usec.
constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
constant TIMER_5USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 5; -- Number of clock cycles for debounce
constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Default: No shift key trap.
-- State encodings, provided as constants
-- for flexibility to the one instantiating the module.
-- In general, the default values need not be changed.
-- State "m1_rx_clk_l" has been chosen on purpose. Since the input
-- synchronizing flip-flops initially contain zero, it takes one clk
-- for them to update to reflect the actual (idle = high) status of
-- the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
-- allows the state machine to transition to m1_rx_clk_h when the true
-- values of the input signals become present at the outputs of the
-- synchronizing flip-flops. This initial transition is harmless, and it
-- eliminates the need for a "reset" pulse before the interface can operate.
type m1_type is ( m1_rx_clk_h, m1_rx_clk_l,
m1_tx_wait_clk_h, m1_tx_force_clk_l,
m1_tx_clk_h, m1_tx_clk_l,
m1_tx_wait_keyboard_ack, m1_tx_done_recovery,
m1_tx_error, m1_tx_rising_edge_marker,
m1_tx_first_wait_clk_h, m1_tx_first_wait_clk_l, m1_tx_reset_timer,
m1_rx_falling_edge_marker, m1_rx_rising_edge_marker );
-- Internal signal declarations
signal timer_60usec_done : std_logic;
signal timer_5usec_done : std_logic;
signal extended : std_logic;
signal released : std_logic;
signal shift_key_on : std_logic;
signal ctrl_key_on : std_logic;
signal caps_key_on : std_logic;
-- NOTE: These two signals used to be one. They
-- were split into two signals because of
-- shift key trapping. With shift key
-- trapping, no event is generated externally,
-- but the "hold" data must still be cleared
-- anyway regardless, in preparation for the
-- next scan codes.
signal rx_output_event : std_logic; -- Used only to clear: hold_released, hold_extended
signal rx_output_strobe : std_logic; -- Used to produce the actual output.
signal tx_parity_bit : std_logic;
signal rx_shifting_done : std_logic;
signal tx_shifting_done : std_logic;
signal shift_key_plus_code: std_logic_vector(8 downto 0);
signal q : std_logic_vector(TOTAL_BITS-1 downto 0);
signal m1_state : m1_type;
signal m1_next_state : m1_type;
signal bit_count : std_logic_vector(3 downto 0);
signal enable_timer_60usec: std_logic;
signal enable_timer_5usec : std_logic;
signal timer_60usec_count : std_logic_vector(TIMER_60USEC_BITS_PP-1 downto 0);
signal timer_5usec_count : std_logic_vector(TIMER_5USEC_BITS_PP-1 downto 0);
signal ascii : std_logic_vector(7 downto 0); -- "REG" type only because a case statement is used.
signal left_shift_key : std_logic;
signal right_shift_key : std_logic;
signal hold_extended : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal hold_released : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal ps2_clk_s : std_logic; -- Synchronous version of this input
signal ps2_data_s : std_logic; -- Synchronous version of this input
signal ps2_clk_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal ps2_data_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal tx_data_empty_o : std_logic;
--
-- key lookup table
--
component keymap_rom
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
begin
my_key_map : keymap_rom
Port map (
clk => clk,
rst => reset,
cs => '1',
rw => '1',
addr => shift_key_plus_code,
data_in => "00000000",
data_out => ascii
);
----------------------------------------------------------------------------
-- Module code
-- assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
-- assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
--
ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z )
begin
if( ps2_clk_hi_z = '1' ) then
ps2_clk <= 'Z';
else
ps2_clk <= '0';
end if;
if( ps2_data_hi_z = '1' ) then
ps2_data <= 'Z';
else
ps2_data <= '0';
end if;
end process;
-- Input "synchronizing" logic -- synchronizes the inputs to the state
-- machine clock, thus avoiding errors related to
-- spurious state machine transitions.
ps2_synch : process(clk, ps2_clk, ps2_data)
begin
if clk'event and clk='0' then
ps2_clk_s <= ps2_clk;
ps2_data_s <= ps2_data;
end if;
end process;
-- State register
m1_state_register : process( clk, reset, m1_state )
begin
if clk'event and clk='0' then
if (reset = '1') then
m1_state <= m1_rx_clk_h;
else
m1_state <= m1_next_state;
end if;
end if;
end process;
m1_state_logic : process( m1_state, q,
tx_shifting_done, tx_write,
ps2_clk_s, ps2_data_s,
timer_60usec_done, timer_5usec_done )
begin
-- Output signals default to this value, unless changed in a state condition.
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
case (m1_state) is
--
-- receive clock transitions
--
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
end if;
when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;
when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;
--
-- write to keyboard (Tx)
--
when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;
when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;
when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
-- This state must be included because the device might possibly
-- delay for up to 10 milliseconds before beginning its clock pulses.
-- During that waiting time, we cannot drive the data (q[0]) because it
-- is possibly 1, which would cause the keyboard to abort its receive
-- and the expected clocks would then never be generated.
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;
when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;
when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;
when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;
when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;
when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
end if;
when m1_tx_error =>
tx_error <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error;
end if;
when others =>
m1_next_state <= m1_rx_clk_h;
end case;
end process;
--
-- This is the bit counter
--
bit_counter: process(clk, reset, m1_state, bit_count )
begin
if clk'event and clk = '0' then
if ( reset = '1' ) or ( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done.
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and
( m1_state = m1_rx_clk_h ) and
( ps2_clk_s = '1' ) then
bit_count <= "0000"; -- rx watchdog timer reset
elsif ( m1_state = m1_rx_falling_edge_marker ) or -- increment for rx
(m1_state = m1_tx_rising_edge_marker) then -- increment for tx
bit_count <= bit_count + 1;
end if;
end if;
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;
if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
end process;
assign: process( bit_count, tx_write, m1_state, tx_data_empty_o, m1_state )
begin
--
-- This is the signal which enables loading of the shift register.
-- It also indicates "ack" to the device writing to the transmitter.
--
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_data_empty_o <= '1';
else
tx_data_empty_o <= '0';
end if;
tx_data_empty <= tx_data_empty_o;
end process;
-- This is the shift register
q_shift : process(clk, tx_data_empty_o, tx_parity_bit, tx_data,
m1_state, q, ps2_data_s, rx_shifting_done )
begin
--
-- This is the ODD parity bit for the transmitted word.
-- assign tx_parity_bit = ~^tx_data;
--
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor
tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );
if clk'event and clk='0' then
if (reset = '1') then
q <= (others=>'0');
elsif (tx_data_empty_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
end process;
--
-- This is the 60usec timer counter
--
timer60usec: process(clk, enable_timer_60usec, timer_60usec_count)
begin
if clk'event and clk = '0' then
if (enable_timer_60usec = '0') then
timer_60usec_count <= (others => '0');
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;
if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
end process;
--
-- This is the 5usec timer counter
--
timer5usec : process(clk, enable_timer_5usec, timer_5usec_count )
begin
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= (others => '0');
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
end process;
--
-- Create the signals which indicate special scan codes received.
-- These are the "unlatched versions."
--
extend_release_decode : process( q, rx_shifting_done, extended, released )
begin
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
else
rx_output_event <= '0';
end if;
end process;
--
-- Store the special scan code status bits
-- Not the final output, but an intermediate storage place,
-- until the entire set of output data can be assembled.
--
special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended, released )
begin
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
end process;
--
-- convert scan code to ascii code
--
scan_to_ascii : process( shift_key_on, caps_key_on, q )
begin
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);
end process;
--
-- These bits contain the status of the two shift keys
--
left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and (rx_shifting_done = '1') then
left_shift_key <= not hold_released;
end if;
end if;
end process;
right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and (rx_shifting_done = '1') then
right_shift_key <= not hold_released;
end if;
end if;
end process;
shift_proc : process( left_shift_key, right_shift_key, shift_key_on, caps_key_on, q )
begin
shift_key_on <= left_shift_key or right_shift_key;
rx_shift_on <= shift_key_on;
end process;
--
-- Control keys
--
ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and (rx_shifting_done = '1') then
ctrl_key_on <= not hold_released;
end if;
end if;
end process;
--
-- Caps lock
--
caps_proc : process(clk, reset, q, rx_shifting_done, hold_released, caps_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and (rx_shifting_done = '1') then
if (hold_released = '0') then
caps_key_on <= not caps_key_on;
end if;
end if;
end if;
end process;
--
-- Output the special scan code flags, the scan code and the ascii
--
special_scan_proc : process(clk, reset, rx_output_strobe,
hold_extended, hold_released,
ascii, ctrl_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
rx_data <= (others=>'0');
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
if ctrl_key_on = '1' then
rx_data <= ascii and x"1f";
else
rx_data <= ascii;
end if;
end if;
end if;
end process;
--
-- Store the final rx output data only when all extend and release codes
-- are received and the next (actual key) scan code is also ready.
-- (the presence of rx_extended or rx_released refers to the
-- the current latest scan code received, not the previously latched flags.)
--
rx_output_proc : process( clk, reset,
rx_shifting_done, rx_output_strobe,
extended, released,
hold_extended, hold_released,
q, ascii, rx_read )
begin
if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and (rx_output_strobe = '0') and
(extended = '0') and (released = '0') and
(hold_released = '0' ) and
(ascii /= "00000000" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
end process;
--
-- This part translates the scan code into an ASCII value...
-- Only the ASCII codes which I considered important have been included.
-- if you want more, just add the appropriate case statement lines...
-- (You will need to know the keyboard scan codes you wish to assign.)
-- The entries are listed in ascending order of ASCII value.
--
--shift_map : process( shift_key_plus_code )
--begin
-- case shift_key_plus_code is
-- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"00d" => ascii <= x"09"; -- Horizontal Tab
-- when x"10d" => ascii <= x"09"; -- Horizontal Tab
-- when x"05a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"15a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"076" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"176" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"029" => ascii <= x"20"; -- Space
-- when x"129" => ascii <= x"20"; -- Space
-- when x"116" => ascii <= x"21"; -- !
-- when x"152" => ascii <= x"22"; -- "
-- when x"126" => ascii <= x"23"; -- #
-- when x"125" => ascii <= x"24"; -- $
-- when x"12e" => ascii <= x"25"; --
-- when x"13d" => ascii <= x"26"; --
-- when x"052" => ascii <= x"27"; --
-- when x"146" => ascii <= x"28"; --
-- when x"145" => ascii <= x"29"; --
-- when x"13e" => ascii <= x"2a"; -- *
-- when x"155" => ascii <= x"2b"; -- +
-- when x"041" => ascii <= x"2c"; -- ,
-- when x"04e" => ascii <= x"2d"; -- -
-- when x"049" => ascii <= x"2e"; -- .
-- when x"04a" => ascii <= x"2f"; -- /
-- when x"045" => ascii <= x"30"; -- 0
-- when x"016" => ascii <= x"31"; -- 1
-- when x"01e" => ascii <= x"32"; -- 2
-- when x"026" => ascii <= x"33"; -- 3
-- when x"025" => ascii <= x"34"; -- 4
-- when x"02e" => ascii <= x"35"; -- 5
-- when x"036" => ascii <= x"36"; -- 6
-- when x"03d" => ascii <= x"37"; -- 7
-- when x"03e" => ascii <= x"38"; -- 8
-- when x"046" => ascii <= x"39"; -- 9
-- when x"14c" => ascii <= x"3a"; -- :
-- when x"04c" => ascii <= x"3b"; -- ;
-- when x"141" => ascii <= x"3c"; -- <
-- when x"055" => ascii <= x"3d"; -- =
-- when x"149" => ascii <= x"3e"; -- >
-- when x"14a" => ascii <= x"3f"; -- ?
-- when x"11e" => ascii <= x"40"; -- @
-- when x"11c" => ascii <= x"41"; -- A
-- when x"132" => ascii <= x"42"; -- B
-- when x"121" => ascii <= x"43"; -- C
-- when x"123" => ascii <= x"44"; -- D
-- when x"124" => ascii <= x"45"; -- E
-- when x"12b" => ascii <= x"46"; -- F
-- when x"134" => ascii <= x"47"; -- G
-- when x"133" => ascii <= x"48"; -- H
-- when x"143" => ascii <= x"49"; -- I
-- when x"13b" => ascii <= x"4a"; -- J
-- when x"142" => ascii <= x"4b"; -- K
-- when x"14b" => ascii <= x"4c"; -- L
-- when x"13a" => ascii <= x"4d"; -- M
-- when x"131" => ascii <= x"4e"; -- N
-- when x"144" => ascii <= x"4f"; -- O
-- when x"14d" => ascii <= x"50"; -- P
-- when x"115" => ascii <= x"51"; -- Q
-- when x"12d" => ascii <= x"52"; -- R
-- when x"11b" => ascii <= x"53"; -- S
-- when x"12c" => ascii <= x"54"; -- T
-- when x"13c" => ascii <= x"55"; -- U
-- when x"12a" => ascii <= x"56"; -- V
-- when x"11d" => ascii <= x"57"; -- W
-- when x"122" => ascii <= x"58"; -- X
-- when x"135" => ascii <= x"59"; -- Y
-- when x"11a" => ascii <= x"5a"; -- Z
-- when x"054" => ascii <= x"5b"; -- [
-- when x"05d" => ascii <= x"5c"; -- \
-- when x"05b" => ascii <= x"5d"; -- ]
-- when x"136" => ascii <= x"5e"; -- ^
-- when x"14e" => ascii <= x"5f"; -- _
-- when x"00e" => ascii <= x"60"; -- `
-- when x"01c" => ascii <= x"61"; -- a
-- when x"032" => ascii <= x"62"; -- b
-- when x"021" => ascii <= x"63"; -- c
-- when x"023" => ascii <= x"64"; -- d
-- when x"024" => ascii <= x"65"; -- e
-- when x"02b" => ascii <= x"66"; -- f
-- when x"034" => ascii <= x"67"; -- g
-- when x"033" => ascii <= x"68"; -- h
-- when x"043" => ascii <= x"69"; -- i
-- when x"03b" => ascii <= x"6a"; -- j
-- when x"042" => ascii <= x"6b"; -- k
-- when x"04b" => ascii <= x"6c"; -- l
-- when x"03a" => ascii <= x"6d"; -- m
-- when x"031" => ascii <= x"6e"; -- n
-- when x"044" => ascii <= x"6f"; -- o
-- when x"04d" => ascii <= x"70"; -- p
-- when x"015" => ascii <= x"71"; -- q
-- when x"02d" => ascii <= x"72"; -- r
-- when x"01b" => ascii <= x"73"; -- s
-- when x"02c" => ascii <= x"74"; -- t
-- when x"03c" => ascii <= x"75"; -- u
-- when x"02a" => ascii <= x"76"; -- v
-- when x"01d" => ascii <= x"77"; -- w
-- when x"022" => ascii <= x"78"; -- x
-- when x"035" => ascii <= x"79"; -- y
-- when x"01a" => ascii <= x"7a"; -- z
-- when x"154" => ascii <= x"7b"; -- {
-- when x"15d" => ascii <= x"7c"; -- |
-- when x"15b" => ascii <= x"7d"; -- }
-- when x"10e" => ascii <= x"7e"; -- ~
-- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when others => ascii <= x"00"; -- 0xff used for unlisted characters.
-- end case;
--end process;
end rtl;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00397.vhd | 1 | 16045 | -- NEED RESULT: ARCH00397.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00397.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00397: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00397: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00397
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00397(ARCH00397)
-- ENT00397_Test_Bench(ARCH00397_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00397 is
end ENT00397 ;
--
--
architecture ARCH00397 of ENT00397 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00397" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)(highb,false)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <=
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb)(highb,false) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_vector_select <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr3_vector_select <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 4 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 5 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00397" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00397" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_vector_savt <= transport Std.Standard.Now ;
chk_st_arr3_vector <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_vector_cnt <= transport s_st_arr3_vector_cnt + 1 ;
wait until (not s_st_arr3_vector(highb)(lowb,true)'Quiet) and
(s_st_arr3_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <=
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns
when 3,
--
c_st_arr3_vector_1(highb)(lowb,true) after 100 ns
when 4,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns when 6 ;
--
end ARCH00397 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00397_Test_Bench is
end ENT00397_Test_Bench ;
--
--
architecture ARCH00397_Test_Bench of ENT00397_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00397 ( ARCH00397 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00397_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/wgtr.vhd | 9 | 22085 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lptqRhamg10D7hMB5OSfJjY8BDtuC5fszVpL4E2MRYDFc7fj4Axi287anZA4s5tt0baXxcxpEVtv
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14608)
`protect data_block
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00386.vhd | 1 | 70428 | -- NEED RESULT: ARCH00386.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00386
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00386(ARCH00386)
-- ENT00386_Test_Bench(ARCH00386_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386 is
end ENT00386 ;
--
--
architecture ARCH00386 of ENT00386 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1(highb,false) after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1(highb,false) after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns ;
--
end ARCH00386 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386_Test_Bench is
end ENT00386_Test_Bench ;
--
--
architecture ARCH00386_Test_Bench of ENT00386_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00386 ( ARCH00386 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00386_Test_Bench ;
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| gpl-3.0 |
grwlf/vsim | vhdl/STD/textio.vhdl | 2 | 5335 | -- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type line is access string;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the textio package of library std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of string;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --V93
file output : text open write_mode is "STD_OUTPUT"; --V93
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --V93
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad string.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out string; good: out boolean);
procedure read (l: inout line; value: out string);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --V93
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
end textio;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/pro000025.vhd | 1 | 2249 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev, Scherbinin.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity test_generate is
generic(N:natural:=6);
port
(
in_bit : in bit;
out_bit : out bit
);
end entity test_generate;
architecture test_generate_arch of test_generate is
function resolve_bit_or(s : bit_vector) return bit is
variable v : bit := '0';
variable i : integer;
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end function resolve_bit_or;
subtype resolved_bit is resolve_bit_or bit;
signal test_resolved_bit : resolved_bit := '0';
type int_vector is array (integer range <>) of integer;
function resolve_integer_sum(s : int_vector) return integer is
variable v : integer := 0;
variable i : integer;
begin
for i in s'range loop
v := v + s(i);
end loop;
return v;
end function resolve_integer_sum;
subtype resolved_integer is resolve_integer_sum integer;
signal test_resolved_integer : resolved_integer := 0;
begin
g1: for i in 1 to N generate
test_resolved_bit <= '1';
end generate g1;
out_bit <= in_bit xor test_resolved_bit;
g2: for i in 1 to N generate
test_resolved_integer <= 1;
end generate g2;
validate_g2: process (test_resolved_integer) is
variable i : integer;
begin
i := test_resolved_integer;
assert ((i > 0 and i = N) or (i = 0))
report "PRO000025: failure: wrong number of drivers generated."
severity ERROR;
end process validate_g2;
end architecture test_generate_arch;
entity ENT00025_Test_Bench is
end ENT00025_Test_Bench;
architecture ARCH00025_Test_Bench of ENT00025_Test_Bench is
signal input, output : bit;
begin
input <= not input after 10 ns;
test_entity: entity work.test_generate
port map
(
in_bit => input,
out_bit => output
);
end ARCH00025_Test_Bench ; | gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00496.vhd | 1 | 10355 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00496
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (6)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00496(ARCH00496)
-- ENT00496_Test_Bench(ARCH00496_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00496 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - g_r1 to g_r1 ;
-- f2 : rec_arr (-g_r1 to g_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-g_r1 to g_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range g_a11 to g_a12 ;
subtype arange2 is integer range g_a21 to g_a22 ;
subtype brange1 is integer range g_b11 to g_b12 ;
subtype brange2 is integer range g_b21 to g_b22 ;
subtype crange is integer range g_c1 to g_c2 ;
subtype drange is integer range g_d1 to g_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00496 ;
--
architecture ARCH00496 of ENT00496 is
begin
B1 :
block
signal s_arr_1 : st_arr_1 ;
signal s_time_matrix : st_time_matrix ;
signal s_bit_vector : st_bit_vector ;
signal s_string : st_string ;
signal s_rec_1 : rec_1 ;
signal toggle : boolean := false ;
procedure p1 (
constant d_a11 : boolean := false ;
constant d_a12 : boolean := true ;
constant d_a21 : integer := 1 ;
constant d_a22 : integer := 5 ;
constant d_b11 : integer := 0 ;
constant d_b12 : integer := 0 ;
constant d_b21 : integer := -5 ;
constant d_b22 : integer := -3 ;
constant d_c1 : integer := 0 ;
constant d_c2 : integer := 4 ;
constant d_d1 : integer := 3 ;
constant d_d2 : integer := 5 ;
constant d_r1 : integer := 1
) is
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - d_r1 to d_r1 ;
-- f2 : rec_arr (-d_r1 to d_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-d_r1 to d_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range d_a11 to d_a12 ;
subtype arange2 is integer range d_a21 to d_a22 ;
subtype brange1 is integer range d_b11 to d_b12 ;
subtype brange2 is integer range d_b21 to d_b22 ;
subtype crange is integer range d_c1 to d_c2 ;
subtype drange is integer range d_d1 to d_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
variable v_arr_1 : st_arr_1 ;
variable v_time_matrix : st_time_matrix ;
variable v_bit_vector : st_bit_vector ;
variable v_string : st_string ;
variable v_rec_1 : rec_1 ;
variable bool : boolean := true ;
--
begin
v_arr_1 :=
( others => (others => c_rec_1_1) ) ;
v_time_matrix :=
( others => (others => 15ms) ) ;
v_bit_vector :=
( others => '0' ) ;
v_string :=
( others => 'a' ) ;
v_rec_1 :=
-- ( f2 => (others => false), others => 0) ;
( others => 0) ;
for i in 1 to 5 loop
bool := bool and v_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and v_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and v_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and v_bit_vector = B"00000" ;
--
bool := bool and v_string = "aaa" ;
--
bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0
and v_rec_1.f3 = 0 ;
-- bool := bool and v_rec_1.f2(1) = false
-- and v_rec_1.f2(0) = false and
-- v_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00496" ,
"Aggregates with others choice in signal assignment"
& " (dynamic)" ,
bool ) ;
end p1 ;
--
begin
process
variable v_arr_1 : st_arr_1 ;
variable v_time_matrix : st_time_matrix ;
variable v_bit_vector : st_bit_vector ;
variable v_string : st_string ;
variable v_rec_1 : rec_1 ;
variable bool : boolean := true ;
--
begin
s_arr_1 <=
( others => (others => c_rec_1_1) ) ;
for i in 2 to 5 loop
s_arr_1 (false, i) <= c_rec_1_2;
end loop;
s_time_matrix <=
( others => (others => 5 fs) ) ;
s_time_matrix (0, -3) <= 10 ns;
s_bit_vector <=
( others => '0' ) ;
s_bit_vector (g_c1) <= '1';
s_bit_vector (g_c1+2) <= '1';
s_string <=
"ab0" ;
s_rec_1 <=
-- ( f2 => (others => false), others => 0) ;
( others => 0) ;
s_rec_1.f3 <= 1;
toggle <= true ;
v_arr_1 :=
( others => (others => c_rec_1_1) ) ;
v_time_matrix :=
( others => (others => 15ms) ) ;
v_bit_vector :=
( others => '0' ) ;
v_string :=
( others => 'a' ) ;
v_rec_1 :=
-- ( f2 => (others => false), others => 0) ;
( others => 0) ;
for i in 1 to 5 loop
bool := bool and v_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and v_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and v_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and v_bit_vector = B"00000" ;
--
bool := bool and v_string = "aaa" ;
--
bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0
and v_rec_1.f3 = 0 ;
-- bool := bool and v_rec_1.f2(1) = false
-- and v_rec_1.f2(0) = false and
-- v_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00496" ,
"Aggregates with others choice in signal assignment"
& " (globally static)" ,
bool ) ;
wait ;
end process ;
process ( toggle )
variable bool : boolean := true ;
begin
if toggle then
bool := bool and s_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and s_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and s_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and s_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and s_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and s_bit_vector = B"10100" ;
--
bool := bool and s_string = "ab0" ;
--
bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0
and s_rec_1.f3 = 1 ;
-- bool := bool and s_rec_1.f2(1) = true
-- and s_rec_1.f2(0) = false and
-- s_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00496" ,
"Aggregates with others choice in variable assignment"
& " (globally static)" ,
bool ) ;
end if ;
p1 ( open, open, open, open,
open, open, open, open,
open, open, open, open, open ) ;
end process ;
end block B1 ;
end ARCH00496 ;
--
entity ENT00496_Test_Bench is
end ENT00496_Test_Bench ;
--
architecture ARCH00496_Test_Bench of ENT00496_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00496 ( ARCH00496 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00496_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00663.vhd | 1 | 1775 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00663
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (15)
-- 14.1 (18)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00663)
-- ENT00663_Test_Bench(ARCH00663_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-AUG-1987 - initial revision
--
-- NOTES:
--
-- NOT SELF-CHECKING : USES 3 ASSERTION STATEMENTS
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00663 of E00000 is
signal z : boolean ;
begin
B1 :
block
begin
z <= true after 1 ns ;
assert B1'BEHAVIOR and ARCH00663'BEHAVIOR and
(not B1'STRUCTURE) and (not ARCH00663'STRUCTURE) report
"ARCH00663 BLOCK B1 : BEHAVIOR/STRUCTURE test failed" ;
end block B1 ;
B2 :
block
begin
P :
process
begin
assert B2'BEHAVIOR and ARCH00663'BEHAVIOR and
(not B2'STRUCTURE) and (not ARCH00663'STRUCTURE) report
"ARCH00663 BLOCK B2 : BEHAVIOR/STRUCTURE test failed" ;
wait ;
end process P ;
end block B2 ;
end ARCH00663 ;
--
entity ENT00663_Test_Bench is
end ENT00663_Test_Bench ;
architecture ARCH00663_Test_Bench of ENT00663_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00663 ) ;
begin
assert (not L1'BEHAVIOR) and ARCH00663_Test_Bench'STRUCTURE report
"ARCH00663_Test_Bench : BEHAVIOR/STRUCTURE test failed" ;
CIS1 : UUT ;
end block L1 ;
end ARCH00663_Test_Bench ;
--
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_handshaking_flags.vhd | 9 | 12378 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_handshaking_flags.vhd | 9 | 12378 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7424)
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`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00326.vhd | 1 | 2849 | -- NEED RESULT: *** An assertion with Report ARCH00326: An assertion with complex string expressions passed and severity of Note should follow
-- NEED RESULT: ARCH00326: An assertion with complex string expressions passed
-- NEED RESULT: *** An assertion with Report ARCH00326: An assertion with complex string expressions passed and severity of Note should follow
-- NEED RESULT: ARCH00326: An assertion with complex string expressions passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00326
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00326(ARCH00326)
-- ENT00326_Test_Bench(ARCH00326_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- Check that assertion messages match comment messages in output
--
use WORK.STANDARD_TYPES.all ;
entity ENT00326 is
generic ( Lowb : Integer := 1 ;
Highb : Integer := 12 ) ;
port ( msg1 : in string ;
msg2 : in string ) ;
constant c_msg : string ( 1 to 12 ) := "passedfailed" ;
end ENT00326 ;
architecture ARCH00326 of ENT00326 is
subtype sm_string is string ( Lowb to Highb ) ;
constant cc_msg : sm_string := "failedpassed" ;
signal Dummy : Boolean := false;
begin
p1 :
process ( Dummy )
begin
print ( "*** An assertion with Report " & msg1 & msg2 & c_msg(1 to 6)
& " and severity of Note should follow" ) ;
end process p1 ;
assert Dummy
report msg1 & msg2 & c_msg(1 to 6)
severity NOTE ;
p2 :
process ( Dummy )
begin
print ( "*** An assertion with Report " & msg1 & msg2 & cc_msg(7 to Highb)
& " and severity of Note should follow" ) ;
end process p2 ;
assert Dummy
report msg1 & msg2 & cc_msg(7 to HighB)
severity NOTE ;
end ARCH00326 ;
entity ENT00326_Test_Bench is
end ENT00326_Test_Bench ;
architecture ARCH00326_Test_Bench of ENT00326_Test_Bench is
begin
L1:
block
subtype p1st is string (1 to 11) ;
signal p1 : p1st := "ARCH00326: " ;
subtype p2st is string (1 to 45) ;
signal p2 : p2st := "An assertion with complex string expressions " ;
component UUT
generic ( Lowb : Integer ;
Highb : Integer ) ;
port ( msg1 : in string ;
msg2 : in string ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00326 ( ARCH00326 ) ;
begin
CIS1 : UUT
generic map ( 1, 12 )
port map ( p1, p2 ) ;
end block L1 ;
end ARCH00326_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00033.vhd | 1 | 24181 | -- NEED RESULT: ARCH00033.P1: Target of a variable assignment may be a aggregate of indexed names passed
-- NEED RESULT: ARCH00033.P2: Target of a variable assignment may be a aggregate of indexed names passed
-- NEED RESULT: ARCH00033.P3: Target of a variable assignment may be a aggregate of indexed names passed
-- NEED RESULT: ARCH00033.P4: Target of a variable assignment may be a aggregate of indexed names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00033
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00033)
-- ENT00033_Test_Bench(ARCH00033_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00033 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
(
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ;
--
(
v_st_arr1_1(st_arr1'Left)
, v_st_arr1_2(st_arr1'Left)
, v_st_arr1_3(st_arr1'Left)
) :=
arr_st_int1 ' (
(others => c_st_arr1_2(st_arr1'Right))) ;
--
(
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ;
--
(
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2))
) :=
arr_st_rec3 ' (
(others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ;
--
correct := correct and
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_2(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_3(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00033.P1" ,
"Target of a variable assignment may be a " &
"aggregate of indexed names" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
(
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ;
--
(
v_st_arr1_1(st_arr1'Left)
, v_st_arr1_2(st_arr1'Left)
, v_st_arr1_3(st_arr1'Left)
) :=
arr_st_int1 ' (
(others => c_st_arr1_2(st_arr1'Right))) ;
--
(
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ;
--
(
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2))
) :=
arr_st_rec3 ' (
(others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ;
--
correct := correct and
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_2(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_3(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00033.P2" ,
"Target of a variable assignment may be a " &
"aggregate of indexed names" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
(
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ;
--
(
v_st_arr1_1(st_arr1'Left)
, v_st_arr1_2(st_arr1'Left)
, v_st_arr1_3(st_arr1'Left)
) :=
arr_st_int1 ' (
(others => c_st_arr1_2(st_arr1'Right))) ;
--
(
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ;
--
(
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2))
) :=
arr_st_rec3 ' (
(others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ;
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_2(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
correct := correct and
v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_3(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00033.P3" ,
"Target of a variable assignment may be a " &
"aggregate of indexed names" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec3_2 : inout st_rec3
; v_st_arr1_2 : inout st_arr1
; v_st_arr2_2 : inout st_arr2
; v_st_arr3_2 : inout st_arr3
)
is
begin
(
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2))
, v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ;
--
(
v_st_arr1_1(st_arr1'Left)
, v_st_arr1_2(st_arr1'Left)
, v_st_arr1_3(st_arr1'Left)
) :=
arr_st_int1 ' (
(others => c_st_arr1_2(st_arr1'Right))) ;
--
(
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2))
, v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2))
) :=
arr_st_arr1 ' (
(others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ;
--
(
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2))
, v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2))
) :=
arr_st_rec3 ' (
(others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ;
--
end Proc1 ;
begin
Proc1 (
v_st_rec3_1
, v_st_arr1_1
, v_st_arr2_1
, v_st_arr3_1
) ;
correct := correct and
v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
Proc1 (
v_st_rec3_2
, v_st_arr1_2
, v_st_arr2_2
, v_st_arr3_2
) ;
correct := correct and
v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_2(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
Proc1 (
v_st_rec3_3
, v_st_arr1_3
, v_st_arr2_3
, v_st_arr3_3
) ;
correct := correct and
v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1_3(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00033.P4" ,
"Target of a variable assignment may be a " &
"aggregate of indexed names" ,
correct) ;
end process P4 ;
--
end ARCH00033 ;
--
entity ENT00033_Test_Bench is
end ENT00033_Test_Bench ;
--
architecture ARCH00033_Test_Bench of ENT00033_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00033 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00033_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00657.vhd | 1 | 4754 | -- NEED RESULT: ARCH00657: Multiple interface declarations in correct order passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00657
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00657(ARCH00657)
-- ENT00657_Test_Bench(ARCH00657_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00657 is
generic (
cinteger1, cinteger2, cinteger3 : integer ;
cbool1, cbool2, cbool3 : boolean ;
cstring1, cstring2, cstring3 : string
) ;
port (
sinteger1, sinteger2, sinteger3 : integer ;
sbool1, sbool2, sbool3 : boolean ;
sstring1, sstring2, sstring3 : string
) ;
end ENT00657 ;
--
architecture ARCH00657 of ENT00657 is
procedure p1 (
constant cinteger1, cinteger2, cinteger3 : integer ;
constant cbool1, cbool2, cbool3 : boolean ;
constant cstring1, cstring2, cstring3 : string ;
variable vinteger1, vinteger2, vinteger3 : inout integer ;
variable vbool1, vbool2, vbool3 : inout boolean ;
variable vstring1, vstring2, vstring3 : inout string ;
signal sinteger1, sinteger2, sinteger3 : integer ;
signal sbool1, sbool2, sbool3 : boolean ;
signal sstring1, sstring2, sstring3 : string ;
variable correct : out boolean
) is
begin
correct :=
cinteger1 = 1 and
cinteger2 = 2 and
cinteger3 = 3 and
cbool1 = true and
cbool2 = false and
cbool3 = true and
cstring1 = "aa" and
cstring2 = "bb" and
cstring3 = "cc" and
vinteger1 = 1 and
vinteger2 = 2 and
vinteger3 = 3 and
vbool1 = true and
vbool2 = false and
vbool3 = true and
vstring1 = "aa" and
vstring2 = "bb" and
vstring3 = "cc" and
sinteger1 = 1 and
sinteger2 = 2 and
sinteger3 = 3 and
sbool1 = true and
sbool2 = false and
sbool3 = true and
sstring1 = "aa" and
sstring2 = "bb" and
sstring3 = "cc" ;
end p1 ;
begin
process
subtype str is string ( 1 to 2 ) ;
variable correct : boolean ;
variable vinteger1 : integer := cinteger1 ;
variable vinteger2 : integer := cinteger2 ;
variable vinteger3 : integer := cinteger3 ;
variable vbool1 : boolean := cbool1 ;
variable vbool2 : boolean := cbool2 ;
variable vbool3 : boolean := cbool3 ;
variable vstring1 : str := cstring1 ;
variable vstring2 : str := cstring2 ;
variable vstring3 : str := cstring3 ;
begin
p1 (
cinteger1, cinteger2, cinteger3,
cbool1, cbool2, cbool3,
cstring1, cstring2, cstring3,
vinteger1, vinteger2, vinteger3,
vbool1, vbool2, vbool3,
vstring1, vstring2, vstring3,
sinteger1, sinteger2, sinteger3,
sbool1, sbool2, sbool3,
sstring1, sstring2, sstring3,
correct ) ;
test_report ( "ARCH00657" ,
"Multiple interface declarations in correct order" ,
correct ) ;
wait ;
end process ;
end ARCH00657 ;
--
entity ENT00657_Test_Bench is
end ENT00657_Test_Bench ;
architecture ARCH00657_Test_Bench of ENT00657_Test_Bench is
subtype str is string ( 1 to 2 ) ;
signal sinteger1 : integer := 1 ;
signal sinteger2 : integer := 2 ;
signal sinteger3 : integer := 3 ;
signal sbool1 : boolean := true ;
signal sbool2 : boolean := false ;
signal sbool3 : boolean := true ;
signal sstring1 : str := "aa" ;
signal sstring2 : str := "bb" ;
signal sstring3 : str := "cc" ;
begin
L1:
block
component UUT
generic (
cinteger1, cinteger2, cinteger3 : integer ;
cbool1, cbool2, cbool3 : boolean ;
cstring1, cstring2, cstring3 : string
) ;
port (
sinteger1, sinteger2, sinteger3 : integer ;
sbool1, sbool2, sbool3 : boolean ;
sstring1, sstring2, sstring3 : string
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00657 ( ARCH00657 ) ;
begin
CIS1 : UUT
generic map ( 1, 2, 3, true, false, true, "aa", "bb", "cc" )
port map ( sinteger1, sinteger2, sinteger3,
sbool1, sbool2, sbool3,
sstring1, sstring2, sstring3 ) ;
end block L1 ;
end ARCH00657_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00346.vhd | 1 | 3150 | -- NEED RESULT: ARCH00346: Indexed names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00346
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 6.4 (1)
-- 6.4 (2)
-- 6.4 (3)
-- 6.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00346(ARCH00346)
-- ENT00346_Test_Bench(ARCH00346_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00346 is
generic ( g : integer := 2 ) ;
begin
end ENT00346 ;
architecture ARCH00346 of ENT00346 is
begin
P :
process
function f ( x : integer ) return st_arr1 is
variable a : st_arr1 := c_st_arr1_2 ;
begin
return a ;
end f ;
function "+" ( a,b : st_arr1 )
return st_arr1 is
variable c : st_arr1 ;
begin
for i in st_arr1'range loop
c(i) := a(i) + b(i) ;
end loop ;
return c ;
end "+" ;
variable i1,i2,i3,i4,i5,i6,i7,i8,i9 : t_int1 := 3;
variable j : integer := 3 ;
variable b : boolean ;
variable a : st_arr1 := c_st_arr1_2 ;
variable r : st_rec3 := c_st_rec3_2 ;
constant c_integer_2 : integer := 10;
begin
i1 := a(1) ; -- this tests 6.4 (2)
i2 := a(g-1) ; -- this tests 6.4 (3)
i3 := a(j+1) ; -- this tests 6.4 (4)
-- these test 6.4 (1)
i4 := a (1) ; -- prefix is a simple name
i5 := r.f3 (lowb,false) (1); -- prefix of (lowb,false) is a selected name
-- prefix of (1) is an indexed name
i6 := a (2 to 4) (j) ; -- prefix of (j) is a slice name
i7 := f(j) (1) ; -- prefix is a function call
i8 := "+" (a,a) (1) ; -- prefix of (a,a) is an operator symbol
i9 := t_int1(a'left(1)) ; -- prefix is an attribute name
test_report ( "ARCH00346" ,
"Indexed names" ,
(i1 = t_int1( c_integer_2 - 1))
and (i2 = t_int1( c_integer_2 - 1))
and (i3 = t_int1( c_integer_2 - 1))
and (i4 = t_int1( c_integer_2 - 1))
and (i5 = t_int1( c_integer_2 - 1))
and (i6 = t_int1( c_integer_2 - 1))
and (i7 = t_int1( c_integer_2 - 1))
and (i8 = 2*t_int1( c_integer_2 - 1))
and (i9 = t_int1(lowb))
) ;
wait ;
end process P ;
end ARCH00346 ;
entity ENT00346_Test_Bench is
end ENT00346_Test_Bench ;
architecture ARCH00346_Test_Bench of ENT00346_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00346 ( ARCH00346 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00346_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/sha256/rtl/sha256_pc.vhd | 4 | 9814 | --
-- Copyright (c) 2011 OrphanedGland ([email protected])
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00662.vhd | 1 | 5414 |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00662
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (19)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00662(ARCH00662)
-- ENT00662_Test_Bench(ARCH00662_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all;
entity ENT00662 is
port ( Pt1 : buffer Bit_Vector ;
Pt2 : buffer Integer ) ;
end ENT00662 ;
--
architecture ARCH00662 of ENT00662 is
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
begin
P2 :
process -- Check formal port on entity (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00662" ,
"The predefined attributes of an interface "&
"object (port) of mode 'buffer' for an entity may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process P2 ;
P3 :
process ( Pt2 ) -- Check formal port on entity (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00662" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'buffer' for an entity may "&
"be read" ,
(Pt2'DELAYED(10 ns) = -2) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
) ;
end if ;
end process P3 ;
L1 : -- Check block ports/generics
block
port ( Pt1 : buffer Bit_Vector ;
Pt2 : buffer Real ) ;
port map ( Pt1 => Pt1, To_Integer(Pt2) => To_Real(Pt2) ) ;
begin
BP2 :
process -- Check formal port on block (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00662" ,
"The predefined attributes of an interface "&
"object (port) of mode 'buffer' for a block may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process BP2 ;
BP3 :
process ( Pt2 ) -- Check formal port on a block (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
Pt2 <= transport -1.0 after 10 ns ;
else
test_report ( "ARCH00662" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'buffer' for a block may be read" ,
(Pt2'DELAYED(10 ns) = real'left) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = real'left)
) ;
end if ;
end process BP3 ;
end block L1 ;
end ARCH00662 ;
--
entity ENT00662_Test_Bench is
end ENT00662_Test_Bench ;
architecture ARCH00662_Test_Bench of ENT00662_Test_Bench is
begin
L1:
block
component UUT
end component ;
subtype ST is Bit_Vector ( 10 to 20 ) ;
constant C : ST := B"10101010101" ;
signal S1 : ST := C ;
signal S2 : Integer := -2 ;
for CIS1 : UUT use entity WORK.ENT00662 ( ARCH00662 )
port map ( S1, S2 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00662_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00495.vhd | 1 | 7759 | -- NEED RESULT: ARCH00495: Aggregates with others choice in signal assignment (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00495
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (6)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00495(ARCH00495)
-- ENT00495_Test_Bench(ARCH00495_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00495 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00495 ;
--
architecture ARCH00495 of ENT00495 is
begin
B1 :
block
signal s_arr_1 : st_arr_1 ;
signal s_time_matrix : st_time_matrix ;
signal s_bit_vector : st_bit_vector ;
signal s_string : st_string ;
signal s_rec_1 : rec_1 ;
signal toggle : boolean := false ;
--
begin
process
variable v_arr_1 : st_arr_1 ;
variable v_time_matrix : st_time_matrix ;
variable v_bit_vector : st_bit_vector ;
variable v_string : st_string ;
variable v_rec_1 : rec_1 ;
variable bool : boolean := true ;
--
begin
s_arr_1 <=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
s_time_matrix <=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
s_bit_vector <=
( 0 => '1', 2 => '1', others => '0' ) ;
s_string <=
( 3 => 'a', 4 => 'b', others => '0' ) ;
s_rec_1 <=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
v_arr_1 :=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
v_time_matrix :=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
v_bit_vector :=
( 0 => '1', 2 => '1', others => '0' ) ;
v_string :=
( 3 => 'a', 4 => 'b', others => '0' ) ;
v_rec_1 :=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
bool := bool and v_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and v_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and v_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and v_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and v_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and v_bit_vector = B"10100" ;
--
bool := bool and v_string = "ab0" ;
--
bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0
and v_rec_1.f3 = 1 ;
-- bool := bool and v_rec_1.f2(1) = true
-- and v_rec_1.f2(0) = false and
-- v_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in signal assignment"
& " (locally static)" ,
bool ) ;
wait ;
end process ;
process ( toggle )
variable bool : boolean := true ;
begin
if toggle then
bool := bool and s_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and s_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and s_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and s_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and s_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and s_bit_vector = B"10100" ;
--
bool := bool and s_string = "ab0" ;
--
bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0
and s_rec_1.f3 = 1 ;
-- bool := bool and s_rec_1.f2(1) = true
-- and s_rec_1.f2(0) = false and
-- s_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in variable assignment"
& " (locally static)" ,
bool ) ;
end if ;
end process ;
end block B1 ;
end ARCH00495 ;
--
entity ENT00495_Test_Bench is
end ENT00495_Test_Bench ;
--
architecture ARCH00495_Test_Bench of ENT00495_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00495 ( ARCH00495 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00495_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00603.vhd | 1 | 608 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00603
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 11.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- N/A
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- will be used in conjunction with test ct00607
--
--
package PKG00603 is
procedure Proc ;
end PKG00603 ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00007.vhd | 1 | 4186 | -- NEED RESULT: ENT00007: Unassociated scalar generics with static subtypes take on default expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00007
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00007(ARCH00007)
-- ENT00007_Test_Bench(ARCH00007_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00007 is
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
begin
end ENT00007 ;
--
architecture ARCH00007 of ENT00007 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
test_report ( "ENT00007" ,
"Unassociated scalar generics with static subtypes" &
" take on default expression" ,
correct) ;
wait ;
end process ;
end ARCH00007 ;
--
entity ENT00007_Test_Bench is
end ENT00007_Test_Bench ;
--
architecture ARCH00007_Test_Bench of ENT00007_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00007 ( ARCH00007 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00007_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00501.vhd | 1 | 5857 | -- NEED RESULT: ARCH00501: Aggregates in attribute specifications (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00501
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (9)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00501(ARCH00501)
-- ENT00501_Test_Bench(ARCH00501_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00501 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00501 ;
--
architecture ARCH00501 of ENT00501 is
begin
B1 :
block
--
begin
process
type dummy is ( d1 , d2 ) ;
attribute a_arr_1 : st_arr_1 ;
attribute a_time_matrix : st_time_matrix ;
attribute a_bit_vector : st_bit_vector ;
attribute a_rec_1 : rec_1 ;
attribute a_string : st_string ;
attribute a_arr_1 of all : type is
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
attribute a_time_matrix of all : type is
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
attribute a_bit_vector of all : type is
( 0 => '1', 2 => '1', others => '0' ) ;
attribute a_string of all : type is
( 3 => 'a', 4 => 'b', others => '0' ) ;
attribute a_rec_1 of all : type is
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
variable bool : boolean := true ;
--
begin
bool := bool and dummy'a_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and dummy'a_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and dummy'a_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and dummy'a_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and dummy'a_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and dummy'a_bit_vector = B"10100" ;
--
bool := bool and dummy'a_string = "ab0" ;
--
bool := bool and dummy'a_rec_1.f1 = 0 and dummy'a_rec_1.f4 = 0
and dummy'a_rec_1.f3 = 1 ;
-- bool := bool and dummy'a_rec_1.f2(1) = true
-- and dummy'a_rec_1.f2(0) = false and
-- dummy'a_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00501" ,
"Aggregates in attribute specifications"
& " (locally static)" ,
bool ) ;
wait ;
end process ;
end block B1 ;
end ARCH00501 ;
--
entity ENT00501_Test_Bench is
end ENT00501_Test_Bench ;
--
architecture ARCH00501_Test_Bench of ENT00501_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00501 ( ARCH00501 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00501_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00067.vhd | 1 | 3275 | -- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00067.P1_1: Exit statement does not effect outer loop passed
-- NEED RESULT: ARCH00067.P1_2: Exit with a label and condition only effects labeled loop passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00067
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.10 (2)
-- 8.10 (3)
-- 8.10 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00067)
-- ENT00067_Test_Bench(ARCH00067_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00067 of E00000 is
signal Dummy : Boolean := false ;
begin
P1_1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in boolean loop
--
correct := true ;
L2 :
for j in 1 to 3 loop
correct := (j = 1) and correct ;
exit L2 ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00067.P1_1" ,
"Exit with a label and no condition only effects " &
"labeled loop",
correct ) ;
--
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00067.P1_1" ,
"Exit statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_1 ;
--
P1_2 :
process ( Dummy )
variable correct : boolean := true ;
variable done : boolean := false ;
variable counter : integer := 0 ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= c_boolean_2 loop
--
correct := (not done) and correct ;
done := true ;
v_boolean := c_boolean_2 ;
for j in 1 to 3 loop
correct := (j = 1) and correct ;
exit L1 when j = j ;
end loop ;
--
counter := counter + 1 ;
--
end loop L1 ;
--
correct := (counter = 0) and correct ;
test_report ( "ARCH00067.P1_2" ,
"Exit with a label and condition only effects " &
"labeled loop",
correct ) ;
--
end process P1_2 ;
--
--
end ARCH00067 ;
--
entity ENT00067_Test_Bench is
end ENT00067_Test_Bench ;
--
architecture ARCH00067_Test_Bench of ENT00067_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00067 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00067_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00181.vhd | 1 | 47936 | -- NEED RESULT: ARCH00181.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00181
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00181
-- PKG00181/BODY
-- ENT00181(ARCH00181)
-- ENT00181_Test_Bench(ARCH00181_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00181 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00181 ;
--
package body PKG00181 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00181 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00181.all ;
entity ENT00181 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_r_st_arr1_vector : inout r_st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_arr2_vector : inout r_st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_arr3_vector : inout r_st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_r_st_rec1_vector : inout r_st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_r_st_rec2_vector : inout r_st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_r_st_rec3_vector : inout r_st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
--
end ENT00181 ;
--
architecture ARCH00181 of ENT00181 is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_arr1_vector,
counter,
correct,
savtime,
chk_r_st_arr1_vector
) ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_arr2_vector,
counter,
correct,
savtime,
chk_r_st_arr2_vector
) ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_arr3_vector,
counter,
correct,
savtime,
chk_r_st_arr3_vector
) ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_r_st_rec1_vector,
counter,
correct,
savtime,
chk_r_st_rec1_vector
) ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_r_st_rec2_vector,
counter,
correct,
savtime,
chk_r_st_rec2_vector
) ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_r_st_rec3_vector,
counter,
correct,
savtime,
chk_r_st_rec3_vector
) ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00181 ;
--
entity ENT00181_Test_Bench is
end ENT00181_Test_Bench ;
--
architecture ARCH00181_Test_Bench of ENT00181_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00181 ( ARCH00181 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00181_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00659.vhd | 1 | 10098 | -- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for an entity may be read passed
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for a block may be read failed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (port) of mode 'inout' for an entity may be read failed
-- NEED RESULT: ARCH00659.Proc2: The predefined attributes of an interface object (variable parameter) of mode 'inout' for a subp may be read failed
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (signal parameter) of mode 'inout' for a subp may be read failed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (signal parameter) of mode 'inout' for a subp may be read passed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (port) of mode 'inout' for a block may be read passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00659
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (17)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00659
-- PKG00659/BODY
-- ENT00659(ARCH00659)
-- ENT00659_Test_Bench(ARCH00659_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00659 is
subtype ST is Bit_Vector ( 10 to 20 ) ;
type Bit_Vector_Array is array (Integer range <>) of ST;
function bf_BV (P : Bit_Vector_Array) return ST;
subtype rBV is bf_BV ST ;
type Int_Arr is array ( Integer range <> ) of Integer ;
function bf_I ( P : Int_Arr ) return Integer ;
subtype rI is bf_I Integer ;
end PKG00659 ;
package body PKG00659 is
function bf_BV (P : Bit_Vector_Array) return ST is
begin
return P(P'Left) ;
end bf_BV ;
function bf_I ( P : Int_Arr ) return Integer is
begin
return P(P'Left) ;
end bf_I ;
end PKG00659 ;
use WORK.STANDARD_TYPES.all, WORK.PKG00659.all ;
entity ENT00659 is
port ( Pt1 : inout rBV ;
Pt2 : inout rI ) ;
end ENT00659 ;
--
architecture ARCH00659 of ENT00659 is
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
procedure Proc2 ( variable G : inout Bit_Vector ) is
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659.Proc2" ,
"The predefined attributes of an interface "&
"object (variable parameter) of mode 'inout' for a "&
"subp may be read" ,
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
end Proc2 ;
Procedure Proc3 ( signal Pt1 : inout Bit_Vector;
variable correct : out boolean ) is
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
correct := (Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
;
end Proc3 ;
procedure Proc4 ( signal Pt2 : inout Integer;
variable correct : out boolean ) is
begin
correct :=
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
;
end Proc4 ;
begin
P2 :
process -- Check formal port on entity (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (port) of mode 'inout' for an entity may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process P2 ;
P3 :
process ( Pt2 ) -- Check formal port on entity (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'inout' for an entity may "&
"be read" ,
(Pt2'DELAYED(10 ns) = -2) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
) ;
end if ;
end process P3 ;
P4 :
process ( Pt2 ) -- Check formal parameters in a subprogram
variable V : Bit_Vector (10 to 20) ;
variable First_Time : boolean := True ;
variable correct : boolean ;
begin
if First_Time then
First_Time := false ;
else
Proc2 (G => V) ;
Proc3 (Pt1, correct) ;
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (signal parameter) of mode 'inout' for a subp "&
"may be read" ,
correct
) ;
Proc4 (Pt2, correct) ;
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (signal parameter) of mode 'inout' for a subp "&
"may be read" ,
correct
) ;
end if ;
end process P4 ;
L1 : -- Check block ports/generics
block
port ( Pt1 : inout Bit_Vector ;
Pt2 : inout Real ) ;
port map ( Pt1 => Pt1, To_Integer(Pt2) => To_Real(Pt2) ) ;
begin
BP2 :
process -- Check formal port on block (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (port) of mode 'inout' for a block may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process BP2 ;
BP3 :
process ( Pt2 ) -- Check formal port on a block (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'inout' for a block may be read" ,
(Pt2'DELAYED(10 ns) = -2.0) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2.0)
) ;
end if ;
end process BP3 ;
end block L1 ;
end ARCH00659 ;
--
use WORK.PKG00659.all;
entity ENT00659_Test_Bench is
end ENT00659_Test_Bench ;
architecture ARCH00659_Test_Bench of ENT00659_Test_Bench is
begin
L1:
block
component UUT
end component ;
constant C : ST := B"10101010101" ;
signal S1 : rBV := C;
signal S2 : rI := -2;
for CIS1 : UUT use entity WORK.ENT00659 ( ARCH00659 )
port map ( S1, S2 ) ;
begin
SigA : S2 <= transport -1 after 10 ns ;
CIS1 : UUT ;
end block L1 ;
end ARCH00659_Test_Bench ;
--
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/sha256_e0.vhd | 4 | 1129 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:52:46 06/02/2011
-- Design Name:
-- Module Name: sha256_e0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_e0 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_e0;
architecture Behavioral of sha256_e0 is
begin
q <= (d(1 downto 0) & d(31 downto 2)) xor (d(12 downto 0) & d(31 downto 13)) xor (d(21 downto 0) & d(31 downto 22));
end Behavioral;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00110.vhd | 1 | 12585 | -- NEED RESULT: ARCH00110.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00110
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00110(ARCH00110)
-- ENT00110_Test_Bench(ARCH00110_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00110 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00110 ;
--
architecture ARCH00110 of ENT00110 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00110 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00110_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00110_Test_Bench ;
--
architecture ARCH00110_Test_Bench of ENT00110_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00110 ( ARCH00110 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
) ;
end block L1 ;
end ARCH00110_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00315.vhd | 1 | 3863 | -- NEED RESULT: ARCH00315: Process with Sens List and End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with Sens List and No End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with No Sens List and End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with No Sens List and No End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Test completed successfully passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00315
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.2 (1)
-- 9.2 (2)
-- 9.2 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00315)
-- ENT00315_Test_Bench(ARCH00315_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00315 of E00000 is
signal s1, s2 : boolean := True ;
signal chk1, chk2, chk3, chk4, Complete : boolean := False ;
begin
P1 : -- Sensitivity List and End Label
process ( s1 )
begin
test_report ( "ARCH00315" ,
"Process with Sens List and End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk1 <= transport True ;
end process P1 ;
P2 : -- Sensitivity List and No End Label
process ( s2 )
begin
test_report ( "ARCH00315" ,
"Process with Sens List and No End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk2 <= transport True ;
end process ;
P3 : -- No Sensitivity List and End Label
process
begin
test_report ( "ARCH00315" ,
"Process with No Sens List and End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk3 <= transport True ;
wait ;
end process P3 ;
P4 : -- No Sensitivity List and No End Label
process
begin
test_report ( "ARCH00315" ,
"Process with No Sens List and No End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk4 <= transport True ;
wait ;
end process ;
complete <= transport True after 100 ns ;
Completion_Test :
process ( complete )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := False ;
else
test_report ( "ARCH00315" ,
"Test completed successfully" ,
(chk1 and chk2 and chk3 and chk4) ) ;
end if ;
end process Completion_Test ;
end ARCH00315 ;
entity ENT00315_Test_Bench is
end ENT00315_Test_Bench ;
architecture ARCH00315_Test_Bench of ENT00315_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00315 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00315_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00105.vhd | 1 | 5784 | -- NEED RESULT: ARCH00105.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00105: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00105: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00105
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00105(ARCH00105)
-- ENT00105_Test_Bench(ARCH00105_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00105 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00105 ;
--
architecture ARCH00105 of ENT00105 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00105.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00105" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00105" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00105" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
--
end ARCH00105 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00105_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00105_Test_Bench ;
--
architecture ARCH00105_Test_Bench of ENT00105_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00105 ( ARCH00105 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00105_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00078.vhd | 1 | 13459 | -- NEED RESULT: ARCH00078.P1: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078.P2: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078.P3: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00078: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00078
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00078)
-- ENT00078_Test_Bench(ARCH00078_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00078 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00078.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00078" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00078.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00078" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00078.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00078" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00078" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00078 ;
--
entity ENT00078_Test_Bench is
end ENT00078_Test_Bench ;
--
architecture ARCH00078_Test_Bench of ENT00078_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00078 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00078_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00440.vhd | 1 | 4709 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00440
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (1)
-- 7.2.4 (4)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00440(ARCH00440)
-- ENT00440_Test_Bench(ARCH00440_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.ARITHMETIC.ALL ;
entity ENT00440 is
generic (
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00440 ;
architecture ARCH00440 of ENT00440 is
constant c2_int_1 : integer :=
(-10) rem i_int_1 + i_int_1 rem i_int_2 + i_int_1 rem (i_int_1 - 1)
- i_int_2 rem (c_int_2 + 1) ;
constant c2_t_int_1 : t_int :=
(1) rem i_t_int_1 + (i_t_int_1) rem i_t_int_2 + (-i_t_int_1) rem 2 -
c_t_int_2 rem (i_t_int_2 - 1) ;
constant c2_st_int_1 : st_int :=
(-0) rem i_st_int_2 + i_t_int_1 rem (i_st_int_1) +
(i_st_int_1 rem i_t_int_2) - (c_st_int_2) rem i_t_int_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
--
begin
-- static expression
case bool is
when (
(-10) rem c_int_1 + c_int_1 rem c_int_2 + c_int_1 rem (c_int_1 - 1)
- c_int_2 rem (c_int_2 + 1) = 5 and
(1) rem c_t_int_1 + (c_t_int_1) rem c_t_int_2 + (-c_t_int_1) rem 2 -
c_t_int_2 rem (c_t_int_2 - 1) = 6 and
(-0) rem c_st_int_2 + c_t_int_1 rem (c_st_int_1) +
(c_st_int_1 rem c_t_int_2) - (c_st_int_2) rem c_t_int_2 = 3
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_int_1 = 5 and
c2_t_int_1 = 6 and
c2_st_int_1 = 3 ;
-- dynamic expression
v2_int_1 :=
(-10) rem v_int_1 + v_int_1 rem v_int_2 + v_int_1 rem (v_int_1 - 1)
- v_int_2 rem (i_int_2 + 1) ;
v2_t_int_1 :=
(1) rem v_t_int_1 + (v_t_int_1) rem v_t_int_2 + (-v_t_int_1) rem 2 -
i_t_int_2 rem (v_t_int_2 - 1) ;
v2_st_int_1 :=
(-0) rem v_st_int_2 + v_t_int_1 rem (v_st_int_1) +
(v_st_int_1 rem v_t_int_2) - (c_st_int_2) rem v_t_int_2 ;
dyn_correct := v2_int_1 = 5 and
v2_t_int_1 = 6 and
v2_st_int_1 = 3 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00440 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00440_Test_Bench is
end ENT00440_Test_Bench ;
architecture ARCH00440_Test_Bench of ENT00440_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00440 ( ARCH00440 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00440" ,
"rem predefined for integer types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00440_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00316.vhd | 1 | 3690 | -- NEED RESULT: ARCH00316: An if statement in a Process passed
-- NEED RESULT: ARCH00316: A procedure/function call and a variable asg in a Process passed
-- NEED RESULT: An assert in a Process Passed
-- NEED RESULT: ARCH00316: A case statement in a Process passed
-- NEED RESULT: ARCH00316: Loop and exit statement in a Process passed
-- NEED RESULT: ARCH00316: Loop and next statement in a Process passed
-- NEED RESULT: ARCH00316: Null, signal asg, and wait statements in a Process passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00316
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.2 (3)
-- 9.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00316)
-- ENT00316_Test_Bench(ARCH00316_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00316 of E00000 is
signal s1 : boolean := false ;
begin
P1 :
process
procedure A_Proc ( variable Entered : inout boolean ) ;
constant C : integer := 2 ;
function A_Func ( Dummy : integer := C ) return boolean is
begin
return Dummy = C ;
end A_Func ;
procedure A_Proc ( variable Entered : inout boolean ) is
begin
Entered := True ;
end A_Proc ;
type A_Type is ( e0, e1, e2, e3, e4, e5 ) ;
subtype A_Subtype is A_Type range e2 to e4 ;
alias An_Alias : Integer range 2 to 4 is C ;
variable A_Var : A_Subtype := A_Type'Val (An_Alias) ; -- e2
attribute An_Attr : A_Subtype ;
attribute An_Attr of A_Var : variable is e2 ;
variable v1, v2 : boolean ;
begin
if A_Var = A_Var'An_Attr then
test_report ( "ARCH00316" ,
"An if statement in a Process" ,
True ) ;
else
test_report ( "ARCH00316" ,
"An if statement in a Process" ,
False ) ;
end if ;
A_Proc ( v1 ) ; -- Returns True
v2 := v1 ;
test_report ( "ARCH00316" ,
"A procedure/function call and a variable asg in a Process" ,
A_Func and v1 and v2 ) ;
assert False
report "An assert in a Process Passed"
severity Note ;
case A_Subtype'Low is
when e2 =>
test_report ( "ARCH00316" ,
"A case statement in a Process" ,
True ) ;
when Others =>
test_report ( "ARCH00316" ,
"A case statement in a Process" ,
False ) ;
end case ;
loop
exit ;
v2 := false ;
end loop ;
test_report ( "ARCH00316" ,
"Loop and exit statement in a Process" ,
v2 ) ;
for i in 1 to 10 loop
next ;
v1 := false;
end loop ;
test_report ( "ARCH00316" ,
"Loop and next statement in a Process" ,
v1 ) ;
null ;
s1 <= transport Not s1 ; -- Schedule True
wait on s1 for 1 ns ;
test_report ( "ARCH00316" ,
"Null, signal asg, and wait statements in a Process" ,
s1 ) ;
wait ;
end process P1 ;
end ARCH00316 ;
entity ENT00316_Test_Bench is
end ENT00316_Test_Bench ;
architecture ARCH00316_Test_Bench of ENT00316_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00316 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00316_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00115.vhd | 1 | 6129 | -- NEED RESULT: ARCH00115.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00115: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00115: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00115
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00115(ARCH00115)
-- ENT00115_Test_Bench(ARCH00115_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00115 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00115.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00115" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00115" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00115" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
--
end ENT00115 ;
--
architecture ARCH00115 of ENT00115 is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
end process P1 ;
--
--
end ARCH00115 ;
--
entity ENT00115_Test_Bench is
end ENT00115_Test_Bench ;
--
architecture ARCH00115_Test_Bench of ENT00115_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00115 ( ARCH00115 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00115_Test_Bench ;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rdmux.vhd | 18 | 69394 | -------------------------------------------------------------------------------
-- axi_datamover_rdmux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rdmux.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_rdmux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the width of the AXI Stream Data Channel
);
port (
-- AXI MMap Data Channel Input -----------------------------------------------
--
mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
-------------------------------------------------------------------------------
-- AXI Master Stream ---------------------------------------------------------
--
mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
--Mux data output --
-------------------------------------------------------------------------------
-- Command Calculator Interface -----------------------------------------------
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
-------------------------------------------------------------------------------
);
end entity axi_datamover_rdmux;
architecture implementation of axi_datamover_rdmux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (channel_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case channel_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- 1024-bit channel case
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH;
Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
mux_data_out <= sig_rdmux_dout;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate
begin
sig_rdmux_dout <= mmap_read_data_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel input mux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_NUX
--
-- Process Description:
-- Implement the 2XN Mux
--
-------------------------------------------------------------
DO_2XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when others => -- 1 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
end case;
end process DO_2XN_NUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel input mux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_NUX
--
-- Process Description:
-- Implement the 4XN Mux
--
-------------------------------------------------------------
DO_4XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when others => -- 3 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
end case;
end process DO_4XN_NUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel input mux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_NUX
--
-- Process Description:
-- Implement the 8XN Mux
--
-------------------------------------------------------------
DO_8XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when others => -- 7 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
end case;
end process DO_8XN_NUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel input mux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_NUX
--
-- Process Description:
-- Implement the 16XN Mux
--
-------------------------------------------------------------
DO_16XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when others => -- 15 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
end case;
end process DO_16XN_NUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel input mux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_NUX
--
-- Process Description:
-- Implement the 32XN Mux
--
-------------------------------------------------------------
DO_32XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when others => -- 31 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
end case;
end process DO_32XN_NUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel input mux case
--
--
------------------------------------------------------------
GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_64XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when others => -- 63 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
end case;
end process DO_64XN_NUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel input mux case
--
--
------------------------------------------------------------
GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_128XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when 63 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
when 64 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*65)-1 downto CHANNEL_DWIDTH*64) ;
when 65 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*66)-1 downto CHANNEL_DWIDTH*65) ;
when 66 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*67)-1 downto CHANNEL_DWIDTH*66) ;
when 67 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*68)-1 downto CHANNEL_DWIDTH*67) ;
when 68 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*69)-1 downto CHANNEL_DWIDTH*68) ;
when 69 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*70)-1 downto CHANNEL_DWIDTH*69) ;
when 70 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*71)-1 downto CHANNEL_DWIDTH*70) ;
when 71 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*72)-1 downto CHANNEL_DWIDTH*71) ;
when 72 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*73)-1 downto CHANNEL_DWIDTH*72) ;
when 73 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*74)-1 downto CHANNEL_DWIDTH*73) ;
when 74 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*75)-1 downto CHANNEL_DWIDTH*74) ;
when 75 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*76)-1 downto CHANNEL_DWIDTH*75) ;
when 76 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*77)-1 downto CHANNEL_DWIDTH*76) ;
when 77 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*78)-1 downto CHANNEL_DWIDTH*77) ;
when 78 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*79)-1 downto CHANNEL_DWIDTH*78) ;
when 79 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*80)-1 downto CHANNEL_DWIDTH*79) ;
when 80 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*81)-1 downto CHANNEL_DWIDTH*80) ;
when 81 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*82)-1 downto CHANNEL_DWIDTH*81) ;
when 82 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*83)-1 downto CHANNEL_DWIDTH*82) ;
when 83 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*84)-1 downto CHANNEL_DWIDTH*83) ;
when 84 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*85)-1 downto CHANNEL_DWIDTH*84) ;
when 85 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*86)-1 downto CHANNEL_DWIDTH*85) ;
when 86 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*87)-1 downto CHANNEL_DWIDTH*86) ;
when 87 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*88)-1 downto CHANNEL_DWIDTH*87) ;
when 88 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*89)-1 downto CHANNEL_DWIDTH*88) ;
when 89 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*90)-1 downto CHANNEL_DWIDTH*89) ;
when 90 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*91)-1 downto CHANNEL_DWIDTH*90) ;
when 91 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*92)-1 downto CHANNEL_DWIDTH*91) ;
when 92 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*93)-1 downto CHANNEL_DWIDTH*92) ;
when 93 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*94)-1 downto CHANNEL_DWIDTH*93) ;
when 94 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*95)-1 downto CHANNEL_DWIDTH*94) ;
when 95 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*96)-1 downto CHANNEL_DWIDTH*95) ;
when 96 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*97 )-1 downto CHANNEL_DWIDTH*96 ) ;
when 97 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*98 )-1 downto CHANNEL_DWIDTH*97 ) ;
when 98 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*99 )-1 downto CHANNEL_DWIDTH*98 ) ;
when 99 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*100)-1 downto CHANNEL_DWIDTH*99 ) ;
when 100 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*101)-1 downto CHANNEL_DWIDTH*100) ;
when 101 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*102)-1 downto CHANNEL_DWIDTH*101) ;
when 102 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*103)-1 downto CHANNEL_DWIDTH*102) ;
when 103 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*104)-1 downto CHANNEL_DWIDTH*103) ;
when 104 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*105)-1 downto CHANNEL_DWIDTH*104) ;
when 105 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*106)-1 downto CHANNEL_DWIDTH*105) ;
when 106 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*107)-1 downto CHANNEL_DWIDTH*106) ;
when 107 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*108)-1 downto CHANNEL_DWIDTH*107) ;
when 108 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*109)-1 downto CHANNEL_DWIDTH*108) ;
when 109 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*110)-1 downto CHANNEL_DWIDTH*109) ;
when 110 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*111)-1 downto CHANNEL_DWIDTH*110) ;
when 111 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*112)-1 downto CHANNEL_DWIDTH*111) ;
when 112 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*113)-1 downto CHANNEL_DWIDTH*112) ;
when 113 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*114)-1 downto CHANNEL_DWIDTH*113) ;
when 114 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*115)-1 downto CHANNEL_DWIDTH*114) ;
when 115 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*116)-1 downto CHANNEL_DWIDTH*115) ;
when 116 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*117)-1 downto CHANNEL_DWIDTH*116) ;
when 117 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*118)-1 downto CHANNEL_DWIDTH*117) ;
when 118 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*119)-1 downto CHANNEL_DWIDTH*118) ;
when 119 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*120)-1 downto CHANNEL_DWIDTH*119) ;
when 120 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*121)-1 downto CHANNEL_DWIDTH*120) ;
when 121 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*122)-1 downto CHANNEL_DWIDTH*121) ;
when 122 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*123)-1 downto CHANNEL_DWIDTH*122) ;
when 123 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*124)-1 downto CHANNEL_DWIDTH*123) ;
when 124 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*125)-1 downto CHANNEL_DWIDTH*124) ;
when 125 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*126)-1 downto CHANNEL_DWIDTH*125) ;
when 126 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*127)-1 downto CHANNEL_DWIDTH*126) ;
when others => -- 127 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*128)-1 downto CHANNEL_DWIDTH*127) ;
end case;
end process DO_128XN_NUX;
end generate GEN_128XN;
end implementation;
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux4_1_x_n.vhd | 18 | 5491 | -------------------------------------------------------------------------------
-- axi_datamover_dre_mux4_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
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--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux4_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 4 to 1 by N bits wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 4 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux4_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 4x Mux slice
);
port (
Sel : In std_logic_vector(1 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux4_1_x_n; --
Architecture implementation of axi_datamover_dre_mux4_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT4_1
--
-- Process Description:
-- This process implements an 4 to 1 mux.
--
-------------------------------------------------------------
SELECT4_1 : process (Sel, I0, I1, I2, I3)
begin
case Sel is
when "00" =>
Y <= I0;
when "01" =>
Y <= I1;
when "10" =>
Y <= I2;
when "11" =>
Y <= I3;
when others =>
Y <= I0;
end case;
end process SELECT4_1;
end implementation; -- axi_datamover_dre_mux4_1_x_n
-------------------------------------------------------------------------------
-- End 4 to 1 xN Mux
-------------------------------------------------------------------------------
| gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/lib_fifo_v1_0/hdl/src/vhdl/sync_fifo_fg.vhd | 7 | 70413 | -- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| gpl-3.0 |
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