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blutsvente/MIX | test/results/udc/inst_xa_e-rtl-a.vhd | 1 | 1494 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_xa_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_xa_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_xa_e
--
architecture rtl of inst_xa_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/proc5.vhd | 5 | 941 | entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedure;
procedure create_clock
( signal clk : inout std_logic;
period : in delay_length;
signal running : in boolean ) is
begin
if running then
clk <= not clk after period / 2;
end if;
end procedure;
signal running : boolean := true;
signal clk : std_logic := '1';
begin
process (clk, running) is
begin
create_clock(clk, 20 ns, running);
end process;
process is
begin
next_cycle(clk, 50);
assert now = 1001 ns;
running <= false;
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_shadow_ok_3_e-c.vhd | 1 | 1361 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_3_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_3_e-c.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_3_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_3_rtl_conf / inst_shadow_ok_3_e
--
configuration inst_shadow_ok_3_rtl_conf of inst_shadow_ok_3_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_3_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_3_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/parse/ir1045.vhd | 4 | 208 | architecture e of a is
begin
-- Test corner case in lexer
-- http://www.eda-stds.org/isac/IRs-VHDL-93/IR1045.txt
x <= bit_vector'('1','2','3');
y <= bit'('1');
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_ok_4_e-e.vhd | 1 | 1305 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ok_4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_4_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_ok_4_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ok_4_e
--
entity inst_ok_4_e is
-- Generics:
-- No Generated Generics for Entity inst_ok_4_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ok_4_e
end inst_ok_4_e;
--
-- End of Generated Entity inst_ok_4_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/spec.vhd | 4 | 1248 | entity c1_ent1 is
end entity;
-------------------------------------------------------------------------------
package p is
end package;
-------------------------------------------------------------------------------
entity e is
end entity;
architecture a of e is
component c1 is
end component;
component c2 is
end component;
for i1: c2 use entity work.c1_ent1; -- Error
for i1: e use entity work.c1_ent1; -- Error
for i1: c1 use entity work.c1_ent1; -- OK
for bad: c1 use entity work.c1_ent1; -- Error
for i2: c1 use entity work.c1_ent1; -- Error
for i1: c1 use entity work.c1_ent1; -- Error
for i3: c1 use entity work.not_here; -- Error
for i3: c1 use entity work.p; -- Error
for all: c2 use entity work.c1_ent1; -- OK
for i5: c1 use entity work.c1_ent1; -- Error
for all: c2 use entity work.c1_ent1; -- Error
for others: c1 use entity work.c1_ent1; -- OK
for i7: c1 use open; -- OK
begin
i1: component c1;
i2: entity work.e;
i3: component c1;
i4: component c2;
b1: block is
begin
i5: component c1;
end block;
i6: component c1;
i7: component c1;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/parse/concat.vhd | 4 | 213 | architecture a of b is
signal x : bit_vector(1 to 3);
signal y : bit_vector(1 to 2);
begin
x <= y & '0';
process is
begin
p := q & g & ('1', '1');
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/20060424a/cgu-e.vhd | 1 | 1219 | -- -------------------------------------------------------------
--
-- Entity Declaration for cgu
--
-- Generated
-- by: wig
-- on: Tue Apr 25 19:40:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: cgu-e.vhd,v 1.1 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: cgu-e.vhd,v $
-- Revision 1.1 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity cgu
--
entity cgu is
-- Generics:
-- No Generated Generics for Entity cgu
-- Generated Port Declaration:
-- No Generated Port for Entity cgu
end cgu;
--
-- End of Generated Entity cgu
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/logic/inst_a_e-e.vhd | 1 | 1638 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 10:55:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.3 2005/07/18 08:59:29 wig Exp $
-- $Date: 2005/07/18 08:59:29 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.3 2005/07/18 08:59:29 wig
-- do not write config for simple logic
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.56 2005/07/15 16:39:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
and_o1 : out std_ulogic;
and_o2 : out std_ulogic_vector(15 downto 0);
or_o1 : out std_ulogic;
or_o2 : out std_ulogic_vector(15 downto 0);
wire_bus_i : in std_ulogic_vector(7 downto 0);
wire_bus_o : out std_ulogic_vector(7 downto 0);
wire_i : in std_ulogic;
wire_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/20051121a/ent_aba-e.vhd | 1 | 1443 | -- -------------------------------------------------------------
--
-- Entity Declaration for ent_aba
--
-- Generated
-- by: wig
-- on: Wed Nov 30 13:58:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aba-e.vhd,v 1.2 2005/11/30 14:04:14 wig Exp $
-- $Date: 2005/11/30 14:04:14 $
-- $Log: ent_aba-e.vhd,v $
-- Revision 1.2 2005/11/30 14:04:14 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aba
--
entity ent_aba is
-- Generics:
-- No Generated Generics for Entity ent_aba
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aba
sc_p_1 : out std_ulogic; -- bad conection bits detected
sc_p_2 : out std_ulogic_vector(31 downto 0) -- reverse order
-- End of Generated Port for Entity ent_aba
);
end ent_aba;
--
-- End of Generated Entity ent_aba
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/array3.vhd | 5 | 530 | entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/regress/generic1.vhd | 5 | 641 | entity bot is
generic ( constant N : integer );
port ( x : out integer );
end entity;
architecture test of bot is
begin
x <= N;
end architecture;
-------------------------------------------------------------------------------
entity generic1 is
end entity;
architecture test of generic1 is
signal xa, xb : integer;
begin
a: entity work.bot
generic map ( 5 )
port map ( xa );
b: entity work.bot
generic map ( 7 )
port map ( xb );
process is
begin
wait for 1 ns;
assert xa = 5;
assert xb = 7;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/regress/func17.vhd | 5 | 477 | entity func17 is
end entity;
architecture test of func17 is
function func(x : bit_vector) return bit_vector is
variable y : bit_vector(1 to x'length) := x;
begin
y(1 + x'length / 2) := '1'; -- Would corrupt X
return y;
end function;
begin
process is
variable b : bit_vector(1 to 3);
begin
b := "101";
assert func(b) = "111";
assert b = "101";
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/padio/names/a_clk-rtl-conf-c.vhd | 1 | 2323 | -- -------------------------------------------------------------
--
-- Generated Configuration for a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: a_clk-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration a_clk_rtl_conf / a_clk
--
configuration a_clk_rtl_conf of a_clk is
for rtl
-- Generated Configuration
for control : a_fsm
use configuration work.a_fsm_rtl_conf;
end for;
for ios : ios_e
use configuration work.ios_e_conf;
end for;
for pad_pads : pad_pads_e
use configuration work.pad_pads_e_conf;
end for;
for test_ctrl : testctrl_e
use configuration work.testctrl_e_rtl_conf;
end for;
for u0_alreg : alreg
use configuration work.alreg_rtl_conf;
end for;
for u1_alreg : alreg
use configuration work.alreg_rtl_conf;
end for;
for u2_alreg : alreg
use configuration work.alreg_rtl_conf;
end for;
for u3_alreg : alreg
use configuration work.alreg_rtl_conf;
end for;
for u_counter : count4
use configuration work.count4_rtl_conf;
end for;
for u_ddrv4 : ddrv4
use configuration work.ddrv4_rtl_conf;
end for;
for u_keypad : keypad
use configuration work.keypad_rtl_conf;
end for;
for u_keyscan : keyscan
use configuration work.keyscan_rtl_conf;
end for;
for u_timegen : timegen
use configuration work.timegen_rtl_conf;
end for;
end for;
end a_clk_rtl_conf;
--
-- End of Generated Configuration a_clk_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_shadow_2_e-e.vhd | 1 | 1341 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_2_e-e.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_shadow_2_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_2_e
--
entity inst_shadow_2_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_2_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_2_e
end inst_shadow_2_e;
--
-- End of Generated Entity inst_shadow_2_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/verilog/mixed/ent_ad-rtl-conf-c.vhd | 1 | 1309 | -- -------------------------------------------------------------
--
-- Generated Configuration for ent_ad
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:27 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-conf-c.vhd,v 1.4 2005/07/19 07:13:20 wig Exp $
-- $Date: 2005/07/19 07:13:20 $
-- $Log: ent_ad-rtl-conf-c.vhd,v $
-- Revision 1.4 2005/07/19 07:13:20 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ad_rtl_conf / ent_ad
--
configuration ent_ad_rtl_conf of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_rtl_conf;
--
-- End of Generated Configuration ent_ad_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/elab/issue17.vhd | 5 | 614 | entity comp4_bot is
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp4_bot is
begin
y <= x;
end architecture;
-------------------------------------------------------------------------------
entity issue17 is
end entity;
architecture rtl of issue17 is
signal b: bit_vector(7 downto 0);
component comp4_bot is
port (
y : out bit_vector(7 downto 0);
x : in bit_vector(7 downto 0) );
end component;
begin
c1: component comp4_bot
port map ( x=>x"aa", y=>b );
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_10_e-e.vhd | 1 | 1287 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_10_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_10_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_10_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_10_e
--
entity inst_10_e is
-- Generics:
-- No Generated Generics for Entity inst_10_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_10_e
end inst_10_e;
--
-- End of Generated Entity inst_10_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_10_e-rtl-conf-c.vhd | 1 | 1304 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_10_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_10_e-rtl-conf-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_10_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_10_e_rtl_conf / inst_10_e
--
configuration inst_10_e_rtl_conf of inst_10_e is
for rtl
-- Generated Configuration
end for;
end inst_10_e_rtl_conf;
--
-- End of Generated Configuration inst_10_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/padio/bus/ios_e-e.vhd | 1 | 4439 | -- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.2 2005/10/06 11:16:05 wig Exp $
-- $Date: 2005/10/06 11:16:05 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.2 2005/10/06 11:16:05 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_0_0_gi : in std_ulogic; -- __W_SINGLEBITBUS
p_mix_iosel_disp_gi : in std_ulogic_vector(3 downto 0);
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/case/check/inst_a_e-rtl-conf-c.vhd | 1 | 1566 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_A_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:18:10 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2007/03/05 08:58:59 wig Exp $
-- $Date: 2007/03/05 08:58:59 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 08:58:59 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_A_e_rtl_conf / inst_A_e
--
configuration inst_A_e_rtl_conf of inst_A_e is
for rtl
-- Generated Configuration
for INST_AA : INST_AA_e
use configuration work.INST_AA_e_rtl_conf;
end for;
end for;
end inst_A_e_rtl_conf;
--
-- End of Generated Configuration inst_A_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/group/arrayref1.vhd | 4 | 584 | entity arrayref is
end entity;
architecture test of arrayref is
type bv2d is array (integer range <>) of bit_vector(1 downto 0);
signal x : bit_vector(2 downto 0); -- 0..2
signal y : bit_vector(1 downto 0); -- 3..4
signal i : integer; -- 5..5
signal p : bv2d(0 to 1); -- 6..9
signal q : bv2d(0 to 2); -- 10..15
signal r : bv2d(0 to 2); -- 16..21
begin
x(0) <= '1';
x(1) <= '0';
y(i) <= '1';
p(0)(i) <= '1';
p(1) <= "00";
q(i) <= "10";
r(2)(i) <= '1';
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/regress/proc11.vhd | 5 | 627 | entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/lower/func5.vhd | 4 | 457 | entity func5 is
end entity;
architecture test of func5 is
function add_one_s(signal s : in integer) return integer is
begin
return s + 1;
end function;
function event(signal s : in integer) return boolean is
begin
return s'event;
end function;
signal x : integer := 5;
begin
process is
begin
assert add_one_s(x) = 6;
assert event(x);
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_2_e-rtl-a.vhd | 1 | 1455 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_2_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_2_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_2_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_2_e
--
architecture rtl of inst_2_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bitsplice/connport/ent_ac-rtl-a.vhd | 1 | 1488 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ac-rtl-a.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: ent_ac-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ac
--
architecture rtl of ent_ac is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/sigport/verilog/ent_ad-e.vhd | 1 | 1386 | -- -------------------------------------------------------------
--
-- Entity Declaration for ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-e.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_ad-e.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ad
--
entity ent_ad is
-- Generics:
-- No Generated Generics for Entity ent_ad
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end ent_ad;
--
-- End of Generated Entity ent_ad
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/issue128.vhd | 5 | 400 | package A_NG is
procedure PROC(SEL: in integer);
end package;
package body A_NG is
procedure PROC(SEL: in integer) is
begin
case SEL is
when 0 | 1 => -- Used to crash in sem_hoist_for_loop_var
for i in 0 to 3 loop
end loop;
when others =>
null;
end case;
end procedure;
end package body;
| gpl-3.0 |
mitchsm/nvc | test/bounds/issue99.vhd | 5 | 321 | entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
| gpl-3.0 |
blutsvente/MIX | test/results/mde_tests/conn_nreset/inst_e_e-e.vhd | 1 | 1488 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.1 2004/04/06 10:50:20 wig Exp $
-- $Date: 2004/04/06 10:50:20 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:20 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_e_e
cgs_ramclk : out std_ulogic;
p_mix_nreset_go : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/autoopen/noaopen/inst_t_e-rtl-conf-c.vhd | 1 | 1391 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/verilog/inst_t_e-rtl-a.vhd | 1 | 2850 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- b instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- b instance
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/case/force/inst_ac_e-rtl-a.vhd | 1 | 1544 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-rtl-a.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ac_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ac_e
--
architecture rtl of inst_ac_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/ramd/vgca_mm-e.vhd | 1 | 1481 | -- -------------------------------------------------------------
--
-- Entity Declaration for vgca_mm
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_mm-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: vgca_mm-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity vgca_mm
--
entity vgca_mm is
-- Generics:
-- No Generated Generics for Entity vgca_mm
-- Generated Port Declaration:
port(
-- Generated Port for Entity vgca_mm
ramd_i : in std_ulogic_vector(31 downto 0);
ramd_i2 : in std_ulogic_vector(31 downto 0);
ramd_i3 : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity vgca_mm
);
end vgca_mm;
--
-- End of Generated Entity vgca_mm
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/20051004c/inst_bug_e-e.vhd | 1 | 1594 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_bug_e
--
-- Generated
-- by: wig
-- on: Thu Oct 6 12:55:50 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bug_e-e.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $
-- $Date: 2005/10/06 13:36:57 $
-- $Log: inst_bug_e-e.vhd,v $
-- Revision 1.1 2005/10/06 13:36:57 wig
-- New testcase or generics
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_bug_e
--
entity inst_bug_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_bug_e
CHROMA_GROUP_DELAY2_G : integer := 1;
CHROMA_GROUP_DELAY_G : integer := 12;
CHROMA_LINE_DELAY2_G : integer := 3;
CHROMA_LINE_DELAY_G : integer := 0;
CHROMA_PIPE_DELAY2_G : integer := 2;
CHROMA_PIPE_DELAY_G : integer := 1
-- End of Generated Generics for Entity inst_bug_e
);
-- Generated Port Declaration:
-- No Generated Port for Entity inst_bug_e
end inst_bug_e;
--
-- End of Generated Entity inst_bug_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/issue236.vhd | 3 | 907 | entity subent is
port (
a : in boolean := false;
b : in boolean;
c : inout string; -- unconstrained
d : out string(1 to 4)
);
end entity;
entity test is
end entity;
architecture a1 of test is
begin
e1: entity work.subent -- ok
port map (
-- a is an unassociated port of mode IN but has a default value
b => true,
c => "1234"
-- d is unassociated port of mode OUT but is constrained
);
e2: entity work.subent -- error
port map (
a => true,
-- b is not allowed to be unassociated
c => "1234"
);
end architecture;
architecture a2 of test is
begin
e2: entity work.subent -- error
port map (
a => true,
b => true
-- c is not allowed to be unassociated
);
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/sigport/verilog/ent_aa-rtl-a.vhd | 1 | 1496 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_aa
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_aa-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_aa
--
architecture rtl of ent_aa is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_shadow_2_e-c.vhd | 1 | 1332 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_2_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_2_rtl_conf / inst_shadow_2_e
--
configuration inst_shadow_2_rtl_conf of inst_shadow_2_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_2_rtl_conf;
--
-- End of Generated Configuration inst_shadow_2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/configuration/cmdline/ent_b-rtl-a.vhd | 1 | 2212 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bitsplice/connport/inst_eb_e-e.vhd | 1 | 1278 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-e.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: inst_eb_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_eb_e
--
entity inst_eb_e is
-- Generics:
-- No Generated Generics for Entity inst_eb_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_eb_e
end inst_eb_e;
--
-- End of Generated Entity inst_eb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/attr8.vhd | 5 | 648 | entity attr8 is
end entity;
architecture test of attr8 is
begin
process is
type myint is range 1 to 3;
subtype myint_sub is myint range 1 to 2;
variable x : integer;
begin
assert myint'val(1) = 1;
assert myint'val(2) = 2;
x := 1;
assert myint'val(x) = 1;
x := 2;
assert myint'val(x) = 2;
assert myint_sub'val(2) = 2;
assert myint_sub'val(x) = 2;
assert myint'pos(myint(x)) = x;
assert myint_sub'pos(myint(x)) = x;
assert myint'pos(1) = 1;
assert myint_sub'pos(1) = 1;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/sem/const2.vhd | 4 | 229 | package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_t_e-e.vhd | 1 | 2216 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
macro_sig1_k1_k2 : in std_ulogic_vector(3 downto 0);
macro_sig1_k1_k4 : in std_ulogic_vector(3 downto 0);
macro_sig1_k3_k2 : in std_ulogic_vector(3 downto 0);
macro_sig1_k3_k4 : in std_ulogic_vector(3 downto 0);
macro_sig2_k1_k2 : in std_ulogic_vector(3 downto 0);
macro_sig2_k1_k4 : in std_ulogic_vector(3 downto 0);
macro_sig2_k3_k2 : in std_ulogic_vector(3 downto 0);
macro_sig2_k3_k4 : in std_ulogic_vector(3 downto 0);
macro_sig4_k1_k2 : out std_ulogic_vector(6 downto 0);
macro_sig4_k1_k4 : out std_ulogic_vector(6 downto 0);
macro_sig4_k3_k2 : out std_ulogic_vector(6 downto 0);
macro_sig4_k3_k4 : out std_ulogic_vector(6 downto 0);
macro_sign_0 : in std_ulogic_vector(3 downto 0);
macro_sign_1 : in std_ulogic_vector(3 downto 0);
macro_sign_2 : in std_ulogic_vector(3 downto 0);
macro_sign_3 : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/constant/inst_e_e-rtl-a.vhd | 1 | 3056 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:05 wig Exp $
-- $Date: 2004/08/18 10:47:05 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:05 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
bad_width_p : in bit_vector(7 downto 0);
const_06_p : in std_ulogic_vector(6 downto 0);
const_07_p : in std_ulogic_vector(5 downto 0);
zero_dup_e : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant const_06_c : std_ulogic_vector(6 downto 0) := "0001111"; -- __I_ConvConstant: 0xf
signal const_06 : std_ulogic_vector(6 downto 0);
constant mix_const_0_c : std_ulogic_vector(5 downto 0) := "001111"; -- __I_ConvConstant: 0xf
signal mix_const_0 : std_ulogic_vector(5 downto 0);
constant mix_const_17_c : bit_vector(7 downto 0) := "1010"; -- __I_VectorConv
signal mix_const_17 : bit_vector(7 downto 0);
constant mix_const_19_c : std_ulogic := '0';
signal mix_const_19 : std_ulogic;
constant mix_const_20_c : std_ulogic := '1';
signal mix_const_20 : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
const_06 <= const_06_c;
mix_const_0 <= mix_const_0_c;
mix_const_17 <= mix_const_17_c;
mix_const_19 <= mix_const_19_c;
mix_const_20 <= mix_const_20_c;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
bad_width_p => mix_const_17, -- #!Illegal
const_06_p => const_06, -- Constant Wire, # take literally, but will not work!
const_07_p => mix_const_0, -- Constant Wire, # take literally, but will not valid VHDL
zero_dup_e => mix_const_19, -- #Illegal
zero_dup_e => mix_const_20 -- #Illegal
);
-- End of Generated Instance Port Map for inst_ea
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/mde_tests/conn_nr_vhdl/inst_ecb_e-e.vhd | 1 | 1401 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ecb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ecb_e-e.vhd,v 1.1 2004/04/06 10:50:04 wig Exp $
-- $Date: 2004/04/06 10:50:04 $
-- $Log: inst_ecb_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:04 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ecb_e
--
entity inst_ecb_e is
-- Generics:
-- No Generated Generics for Entity inst_ecb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ecb_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecb_e
);
end inst_ecb_e;
--
-- End of Generated Entity inst_ecb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/proc2.vhd | 5 | 693 | entity proc2 is
end entity;
architecture test of proc2 is
type int_array is array (integer range <>) of integer;
procedure fill(a : out int_array) is
begin
for i in a'range loop
a(i) := a'length;
end loop;
end procedure;
procedure fill2(a : out int_array; v : in integer) is
begin
a := (6, 6, 6);
end procedure;
begin
process is
variable x : int_array(1 to 3);
variable y : int_array(5 to 6);
begin
fill(x);
assert x = (3, 3, 3);
fill(y);
assert y = (2, 2);
fill2(x, 6);
assert x = (6, 6, 6);
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/regress/jcore3.vhd | 3 | 437 | entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
wait;
end process;
c: process is
begin
y <= 1;
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/open/inst_b_e-e.vhd | 1 | 1638 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Thu Jan 27 08:21:01 2005
-- cmd: h:/work/mix_new/mix/mix_0.pl -strip -nodelta ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.3 2005/11/30 14:04:19 wig Exp $
-- $Date: 2005/11/30 14:04:19 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:19 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.48 2005/01/26 14:01:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
mix_key_open : out std_ulogic; -- replace name
non_open : in std_ulogic_vector(2 downto 0);
non_open_bit : in std_ulogic;
open_bit_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
open_bit_3 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
open_bit_4 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bitsplice/connport/ent_ad-rtl-conf-c.vhd | 1 | 1274 | -- -------------------------------------------------------------
--
-- Generated Configuration for ent_ad
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:21 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-conf-c.vhd,v 1.1 2007/03/05 10:01:23 wig Exp $
-- $Date: 2007/03/05 10:01:23 $
-- $Log: ent_ad-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 10:01:23 wig
-- Create all lowercase filenames since 2007-03-03
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ad_RTL_CONF / ent_ad
--
configuration ent_ad_RTL_CONF of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_RTL_CONF;
--
-- End of Generated Configuration ent_ad_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bitsplice/inst_ec_e-e.vhd | 1 | 1541 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Oct 10 12:25:03 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-e.vhd,v 1.3 2005/11/30 14:20:41 wig Exp $
-- $Date: 2005/11/30 14:20:41 $
-- $Log: inst_ec_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:20:41 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ec_e
--
entity inst_ec_e is
-- Generics:
-- No Generated Generics for Entity inst_ec_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ec_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ec_e
);
end inst_ec_e;
--
-- End of Generated Entity inst_ec_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/constant/inst_ab_e-e.vhd | 1 | 2050 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
-- No Generated Generics for Entity inst_ab_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
bus20040728_altop_o1 : out std_ulogic_vector(3 downto 0);
bus20040728_o1 : out std_ulogic_vector(1 downto 0);
bus20040728_o2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
bus20040728_top_o1 : out std_ulogic_vector(3 downto 0);
bus20050930 : out std_ulogic_vector(4 downto 0);
bus20050930_2 : out std_ulogic_vector(5 downto 0);
bus20050930_3 : out std_ulogic_vector(4 downto 0);
bus20050930_p7 : out std_ulogic;
const_04 : in std_ulogic_vector(3 downto 0);
const_08_p : in std_ulogic_vector(4 downto 0);
const_09_p : in std_ulogic_vector(2 downto 0);
const_10_2 : in std_ulogic_vector(3 downto 0);
inst_duo_2 : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/issue227.vhd | 4 | 1196 | entity issue227 is
end entity issue227;
use std.textio.all;
architecture test of issue227 is
procedure proc(
delay : time := 0 ns;
a,b : integer := 1) is
begin
wait for delay;
write(OUTPUT, integer'image(a) & integer'image(b) & LF);
end procedure proc;
function func(a,b : integer := 1) return integer is
begin
return 10*a+b;
end function func;
begin
proc; -- all unassociated
proc(1 ns, 2, b => open); -- named OPEN
proc(2 ns, open, b => 2); -- positional OPEN
proc(3 ns, a => 2); -- one unassociated
process
begin
wait for 4 ns;
proc; -- all unassociated
proc(0 ns, 2, b => open); -- named OPEN
proc(0 ns, open, b => 2); -- positional OPEN
proc(0 ns, a => 2); -- one unassociated
write(OUTPUT, integer'image(func) & LF);
write(OUTPUT, integer'image(func(a => 2, b => open)) & LF);
write(OUTPUT, integer'image(func(open, b => 2)) & LF);
write(OUTPUT, integer'image(func(a => 2)) & LF);
wait;
end process;
end architecture test;
| gpl-3.0 |
blutsvente/MIX | test/results/macro/ifelsif/inst_a_e-e.vhd | 1 | 2356 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 6 12:38:07 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Ifelsif -nodelta -bak ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1 2007/03/06 12:44:33 wig Exp $
-- $Date: 2007/03/06 12:44:33 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.1 2007/03/06 12:44:33 wig
-- Adding IF/ELSIF/ELSE for generators and testcase.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
gensig_1 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
port_mac_b : in std_ulogic_vector(3 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/autoopen/aaa/inst_t_e-e.vhd | 1 | 1759 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2004/04/06 11:19:56 wig Exp $
-- $Date: 2004/04/06 11:19:56 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2004/04/06 11:19:56 wig
-- Adding result/autoopen
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
s_ai14 : in std_ulogic_vector(7 downto 0);
s_ai16 : in std_ulogic_vector(7 downto 0);
s_ai6 : in std_ulogic;
s_ai8 : in std_ulogic;
s_aio17 : inout std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao11 : out std_ulogic_vector(7 downto 0);
s_ao13 : out std_ulogic_vector(7 downto 0);
s_ao3 : out std_ulogic;
s_ao5 : out std_ulogic;
s_eo3 : out std_ulogic;
s_eo5 : out std_ulogic
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/inst/inst_xa_e-e.vhd | 1 | 1552 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_xa_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-e.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_xa_e-e.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_xa_e
--
entity inst_xa_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_xa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end inst_xa_e;
--
-- End of Generated Entity inst_xa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/ramd/tap_con-struct-a.vhd | 1 | 1780 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of tap_con
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: tap_con-struct-a.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: tap_con-struct-a.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of tap_con
--
architecture struct of tap_con is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component tap_con_ctrl --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_tap_con_ctrl
i_tap_con_ctrl: tap_con_ctrl
;
-- End of Generated Instance Port Map for i_tap_con_ctrl
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bitsplice/vhdportsort/inst_ea_e-e.vhd | 1 | 3870 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_ea_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ea_e
--
entity inst_ea_e is
-- Generics:
-- No Generated Generics for Entity inst_ea_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ea_e
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
video_i : in std_ulogic_vector(3 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_3_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_2_6_6_gi : in std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic;
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_widesig_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ea_e
);
end inst_ea_e;
--
-- End of Generated Entity inst_ea_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/autoopen/inst_t_e-rtl-conf-c.vhd | 1 | 1579 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:52:39 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.3 2006/01/19 08:50:42 wig Exp $
-- $Date: 2006/01/19 08:50:42 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.3 2006/01/19 08:50:42 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_e : inst_e_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_e_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/intra/instance/ent_t-e.vhd | 1 | 1749 | -- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.2 2006/01/19 09:18:58 wig Exp $
-- $Date: 2006/01/19 09:18:58 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.2 2006/01/19 09:18:58 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
generic(
-- Generated Generics for Entity ent_t
generic_20 : integer := 32 -- Parameter for generic on topGeneric on top
-- End of Generated Generics for Entity ent_t
);
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
const_p_18 : in std_ulogic_vector(11 downto 0); -- Constant on top
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/real.vhd | 3 | 758 | entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
process is
variable i : integer;
begin
i := integer(x); -- OK
x <= real(i); -- OK
x <= real(5); -- OK
x <= real(bit'('1')); -- Error
end process;
process is
variable x : real;
begin
x := real'left; -- OK
x := real'right; -- OK
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/configuration/ent_a-rtl-conf-c.vhd | 1 | 2349 | -- -------------------------------------------------------------
--
-- Generated Configuration for ent_a
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:17:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-conf-c.vhd,v 1.4 2005/12/14 12:38:06 wig Exp $
-- $Date: 2005/12/14 12:38:06 $
-- $Log: ent_a-rtl-conf-c.vhd,v $
-- Revision 1.4 2005/12/14 12:38:06 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: adding my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_a_rtl_conf / ent_a
--
configuration ent_a_rtl_conf of ent_a is
for rtl
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_rtl_conf;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_rtl_conf;
end for;
for inst_ac : ent_ac
use configuration work.ent_ac_rtl_conf;
end for;
for inst_ad : ent_ad
use configuration work.ent_ad_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ae : ent_ae
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ae_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_a_rtl_conf;
--
-- End of Generated Configuration ent_a_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/typecast/inst_ab-rtl-a.vhd | 1 | 1429 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:14:02 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab-rtl-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_ab-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ab
--
architecture rtl of inst_ab is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/protected1.vhd | 5 | 1241 | entity protected1 is
end entity;
architecture test of protected1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 0;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 3;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 3;
x.decrement;
assert x.value = 2;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/misc/kcuart.vhd | 5 | 724 | entity kcuart is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of kcuart is
signal clk : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0);
signal tx_full : std_logic;
signal tx_wr : std_logic := '0';
signal uart_tx : std_logic;
signal en_16_x_baud : std_logic;
begin
clk <= not clk after 5 ns;
tx_i: entity work.uart_tx6
port map (
data_in => tx_data,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => tx_wr,
buffer_full => tx_full,
buffer_reset => '0',
clk => clk );
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/verilog/uamn/ent_b-rtl-conf-c.vhd | 1 | 1564 | -- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Wed Oct 19 08:55:30 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_UAMN -nodelta -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.2 2005/10/24 12:14:02 wig Exp $
-- $Date: 2005/10/24 12:14:02 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/10/24 12:14:02 wig
-- added output.language.verilog = ansistyle,2001param
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.61 2005/10/18 09:34:36 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_ba : ent_ba
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ba_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/configuration/cmdline/ent_a-rtl-a.vhd | 1 | 7578 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic; -- Use internally test1
port_aa_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 : out std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_aa_6 : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : out std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_ADD_MY_SIG : out std_test -- adding my own macro
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
--__I_COMPONENT_NOCOMPDEC__ inst_ab
--__I_COMPONENT_NOCOMPDEC__ inst_ac
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
-- Generated Generics for Entity ent_ae
-- End of Generated Generics for Entity ent_ae
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0); -- Use internally test2, no port generated
port_ae_5 : in std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_ae_6 : in std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_i_ae : in std_ulogic_vector(6 downto 0); -- Input Bus
sig_o_ae : out std_ulogic_vector(7 downto 0) -- Output Bus
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_ADD_MY_SIG : std_test;
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13, -- Create internal signal name
sig_ADD_MY_SIG => sig_ADD_MY_SIG -- adding my own macro
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
macro_sig => sig_ADD_MY_SIG, -- adding my own macro
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/assert.vhd | 5 | 616 | entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/padio/given/pad_pads_e-e.vhd | 1 | 3086 | -- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-e.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: pad_pads_e-e.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity pad_pads_e
--
entity pad_pads_e is
-- Generics:
-- No Generated Generics for Entity pad_pads_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end pad_pads_e;
--
-- End of Generated Entity pad_pads_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_shadow_b_e-e.vhd | 1 | 1341 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_b_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_b_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_shadow_b_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_b_e
--
entity inst_shadow_b_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_b_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_b_e
end inst_shadow_b_e;
--
-- End of Generated Entity inst_shadow_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/padio/names/pad_pads_e-e.vhd | 1 | 3086 | -- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-e.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: pad_pads_e-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity pad_pads_e
--
entity pad_pads_e is
-- Generics:
-- No Generated Generics for Entity pad_pads_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end pad_pads_e;
--
-- End of Generated Entity pad_pads_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/verilog/vhdl/ent_ab-rtl-a.vhd | 1 | 1515 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_ab-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ab
--
architecture rtl of ent_ab is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/verilog/mixed/ent_ab-e.vhd | 1 | 1674 | -- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 30 10:05:42 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-e.vhd,v 1.6 2005/11/30 14:04:19 wig Exp $
-- $Date: 2005/11/30 14:04:19 $
-- $Log: ent_ab-e.vhd,v $
-- Revision 1.6 2005/11/30 14:04:19 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ab
--
entity ent_ab is
-- Generics:
-- No Generated Generics for Entity ent_ab
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic; -- Use internally test1
port_ab_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_14 : in std_ulogic_vector(6 downto 0) -- Multiline comment 1
-- Multiline comment 2
-- Multiline comment 3
-- End of Generated Port for Entity ent_ab
);
end ent_ab;
--
-- End of Generated Entity ent_ab
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/macro/inst_shadow_6_e-rtl-a.vhd | 1 | 1490 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_6_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_6_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_6_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_6_e
--
architecture rtl of inst_shadow_6_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/genwidth/inst_ab_e-e.vhd | 1 | 1464 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.2 2004/11/10 09:54:10 wig Exp $
-- $Date: 2004/11/10 09:54:10 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.2 2004/11/10 09:54:10 wig
-- testcase extended
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.46 2004/08/18 10:45:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_ab_e
width : integer := 8
-- End of Generated Generics for Entity inst_ab_e
);
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
y_p0_i : in std_ulogic_vector(width - 1 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/lower/pack1.vhd | 4 | 175 | package pack1 is
end package;
package body pack1 is
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
end package body;
| gpl-3.0 |
mitchsm/nvc | test/sem/scope.vhd | 2 | 7103 | package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1;
b : out pack2.my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
-------------------------------------------------------------------------------
architecture labels of bar is
signal mySignalVector: bit_vector (7 downto 0);
signal myOtherSignal: bit := '1';
begin
process
begin
L1:
for i in 0 to 9 loop
for i in 0 to 7 loop
mySignalVector(i) <= myOtherSignal;
report "outer loop i = " & integer'image(L1.i);
report "inner loop i = " & integer'image(i);
report integer'image(L1.x); -- Error
end loop;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/sigport/use/ent_ac-rtl-a.vhd | 1 | 1496 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ac-rtl-a.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_ac-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ac
--
architecture rtl of ent_ac is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/inst_t_e-e.vhd | 1 | 1442 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.3 2006/01/19 08:50:40 wig Exp $
-- $Date: 2006/01/19 08:50:40 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.3 2006/01/19 08:50:40 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
signal_bb_ab : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/20051014b/ent_a-struct-a.vhd | 1 | 4463 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_a
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-struct-a.vhd,v 1.2 2005/12/14 12:49:24 wig Exp $
-- $Date: 2005/12/14 12:49:24 $
-- $Log: ent_a-struct-a.vhd,v $
-- Revision 1.2 2005/12/14 12:49:24 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of ent_a
--
architecture struct of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
x_des_01 : in std_ulogic; -- des_01 lengthy comment
a_des_02 : in std_ulogic; -- des_02 0123456789 0123456789 0123456789
k_des_03 : in std_ulogic; -- des_03 0123456789
-- des_03 0123456789
-- des_03 0123456789
d_des_04 : in std_ulogic; -- des_04 0TEST_MACRO123456789 0123456789
v_des_05 : in std_ulogic; -- des_05 0123456789 0TEST_MACRO123456789 0123456789
t_des_06 : in std_ulogic; -- des_06 0123456789 0123456TEST_MACRO789 0123456789
b_des_07 : in std_ulogic; -- des_07 0123456789 0123456789TEST_MACRO 0123456789
c_des_08 : in std_ulogic; -- des_08 0123456789
-- des_08 0TEST_MACRO123456789
-- des_08 0123456789
c_des__09 : in std_ulogic; -- des_09 0123456789
-- des_09 0123456TEST_MACRO789
-- des_09 0123456789
c_des_10 : in std_ulogic -- des10 0123456789
-- des_10 0123456789TEST_MACRO
-- des_10 0123456789
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal a_des_02 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal b_des_07 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des_08 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des__09 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal d_des_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal k_des_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal t_des_06 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_des_05 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal x_des_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
a_des_02 <= p_mix_a_des_02_gi; -- __I_I_BIT_PORT
b_des_07 <= p_mix_b_des_07_gi; -- __I_I_BIT_PORT
c_des_08 <= p_mix_c_des_08_gi; -- __I_I_BIT_PORT
c_des_10 <= p_mix_c_des_10_gi; -- __I_I_BIT_PORT
c_des__09 <= p_mix_c_des__09_gi; -- __I_I_BIT_PORT
d_des_04 <= p_mix_d_des_04_gi; -- __I_I_BIT_PORT
k_des_03 <= p_mix_k_des_03_gi; -- __I_I_BIT_PORT
t_des_06 <= p_mix_t_des_06_gi; -- __I_I_BIT_PORT
v_des_05 <= p_mix_v_des_05_gi; -- __I_I_BIT_PORT
x_des_01 <= p_mix_x_des_01_gi; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
a_des_02 => a_des_02, -- des_02 01...
b_des_07 => b_des_07, -- des_07 01...
c_des_08 => c_des_08, -- des_08 01...
c_des_10 => c_des_10, -- des10 012...
c_des__09 => c_des__09, -- des_09 01...
d_des_04 => d_des_04, -- des_04 0T...
k_des_03 => k_des_03, -- des_03 01...
t_des_06 => t_des_06, -- des_06 01...
v_des_05 => v_des_05, -- des_05 01...
x_des_01 => x_des_01 -- des_01 le...
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
;
-- End of Generated Instance Port Map for inst_ab
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/parse/context.vhd | 4 | 378 | context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
| gpl-3.0 |
blutsvente/MIX | test/results/mde_tests/conn_nreset/inst_ea_e-e.vhd | 1 | 1941 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-e.vhd,v 1.1 2004/04/06 10:50:21 wig Exp $
-- $Date: 2004/04/06 10:50:21 $
-- $Log: inst_ea_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:21 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ea_e
--
entity inst_ea_e is
-- Generics:
-- No Generated Generics for Entity inst_ea_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end inst_ea_e;
--
-- End of Generated Entity inst_ea_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/bounds/issue150.vhd | 4 | 432 | library ieee;
use ieee.numeric_std.all;
entity issue150 is
end entity issue150;
architecture tb of issue150 is
type t_lut8x8 is array (0 to 7,0 to 7) of integer;
constant C_SAMPLE : t_lut8x8 := (
(1,1,1,1,1,1,1,1),
(1,1,1,1,1,1,1,1),
(1,1,1,1,1,1,1,1),
(1,1,1,1,1,1,1,1),
(1,1,1,1,1,1,1,1),
(1,1,1,1,1,1,1,1) ); -- Crash lowering here
begin
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/constbug/vgca_top-struct-conf-c.vhd | 1 | 2057 | -- -------------------------------------------------------------
--
-- Generated Configuration for vgca_top
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_top-struct-conf-c.vhd,v 1.2 2004/08/18 10:46:56 wig Exp $
-- $Date: 2004/08/18 10:46:56 $
-- $Log: vgca_top-struct-conf-c.vhd,v $
-- Revision 1.2 2004/08/18 10:46:56 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vgca_top_struct_conf / vgca_top
--
configuration vgca_top_struct_conf of vgca_top is
for struct
-- Generated Configuration
for i_adc : vgca_video_adcs
use configuration work.vgca_video_adcs_struct_conf;
end for;
for i_cadc : vgca_cadc8_vin6
use configuration work.vgca_cadc8_vin6_struct_conf;
end for;
for i_dac : vgca_dac
use configuration work.vgca_dac_struct_conf;
end for;
for i_padframe : padframe
use configuration work.padframe_empty_conf;
end for;
for i_vgca : vgca
use configuration work.vgca_struct_conf;
end for;
for i_vgca_dcs_shell : vgca_dcs_shell
use configuration work.vgca_dcs_shell_struct_cfg;
end for;
for i_vgca_mcc_shell : vgca_mcc_shell
use configuration work.vgca_mcc_shell_struct_cfg;
end for;
for i_vgca_tc : vgca_tc
use configuration work.vgca_tc_struct_conf;
end for;
end for;
end vgca_top_struct_conf;
--
-- End of Generated Configuration vgca_top_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/textio1.vhd | 4 | 894 | entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
--write(l, 50 ns, field => 20, justified => right, unit => us);
--writeline(output, l);
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/mde_tests/nreset2/inst_e_e-e.vhd | 1 | 1270 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.1 2004/04/06 10:50:40 wig Exp $
-- $Date: 2004/04/06 10:50:40 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:40 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_e_e
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/logic/inst_aa_e-e.vhd | 1 | 1500 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 10:55:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e.vhd,v 1.3 2005/07/18 08:59:29 wig Exp $
-- $Date: 2005/07/18 08:59:29 $
-- $Log: inst_aa_e-e.vhd,v $
-- Revision 1.3 2005/07/18 08:59:29 wig
-- do not write config for simple logic
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.56 2005/07/15 16:39:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
-- No Generated Generics for Entity inst_aa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa_e
and_i1_1 : out std_ulogic;
and_i2_1 : out std_ulogic_vector(15 downto 0);
or_i1_1 : out std_ulogic;
or_i2_1 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/case/check/inst_ac_e-rtl-a.vhd | 1 | 1654 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-rtl-a.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ac_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ac_e
--
architecture rtl of inst_ac_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/logic/inst_a_e-rtl-a.vhd | 1 | 4768 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:28:20 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--__I_SIMPLE_LOGIC__ inst_a_and
--__I_SIMPLE_LOGIC__ inst_a_or
--__I_SIMPLE_LOGIC__ inst_a_wire
component inst_aa_e -- the aa instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
and_i1_1 : out std_ulogic;
and_i2_1 : out std_ulogic_vector(15 downto 0);
or_i1_1 : out std_ulogic;
or_i2_1 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e -- the ab instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
and_i1_2 : out std_ulogic;
and_i1_3_p : out std_ulogic;
and_i2_2 : out std_ulogic_vector(15 downto 0);
and_i2_3_p : out std_ulogic_vector(15 downto 0);
or_i1_2 : out std_ulogic;
or_i1_3_p : out std_ulogic;
or_i2_2 : out std_ulogic_vector(15 downto 0);
or_i2_3_p : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal and_i1_1 : std_ulogic;
signal and_i1_2 : std_ulogic;
signal and_i1_3 : std_ulogic;
signal and_i2_1 : std_ulogic_vector(15 downto 0);
signal and_i2_2 : std_ulogic_vector(15 downto 0);
signal and_i3_3 : std_ulogic_vector(15 downto 0);
signal or_i1_1 : std_ulogic;
signal or_i1_2 : std_ulogic;
signal or_i1_3 : std_ulogic;
signal or_i2_1 : std_ulogic_vector(15 downto 0);
signal or_i2_2 : std_ulogic_vector(15 downto 0);
signal or_i3_3 : std_ulogic_vector(15 downto 0);
signal wire_bus_si : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal wire_bus_so : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal wire_si : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal wire_so : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
wire_bus_si <= wire_bus_i; -- __I_I_BUS_PORT
wire_bus_o <= wire_bus_so; -- __I_O_BUS_PORT
wire_si <= wire_i; -- __I_I_BIT_PORT
wire_o <= wire_so; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Logic for inst_a_and
and_o1 <=
and_i1_2
AND and_i1_1
AND and_i1_3;
-- End of Generated Logic for inst_a_and
-- Generated Logic for inst_a_and_1
and_o2 <=
and_i2_2
AND and_i2_1
AND and_i3_3;
-- End of Generated Logic for inst_a_and_1
-- Generated Logic for inst_a_or
or_o1 <=
or_i1_2
OR or_i1_3
OR or_i1_1;
-- End of Generated Logic for inst_a_or
-- Generated Logic for inst_a_or_1
or_o2 <=
or_i2_2
OR or_i2_1
OR or_i3_3;
-- End of Generated Logic for inst_a_or_1
-- Generated Logic for inst_a_wire
wire_so <=
wire_si;
-- End of Generated Logic for inst_a_wire
-- Generated Logic for inst_a_wire_1
wire_bus_so <=
wire_bus_si;
-- End of Generated Logic for inst_a_wire_1
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa_e -- the aa instance
port map (
and_i1_1 => and_i1_1,
and_i2_1 => and_i2_1,
or_i1_1 => or_i1_1,
or_i2_1 => or_i2_1
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab_e -- the ab instance
port map (
and_i1_2 => and_i1_2,
and_i1_3_p => and_i1_3,
and_i2_2 => and_i2_2,
and_i2_3_p => and_i3_3,
or_i1_2 => or_i1_2,
or_i1_3_p => or_i1_3,
or_i2_2 => or_i2_2,
or_i2_3_p => or_i3_3
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/constant/inst_ad_e-rtl-a.vhd | 1 | 1485 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ad_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ad_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:03 wig Exp $
-- $Date: 2004/08/18 10:47:03 $
-- $Log: inst_ad_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:03 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ad_e
--
architecture rtl of inst_ad_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/inst_bb_e-e.vhd | 1 | 1473 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_bb_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bb_e-e.vhd,v 1.3 2006/01/19 08:50:39 wig Exp $
-- $Date: 2006/01/19 08:50:39 $
-- $Log: inst_bb_e-e.vhd,v $
-- Revision 1.3 2006/01/19 08:50:39 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_bb_e
--
entity inst_bb_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_bb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end inst_bb_e;
--
-- End of Generated Entity inst_bb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/mix/inst_xa_e-e.vhd | 1 | 1552 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_xa_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-e.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_xa_e-e.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_xa_e
--
entity inst_xa_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_xa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end inst_xa_e;
--
-- End of Generated Entity inst_xa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/nreset2/vor-rtl-conf-c.vhd | 1 | 1220 | -- -------------------------------------------------------------
--
-- Generated Configuration for vor
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:56:34 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-rtl-conf-c.vhd,v 1.1 2004/04/06 10:46:48 wig Exp $
-- $Date: 2004/04/06 10:46:48 $
-- $Log: vor-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:46:48 wig
-- Adding result/nreset2
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vor_rtl_conf / vor
--
configuration vor_rtl_conf of vor is
for rtl
-- Generated Configuration
end for;
end vor_rtl_conf;
--
-- End of Generated Configuration vor_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/open/inst_b_e-rtl-conf-c.vhd | 1 | 1290 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_b_e
--
-- Generated
-- by: wig
-- on: Thu Jan 27 08:21:01 2005
-- cmd: h:/work/mix_new/mix/mix_0.pl -strip -nodelta ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-conf-c.vhd,v 1.2 2005/01/27 07:29:28 wig Exp $
-- $Date: 2005/01/27 07:29:28 $
-- $Log: inst_b_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/01/27 07:29:28 wig
-- reworked %OPEN% setup and testcase
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.48 2005/01/26 14:01:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/sigport/ent_t-e.vhd | 1 | 1510 | -- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/sem/issue178.vhd | 5 | 418 | entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/lower/choice1.vhd | 2 | 390 | entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
| gpl-3.0 |
mitchsm/nvc | test/regress/issue163.vhd | 5 | 1281 | package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/verilog/mixed/ent_aa-rtl-a.vhd | 1 | 1473 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_aa
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-rtl-a.vhd,v 1.5 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_aa-rtl-a.vhd,v $
-- Revision 1.5 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_aa
--
architecture rtl of ent_aa is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/mde_tests/conn_nr_vhdl/inst_ebb_e-e.vhd | 1 | 1553 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_ebb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ebb_e-e.vhd,v 1.1 2004/04/06 10:50:00 wig Exp $
-- $Date: 2004/04/06 10:50:00 $
-- $Log: inst_ebb_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:00 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ebb_e
--
entity inst_ebb_e is
-- Generics:
-- No Generated Generics for Entity inst_ebb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
req_select_o : out std_ulogic_vector(5 downto 0);
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_ebb_e
);
end inst_ebb_e;
--
-- End of Generated Entity inst_ebb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/constant/inst_t_e-e.vhd | 1 | 1263 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.3 2004/08/18 10:47:07 wig Exp $
-- $Date: 2004/08/18 10:47:07 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:07 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
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