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stringlengths 6
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stringlengths 5
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stringclasses 54
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stringclasses 15
values |
|---|---|---|---|---|---|
mitchsm/nvc | test/regress/alias3.vhd | 5 | 763 | entity alias3 is
end entity;
architecture test of alias3 is
type int_array is array (integer range <>) of integer;
function cut(x : int_array; low, high: integer) return int_array is
alias a : int_array(1 to x'length) is x;
begin
return a(low to high);
end function;
signal s : int_array(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable x : int_array(1 to 5) := (1, 2, 3, 4, 5);
variable y : int_array(4 downto 0) := (4, 3, 2, 1, 0);
alias sa : int_array(4 downto 0) is x;
begin
assert x(2 to 4) = (2, 3, 4);
assert sa(3 downto 1) = (2, 3, 4);
assert cut(x, 2, 3) = (2, 3);
assert cut(y, 1, 2) = (4, 3);
wait;
end process;
end architecture;
| gpl-3.0 |
blutsvente/MIX | test/results/configuration/cfgfile/ent_t-rtl-a.vhd | 1 | 6206 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.1 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.1 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
mitchsm/nvc | test/regress/issue229.vhd | 5 | 361 | use std.textio.all;
entity issue229 is
end entity issue229;
architecture test of issue229 is
begin
process
begin
for ii in 1 to 2049 loop
write(OUTPUT, integer'image(1));
end loop;
wait;
end process;
-- Alternatively, delete the for loop and the wait statement -- it fails the same way
end architecture test;
| gpl-3.0 |
mitchsm/nvc | test/parse/procedure.vhd | 4 | 490 | package p is
procedure foo(x : in integer; y : out integer);
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end procedure;
procedure bar(file x : text);
procedure baz is
type foo;
alias x is y;
constant k : integer := 2;
begin
end procedure;
procedure tralala is
use work.foo;
begin
end procedure;
end package body;
| gpl-3.0 |
blutsvente/MIX | test/results/generic/inst_1_e-rtl-a.vhd | 1 | 1452 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_1_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_1_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_1_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_1_e
--
architecture rtl of inst_1_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/bugver/ramd/vgca_cpu-e.vhd | 1 | 1293 | -- -------------------------------------------------------------
--
-- Entity Declaration for vgca_cpu
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_cpu-e.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: vgca_cpu-e.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity vgca_cpu
--
entity vgca_cpu is
-- Generics:
-- No Generated Generics for Entity vgca_cpu
-- Generated Port Declaration:
-- No Generated Port for Entity vgca_cpu
end vgca_cpu;
--
-- End of Generated Entity vgca_cpu
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/constant/inst_a_e-rtl-a.vhd | 1 | 15954 | -- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
bit_vector_p : in bit_vector(7 downto 0);
bug20040329a_t1 : in std_ulogic;
bug20040329a_t2 : in std_ulogic;
bug20040329a_t3 : in std_ulogic;
bug20040329a_t4 : in std_ulogic;
bus20040728_all_i : in std_ulogic_vector(7 downto 0);
bus20040728_part_i : in std_ulogic_vector(7 downto 0);
bus20050930 : in std_ulogic_vector(7 downto 0);
bus20050930_2 : in std_ulogic_vector(7 downto 0);
bus20050930_3 : in std_ulogic_vector(7 downto 0);
const_01_p : in std_ulogic;
const_02_p : in std_ulogic;
const_03 : in std_ulogic_vector(6 downto 0);
const_05 : in std_ulogic;
inst_duo_1 : in std_ulogic_vector(7 downto 0);
int_time_p : in time;
integer_p : in integer;
one_p : in std_ulogic;
real_p : in real;
real_time_p : in time;
reale_p : in real;
std_u_11_vport : in std_ulogic_vector(7 downto 0);
std_u_logic_bin_p : in std_ulogic_vector(7 downto 0);
std_u_logic_binv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_hexerr_p : in std_ulogic_vector(3 downto 0);
std_u_logic_octv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_port_02 : in std_ulogic_vector(7 downto 0);
std_u_logic_quadv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_vport : in std_ulogic_vector(7 downto 0);
std_u_logic_vport_ext : in std_ulogic_vector(10 downto 0);
std_ulogic_vector_p : in std_ulogic_vector(7 downto 0);
string_p : in string;
under_p : in real;
vector_duo_1 : in std_ulogic_vector(7 downto 0);
vector_duo_2 : in std_ulogic_vector(7 downto 0);
vhdl_basehex_p : in integer;
vhdlbase2_p : in integer;
zero_p : in std_ulogic
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
bus20040728_altop_o1 : out std_ulogic_vector(3 downto 0);
bus20040728_o1 : out std_ulogic_vector(1 downto 0);
bus20040728_o2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
bus20040728_top_o1 : out std_ulogic_vector(3 downto 0);
bus20050930 : out std_ulogic_vector(4 downto 0);
bus20050930_2 : out std_ulogic_vector(5 downto 0);
bus20050930_3 : out std_ulogic_vector(4 downto 0);
bus20050930_p7 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
const_04 : in std_ulogic_vector(3 downto 0);
const_08_p : in std_ulogic_vector(4 downto 0);
const_09_p : in std_ulogic_vector(2 downto 0);
const_10_2 : in std_ulogic_vector(3 downto 0);
inst_duo_2 : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
component inst_ac_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ac_e
bus20040728_oc : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_ac_e
);
end component;
-- ---------
component inst_ad_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ae_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ae_e
bus20040728_altop_i : in std_ulogic_vector(7 downto 0);
p_mix_bus20040728_top_7_4_gi : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity inst_ae_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant bug20040329a_t1_c : std_ulogic := 16#0#; -- __I_ConvConstant2:0x0
signal bug20040329a_t1 : std_ulogic;
constant bug20040329a_t2_c : std_ulogic := '0';
signal bug20040329a_t2 : std_ulogic;
constant bug20040329a_t3_c : std_ulogic := 2#0#; -- __I_ConvConstant3:0b0
signal bug20040329a_t3 : std_ulogic;
constant bug20040329a_t4_c : std_ulogic := 2#0101_0101#; -- __I_ConvConstant3:0b0101_0101
signal bug20040329a_t4 : std_ulogic;
constant bus20040728_c : std_ulogic_vector(7 downto 0) := ( others => '0' );
signal bus20040728 : std_ulogic_vector(7 downto 0);
constant bus20040728_altconst : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant bus20040728_altconst2 : std_ulogic := '1'; -- __W_SINGLE_BIT_BUS
signal bus20040728_altop : std_ulogic_vector(7 downto 0);
signal bus20040728_part : std_ulogic_vector(7 downto 0);
constant bus20040728_part_c1 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant bus20040728_part_c2 : std_ulogic_vector(2 downto 0) := ( others => '0' );
signal bus20040728_top : std_ulogic_vector(7 downto 0);
constant bus20040728_top_c1 : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant bus20040728_top_c2 : std_ulogic := '1'; -- __W_SINGLE_BIT_BUS
constant bus20050930_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930 : std_ulogic_vector(7 downto 0);
constant bus20050930_2_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930_2 : std_ulogic_vector(7 downto 0);
constant bus20050930_3_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930_3 : std_ulogic_vector(7 downto 0);
constant const_01_c : std_ulogic := '0';
signal const_01 : std_ulogic;
constant const_02_c : std_ulogic := '1';
signal const_02 : std_ulogic;
constant const_03_c : std_ulogic_vector(6 downto 0) := "64"; -- __I_VectorConv
signal const_03 : std_ulogic_vector(6 downto 0);
constant const_04_c : std_ulogic_vector(3 downto 0) := "32"; -- __I_VectorConv
signal const_04 : std_ulogic_vector(3 downto 0);
constant const_05_c : std_ulogic := '1';
signal const_05 : std_ulogic;
constant mix_const_1_c : std_ulogic_vector(4 downto 0) := ( others => '0' );
signal mix_const_1 : std_ulogic_vector(4 downto 0);
constant mix_const_10_c : integer := 16#FF#; -- __I_ConstNoconv
signal mix_const_10 : integer;
constant mix_const_11_c : integer := 2#1010_1010#; -- __I_ConstNoconv
signal mix_const_11 : integer;
constant mix_const_12_c : real := 2.2E-6; -- __I_ConstNoconv
signal mix_const_12 : real;
constant mix_const_13_c : time := 10 ns;
signal mix_const_13 : time;
constant mix_const_14_c : time := 2.27 us;
signal mix_const_14 : time;
constant mix_const_15_c : string := "ein string"; -- __I_ConstNoconv
signal mix_const_15 : string;
constant mix_const_16_c : bit_vector(7 downto 0) := "11111111"; -- __I_VectorConv
signal mix_const_16 : bit_vector(7 downto 0);
constant mix_const_18_c : std_ulogic_vector(7 downto 0) := "01010101"; -- __I_VectorConv
signal mix_const_18 : std_ulogic_vector(7 downto 0);
constant mix_const_2_c : std_ulogic_vector(2 downto 0) := ( others => '1' );
signal mix_const_2 : std_ulogic_vector(2 downto 0);
constant mix_const_21_c : std_ulogic_vector(7 downto 0) := "10101100"; -- __I_VectorConv
signal mix_const_21 : std_ulogic_vector(7 downto 0);
constant mix_const_22_c : std_ulogic_vector(7 downto 0) := "10101100"; -- __I_VectorConv
signal mix_const_22 : std_ulogic_vector(7 downto 0);
constant mix_const_23_c : std_ulogic_vector(7 downto 0) := "11111111"; -- __I_ConvConstant: 16#FF#
signal mix_const_23 : std_ulogic_vector(7 downto 0);
constant mix_const_24_c : std_ulogic_vector(7 downto 0) := "00010001"; -- __I_ConvConstant: 16#11#
signal mix_const_24 : std_ulogic_vector(7 downto 0);
constant mix_const_25_c : std_ulogic_vector(10 downto 0) := "00011111111"; -- __I_ConvConstant: 16#FF#
signal mix_const_25 : std_ulogic_vector(10 downto 0);
constant mix_const_26_c : std_ulogic_vector(7 downto 0) := "11111111"; -- __I_ConvConstant: 0xff
signal mix_const_26 : std_ulogic_vector(7 downto 0);
constant mix_const_27_c : std_ulogic_vector(7 downto 0) := "01010101"; -- __I_ConvConstant: 0b01010101
signal mix_const_27 : std_ulogic_vector(7 downto 0);
constant mix_const_28_c : std_ulogic_vector(7 downto 0) := "00000111"; -- __I_ConvConstant: 8#07#
signal mix_const_28 : std_ulogic_vector(7 downto 0);
constant mix_const_29_c : std_ulogic_vector(7 downto 0) := "11001100"; -- __I_ConvConstant: 2#11001100#
signal mix_const_29 : std_ulogic_vector(7 downto 0);
constant mix_const_3_c : std_ulogic_vector(3 downto 0) := ( others => '1' );
signal mix_const_3 : std_ulogic_vector(3 downto 0);
constant mix_const_30_c : std_ulogic_vector(7 downto 0) := 4#3030#; -- __I_ConvConstant: 4#3030#
signal mix_const_30 : std_ulogic_vector(7 downto 0);
constant mix_const_31_c : std_ulogic_vector(3 downto 0) := "11101110"; -- __E_VECTOR_WIDTH -- __I_ConvConstant: 16#ee#
signal mix_const_31 : std_ulogic_vector(3 downto 0);
constant mix_const_4_c : std_ulogic_vector(3 downto 0) := ( others => '0' );
signal mix_const_4 : std_ulogic_vector(3 downto 0);
constant mix_const_5_c : std_ulogic := '0';
signal mix_const_5 : std_ulogic;
constant mix_const_6_c : std_ulogic := '1';
signal mix_const_6 : std_ulogic;
constant mix_const_7_c : integer := 10; -- __I_ConstNoconv
signal mix_const_7 : integer;
constant mix_const_8_c : real := 10.2; -- __I_ConstNoconv
signal mix_const_8 : real;
constant mix_const_9_c : real := 1_000_000.0; -- __I_ConstNoconv
signal mix_const_9 : real;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
bug20040329a_t1 <= bug20040329a_t1_c;
bug20040329a_t2 <= bug20040329a_t2_c;
bug20040329a_t3 <= bug20040329a_t3_c;
bug20040329a_t4 <= bug20040329a_t4_c;
bus20040728 <= bus20040728_c;
bus20040728_altop(3 downto 1) <= bus20040728_altconst;
--!wig: bus20040728_altconst2 is one bit!
bus20040728_altop(0) <= bus20040728_altconst2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20040728_part(2) <= bus20040728_part_c1; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20040728_part(6 downto 4) <= bus20040728_part_c2;
bus20040728_top(3 downto 1) <= bus20040728_top_c1;
bus20040728_top(0) <= bus20040728_top_c2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20050930(6 downto 5) <= bus20050930_c;
bus20050930_2(6 downto 5) <= bus20050930_2_c;
bus20050930_3(6 downto 5) <= bus20050930_3_c;
const_01 <= const_01_c;
const_02 <= const_02_c;
const_03 <= const_03_c;
const_04 <= const_04_c;
const_05 <= const_05_c;
mix_const_1 <= mix_const_1_c;
mix_const_10 <= mix_const_10_c;
mix_const_11 <= mix_const_11_c;
mix_const_12 <= mix_const_12_c;
mix_const_13 <= mix_const_13_c;
mix_const_14 <= mix_const_14_c;
mix_const_15 <= mix_const_15_c;
mix_const_16 <= mix_const_16_c;
mix_const_18 <= mix_const_18_c;
mix_const_2 <= mix_const_2_c;
mix_const_21 <= mix_const_21_c;
mix_const_22 <= mix_const_22_c;
mix_const_23 <= mix_const_23_c;
mix_const_24 <= mix_const_24_c;
mix_const_25 <= mix_const_25_c;
mix_const_26 <= mix_const_26_c;
mix_const_27 <= mix_const_27_c;
mix_const_28 <= mix_const_28_c;
mix_const_29 <= mix_const_29_c;
mix_const_3 <= mix_const_3_c;
mix_const_30 <= mix_const_30_c;
mix_const_31 <= mix_const_31_c;
mix_const_4 <= mix_const_4_c;
mix_const_5 <= mix_const_5_c;
mix_const_6 <= mix_const_6_c;
mix_const_7 <= mix_const_7_c;
mix_const_8 <= mix_const_8_c;
mix_const_9 <= mix_const_9_c;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
bit_vector_p => mix_const_16,
bug20040329a_t1 => bug20040329a_t1,
bug20040329a_t2 => bug20040329a_t2,
bug20040329a_t3 => bug20040329a_t3,
bug20040329a_t4 => bug20040329a_t4,
bus20040728_all_i => bus20040728,
bus20040728_part_i => bus20040728_part,
bus20050930 => bus20050930, -- assign 6:5 a 1
bus20050930_2 => bus20050930_2, -- create port 5:0
bus20050930_3 => bus20050930_3, -- creates duplicate assignment
const_01_p => const_01,
const_02_p => const_02,
const_03 => const_03, -- Constant Wire, wire port const_wire to constant
const_05 => const_05, -- Constant Wire, wire port const_wire to constant
inst_duo_1 => mix_const_22,
int_time_p => mix_const_13,
integer_p => mix_const_7,
one_p => mix_const_6,
real_p => mix_const_8,
real_time_p => mix_const_14,
reale_p => mix_const_12,
std_u_11_vport => mix_const_24,
std_u_logic_bin_p => mix_const_27,
std_u_logic_binv_p => mix_const_29,
std_u_logic_hexerr_p => mix_const_31,
std_u_logic_octv_p => mix_const_28,
std_u_logic_port_02 => mix_const_26,
std_u_logic_quadv_p => mix_const_30,
std_u_logic_vport => mix_const_23,
std_u_logic_vport_ext => mix_const_25,
std_ulogic_vector_p => mix_const_18,
string_p => mix_const_15,
under_p => mix_const_9,
vector_duo_1 => mix_const_21,
vector_duo_2 => mix_const_21,
vhdl_basehex_p => mix_const_10,
vhdlbase2_p => mix_const_11,
zero_p => mix_const_5
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
bus20040728_altop_o1 => bus20040728_altop(7 downto 4),
bus20040728_o1 => bus20040728_part(1 downto 0),
bus20040728_o2 => bus20040728_part(3),
bus20040728_top_o1 => bus20040728_top(7 downto 4),
bus20050930 => bus20050930(4 downto 0), -- assign 6:5 a 1
bus20050930_2(4 downto 0) => bus20050930_2(4 downto 0), -- create port 5:0
bus20050930_2(5) => bus20050930_2(7), -- create port 5:0
bus20050930_3 => bus20050930_3(4 downto 0), -- creates duplicate assignment
bus20050930_3(0) => bus20050930_3(7), -- creates duplicate assignment
bus20050930_p7 => bus20050930(7) -- assign 6:5 a 1
const_04 => const_04, -- Constant Wire, wire port const_wire to constant
const_08_p => mix_const_1, -- Set to 0
const_09_p => mix_const_2, -- Set to 1
const_10_2(0) => mix_const_3(0),
const_10_2(1) => mix_const_4(0),
const_10_2(2) => mix_const_3(0), -- Set two pins to 1
const_10_2(3) => mix_const_4(0), -- Set two pins to 0
inst_duo_2 => mix_const_22
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
port map (
bus20040728_oc => bus20040728_part(7)
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: inst_ad_e
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: inst_ae_e
port map (
bus20040728_altop_i => bus20040728_altop,
p_mix_bus20040728_top_7_4_gi => bus20040728_top(7 downto 4)
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/padio/bus/ioblock3_e-conf-c.vhd | 1 | 1932 | -- -------------------------------------------------------------
--
-- Generated Configuration for ioblock3_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-conf-c.vhd,v 1.1 2004/04/06 10:44:23 wig Exp $
-- $Date: 2004/04/06 10:44:23 $
-- $Log: ioblock3_e-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:44:23 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ioblock3_e_conf / ioblock3_e
--
configuration ioblock3_e_conf of ioblock3_e is
for rtl
-- Generated Configuration
for ioc_data_10 : ioc_r_iou
use configuration work.ioc_r_iou_conf;
end for;
for ioc_data_9 : ioc_r_iou
use configuration work.ioc_r_iou_conf;
end for;
for ioc_data_i33 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_data_i34 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_data_o35 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
for ioc_data_o36 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
for ioc_disp_10 : ioc_r_io3
use configuration work.ioc_r_io3_conf;
end for;
for ioc_disp_9 : ioc_r_io3
use configuration work.ioc_r_io3_conf;
end for;
end for;
end ioblock3_e_conf;
--
-- End of Generated Configuration ioblock3_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/udc/verilog/inst_xa_e-e.vhd | 1 | 1470 | -- -------------------------------------------------------------
--
-- Entity Declaration for inst_xa_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-e.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_xa_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_xa_e
--
entity inst_xa_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_xa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end inst_xa_e;
--
-- End of Generated Entity inst_xa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
| gpl-3.0 |
blutsvente/MIX | test/results/autoopen/inst_aa_e-rtl-conf-c.vhd | 1 | 1430 | -- -------------------------------------------------------------
--
-- Generated Configuration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:52:39 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-rtl-conf-c.vhd,v 1.3 2006/01/19 08:50:42 wig Exp $
-- $Date: 2006/01/19 08:50:42 $
-- $Log: inst_aa_e-rtl-conf-c.vhd,v $
-- Revision 1.3 2006/01/19 08:50:42 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_aa_e_rtl_conf / inst_aa_e
--
configuration inst_aa_e_rtl_conf of inst_aa_e is
for rtl
-- Generated Configuration
for inst_aaa : inst_aaa_e
use configuration work.inst_aaa_e_rtl_conf;
end for;
end for;
end inst_aa_e_rtl_conf;
--
-- End of Generated Configuration inst_aa_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
| gpl-3.0 |
Candyroot/Floating-Point-Addition | pda/@rounding/_primary.vhd | 4 | 534 | library verilog;
use verilog.vl_types.all;
entity Rounding is
port(
clk : in vl_logic;
res : in vl_logic;
shift : in vl_logic_vector(27 downto 0);
incre : in vl_logic_vector(8 downto 0);
exp_result : out vl_logic_vector(7 downto 0);
fra_result : out vl_logic_vector(27 downto 0);
result : out vl_logic_vector(31 downto 0);
overflow : out vl_logic
);
end Rounding;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/afifo.vhd | 20 | 9200 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
| gpl-3.0 |
makestuff/umdkv2 | vhdl/spi-funnel/spi_funnel.vhdl | 1 | 4941 | --
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_funnel is
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- CPU I/O
cpuByteWide_in : in std_logic;
cpuWrData_in : in std_logic_vector(15 downto 0);
cpuWrValid_in : in std_logic;
cpuRdData_out : out std_logic_vector(15 downto 0);
cpuRdStrobe_in : in std_logic;
-- Sending SPI data
sendData_out : out std_logic_vector(7 downto 0);
sendValid_out : out std_logic;
sendReady_in : in std_logic;
-- Receiving SPI data
recvData_in : in std_logic_vector(7 downto 0);
recvValid_in : in std_logic;
recvReady_out : out std_logic
);
end entity;
architecture rtl of spi_funnel is
type SStateType is (
S_WRITE_MSB,
S_WRITE_LSB
);
type RStateType is (
S_WAIT_MSB,
S_WAIT_LSB
);
signal sstate : SStateType := S_WRITE_MSB;
signal sstate_next : SStateType;
signal rstate : RStateType := S_WAIT_MSB;
signal rstate_next : RStateType;
signal byteWide : std_logic := '0';
signal byteWide_next : std_logic;
signal lsb : std_logic_vector(7 downto 0) := (others => '0');
signal lsb_next : std_logic_vector(7 downto 0);
signal readData : std_logic_vector(15 downto 0) := (others => '0');
signal readData_next : std_logic_vector(15 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
sstate <= S_WRITE_MSB;
rstate <= S_WAIT_MSB;
lsb <= (others => '0');
readData <= (others => '0');
byteWide <= '0';
else
sstate <= sstate_next;
rstate <= rstate_next;
lsb <= lsb_next;
readData <= readData_next;
byteWide <= byteWide_next;
end if;
end if;
end process;
-- Send state machine
process(sstate, lsb, cpuWrData_in, cpuWrValid_in, sendReady_in, cpuByteWide_in, cpuRdStrobe_in, byteWide)
begin
sstate_next <= sstate;
sendValid_out <= '0';
lsb_next <= lsb;
byteWide_next <= byteWide;
case sstate is
-- Now send the LSB to SPI and return:
when S_WRITE_LSB =>
sendData_out <= lsb;
if ( sendReady_in = '1' ) then
sendValid_out <= '1';
sstate_next <= S_WRITE_MSB;
end if;
-- When the CPU writes a word, send the MSB to SPI:
when others =>
sendData_out <= x"55";
if ( cpuByteWide_in = '1' ) then
-- We're sending single bytes rather than 16-bit words. Note
-- the lack of byte auto-read.
if ( cpuWrValid_in = '1' ) then
-- Write next word
sendData_out <= cpuWrData_in(15 downto 8);
sendValid_out <= '1';
byteWide_next <= '1';
end if;
else
-- We're sending 16-bit words rather than single bytes. Note
-- the word auto-read.
if ( cpuWrValid_in = '1' ) then
-- Write next word
sstate_next <= S_WRITE_LSB;
sendData_out <= cpuWrData_in(15 downto 8);
sendValid_out <= '1';
lsb_next <= cpuWrData_in(7 downto 0);
byteWide_next <= '0';
elsif ( cpuRdStrobe_in = '1' ) then
-- Auto-fetch next word when reading
sstate_next <= S_WRITE_LSB;
sendData_out <= x"FF";
sendValid_out <= '1';
lsb_next <= x"FF";
byteWide_next <= '0';
end if;
end if;
end case;
end process;
-- Receive state machine
process(rstate, readData, recvData_in, recvValid_in, byteWide)
begin
rstate_next <= rstate;
readData_next <= readData;
case rstate is
-- Wait for the LSB to arrive:
when S_WAIT_LSB =>
if ( recvValid_in = '1' ) then
rstate_next <= S_WAIT_MSB;
readData_next(7 downto 0) <= recvData_in;
end if;
-- When bytes arrive over SPI, present them (as bytes or words) to the CPU
when others =>
if ( recvValid_in = '1' ) then
if ( byteWide = '1' ) then
-- We're receiving single bytes rather than 16-bit words
readData_next <= recvData_in & x"AA"; --"XXXXXXXX";
else
-- We're receiving 16-bit words rather than single bytes
rstate_next <= S_WAIT_LSB;
readData_next(15 downto 8) <= recvData_in;
end if;
end if;
end case;
end process;
cpuRdData_out <= readData;
recvReady_out <= '1'; -- ready for data from 8-bit side
end architecture;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/mcb_flow_control.vhd | 20 | 18501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/mcb_flow_control.vhd | 20 | 18501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/mcb_flow_control.vhd | 20 | 18501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/i2c-master/i2c_master_registers.vhd | 2 | 5668 | -- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_registers is
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end;
architecture arch of i2c_master_registers is
signal ctr_int : std_logic_vector(7 downto 0);
signal cr_int : std_logic_vector(7 downto 0);
signal al : std_logic; -- status register arbitration lost bit
signal rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
begin
-- generate prescale regisres, control registers, and transmit register
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case (wb_adr_i) is
when "000" => prer(7 downto 0) <= wb_dat_i;
when "001" => prer(15 downto 8) <= wb_dat_i;
when "010" => ctr_int <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when others => NULL;
end case;
end if;
end if;
end process;
ctr <= ctr_int;
-- generate command register (special case)
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
cr_int <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr_int <= (others => '0');
elsif (wb_wacc = '1') then
if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
cr_int <= wb_dat_i;
end if;
else
if ((done = '1') OR (i2c_al = '1')) then
cr_int(7 downto 4) <= "0000"; -- clear command b
end if; -- or when aribitr
cr_int(2 downto 1) <= "00"; -- reserved bits
cr_int(0) <= '0'; -- clear IRQ_ACK b
end if;
end if;
end process;
cr <= cr_int;
-- generate status register block + interrupt request signal
-- each output will be assigned to corresponding sr register locations on top level
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al OR (al AND NOT(cr_int(7)));
rxack <= irxack;
tip <= (cr_int(5) OR cr_int(4));
irq_flag <= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
end if;
end if;
end process;
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= "000"; -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end arch;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/gn4124-core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd | 2 | 22920 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_clk_pll_s2_diff is
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s2_diff;
architecture arch_serdes_1_to_n_clk_pll_s2_diff of serdes_1_to_n_clk_pll_s2_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0); --
signal cascade : std_logic; --
signal pd_edge : std_logic; --
signal busys : std_logic; --
signal busym : std_logic; --
signal rx_clk_in : std_logic; --
signal feedback : std_logic; --
signal buf_P_clk : std_logic; --
signal iob_data_in : std_logic; --
signal rx_bufg_pll_x1_int : std_logic;
signal rxioclk_int : std_logic;
signal rx_serdesstrobe_int : std_logic;
signal rx_pllout_xs_int : std_logic;
signal rx_pllout_x1 : std_logic;
signal rx_pll_lckd_int : std_logic;
signal state : integer range 0 to 9;
signal bslip : std_logic;
signal count : std_logic_vector(2 downto 0);
signal busyd : std_logic;
signal counter : std_logic_vector(11 downto 0);
signal clk_iserdes_data : std_logic_vector(S-1 downto 0);
signal cal_clk : std_logic;
signal rst_clk : std_logic;
signal rx_bufplllckd : std_logic;
signal not_rx_bufpll_lckd : std_logic;
signal busy_clk : std_logic;
signal enable : std_logic;
constant RX_SWAP_CLK : std_logic := '0'; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int;
rxioclk <= rxioclk_int;
rx_serdesstrobe <= rx_serdesstrobe_int;
rx_pllout_xs <= rx_pllout_xs_int;
rx_pll_lckd <= rx_pll_lckd_int;
bitslip <= bslip;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK; -- Invert clock as required
busy_clk <= busym;
datain <= clk_iserdes_data;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0;
enable <= '0';
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk;
if counter(5) = '1' then
enable <= '1';
end if;
if counter(11) = '1' then
state <= 0;
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
else
counter <= counter + 1;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1;
elsif state = 1 then -- cal high
cal_clk <= '1'; state <= 2;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0'; state <= 3; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1'; state <= 4; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0'; state <= 5;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6;
count <= "000";
elsif state = 6 then -- hang around
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 7 then
if BS = true and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1'; -- bitslip needed
state <= 8;
count <= "000";
else
state <= 9;
end if;
elsif state = 8 then
bslip <= '0'; -- bitslip low
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 9 then -- repeat after a delay
state <= 9;
end if;
end if;
end if;
end process;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S);
end generate;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 90.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int);
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd);
end arch_serdes_1_to_n_clk_pll_s2_diff;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | reg.vhd | 1 | 2921 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- register on a register bus
entity reg is
generic (REG_BYTES : integer;
DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out std_logic_vector(REG_BYTES*8 - 1 downto 0));
end reg;
-- Operation:
-- Hold the @Value. Access it when address on the bus matches @REG_ADDR_BASE.
-- Writes are atomic - @Value is changed only when address on the bus is out of
-- the range of addresses of this register.
-- Writes to register must be 'clock-in-clock' to ensure atomicity of the value.
architecture Behavioral of reg is
constant OFFSET_LEN : integer := integer(ceil(log2(real(REG_BYTES))));
constant REG_BITS : integer := REG_BYTES*8;
subtype OffsetRange is natural range OFFSET_LEN - 1 downto 0;
subtype AddrRange is natural range REG_ADDR_W - 1 downto OFFSET_LEN;
signal offset : integer;
signal bus_addr, reg_addr : std_logic_vector(AddrRange);
signal v_atomic, v_new : std_logic_vector(REG_BITS - 1 downto 0) := CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
begin
offset <= CONV_integer(RegBusI.addr(OffsetRange));
bus_addr <= RegBusI.addr(AddrRange);
reg_addr <= REG_ADDR_BASE(AddrRange);
Value <= v_atomic;
update : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if bus_addr = reg_addr then
if RegBusI.wr = '1' then
v_new(7 + offset*8 downto offset*8) <= RegBusI.data;
else
RegBusO.data <= v_atomic(7 + offset*8 downto offset*8);
end if;
else
v_atomic <= v_new;
end if;
if Rst = '1' then
v_new <= CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
RegBusO.addr <= reg_addr_invl;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
Project-Bonfire/Bonfire | Packages/router_pack_vc.vhd | 1 | 7820 | ---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package router_pack is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
valid_in_vc: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_en_vc_N : in std_logic;
read_en_vc_E : in std_logic;
read_en_vc_W : in std_logic;
read_en_vc_S : in std_logic;
read_en_vc_L : in std_logic;
credit_out: out std_logic;
credit_out_vc: out std_logic;
empty_out: out std_logic;
empty_out_vc: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
Data_out_vc: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- vc signals
credit_in_vc_N, credit_in_vc_E, credit_in_vc_W, credit_in_vc_S, credit_in_vc_L: in std_logic;
req_N_N_vc, req_N_E_vc, req_N_W_vc, req_N_S_vc, req_N_L_vc: in std_logic;
req_E_N_vc, req_E_E_vc, req_E_W_vc, req_E_S_vc, req_E_L_vc: in std_logic;
req_W_N_vc, req_W_E_vc, req_W_W_vc, req_W_S_vc, req_W_L_vc: in std_logic;
req_S_N_vc, req_S_E_vc, req_S_W_vc, req_S_S_vc, req_S_L_vc: in std_logic;
req_L_N_vc, req_L_E_vc, req_L_W_vc, req_L_S_vc, req_L_L_vc: in std_logic;
empty_vc_N, empty_vc_E, empty_vc_W, empty_vc_S, empty_vc_L: in std_logic;
valid_vc_N, valid_vc_E, valid_vc_W, valid_vc_S, valid_vc_L : out std_logic;
grant_N_N_vc, grant_N_E_vc, grant_N_W_vc, grant_N_S_vc, grant_N_L_vc: out std_logic;
grant_E_N_vc, grant_E_E_vc, grant_E_W_vc, grant_E_S_vc, grant_E_L_vc: out std_logic;
grant_W_N_vc, grant_W_E_vc, grant_W_W_vc, grant_W_S_vc, grant_W_L_vc: out std_logic;
grant_S_N_vc, grant_S_E_vc, grant_S_W_vc, grant_S_S_vc, grant_S_L_vc: out std_logic;
grant_L_N_vc, grant_L_E_vc, grant_L_W_vc, grant_L_S_vc, grant_L_L_vc: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
North_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (9 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT NI_vc is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111110"; -- NI's memory mapped reserved VC_0
reserved_address_vc : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved for VC_1
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
credit_in_vc: in std_logic;
valid_out_vc: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
credit_out_vc: out std_logic;
valid_in_vc: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end COMPONENT; --entity NI_vc
end; --package body
| gpl-3.0 |
Project-Bonfire/Bonfire | RTL/base_line/xbar.vhd | 20 | 1004 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end; | gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/data_prbs_gen.vhd | 20 | 4942 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: data_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is used LFSR to generate random data for memory
-- data write or memory data read comparison.The first data is
-- seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
-- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END data_prbs_gen;
ARCHITECTURE trans OF data_prbs_gen IS
SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
SIGNAL i : INTEGER;
BEGIN
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
lfsr_q(2) <= lfsr_q(1);
lfsr_q(1) <= lfsr_q(32);
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
BEGIN
prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
END PROCESS;
prbs_o <= prbs;
END trans;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ddr3_ctrl_wrapper_pkg.vhd | 2 | 40393 | --==============================================================================
--! @file ddr3_ctrl_wrapper_pkg.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Wrapper Package
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 controller wrapper package
--------------------------------------------------------------------------------
--! @details
--! Contains DDR3 controller wrapper component declaration.
--! Component used in the wrapper are generated using Xilinx CoreGen.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 06.07.2012 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_wrapper_pkg
--==============================================================================
package ddr3_ctrl_wrapper_pkg is
--============================================================================
--! Components declaration
--============================================================================
----------------------------------------------------------------------------
-- SPEC
----------------------------------------------------------------------------
component ddr3_ctrl_spec_bank3_32b_32b
generic
(C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
C3_RST_ACT_LOW : integer := 1;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 14;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component ddr3_ctrl_spec_bank3_32b_32b;
component ddr3_ctrl_spec_bank3_64b_32b
generic
(C3_P0_MASK_SIZE : integer := 8;
C3_P0_DATA_PORT_SIZE : integer := 64;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 14;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component ddr3_ctrl_spec_bank3_64b_32b;
----------------------------------------------------------------------------
-- SVEC
----------------------------------------------------------------------------
component ddr3_ctrl_svec_bank4_32b_32b
generic
(C4_P0_MASK_SIZE : integer := 4;
C4_P0_DATA_PORT_SIZE : integer := 32;
C4_P1_MASK_SIZE : integer := 4;
C4_P1_DATA_PORT_SIZE : integer := 32;
C4_MEMCLK_PERIOD : integer := 3000;
C4_RST_ACT_LOW : integer := 1;
C4_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C4_CALIB_SOFT_IP : string := "TRUE";
C4_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C4_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C4_NUM_DQ_PINS : integer := 16;
C4_MEM_ADDR_WIDTH : integer := 14;
C4_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb4_dram_dq : inout std_logic_vector(C4_NUM_DQ_PINS-1 downto 0);
mcb4_dram_a : out std_logic_vector(C4_MEM_ADDR_WIDTH-1 downto 0);
mcb4_dram_ba : out std_logic_vector(C4_MEM_BANKADDR_WIDTH-1 downto 0);
mcb4_dram_ras_n : out std_logic;
mcb4_dram_cas_n : out std_logic;
mcb4_dram_we_n : out std_logic;
mcb4_dram_odt : out std_logic;
mcb4_dram_reset_n : out std_logic;
mcb4_dram_cke : out std_logic;
mcb4_dram_dm : out std_logic;
mcb4_dram_udqs : inout std_logic;
mcb4_dram_udqs_n : inout std_logic;
mcb4_rzq : inout std_logic;
mcb4_dram_udm : out std_logic;
c4_sys_clk : in std_logic;
c4_sys_rst_i : in std_logic;
c4_calib_done : out std_logic;
c4_clk0 : out std_logic;
c4_rst0 : out std_logic;
mcb4_dram_dqs : inout std_logic;
mcb4_dram_dqs_n : inout std_logic;
mcb4_dram_ck : out std_logic;
mcb4_dram_ck_n : out std_logic;
c4_p0_cmd_clk : in std_logic;
c4_p0_cmd_en : in std_logic;
c4_p0_cmd_instr : in std_logic_vector(2 downto 0);
c4_p0_cmd_bl : in std_logic_vector(5 downto 0);
c4_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c4_p0_cmd_empty : out std_logic;
c4_p0_cmd_full : out std_logic;
c4_p0_wr_clk : in std_logic;
c4_p0_wr_en : in std_logic;
c4_p0_wr_mask : in std_logic_vector(C4_P0_MASK_SIZE - 1 downto 0);
c4_p0_wr_data : in std_logic_vector(C4_P0_DATA_PORT_SIZE - 1 downto 0);
c4_p0_wr_full : out std_logic;
c4_p0_wr_empty : out std_logic;
c4_p0_wr_count : out std_logic_vector(6 downto 0);
c4_p0_wr_underrun : out std_logic;
c4_p0_wr_error : out std_logic;
c4_p0_rd_clk : in std_logic;
c4_p0_rd_en : in std_logic;
c4_p0_rd_data : out std_logic_vector(C4_P0_DATA_PORT_SIZE - 1 downto 0);
c4_p0_rd_full : out std_logic;
c4_p0_rd_empty : out std_logic;
c4_p0_rd_count : out std_logic_vector(6 downto 0);
c4_p0_rd_overflow : out std_logic;
c4_p0_rd_error : out std_logic;
c4_p1_cmd_clk : in std_logic;
c4_p1_cmd_en : in std_logic;
c4_p1_cmd_instr : in std_logic_vector(2 downto 0);
c4_p1_cmd_bl : in std_logic_vector(5 downto 0);
c4_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c4_p1_cmd_empty : out std_logic;
c4_p1_cmd_full : out std_logic;
c4_p1_wr_clk : in std_logic;
c4_p1_wr_en : in std_logic;
c4_p1_wr_mask : in std_logic_vector(C4_P1_MASK_SIZE - 1 downto 0);
c4_p1_wr_data : in std_logic_vector(C4_P1_DATA_PORT_SIZE - 1 downto 0);
c4_p1_wr_full : out std_logic;
c4_p1_wr_empty : out std_logic;
c4_p1_wr_count : out std_logic_vector(6 downto 0);
c4_p1_wr_underrun : out std_logic;
c4_p1_wr_error : out std_logic;
c4_p1_rd_clk : in std_logic;
c4_p1_rd_en : in std_logic;
c4_p1_rd_data : out std_logic_vector(C4_P1_DATA_PORT_SIZE - 1 downto 0);
c4_p1_rd_full : out std_logic;
c4_p1_rd_empty : out std_logic;
c4_p1_rd_count : out std_logic_vector(6 downto 0);
c4_p1_rd_overflow : out std_logic;
c4_p1_rd_error : out std_logic
);
end component ddr3_ctrl_svec_bank4_32b_32b;
component ddr3_ctrl_svec_bank4_64b_32b
generic
(C4_P0_MASK_SIZE : integer := 8;
C4_P0_DATA_PORT_SIZE : integer := 64;
C4_P1_MASK_SIZE : integer := 4;
C4_P1_DATA_PORT_SIZE : integer := 32;
C4_MEMCLK_PERIOD : integer := 3000;
C4_RST_ACT_LOW : integer := 1;
C4_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C4_CALIB_SOFT_IP : string := "TRUE";
C4_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C4_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C4_NUM_DQ_PINS : integer := 16;
C4_MEM_ADDR_WIDTH : integer := 14;
C4_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb4_dram_dq : inout std_logic_vector(C4_NUM_DQ_PINS-1 downto 0);
mcb4_dram_a : out std_logic_vector(C4_MEM_ADDR_WIDTH-1 downto 0);
mcb4_dram_ba : out std_logic_vector(C4_MEM_BANKADDR_WIDTH-1 downto 0);
mcb4_dram_ras_n : out std_logic;
mcb4_dram_cas_n : out std_logic;
mcb4_dram_we_n : out std_logic;
mcb4_dram_odt : out std_logic;
mcb4_dram_reset_n : out std_logic;
mcb4_dram_cke : out std_logic;
mcb4_dram_dm : out std_logic;
mcb4_dram_udqs : inout std_logic;
mcb4_dram_udqs_n : inout std_logic;
mcb4_rzq : inout std_logic;
mcb4_dram_udm : out std_logic;
c4_sys_clk : in std_logic;
c4_sys_rst_i : in std_logic;
c4_calib_done : out std_logic;
c4_clk0 : out std_logic;
c4_rst0 : out std_logic;
mcb4_dram_dqs : inout std_logic;
mcb4_dram_dqs_n : inout std_logic;
mcb4_dram_ck : out std_logic;
mcb4_dram_ck_n : out std_logic;
c4_p0_cmd_clk : in std_logic;
c4_p0_cmd_en : in std_logic;
c4_p0_cmd_instr : in std_logic_vector(2 downto 0);
c4_p0_cmd_bl : in std_logic_vector(5 downto 0);
c4_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c4_p0_cmd_empty : out std_logic;
c4_p0_cmd_full : out std_logic;
c4_p0_wr_clk : in std_logic;
c4_p0_wr_en : in std_logic;
c4_p0_wr_mask : in std_logic_vector(C4_P0_MASK_SIZE - 1 downto 0);
c4_p0_wr_data : in std_logic_vector(C4_P0_DATA_PORT_SIZE - 1 downto 0);
c4_p0_wr_full : out std_logic;
c4_p0_wr_empty : out std_logic;
c4_p0_wr_count : out std_logic_vector(6 downto 0);
c4_p0_wr_underrun : out std_logic;
c4_p0_wr_error : out std_logic;
c4_p0_rd_clk : in std_logic;
c4_p0_rd_en : in std_logic;
c4_p0_rd_data : out std_logic_vector(C4_P0_DATA_PORT_SIZE - 1 downto 0);
c4_p0_rd_full : out std_logic;
c4_p0_rd_empty : out std_logic;
c4_p0_rd_count : out std_logic_vector(6 downto 0);
c4_p0_rd_overflow : out std_logic;
c4_p0_rd_error : out std_logic;
c4_p1_cmd_clk : in std_logic;
c4_p1_cmd_en : in std_logic;
c4_p1_cmd_instr : in std_logic_vector(2 downto 0);
c4_p1_cmd_bl : in std_logic_vector(5 downto 0);
c4_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c4_p1_cmd_empty : out std_logic;
c4_p1_cmd_full : out std_logic;
c4_p1_wr_clk : in std_logic;
c4_p1_wr_en : in std_logic;
c4_p1_wr_mask : in std_logic_vector(C4_P1_MASK_SIZE - 1 downto 0);
c4_p1_wr_data : in std_logic_vector(C4_P1_DATA_PORT_SIZE - 1 downto 0);
c4_p1_wr_full : out std_logic;
c4_p1_wr_empty : out std_logic;
c4_p1_wr_count : out std_logic_vector(6 downto 0);
c4_p1_wr_underrun : out std_logic;
c4_p1_wr_error : out std_logic;
c4_p1_rd_clk : in std_logic;
c4_p1_rd_en : in std_logic;
c4_p1_rd_data : out std_logic_vector(C4_P1_DATA_PORT_SIZE - 1 downto 0);
c4_p1_rd_full : out std_logic;
c4_p1_rd_empty : out std_logic;
c4_p1_rd_count : out std_logic_vector(6 downto 0);
c4_p1_rd_overflow : out std_logic;
c4_p1_rd_error : out std_logic
);
end component ddr3_ctrl_svec_bank4_64b_32b;
component ddr3_ctrl_svec_bank5_32b_32b
generic
(C5_P0_MASK_SIZE : integer := 4;
C5_P0_DATA_PORT_SIZE : integer := 32;
C5_P1_MASK_SIZE : integer := 4;
C5_P1_DATA_PORT_SIZE : integer := 32;
C5_MEMCLK_PERIOD : integer := 3000;
C5_RST_ACT_LOW : integer := 1;
C5_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C5_CALIB_SOFT_IP : string := "TRUE";
C5_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C5_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C5_NUM_DQ_PINS : integer := 16;
C5_MEM_ADDR_WIDTH : integer := 14;
C5_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb5_dram_dq : inout std_logic_vector(C5_NUM_DQ_PINS-1 downto 0);
mcb5_dram_a : out std_logic_vector(C5_MEM_ADDR_WIDTH-1 downto 0);
mcb5_dram_ba : out std_logic_vector(C5_MEM_BANKADDR_WIDTH-1 downto 0);
mcb5_dram_ras_n : out std_logic;
mcb5_dram_cas_n : out std_logic;
mcb5_dram_we_n : out std_logic;
mcb5_dram_odt : out std_logic;
mcb5_dram_reset_n : out std_logic;
mcb5_dram_cke : out std_logic;
mcb5_dram_dm : out std_logic;
mcb5_dram_udqs : inout std_logic;
mcb5_dram_udqs_n : inout std_logic;
mcb5_rzq : inout std_logic;
mcb5_dram_udm : out std_logic;
c5_sys_clk : in std_logic;
c5_sys_rst_i : in std_logic;
c5_calib_done : out std_logic;
c5_clk0 : out std_logic;
c5_rst0 : out std_logic;
mcb5_dram_dqs : inout std_logic;
mcb5_dram_dqs_n : inout std_logic;
mcb5_dram_ck : out std_logic;
mcb5_dram_ck_n : out std_logic;
c5_p0_cmd_clk : in std_logic;
c5_p0_cmd_en : in std_logic;
c5_p0_cmd_instr : in std_logic_vector(2 downto 0);
c5_p0_cmd_bl : in std_logic_vector(5 downto 0);
c5_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c5_p0_cmd_empty : out std_logic;
c5_p0_cmd_full : out std_logic;
c5_p0_wr_clk : in std_logic;
c5_p0_wr_en : in std_logic;
c5_p0_wr_mask : in std_logic_vector(C5_P0_MASK_SIZE - 1 downto 0);
c5_p0_wr_data : in std_logic_vector(C5_P0_DATA_PORT_SIZE - 1 downto 0);
c5_p0_wr_full : out std_logic;
c5_p0_wr_empty : out std_logic;
c5_p0_wr_count : out std_logic_vector(6 downto 0);
c5_p0_wr_underrun : out std_logic;
c5_p0_wr_error : out std_logic;
c5_p0_rd_clk : in std_logic;
c5_p0_rd_en : in std_logic;
c5_p0_rd_data : out std_logic_vector(C5_P0_DATA_PORT_SIZE - 1 downto 0);
c5_p0_rd_full : out std_logic;
c5_p0_rd_empty : out std_logic;
c5_p0_rd_count : out std_logic_vector(6 downto 0);
c5_p0_rd_overflow : out std_logic;
c5_p0_rd_error : out std_logic;
c5_p1_cmd_clk : in std_logic;
c5_p1_cmd_en : in std_logic;
c5_p1_cmd_instr : in std_logic_vector(2 downto 0);
c5_p1_cmd_bl : in std_logic_vector(5 downto 0);
c5_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c5_p1_cmd_empty : out std_logic;
c5_p1_cmd_full : out std_logic;
c5_p1_wr_clk : in std_logic;
c5_p1_wr_en : in std_logic;
c5_p1_wr_mask : in std_logic_vector(C5_P1_MASK_SIZE - 1 downto 0);
c5_p1_wr_data : in std_logic_vector(C5_P1_DATA_PORT_SIZE - 1 downto 0);
c5_p1_wr_full : out std_logic;
c5_p1_wr_empty : out std_logic;
c5_p1_wr_count : out std_logic_vector(6 downto 0);
c5_p1_wr_underrun : out std_logic;
c5_p1_wr_error : out std_logic;
c5_p1_rd_clk : in std_logic;
c5_p1_rd_en : in std_logic;
c5_p1_rd_data : out std_logic_vector(C5_P1_DATA_PORT_SIZE - 1 downto 0);
c5_p1_rd_full : out std_logic;
c5_p1_rd_empty : out std_logic;
c5_p1_rd_count : out std_logic_vector(6 downto 0);
c5_p1_rd_overflow : out std_logic;
c5_p1_rd_error : out std_logic
);
end component ddr3_ctrl_svec_bank5_32b_32b;
component ddr3_ctrl_svec_bank5_64b_32b
generic
(C5_P0_MASK_SIZE : integer := 8;
C5_P0_DATA_PORT_SIZE : integer := 64;
C5_P1_MASK_SIZE : integer := 4;
C5_P1_DATA_PORT_SIZE : integer := 32;
C5_MEMCLK_PERIOD : integer := 3000;
C5_RST_ACT_LOW : integer := 1;
C5_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C5_CALIB_SOFT_IP : string := "TRUE";
C5_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C5_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C5_NUM_DQ_PINS : integer := 16;
C5_MEM_ADDR_WIDTH : integer := 14;
C5_MEM_BANKADDR_WIDTH : integer := 3
);
port
(mcb5_dram_dq : inout std_logic_vector(C5_NUM_DQ_PINS-1 downto 0);
mcb5_dram_a : out std_logic_vector(C5_MEM_ADDR_WIDTH-1 downto 0);
mcb5_dram_ba : out std_logic_vector(C5_MEM_BANKADDR_WIDTH-1 downto 0);
mcb5_dram_ras_n : out std_logic;
mcb5_dram_cas_n : out std_logic;
mcb5_dram_we_n : out std_logic;
mcb5_dram_odt : out std_logic;
mcb5_dram_reset_n : out std_logic;
mcb5_dram_cke : out std_logic;
mcb5_dram_dm : out std_logic;
mcb5_dram_udqs : inout std_logic;
mcb5_dram_udqs_n : inout std_logic;
mcb5_rzq : inout std_logic;
mcb5_dram_udm : out std_logic;
c5_sys_clk : in std_logic;
c5_sys_rst_i : in std_logic;
c5_calib_done : out std_logic;
c5_clk0 : out std_logic;
c5_rst0 : out std_logic;
mcb5_dram_dqs : inout std_logic;
mcb5_dram_dqs_n : inout std_logic;
mcb5_dram_ck : out std_logic;
mcb5_dram_ck_n : out std_logic;
c5_p0_cmd_clk : in std_logic;
c5_p0_cmd_en : in std_logic;
c5_p0_cmd_instr : in std_logic_vector(2 downto 0);
c5_p0_cmd_bl : in std_logic_vector(5 downto 0);
c5_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c5_p0_cmd_empty : out std_logic;
c5_p0_cmd_full : out std_logic;
c5_p0_wr_clk : in std_logic;
c5_p0_wr_en : in std_logic;
c5_p0_wr_mask : in std_logic_vector(C5_P0_MASK_SIZE - 1 downto 0);
c5_p0_wr_data : in std_logic_vector(C5_P0_DATA_PORT_SIZE - 1 downto 0);
c5_p0_wr_full : out std_logic;
c5_p0_wr_empty : out std_logic;
c5_p0_wr_count : out std_logic_vector(6 downto 0);
c5_p0_wr_underrun : out std_logic;
c5_p0_wr_error : out std_logic;
c5_p0_rd_clk : in std_logic;
c5_p0_rd_en : in std_logic;
c5_p0_rd_data : out std_logic_vector(C5_P0_DATA_PORT_SIZE - 1 downto 0);
c5_p0_rd_full : out std_logic;
c5_p0_rd_empty : out std_logic;
c5_p0_rd_count : out std_logic_vector(6 downto 0);
c5_p0_rd_overflow : out std_logic;
c5_p0_rd_error : out std_logic;
c5_p1_cmd_clk : in std_logic;
c5_p1_cmd_en : in std_logic;
c5_p1_cmd_instr : in std_logic_vector(2 downto 0);
c5_p1_cmd_bl : in std_logic_vector(5 downto 0);
c5_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c5_p1_cmd_empty : out std_logic;
c5_p1_cmd_full : out std_logic;
c5_p1_wr_clk : in std_logic;
c5_p1_wr_en : in std_logic;
c5_p1_wr_mask : in std_logic_vector(C5_P1_MASK_SIZE - 1 downto 0);
c5_p1_wr_data : in std_logic_vector(C5_P1_DATA_PORT_SIZE - 1 downto 0);
c5_p1_wr_full : out std_logic;
c5_p1_wr_empty : out std_logic;
c5_p1_wr_count : out std_logic_vector(6 downto 0);
c5_p1_wr_underrun : out std_logic;
c5_p1_wr_error : out std_logic;
c5_p1_rd_clk : in std_logic;
c5_p1_rd_en : in std_logic;
c5_p1_rd_data : out std_logic_vector(C5_P1_DATA_PORT_SIZE - 1 downto 0);
c5_p1_rd_full : out std_logic;
c5_p1_rd_empty : out std_logic;
c5_p1_rd_count : out std_logic_vector(6 downto 0);
c5_p1_rd_overflow : out std_logic;
c5_p1_rd_error : out std_logic
);
end component ddr3_ctrl_svec_bank5_64b_32b;
----------------------------------------------------------------------------
-- VFC
----------------------------------------------------------------------------
component ddr3_ctrl_vfc_bank1_32b_32b
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 3000;
C1_RST_ACT_LOW : integer := 0;
C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C1_CALIB_SOFT_IP : string := "TRUE";
C1_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C1_NUM_DQ_PINS : integer := 16;
C1_MEM_ADDR_WIDTH : integer := 14;
C1_MEM_BANKADDR_WIDTH : integer := 3
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c1_p1_cmd_clk : in std_logic;
c1_p1_cmd_en : in std_logic;
c1_p1_cmd_instr : in std_logic_vector(2 downto 0);
c1_p1_cmd_bl : in std_logic_vector(5 downto 0);
c1_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p1_cmd_empty : out std_logic;
c1_p1_cmd_full : out std_logic;
c1_p1_wr_clk : in std_logic;
c1_p1_wr_en : in std_logic;
c1_p1_wr_mask : in std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
c1_p1_wr_data : in std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_wr_full : out std_logic;
c1_p1_wr_empty : out std_logic;
c1_p1_wr_count : out std_logic_vector(6 downto 0);
c1_p1_wr_underrun : out std_logic;
c1_p1_wr_error : out std_logic;
c1_p1_rd_clk : in std_logic;
c1_p1_rd_en : in std_logic;
c1_p1_rd_data : out std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_rd_full : out std_logic;
c1_p1_rd_empty : out std_logic;
c1_p1_rd_count : out std_logic_vector(6 downto 0);
c1_p1_rd_overflow : out std_logic;
c1_p1_rd_error : out std_logic
);
end component ddr3_ctrl_vfc_bank1_32b_32b;
component ddr3_ctrl_vfc_bank1_64b_32b
generic
(
C1_P0_MASK_SIZE : integer := 8;
C1_P0_DATA_PORT_SIZE : integer := 64;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 3000;
C1_RST_ACT_LOW : integer := 0;
C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C1_CALIB_SOFT_IP : string := "TRUE";
C1_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C1_NUM_DQ_PINS : integer := 16;
C1_MEM_ADDR_WIDTH : integer := 14;
C1_MEM_BANKADDR_WIDTH : integer := 3
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c1_p1_cmd_clk : in std_logic;
c1_p1_cmd_en : in std_logic;
c1_p1_cmd_instr : in std_logic_vector(2 downto 0);
c1_p1_cmd_bl : in std_logic_vector(5 downto 0);
c1_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p1_cmd_empty : out std_logic;
c1_p1_cmd_full : out std_logic;
c1_p1_wr_clk : in std_logic;
c1_p1_wr_en : in std_logic;
c1_p1_wr_mask : in std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
c1_p1_wr_data : in std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_wr_full : out std_logic;
c1_p1_wr_empty : out std_logic;
c1_p1_wr_count : out std_logic_vector(6 downto 0);
c1_p1_wr_underrun : out std_logic;
c1_p1_wr_error : out std_logic;
c1_p1_rd_clk : in std_logic;
c1_p1_rd_en : in std_logic;
c1_p1_rd_data : out std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_rd_full : out std_logic;
c1_p1_rd_empty : out std_logic;
c1_p1_rd_count : out std_logic_vector(6 downto 0);
c1_p1_rd_overflow : out std_logic;
c1_p1_rd_error : out std_logic
);
end component ddr3_ctrl_vfc_bank1_64b_32b;
end ddr3_ctrl_wrapper_pkg;
package body ddr3_ctrl_wrapper_pkg is
end ddr3_ctrl_wrapper_pkg;
| gpl-3.0 |
makestuff/umdkv2 | vhdl/spi-funnel/tb_unit/spi_funnel_tb.vhdl | 1 | 6114 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_funnel_tb is
end entity;
architecture behavioural of spi_funnel_tb is
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
signal cpuWrData : std_logic_vector(15 downto 0);
signal cpuWrValid : std_logic;
signal cpuRdData : std_logic_vector(15 downto 0);
signal cpuByteWide : std_logic;
signal sendData : std_logic_vector(7 downto 0);
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
signal recvReady : std_logic;
signal spiClk : std_logic;
signal spiDataOut : std_logic;
signal spiDataIn : std_logic;
begin
-- Instantiate the memory arbiter for testing
uut: entity work.spi_funnel
port map(
clk_in => sysClk,
reset_in => reset,
-- CPU I/O
cpuByteWide_in => cpuByteWide,
cpuWrData_in => cpuWrData,
cpuWrValid_in => cpuWrValid,
cpuRdData_out => cpuRdData,
cpuRdStrobe_in => '0',
-- Sending SPI data
sendData_out => sendData,
sendValid_out => sendValid,
sendReady_in => sendReady,
-- Receiving SPI data
recvData_in => recvData,
recvValid_in => recvValid,
recvReady_out => recvReady
);
-- SPI master
spi_master : entity work.spi_master
generic map(
SLOW_COUNT => "111011", -- spiClk = sysClk/120 (400kHz @48MHz)
FAST_COUNT => "000000", -- spiClk = sysClk/2 (24MHz @48MHz)
BIT_ORDER => '1' -- MSB first
)
port map(
clk_in => sysClk,
reset_in => reset,
-- Send pipe
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
-- Receive pipe
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
-- SPI interface
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset one cycle after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
process
begin
cpuByteWide <= 'X';
cpuWrData <= (others => 'X');
cpuWrValid <= '0';
spiDataIn <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"0306";
cpuByteWide <= '0';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"55CA";
cpuByteWide <= '1';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
--cpuByteWide <= '1';
--cpuWrData <= x"0055";
--cpuWrValid <= '1';
--wait until rising_edge(sysClk);
--cpuWrData <= (others => 'X');
--cpuWrValid <= '0';
wait;
end process;
end architecture;
| gpl-3.0 |
maxx04/cam_sim | cam_sim.srcs/sim_1/new/bmp_wreiter.vhd | 1 | 2567 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 20:50:53
-- Design Name:
-- Module Name: bmp_wreiter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Ändert gelesene BMP datei und schreibt es in neues BMP.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use work.sim_bmppack.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity bmp_wreiter is
GENERIC(byte_per_pixel : natural := 3);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
start_frame : in STD_LOGIC;
x, y : in natural;
pixel_data : in std_logic_vector(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : in sensor_vector;
sensor_data_ready : in STD_LOGIC);
end bmp_wreiter;
architecture Behavioral of bmp_wreiter is
signal file_writed : std_logic := '0';
signal ImageWidth, ImageHeight, x_old : natural := 0;
signal px_data_tmp : std_logic_vector(23 downto 0) := (others => '0');
begin
writer : process is
variable tmp_sensor_vec : sensor_vector;
variable tmp_sensor : sensor;
begin
wait until rising_edge(clk);
if resetn = '1' then
if (x /= x_old) then
x_old <= x;
if (pixel_data_ready = '1') then -- selber bild abbilden
SetPixel(x, y, pixel_data);
end if;
if (sensor_data_ready = '1' ) then -- sensor abbilden
tmp_sensor := vector2sensor(sensor_data);
px_data_tmp (7 downto 0) <= conv_std_logic_vector(tmp_sensor.color.r, 8);
px_data_tmp (15 downto 8) <= conv_std_logic_vector(tmp_sensor.color.g, 8);
px_data_tmp (23 downto 16) <= conv_std_logic_vector(tmp_sensor.color.b, 8);
end if;
if (y = 640) then -- FIXME ende schreiben, dann
DrawCross(tmp_sensor.pos.x, tmp_sensor.pos.y, px_data_tmp);
if file_writed = '0' then
report "write File...";
WriteFile(" ..\..\test_out.bmp");
file_writed <= '1';
report "File is written.";
end if;
wait;
end if;
end if;
end if;
end process writer;
end Behavioral;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/common/common_pkg.vhd | 1 | 1881 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
package common_pkg is
component generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end component generic_async_fifo;
end common_pkg;
package body common_pkg is
end common_pkg;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | tb_bus_append.vhd | 1 | 2823 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_bus_append IS
END tb_bus_append;
ARCHITECTURE behavior OF tb_bus_append IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_append
GENERIC ( N_BYTES : integer );
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Cnt64 : std_logic_vector(63 downto 0) := (others => '0');
signal InPkt : std_logic := '0';
signal InData : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OutPkt : std_logic;
signal OutData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bus_append
GENERIC MAP ( N_BYTES => 8 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Value => Cnt64,
InPkt => InPkt,
InData => InData,
OutPkt => OutPkt,
OutData => OutData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
Cnt64_process :process
begin
wait for Clk_period;
Cnt64 <= Cnt64 + 1;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
InPkt <= '1';
for i in 0 to 6 loop
InData <= X"55";
wait for Clk_period;
end loop;
InData <= X"d5";
wait for Clk_period;
for i in 0 to 63 loop
InData <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
-- InData <= x"00";
-- wait for Clk_period;
InPkt <= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
makestuff/umdkv2 | templates/fx2min/vhdl/lx9r3.vhdl | 2 | 6552 | -- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.001______0.000______50.0______200.000____150.000
-- CLK_OUT2____48.001____180.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________48____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_gen is
port
(-- Clock in ports
clk_in : in std_logic;
-- Clock out ports
clk000_out : out std_logic;
clk180_out : out std_logic;
-- Status and control signals
locked_out : out std_logic
);
end clk_gen;
architecture xilinx of clk_gen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_gen,clk_wiz_v4_1,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.833,clkin2_period=20.833,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk180 : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clk_in);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.833,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => clk180,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
locked_out <= locked_internal;
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
clk000_out <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => clk180_out,
I => clk180);
end xilinx;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | tb_mdio_ctrl.vhd | 1 | 3158 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mdio_ctrl IS
END tb_mdio_ctrl;
ARCHITECTURE behavior OF tb_mdio_ctrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mdio_ctrl
PORT(
clk : IN std_logic;
rst : IN std_logic;
cnt_5 : IN std_logic;
cnt_23 : IN std_logic;
mdc : OUT std_logic;
mdio_i : IN std_logic;
mdio_o : OUT std_logic;
mdio_t : OUT std_logic;
op : IN std_logic;
addr : IN std_logic_vector(4 downto 0);
data_i : IN std_logic_vector(15 downto 0);
data_o : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic;
kick : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal cnt64 : std_logic_vector(63 downto 0) := ( others => '0' );
signal mdio_i : std_logic := '0';
signal op : std_logic := '0';
signal addr : std_logic_vector(4 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
signal kick : std_logic := '0';
--Outputs
signal mdc : std_logic;
signal mdio_o : std_logic;
signal mdio_t : std_logic;
signal data_o : std_logic_vector(15 downto 0);
signal busy : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mdio_ctrl PORT MAP (
clk => clk,
rst => rst,
cnt_5 => cnt64(5),
cnt_23 => cnt64(8),
mdc => mdc,
mdio_i => mdio_i,
mdio_o => mdio_o,
mdio_t => mdio_t,
op => op,
addr => addr,
data_i => data_i,
data_o => data_o,
busy => busy,
kick => kick
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
cnt_64_p :process
begin
cnt64 <= cnt64 + 8;
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
wait for 5us;
kick <= '1';
wait for clk_period;
kick <= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd | 10 | 299135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:04 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
-- Rev 1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
-- Rev 1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010
-- Rev 1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
-- CDC static timing issue. 2-14-2011
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
--CR 596422
constant allzero : std_logic_vector(127 downto 0) := (others => '0');
--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
----------------------------------------------------------------------------
-- signal Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal selfrefresh_mode_sig : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
signal uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
signal uo_done_cal_sig : std_logic;
signal wait_200us_counter : std_logic_vector(15 downto 0);
signal cke_train_reg : std_logic;
signal wait_200us_done_r1 : std_logic;
signal wait_200us_done_r2 : std_logic;
signal syn1_sys_rst : std_logic;
signal syn2_sys_rst : std_logic;
signal selfrefresh_enter_r1 : std_logic;
signal selfrefresh_enter_r2 : std_logic;
signal selfrefresh_enter_r3 : std_logic;
signal gated_pll_lock : std_logic;
signal soft_cal_selfrefresh_req : std_logic;
signal normal_operation_window : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Assign the output signals with corresponding intermediate signals
uo_done_cal <= uo_done_cal_sig;
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
syn_uiclk_pll_lock <= pll_lock;
end if;
end if;
end process;
-- logic to determine if Memory is SELFREFRESH mode operation or NORMAL mode.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
normal_operation_window <= '1';
elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
normal_operation_window <= '0';
elsif ((selfrefresh_enter_r2 = '0') and (selfrefresh_mode_sig = '0')) then
normal_operation_window <= '1';
else
normal_operation_window <= normal_operation_window;
end if;
end if;
end process;
process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
begin
if (normal_operation_window = '1') then
gated_pll_lock <= pll_lock;
else
gated_pll_lock <= syn_uiclk_pll_lock;
end if;
end process;
-- int_sys_rst will be asserted if pll lose lock during normal operation.
-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
-- reset will not be generated.
int_sys_rst <= sys_rst or not(gated_pll_lock);
-- synchronize the selfrefresh_enter
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
selfrefresh_enter_r1 <= '0';
selfrefresh_enter_r2 <= '0';
selfrefresh_enter_r3 <= '0';
else
selfrefresh_enter_r1 <= selfrefresh_enter;
selfrefresh_enter_r2 <= selfrefresh_enter_r1;
selfrefresh_enter_r3 <= selfrefresh_enter_r2;
end if;
end if;
end process;
-- The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
-- It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
-- This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
soft_cal_selfrefresh_req <= '0';
elsif (selfrefresh_enter_r3 = '1') then
soft_cal_selfrefresh_req <= '1';
elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then
soft_cal_selfrefresh_req <= '0';
else
soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
end if;
end if;
end process;
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
--process(ui_clk)
--begin
--if (ui_clk'event and ui_clk = '1') then
-- syn1_sys_rst <= sys_rst;
-- syn2_sys_rst <= syn1_sys_rst;
--end if;
--end process;
uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
--RST => syn2_sys_rst,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
--PLL_LOCK => pll_lock,
PLL_LOCK => gated_pll_lock,
--SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_REQ => soft_cal_selfrefresh_req, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode_sig, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
selfrefresh_mode_sig <= '0';
-- synthesis translate_off
init_sequence: if (C_SIMULATION = "FALSE") generate
-- synthesis translate_on
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
wait_200us_counter <= (others => '0');
elsif (ui_clk'event and ui_clk = '1') then -- UI_CLK maximum is up to 100 MHz
if (wait_200us_counter(15) = '1') then
wait_200us_counter <= wait_200us_counter;
else
wait_200us_counter <= wait_200us_counter + '1';
end if;
end if;
end process;
-- synthesis translate_off
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
wait_200us_counter <= X"FFFF";
process
begin
report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
wait;
end process;
end generate;
-- synthesis translate_on
gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
process (ui_clk)
begin
-- When wait_200us_[13] and wait_200us_[14] are both asserted,
-- 200 us wait should have been passed.
if (ui_clk'event and ui_clk = '1') then
if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
wait_200us_done_r1 <= '1';
else
wait_200us_done_r1 <= '0';
end if;
wait_200us_done_r2 <= wait_200us_done_r1;
end if;
end process;
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
cke_train_reg <= '0';
elsif (ui_clk'event and ui_clk = '1') then
if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
cke_train_reg <= '1';
elsif (uo_done_cal_sig = '1') then
cke_train_reg <= '0';
end if;
end if;
end process;
cke_train <= cke_train_reg;
end generate;
gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
cke_train <= '0';
end generate;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
selfrefresh_mode <= selfrefresh_mode_sig;
end aarch;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | tb_ctrl_regs.vhd | 1 | 2782 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_ctrl_regs IS
END tb_ctrl_regs;
ARCHITECTURE behavior OF tb_ctrl_regs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl_regs
PORT(
Clk : IN std_logic;
PktIn : IN std_logic;
DataIn : IN std_logic_vector(7 downto 0);
PktOut : OUT std_logic;
DataOut : OUT std_logic_vector(7 downto 0);
Regs : OUT std_logic_vector(79 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut : std_logic;
signal DataOut : std_logic_vector(7 downto 0);
signal Regs : std_logic_vector(79 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl_regs PORT MAP (
Clk => Clk,
PktIn => PktIn,
DataIn => DataIn,
PktOut => PktOut,
DataOut => DataOut,
Regs => Regs
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 200 ns;
PktIn <= '1';
wait for Clk_period * 8;
for i in 1 to 1 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
DataIn <= X"00";
wait for Clk_period * 7;
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
wait;
end process;
END;
| gpl-3.0 |
cretingame/Yarr-fw | syn/xpressk7/ddr3_revA/top_level.vhd | 1 | 18986 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
Port ( ---------------------------------------------------------------------------
-- Xilinx Hard IP Interface
-- . Clock and Resets
pcie_clk_p : in std_logic;
pcie_clk_n : in std_logic;
clk200_n : in STD_LOGIC;
clk200_p : in STD_LOGIC;
rst_n_i : in STD_LOGIC;
sys_rst_n_i : in STD_LOGIC;
-- . Serial I/F
pci_exp_txn : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txn ,
pci_exp_txp : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txp ,
pci_exp_rxn : in std_logic_vector(4-1 downto 0);--input wire [4 -1:0] pci_exp_rxn ,
pci_exp_rxp : in std_logic_vector(4-1 downto 0);
-- . IO
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (2 downto 0);
--front_led_o : out STD_LOGIC_VECTOR (3 downto 0);
-- . DDR3
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
--init_calib_complete : out std_logic;
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end top_level;
architecture Behavioral of top_level is
constant AXI_BUS_WIDTH : integer := 64;
component simple_counter is
Port (
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
COMPONENT pcie_7x_0
PORT (
pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_clk_out : OUT STD_LOGIC;
user_reset_out : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_cfg_req : OUT STD_LOGIC;
tx_err_drop : OUT STD_LOGIC;
s_axis_tx_tready : OUT STD_LOGIC;
s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tx_tlast : IN STD_LOGIC;
s_axis_tx_tvalid : IN STD_LOGIC;
s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rx_tlast : OUT STD_LOGIC;
m_axis_rx_tvalid : OUT STD_LOGIC;
m_axis_rx_tready : IN STD_LOGIC;
m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_pmcsr_pme_en : OUT STD_LOGIC;
cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pmcsr_pme_status : OUT STD_LOGIC;
cfg_received_func_lvl_rst : OUT STD_LOGIC;
cfg_interrupt : IN STD_LOGIC;
cfg_interrupt_rdy : OUT STD_LOGIC;
cfg_interrupt_assert : IN STD_LOGIC;
cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable : OUT STD_LOGIC;
cfg_interrupt_msixenable : OUT STD_LOGIC;
cfg_interrupt_msixfm : OUT STD_LOGIC;
cfg_interrupt_stat : IN STD_LOGIC;
cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_to_turnoff : OUT STD_LOGIC;
cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_bridge_serr_en : OUT STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_pme_int_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
cfg_msg_received_err_cor : OUT STD_LOGIC;
cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
cfg_msg_received_err_fatal : OUT STD_LOGIC;
cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
cfg_msg_received_pm_pme : OUT STD_LOGIC;
cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
cfg_msg_received_assert_int_a : OUT STD_LOGIC;
cfg_msg_received_assert_int_b : OUT STD_LOGIC;
cfg_msg_received_assert_int_c : OUT STD_LOGIC;
cfg_msg_received_assert_int_d : OUT STD_LOGIC;
cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC
);
END COMPONENT;
component app is
Generic(
AXI_BUS_WIDTH : integer := 64;
DMA_MEMORY_SELECTED : string := "DDR3"
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i : in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Clocks
signal sys_clk : STD_LOGIC;
--signal clk200 : STD_LOGIC;
signal aclk : STD_LOGIC;
signal arstn_s : STD_LOGIC;
signal rst_s : STD_LOGIC;
--Wishbone bus
signal usr_led_s : std_logic_vector(3 downto 0);
--signal count_s : STD_LOGIC_VECTOR (28 downto 0);
-- AXI-stream bus to PCIE
signal s_axis_tx_tready_s : STD_LOGIC;
signal s_axis_tx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal s_axis_tx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal s_axis_tx_tlast_s : STD_LOGIC;
signal s_axis_tx_tvalid_s : STD_LOGIC;
signal s_axis_tx_tuser_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal m_axis_rx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal m_axis_rx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal m_axis_rx_tlast_s : STD_LOGIC;
signal m_axis_rx_tvalid_s : STD_LOGIC;
signal m_axis_rx_tready_s : STD_LOGIC;
signal m_axis_rx_tuser_s : STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIE signals
signal user_lnk_up_s : STD_LOGIC;
signal user_app_rdy_s : STD_LOGIC;
signal tx_err_drop_s : STD_LOGIC;
signal cfg_interrupt_s : STD_LOGIC;
signal cfg_interrupt_rdy_s : STD_LOGIC;
signal cfg_interrupt_assert_s : STD_LOGIC;
signal cfg_interrupt_di_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_do_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_mmenable_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal cfg_interrupt_msienable_s : STD_LOGIC;
signal cfg_interrupt_msixenable_s : STD_LOGIC;
signal cfg_interrupt_msixfm_s : STD_LOGIC;
signal cfg_interrupt_stat_s : STD_LOGIC;
signal cfg_pciecap_interrupt_msgnum_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIE ID
signal cfg_bus_number_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_device_number_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal cfg_function_number_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
--PCIE debug
signal cfg_dstatus_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- LVDS input to internal single
-- CLK_IBUFDS : IBUFDS
-- generic map(
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- I => clk200_p,
-- IB => clk200_n,
-- O => clk200
-- );
-- design_1_0: component design_1
-- port map (
-- CLK_IN_D_clk_n(0) => pcie_clk_n,
-- CLK_IN_D_clk_p(0) => pcie_clk_p,
-- IBUF_OUT(0) => sys_clk
-- );
refclk_ibuf : IBUFDS_GTE2
port map(
O => sys_clk,
ODIV2 => open,
I => pcie_clk_p,
IB => pcie_clk_n,
CEB => '0');
rst_s <= not rst_n_i;
arstn_s <= sys_rst_n_i or rst_n_i;
pcie_0 : pcie_7x_0
PORT MAP (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
user_clk_out => aclk,
user_reset_out => open, -- TODO
user_lnk_up => user_lnk_up_s,
user_app_rdy => user_app_rdy_s,
tx_err_drop => tx_err_drop_s,
s_axis_tx_tready => s_axis_tx_tready_s,
s_axis_tx_tdata => s_axis_tx_tdata_s,
s_axis_tx_tkeep => s_axis_tx_tkeep_s,
s_axis_tx_tlast => s_axis_tx_tlast_s,
s_axis_tx_tvalid => s_axis_tx_tvalid_s,
s_axis_tx_tuser => s_axis_tx_tuser_s,
m_axis_rx_tdata => m_axis_rx_tdata_s,
m_axis_rx_tkeep => m_axis_rx_tkeep_s,
m_axis_rx_tlast => m_axis_rx_tlast_s,
m_axis_rx_tvalid => m_axis_rx_tvalid_s,
m_axis_rx_tready => m_axis_rx_tready_s,
m_axis_rx_tuser => m_axis_rx_tuser_s,
cfg_interrupt => cfg_interrupt_s,
cfg_interrupt_rdy => cfg_interrupt_rdy_s,
cfg_interrupt_assert => cfg_interrupt_assert_s,
cfg_interrupt_di => cfg_interrupt_di_s,
cfg_interrupt_do => cfg_interrupt_do_s,
cfg_interrupt_mmenable => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm => cfg_interrupt_msixfm_s,
cfg_interrupt_stat => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum_s,
cfg_dstatus => cfg_dstatus_s,
cfg_bus_number => cfg_bus_number_s,
cfg_device_number => cfg_device_number_s,
cfg_function_number => cfg_function_number_s,
sys_clk => sys_clk,
sys_rst_n => sys_rst_n_i
);
app_0:app
generic map(
AXI_BUS_WIDTH => 64,
DMA_MEMORY_SELECTED => "DDR3"
)
port map(
clk_i => aclk,
sys_clk_n_i => clk200_n,
sys_clk_p_i => clk200_p,
rst_i => rst_s,
user_lnk_up_i => user_lnk_up_s,
user_app_rdy_i => user_app_rdy_s,
-- AXI-Stream bus
m_axis_tx_tready_i => s_axis_tx_tready_s,
m_axis_tx_tdata_o => s_axis_tx_tdata_s,
m_axis_tx_tkeep_o => s_axis_tx_tkeep_s,
m_axis_tx_tlast_o => s_axis_tx_tlast_s,
m_axis_tx_tvalid_o => s_axis_tx_tvalid_s,
m_axis_tx_tuser_o => s_axis_tx_tuser_s,
s_axis_rx_tdata_i => m_axis_rx_tdata_s,
s_axis_rx_tkeep_i => m_axis_rx_tkeep_s,
s_axis_rx_tlast_i => m_axis_rx_tlast_s,
s_axis_rx_tvalid_i => m_axis_rx_tvalid_s,
s_axis_rx_tready_o => m_axis_rx_tready_s,
s_axis_rx_tuser_i => m_axis_rx_tuser_s,
-- PCIe interrupt config
cfg_interrupt_o => cfg_interrupt_s,
cfg_interrupt_rdy_i => cfg_interrupt_rdy_s,
cfg_interrupt_assert_o => cfg_interrupt_assert_s,
cfg_interrupt_di_o => cfg_interrupt_di_s,
cfg_interrupt_do_i => cfg_interrupt_do_s,
cfg_interrupt_mmenable_i => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable_i => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable_i => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm_i => cfg_interrupt_msixfm_s,
cfg_interrupt_stat_o => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum_o => cfg_pciecap_interrupt_msgnum_s,
-- PCIe ID
cfg_bus_number_i => cfg_bus_number_s,
cfg_device_number_i => cfg_device_number_s,
cfg_function_number_i => cfg_function_number_s,
-- PCIe debug
tx_err_drop_i => tx_err_drop_s,
cfg_dstatus_i => cfg_dstatus_s,
--DDR3
ddr3_dq_io => ddr3_dq,
ddr3_dqs_p_io => ddr3_dqs_p,
ddr3_dqs_n_io => ddr3_dqs_n,
--init_calib_complete_o => init_calib_complete,
ddr3_addr_o => ddr3_addr,
ddr3_ba_o => ddr3_ba,
ddr3_ras_n_o => ddr3_ras_n,
ddr3_cas_n_o => ddr3_cas_n,
ddr3_we_n_o => ddr3_we_n,
ddr3_reset_n_o => ddr3_reset_n,
ddr3_ck_p_o => ddr3_ck_p,
ddr3_ck_n_o => ddr3_ck_n,
ddr3_cke_o => ddr3_cke,
ddr3_cs_n_o => ddr3_cs_n,
ddr3_dm_o => ddr3_dm,
ddr3_odt_o => ddr3_odt,
--I/O
usr_sw_i => usr_sw_i,
usr_led_o => usr_led_s,
front_led_o => open--front_led_o
);
usr_led_o <= usr_led_s(2 downto 0);
--m_axis_rx_tready_s <= '1';
end Behavioral;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/write_data_path.vhd | 20 | 9135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | debouncer.vhd | 2 | 1921 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Input debouncer and stabilisation circuit
-- use to make sure inputs from buttons don't jump around
entity debouncer is
port (Clk : in std_logic;
Input : in std_logic;
Output : out std_logic);
end debouncer;
-- Operation:
-- There are two stages of input flop-flops followed by a counter
-- signal must stay high for 128 cycles of @Clk to make @Output
-- go high as well.
-- Output goes low as soon as output of second stage (@Input after
-- two clock cycles) goes low.
architecture Behavioral of debouncer is
signal stage_1, stage_2 : std_logic;
signal counter : std_logic_vector(7 downto 0);
begin
Output <= counter(7);
stage_1 <= Input when RISING_EDGE(Clk);
stage_2 <= stage_1 when RISING_EDGE(Clk);
cnt : process (Clk)
begin
if RISING_EDGE(Clk) then
if stage_2 = '1' and counter(7) = '0' then
counter <= counter + 1;
end if;
if stage_2 = '0' then
counter <= ( others => '0' );
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
maxx04/cam_sim | cam_sim.srcs/sim_1/imports/BMP/sim_tb_bmpread.vhd | 1 | 5719 | -------------------------------------------------------------------------------
-- Title : Testbench BMP Read
-- Project :
-------------------------------------------------------------------------------
-- File : sim_tb_bmpread.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-12-26
-- Platform : ModelSIM
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.sim_bmppack.all;
entity sim_tb_bmpread is
port(
resetn : in std_logic;
pclk : in std_logic;
pixel_data : out std_logic_vector(7 downto 0 );
pixel_out_hsync, pixel_out_vsync, pixel_out_href : out std_logic );
end sim_tb_bmpread;
-------------------------------------------------------------------------------
architecture BMP_to_OV7670 of sim_tb_bmpread is
signal clk : std_logic := '0';
signal ImageWidth, ImageHeight : integer := 0;
signal bit_number : integer := 0;
signal temp_hsync, temp_vsync, temp_href, temp_pixel_clock : std_logic ;
signal pixel_data_temp : std_logic_vector(23 downto 0);
signal data: std_logic_vector(7 downto 0);
signal npixel, nline : integer;
constant VSYNC_Width : integer := 3; --sehe Datenblatt OV 7670
constant VSYNC_for : integer := 17;
constant VSYNC_after : integer := 10;
constant HSYNC_Width : integer := 80;
constant HSYNC_for : integer := 45;
constant HSYNC_after : integer := 19;
constant byte_per_pixel : integer := 3;
begin
assert byte_per_pixel < 4
report " byte_per_pixel to big "
severity failure;
read_file: process
variable px_count, x_count, y_count, line_count, byte_count, bit_number : integer := 0 ;
begin
report "read File...";
ReadFile("test.bmp");
GetWidth(ImageWidth);
GetHeigth(ImageHeight);
if resetn = '1' then
loop EXIT WHEN line_count = (ImageHeight + VSYNC_for + VSYNC_Width + VSYNC_after);
wait until pclk'event and clk = '0'; -- bei negative flanke
temp_pixel_clock <= '0';
-- HSYNC
if (px_count >= 0 and px_count < HSYNC_Width - 1) then
temp_hsync <= '0';
else
temp_hsync <= '1' ;
end if ;
-- HREF
if (px_count >= (HSYNC_for + HSYNC_Width)
and px_count < (HSYNC_for + HSYNC_Width + ImageWidth)
and line_count >= (VSYNC_for + VSYNC_Width)
and line_count < (VSYNC_for + VSYNC_Width + ImageHeight)) then
if (bit_number = 0) then
GetPixel( px_count - (HSYNC_for + HSYNC_Width), line_count - (VSYNC_for + VSYNC_Width), pixel_data_temp);
npixel <= px_count - (HSYNC_for + HSYNC_Width);
nline <= line_count - (VSYNC_for + VSYNC_Width);
end if;
temp_href <= '1';
else
pixel_data_temp <= (others => '0');
temp_href <= '0';
end if ;
-- vsync control
if line_count < VSYNC_Width then -- nach 510 lines line_count soll auf 0
temp_vsync <= '1' ;
else
temp_vsync <= '0' ;
end if ;
if (px_count = (HSYNC_for + HSYNC_Width + ImageWidth - 1 + HSYNC_after) ) then -- neue line
px_count := 0 ; -- abnullen
bit_number := 0;
if (line_count > ( VSYNC_for + VSYNC_Width + ImageHeight - 1 + VSYNC_after)) then -- neues Frame
line_count := 0; -- abnullen
else
line_count := line_count + 1 ;
end if;
end if ;
if line_count >= (VSYNC_for + VSYNC_Width + ImageHeight - 1 + VSYNC_after) then -- volle frame
line_count := 0;
px_count := 0;
bit_number := 0;
end if;
wait until pclk'event and pclk = '1'; -- bei positive flanke
temp_pixel_clock <= '1';
case bit_number is
when 0 =>
data <= pixel_data_temp(23 downto 16);
when 1 =>
data <= pixel_data_temp(15 downto 8);
when 2 =>
data <= pixel_data_temp(7 downto 0);
end case;
if ( bit_number = byte_per_pixel - 1) then -- pixel ausgabe
px_count := px_count + 1;
bit_number := 0;
else
bit_number := bit_number + 1;
end if;
end loop;
wait; -- one shot at time zero,
end if; -- reset
end process read_file;
clk_domain_latch : process(pclk, resetn)
begin
if resetn = '0' then
pixel_out_hsync <= '0' ;
pixel_out_vsync <= '1' ;
pixel_out_href <= '0';
pixel_data <= (others => '0');
elsif falling_edge(pclk) then
-- pixel_out_clk <= temp_pixel_clock ;
pixel_out_href <= temp_href;
pixel_out_hsync <= temp_hsync ;
pixel_out_vsync <= temp_vsync ;
pixel_data <= data ;
end if ;
end process ;
end BMP_to_OV7670;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/rtl/memc3_infrastructure.vhd | 6 | 12267 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/kintex7/app.vhd | 1 | 56713 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/18/2016 01:10:56 PM
-- Design Name:
-- Module Name: app - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.app_pkg.all;
entity app is
Generic(
AXI_BUS_WIDTH : integer := 64;
axis_data_width_c : integer := 64;
axis_rx_tkeep_width_c : integer := 64/8;
axis_rx_tuser_width_c : integer := 22;
wb_address_width_c : integer := 32;
wb_data_width_c : integer := 32;
address_mask_c : STD_LOGIC_VECTOR(32-1 downto 0) := X"000FFFFF";
DMA_MEMORY_SELECTED : string := "DDR3" -- DDR3, BRAM, DEMUX
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i: in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end app;
architecture Behavioral of app is
constant DEBUG_C : std_logic_vector(5 downto 0) := "000000";
signal rst_n_s : std_logic;
signal count_s : STD_LOGIC_VECTOR (28 downto 0);
signal gray_count_s : STD_LOGIC_VECTOR (28 downto 0);
signal ddr_count_s : STD_LOGIC_VECTOR (28 downto 0);
signal eop_s : std_logic; -- Arbiter end of operation
signal cfg_interrupt_s : std_logic;
signal pcie_id_s : std_logic_vector (15 downto 0); -- Completer/Requester ID
---------------------------------------------------------
-- debug signals
signal wbm_states_ds : STD_LOGIC_VECTOR(3 downto 0);
signal wbm_op_ds : STD_LOGIC_VECTOR(2 downto 0);
signal wbm_header_type_ds : STD_LOGIC;
signal wbm_payload_length_ds : STD_LOGIC_VECTOR(9 downto 0);
signal wbm_address_ds : STD_LOGIC_VECTOR(31 downto 0);
signal dma_ctrl_current_state_ds : std_logic_vector (2 downto 0);
signal dma_ctrl_ds : std_logic_vector(31 downto 0);
signal dma_stat_ds : std_logic_vector(31 downto 0);
signal dma_attrib_ds : std_logic_vector(31 downto 0);
---------------------------------------------------------
-- CSR Wishbone bus
signal wb_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_cyc_s : STD_LOGIC;
signal wb_sel_s : STD_LOGIC_VECTOR (4 - 1 downto 0);
signal wb_stb_s : STD_LOGIC;
signal wb_we_s : STD_LOGIC;
signal wb_ack_s : STD_LOGIC;
signal wb_stall_s : std_logic; -- Stall
signal wb_err_s : std_logic; -- Error
signal wb_rty_s : std_logic; -- Retry
signal wb_int_s : std_logic; -- Interrupt
signal wb_dma_ctrl_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dma_ctrl_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dma_ctrl_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dma_ctrl_cyc_s : STD_LOGIC;
--signal wb_dma_ctrl_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_dma_ctrl_stb_s : STD_LOGIC;
signal wb_dma_ctrl_we_s : STD_LOGIC;
signal wb_dma_ctrl_ack_s : STD_LOGIC;
signal wb_mem_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_mem_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_mem_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_mem_cyc_s : STD_LOGIC;
--signal wb_mem_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_mem_stb_s : STD_LOGIC;
signal wb_mem_we_s : STD_LOGIC;
signal wb_mem_ack_s : STD_LOGIC;
signal wb_dbg_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dbg_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dbg_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dbg_cyc_s : std_logic;
signal wb_dbg_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_dbg_stb_s : STD_LOGIC;
signal wb_dbg_we_s : STD_LOGIC;
signal wb_dbg_ack_s : STD_LOGIC;
---------------------------------------------------------
-- Slave AXI-Stream from arbiter to pcie_tx
signal s_axis_rx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tuser_s : STD_LOGIC_VECTOR (21 downto 0);
signal s_axis_rx_tlast_s : STD_LOGIC;
signal s_axis_rx_tvalid_s :STD_LOGIC;
signal s_axis_rx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- Master AXI-Stream pcie_rx to wishbone master
signal m_axis_tx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal m_axis_tx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal m_axis_tx_tuser_s : STD_LOGIC_VECTOR (3 downto 0);
signal m_axis_tx_tlast_s : STD_LOGIC;
signal m_axis_tx_tvalid_s : STD_LOGIC;
signal m_axis_tx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- From Wishbone master (wbm) to L2P DMA
signal pd_wbm_address_s : STD_LOGIC_VECTOR(63 downto 0);
signal pd_wbm_data_s : STD_LOGIC_VECTOR(31 downto 0);
signal p2l_wbm_rdy_s : std_logic;
signal pd_pdm_data_valid_w_s : std_logic_vector(1 downto 0);
signal pd_wbm_valid_s : std_logic;
signal pd_wbm_hdr_rid_s : std_logic_vector(15 downto 0); -- Requester ID
signal pd_wbm_hdr_tag_s : std_logic_vector(7 downto 0);
signal pd_wbm_target_mrd_s : std_logic; -- Target memory read
signal pd_wbm_target_mwr_s : std_logic;
signal wbm_pd_ready_s : std_logic;
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_header_type_s : STD_LOGIC;
signal pd_payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
---------------------------------------------------------
-- From Wishbone master (wbm) to L2P DMA
signal pd_pdm_data_valid_s : STD_LOGIC;
signal pd_pdm_data_last_s : STD_LOGIC;
signal pd_pdm_data_s : STD_LOGIC_VECTOR(axis_data_width_c - 1 downto 0);
signal pd_pdm_keep_s : std_logic_vector(7 downto 0);
signal p2l_dma_rdy_s : std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
signal wbm_arb_tdata_s : std_logic_vector (axis_data_width_c - 1 downto 0);
signal wbm_arb_tkeep_s : std_logic_vector (axis_data_width_c/8 - 1 downto 0);
signal wbm_arb_tlast_s : std_logic;
signal wbm_arb_tvalid_s : std_logic;
signal wbm_arb_req_s : std_logic;
signal wbm_arb_tready_s : std_logic;
signal dma_ctrl_irq_s : std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
signal dma_ctrl_carrier_addr_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_h_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_l_s : std_logic_vector(31 downto 0);
signal dma_ctrl_len_s : std_logic_vector(31 downto 0);
signal dma_ctrl_start_l2p_s : std_logic; -- To the L2P DMA master
signal dma_ctrl_start_p2l_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_start_next_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_byte_swap_s : std_logic_vector(1 downto 0);
signal dma_ctrl_abort_s : std_logic;
signal dma_ctrl_done_s : std_logic;
signal dma_ctrl_error_s : std_logic;
signal dma_ctrl_l2p_done_s : std_logic;
signal dma_ctrl_l2p_error_s : std_logic;
signal dma_ctrl_p2l_done_s : std_logic;
signal dma_ctrl_p2l_error_s : std_logic;
---------------------------------------------------------
-- From P2L DMA master
signal next_item_carrier_addr_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_h_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_l_s : std_logic_vector(31 downto 0);
signal next_item_len_s : std_logic_vector(31 downto 0);
signal next_item_next_l_s : std_logic_vector(31 downto 0);
signal next_item_next_h_s : std_logic_vector(31 downto 0);
signal next_item_attrib_s : std_logic_vector(31 downto 0);
signal next_item_valid_s : std_logic;
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
signal pdm_arb_tvalid_s : std_logic; -- Read completion signals
signal pdm_arb_tlast_s : std_logic; -- Toward the arbiter
signal pdm_arb_tdata_s : std_logic_vector(63 downto 0);
signal pdm_arb_tkeep_s : std_logic_vector(7 downto 0);
signal pdm_arb_req_s : std_logic;
signal pdm_arb_tready_s : std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
signal p2l_dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal p2l_dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal p2l_dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal p2l_dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal p2l_dma_cyc_s : std_logic; -- Read or write cycle
signal p2l_dma_stb_s : std_logic; -- Read or write strobe
signal p2l_dma_we_s : std_logic; -- Write
signal p2l_dma_ack_s : std_logic; -- Acknowledge
signal p2l_dma_stall_s : std_logic; -- for pipelined Wishbone
signal l2p_dma_adr_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_s2m_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_m2s_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_sel_s : std_logic_vector(3 downto 0);
signal l2p_dma_cyc_s : std_logic;
signal l2p_dma_stb_s : std_logic;
signal l2p_dma_we_s : std_logic;
signal l2p_dma_ack_s : std_logic;
signal l2p_dma_stall_s : std_logic;
signal dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal dma_cyc_s : std_logic; -- Read or write cycle
signal dma_stb_s : std_logic; -- Read or write strobe
signal dma_we_s : std_logic; -- Write
signal dma_ack_s : std_logic; -- Acknowledge
signal dma_stall_s : std_logic; -- for pipelined Wishbone
signal l2p_current_state_ds : std_logic_vector (2 downto 0);
signal l2p_data_cnt_ds : unsigned(12 downto 0);
signal l2p_len_cnt_ds : unsigned(12 downto 0);
signal l2p_timeout_cnt_ds : unsigned(12 downto 0);
signal wb_timeout_cnt_ds : unsigned(12 downto 0);
-- Data FIFO
signal data_fifo_rd_ds : std_logic;
signal data_fifo_wr_ds : std_logic;
signal data_fifo_empty_ds : std_logic;
signal data_fifo_full_ds : std_logic;
signal data_fifo_dout_ds : std_logic_vector(axis_data_width_c-1 downto 0);
signal data_fifo_din_ds : std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
signal addr_fifo_rd_ds : std_logic;
signal addr_fifo_wr_ds : std_logic;
signal addr_fifo_empty_ds : std_logic;
signal addr_fifo_full_ds : std_logic;
signal addr_fifo_dout_ds : std_logic_vector(64-1 downto 0);
signal addr_fifo_din_ds : std_logic_vector(axis_data_width_c-1 downto 0);
--constant cyc_nb_exp_c : integer := 2;
--constant cyc_nb_c : integer := 2**cyc_nb_exp_c;
--type ram_dma_data_bus is array (cyc_nb_c-1 downto 0) of std_logic_vector(64-1 downto 0);
signal dummyram_sel_s : std_logic;
signal ddr3ram_sel_s : std_logic;
signal dummyaddress_sel_s : std_logic;
signal dummydeadbeef_sel_s : std_logic;
---------------------------------------------------------
-- From DMA master to Dummy RAM
signal dma_bram_adr_s : std_logic_vector(32-1 downto 0); -- Adress
signal dma_bram_dat_s2m_s : std_logic_vector(64-1 downto 0); -- Data in
signal dma_bram_dat_m2s_s : std_logic_vector(64-1 downto 0); -- Data out
signal dma_bram_sel_s : std_logic_vector(8-1 downto 0); -- Byte select
signal dma_bram_cyc_s : std_logic; -- Read or write cycle
signal dma_bram_stb_s : std_logic; -- Read or write strobe
signal dma_bram_we_s : std_logic; -- Write
signal dma_bram_ack_s : std_logic; -- Acknowledge
signal dma_bram_stall_s : std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- From DMA master to DDR3 control
signal dma_ddr_addr_s : std_logic_vector(32-1 downto 0); -- Adress
signal dma_ddr_dat_s2m_s : std_logic_vector(64-1 downto 0); -- Data in
signal dma_ddr_dat_m2s_s : std_logic_vector(64-1 downto 0); -- Data out
signal dma_ddr_sel_s : std_logic_vector(8-1 downto 0); -- Byte select
signal dma_ddr_cyc_s : std_logic; -- Read or write cycle
signal dma_ddr_stb_s : std_logic; -- Read or write strobe
signal dma_ddr_we_s : std_logic; -- Write
signal dma_ddr_ack_s : std_logic; -- Acknowledge
signal dma_ddr_stall_s : std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- DDR3 control to output
signal ddr3_dq_s : std_logic_vector(63 downto 0);
signal ddr3_dqs_p_s : std_logic_vector(7 downto 0);
signal ddr3_dqs_n_s : std_logic_vector(7 downto 0);
signal init_calib_complete_s : std_logic;
signal ddr3_addr_s : std_logic_vector(14 downto 0);
signal ddr3_ba_s : std_logic_vector(2 downto 0);
signal ddr3_ras_n_s : std_logic;
signal ddr3_cas_n_s : std_logic;
signal ddr3_we_n_s : std_logic;
signal ddr3_reset_n_s : std_logic;
signal ddr3_ck_p_s : std_logic_vector(0 downto 0);
signal ddr3_ck_n_s : std_logic_vector(0 downto 0);
signal ddr3_cke_s : std_logic_vector(0 downto 0);
signal ddr3_cs_n_s : std_logic_vector(0 downto 0);
signal ddr3_dm_s : std_logic_vector(7 downto 0);
signal ddr3_odt_s : std_logic_vector(0 downto 0);
---------------------------------------------------------
-- DDR3 control to MIG
signal ddr_app_addr_s : std_logic_vector(28 downto 0);
signal ddr_app_cmd_s : std_logic_vector(2 downto 0);
signal ddr_app_cmd_en_s : std_logic;
signal ddr_app_wdf_data_s : std_logic_vector(511 downto 0);
signal ddr_app_wdf_end_s : std_logic;
signal ddr_app_wdf_mask_s : std_logic_vector(63 downto 0);
signal ddr_app_wdf_wren_s : std_logic;
signal ddr_app_rd_data_s : std_logic_vector(511 downto 0);
signal ddr_app_rd_data_end_s : std_logic;
signal ddr_app_rd_data_valid_s : std_logic;
signal ddr_app_rdy_s : std_logic;
signal ddr_app_wdf_rdy_s : std_logic;
signal ddr_app_ui_clk_s : std_logic;
signal ddr_app_ui_clk_sync_rst_s : std_logic;
----------------------------------------------------------------------------
-- DDR3 Debug signalss
signal ddr_rd_fifo_full_ds : std_logic_vector(1 downto 0);
signal ddr_rd_fifo_empty_ds : std_logic_vector(1 downto 0);
signal ddr_rd_fifo_rd_ds : std_logic_vector(1 downto 0);
signal ddr_rd_mask_rd_data_count_ds : std_logic_vector(3 downto 0);
signal ddr_rd_data_rd_data_count_ds : std_logic_vector(3 downto 0);
signal ddr_wb_rd_mask_dout_ds : std_logic_vector(7 downto 0);
signal ddr_wb_rd_mask_addr_dout_ds : std_logic_vector(29-1 downto 0);
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
signal ldm_arb_tdata_s : std_logic_vector (axis_data_width_c - 1 downto 0);
signal ldm_arb_tkeep_s : std_logic_vector (axis_data_width_c/8 - 1 downto 0);
signal ldm_arb_tlast_s : std_logic;
signal ldm_arb_tvalid_s : std_logic;
signal ldm_arb_tready_s : std_logic;
signal ldm_arb_req_s : std_logic;
--signal arb_ldm_gnt_s : std_logic;
begin
rst_n_s <= not rst_i;
s_axis_rx_tdata_s <= s_axis_rx_tdata_i;
s_axis_rx_tkeep_s <= s_axis_rx_tkeep_i;
s_axis_rx_tlast_s <= s_axis_rx_tlast_i;
s_axis_rx_tready_o <= s_axis_rx_tready_s;
s_axis_rx_tuser_s <= s_axis_rx_tuser_i;
s_axis_rx_tvalid_s <= s_axis_rx_tvalid_i;
-- Master AXI-Stream
m_axis_tx_tdata_o <= m_axis_tx_tdata_s;
m_axis_tx_tkeep_o <= m_axis_tx_tkeep_s;
m_axis_tx_tuser_o <= m_axis_tx_tuser_s;
m_axis_tx_tlast_o <= m_axis_tx_tlast_s;
m_axis_tx_tvalid_o <= m_axis_tx_tvalid_s;
m_axis_tx_tready_s <= m_axis_tx_tready_i;
cfg_interrupt_assert_o <= '0';
cfg_interrupt_di_o <= (others => '0');
cfg_interrupt_stat_o <= '0';
cfg_pciecap_interrupt_msgnum_o <= (others => '0');
cfg_interrupt_o <= cfg_interrupt_s;
pcie_id_s <= cfg_bus_number_i & cfg_device_number_i & cfg_function_number_i;
wbm_pd_ready_s <= p2l_wbm_rdy_s and p2l_dma_rdy_s;
interrupt_p : process(rst_i,clk_i)
begin
if (rst_i = '1') then
cfg_interrupt_s <= '0';
elsif(clk_i'event and clk_i = '1') then
cfg_interrupt_s <= cfg_interrupt_s;
if (cfg_interrupt_rdy_i = '1') then
cfg_interrupt_s <= '0';
end if;
if (dma_ctrl_irq_s /= "00") then
cfg_interrupt_s <= '1';
end if;
end if;
end process interrupt_p;
cnt:simple_counter
port map(
enable_i => dma_ctrl_irq_s(0),
rst_i => rst_i,
clk_i => clk_i,
count_o => count_s,
gray_count_o => gray_count_s
);
cnt_sync:m_clk_sync
Generic map(
data_width_g => 29
)
Port map(
rst0_i => rst_i,
rst1_i => ddr_app_ui_clk_sync_rst_s,
clk0_i => clk_i,
clk1_i => ddr_app_ui_clk_s,
data0_i => count_s,
data1_o => ddr_count_s
);
p2l_dec_comp:p2l_decoder
port map(
clk_i => clk_i,
rst_i => rst_i,
-- Slave AXI-Stream
s_axis_rx_tdata_i => s_axis_rx_tdata_s,
s_axis_rx_tkeep_i => s_axis_rx_tkeep_s,
s_axis_rx_tlast_i => s_axis_rx_tlast_s,
s_axis_rx_tready_o => s_axis_rx_tready_s,
s_axis_rx_tuser_i => s_axis_rx_tuser_s,
s_axis_rx_tvalid_i => s_axis_rx_tvalid_s,
-- To the wishbone master
pd_wbm_address_o => pd_wbm_address_s,
pd_wbm_data_o => pd_wbm_data_s,
pd_wbm_valid_o => pd_wbm_valid_s,
pd_wbm_hdr_rid_o => pd_wbm_hdr_rid_s,
pd_wbm_hdr_tag_o => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_o => pd_wbm_target_mrd_s,
pd_wbm_target_mwr_o => pd_wbm_target_mwr_s,
wbm_pd_ready_i => wbm_pd_ready_s,
pd_op_o => pd_op_s,
pd_header_type_o => pd_header_type_s,
pd_payload_length_o => pd_payload_length_s,
-- L2P DMA
pd_pdm_data_valid_o => pd_pdm_data_valid_s,
pd_pdm_data_valid_w_o => pd_pdm_data_valid_w_s,
pd_pdm_data_last_o => pd_pdm_data_last_s,
pd_pdm_keep_o => pd_pdm_keep_s,
pd_pdm_data_o => pd_pdm_data_s
);
wb32:wbmaster32
generic map (
g_ACK_TIMEOUT => 100 -- Wishbone ACK timeout (in wb_clk cycles)
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i => pd_wbm_valid_s, -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i => pd_wbm_hdr_rid_s, -- Requester ID
pd_wbm_hdr_cid_i => pcie_id_s, --X"0100", -- Completer ID
pd_wbm_hdr_tag_i => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_i => pd_wbm_target_mrd_s, -- Target memory read
pd_wbm_target_mwr_i => pd_wbm_target_mwr_s, -- Target memory write
--
-- Address
pd_wbm_addr_start_i => pd_wbm_valid_s, -- Address strobe
pd_wbm_addr_i => pd_wbm_address_s(31 downto 0),-- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i => pd_wbm_valid_s, -- Indicates Data is valid
--pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i => pd_wbm_data_s, -- Data
--pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o => open,-- Ready to accept target write
p2l_rdy_o => p2l_wbm_rdy_s,--wbm_pd_ready_s, -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i => "11",-- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_tdata_o => wbm_arb_tdata_s,
wbm_arb_tkeep_o => wbm_arb_tkeep_s,
--wbm_arb_tuser_o => wbm_arb_tuser_s,
wbm_arb_tlast_o => wbm_arb_tlast_s,
wbm_arb_tvalid_o => wbm_arb_tvalid_s,
wbm_arb_tready_i => wbm_arb_tready_s,
wbm_arb_req_o => wbm_arb_req_s,
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i => clk_i, -- Wishbone bus clock
wb_adr_o => wb_adr_s(30 downto 0),-- Address
wb_dat_o => wb_dat_m2s_s,-- Data out
wb_sel_o => wb_sel_s, -- Byte select
wb_stb_o => wb_stb_s, -- Strobe
wb_we_o => wb_we_s, -- Write
wb_cyc_o => wb_cyc_s, -- Cycle
wb_dat_i => wb_dat_s2m_s,-- Data in
wb_ack_i => wb_ack_s, -- Acknowledge
wb_stall_i => wb_stall_s, -- Stall
wb_err_i => wb_err_s, -- Error
wb_rty_i => wb_rty_s, -- Retry
wb_int_i => wb_int_s -- Interrupt
);
wb_stall_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
wb_int_s <= '0';
wb_dma_ctrl_adr_s <= wb_adr_s(31 downto 0);
wb_dma_ctrl_dat_m2s_s <= wb_dat_m2s_s;
wb_dma_ctrl_stb_s <= wb_stb_s;
wb_dma_ctrl_we_s <= wb_we_s;
wb_dbg_adr_s <= wb_adr_s(31 downto 0);
wb_dbg_dat_m2s_s <= wb_dat_m2s_s;
wb_dbg_stb_s <= wb_stb_s;
wb_dbg_we_s <= wb_we_s;
wb_dbg_sel_s <= (others => '1');
wb_mem_adr_s <= wb_adr_s(31 downto 0);
wb_mem_dat_m2s_s <= wb_dat_m2s_s;
wb_mem_stb_s <= wb_stb_s;
wb_mem_we_s <= wb_we_s;
-- CSR Wishbone adress demux
process(wb_adr_s,wb_cyc_s,wb_mem_cyc_s,wb_cyc_s,wb_dma_ctrl_dat_s2m_s,wb_dma_ctrl_ack_s,wb_mem_dat_s2m_s,wb_mem_ack_s,wb_dbg_dat_s2m_s,wb_dbg_ack_s)
begin
if wb_adr_s(31 downto 4) = X"0000000" then
wb_dma_ctrl_cyc_s <= wb_cyc_s;
wb_dbg_cyc_s <= '0';
wb_mem_cyc_s <= '0';
wb_dat_s2m_s <= wb_dma_ctrl_dat_s2m_s;
wb_ack_s <= wb_dma_ctrl_ack_s;
elsif wb_adr_s(31 downto 4) = X"0000001" then
wb_dma_ctrl_cyc_s <= '0';
wb_dbg_cyc_s <= wb_cyc_s;
wb_mem_cyc_s <= '0';
wb_dat_s2m_s <= wb_dbg_dat_s2m_s;
wb_ack_s <= wb_dbg_ack_s;
else
wb_dma_ctrl_cyc_s <= '0';
wb_dbg_cyc_s <= '0';
wb_mem_cyc_s <= wb_cyc_s;
wb_dat_s2m_s <= wb_mem_dat_s2m_s;
wb_ack_s <= wb_mem_ack_s;
end if;
end process;
csr_ram:bram_wbs32
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => wb_mem_adr_s(5 - 1 downto 0),
--wb_dat_i(63 downto 32) => X"00000000",
wb_dat_i => wb_mem_dat_m2s_s,
wb_we_i => wb_mem_we_s,
wb_stb_i => wb_mem_stb_s,
wb_cyc_i => wb_mem_cyc_s,
wb_lock_i => wb_mem_stb_s,
-- Wishbone Slave out
--wb_dat_o(63 downto 32) => wb_null,--open,
wb_dat_o => wb_mem_dat_s2m_s,
wb_ack_o => wb_mem_ack_s
);
dma_ctrl:dma_controller
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o => dma_ctrl_irq_s,
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_o => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_o => dma_ctrl_host_addr_l_s,
dma_ctrl_len_o => dma_ctrl_len_s,
dma_ctrl_start_l2p_o => dma_ctrl_start_l2p_s, -- To the L2P DMA master
dma_ctrl_start_p2l_o => dma_ctrl_start_p2l_s, -- To the P2L DMA master
dma_ctrl_start_next_o => dma_ctrl_start_next_s, -- To the P2L DMA master
dma_ctrl_byte_swap_o => dma_ctrl_byte_swap_s,
dma_ctrl_abort_o => dma_ctrl_abort_s,
dma_ctrl_done_i => dma_ctrl_done_s,
dma_ctrl_error_i => dma_ctrl_error_s,
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i => next_item_carrier_addr_s,
next_item_host_addr_h_i => next_item_host_addr_h_s,
next_item_host_addr_l_i => next_item_host_addr_l_s,
next_item_len_i => next_item_len_s,
next_item_next_l_i => next_item_next_l_s,
next_item_next_h_i => next_item_next_h_s,
next_item_attrib_i => next_item_attrib_s,
next_item_valid_i => next_item_valid_s,
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i => clk_i, -- Bus clock
wb_adr_i => wb_dma_ctrl_adr_s(3 downto 0), -- Adress
wb_dat_o => wb_dma_ctrl_dat_s2m_s, -- Data in
wb_dat_i => wb_dma_ctrl_dat_m2s_s, -- Data out
wb_sel_i => "1111", -- Byte select
wb_cyc_i => wb_dma_ctrl_cyc_s, -- Read or write cycle
wb_stb_i => wb_dma_ctrl_stb_s, -- Read or write strobe
wb_we_i => wb_dma_ctrl_we_s, -- Write
wb_ack_o => wb_dma_ctrl_ack_s, -- Acknowledge
dma_ctrl_current_state_do => dma_ctrl_current_state_ds,
dma_ctrl_do => dma_ctrl_ds,
dma_stat_do => dma_stat_ds,
dma_attrib_do => dma_attrib_ds
);
-- Status signals from DMA masters
dma_ctrl_done_s <= dma_ctrl_l2p_done_s or dma_ctrl_p2l_done_s;
dma_ctrl_error_s <= dma_ctrl_l2p_error_s or dma_ctrl_p2l_error_s;
dbg_reg_comp:debugregisters
Port map(
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => wb_dbg_adr_s(3 downto 0),
wb_dat_i => wb_dbg_dat_m2s_s,
wb_we_i => wb_dbg_we_s,
wb_stb_i => wb_dbg_stb_s,
wb_cyc_i => wb_dbg_cyc_s,
-- Wishbone Slave out
wb_dat_o => wb_dbg_dat_s2m_s,
wb_ack_o => wb_dbg_ack_s,
-- input/ouput
dummyram_sel_o => dummyram_sel_s,
ddr3ram_sel_o => ddr3ram_sel_s,
dummyaddress_sel_o => dummyaddress_sel_s,
dummydeadbeef_sel_o => dummydeadbeef_sel_s,
usr_led_o => usr_led_o,
usr_sw_i => usr_sw_i--,
--ddr_init_calib_complete_i => init_calib_complete_s
);
p2l_dma:p2l_dma_master
generic map (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP => false
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_p2l_i => dma_ctrl_start_p2l_s,
dma_ctrl_start_next_i => dma_ctrl_start_next_s,
dma_ctrl_done_o => dma_ctrl_p2l_done_s,
dma_ctrl_error_o => dma_ctrl_p2l_error_s,
dma_ctrl_byte_swap_i => "111",
dma_ctrl_abort_i => dma_ctrl_abort_s,
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_master_cpld_i => '1', -- Master read completion with data
pd_pdm_master_cpln_i => '0', -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i => pd_pdm_data_valid_s, -- Indicates Data is valid
pd_pdm_data_valid_w_i => pd_pdm_data_valid_w_s,
pd_pdm_data_last_i => pd_pdm_data_last_s, -- Indicates end of the packet
pd_pdm_data_i => pd_pdm_data_s, -- Data
pd_pdm_be_i => pd_pdm_keep_s, -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o => p2l_dma_rdy_s, -- De-asserted to pause transfer already in progress
rx_error_o => open, -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o => pdm_arb_tvalid_s, -- Read completion signals
pdm_arb_tlast_o => pdm_arb_tlast_s, -- Toward the arbiter
pdm_arb_tdata_o => pdm_arb_tdata_s,
pdm_arb_tkeep_o => pdm_arb_tkeep_s,
pdm_arb_req_o => pdm_arb_req_s,
arb_pdm_gnt_i => pdm_arb_tready_s,
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i => clk_i, -- Bus clock
p2l_dma_adr_o => p2l_dma_adr_s, -- Adress
p2l_dma_dat_i => p2l_dma_dat_s2m_s, -- Data in
p2l_dma_dat_o => p2l_dma_dat_m2s_s, -- Data out
p2l_dma_sel_o => p2l_dma_sel_s, -- Byte select
p2l_dma_cyc_o => p2l_dma_cyc_s, -- Read or write cycle
p2l_dma_stb_o => p2l_dma_stb_s, -- Read or write strobe
p2l_dma_we_o => p2l_dma_we_s, -- Write
p2l_dma_ack_i => p2l_dma_ack_s, -- Acknowledge
p2l_dma_stall_i => p2l_dma_stall_s, -- for pipelined Wishbone
l2p_dma_cyc_i => l2p_dma_cyc_s, -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o => next_item_carrier_addr_s,
next_item_host_addr_h_o => next_item_host_addr_h_s,
next_item_host_addr_l_o => next_item_host_addr_l_s,
next_item_len_o => next_item_len_s,
next_item_next_l_o => next_item_next_l_s,
next_item_next_h_o => next_item_next_h_s,
next_item_attrib_o => next_item_attrib_s,
next_item_valid_o => next_item_valid_s
);
-----------------------------------------------------------------------------
-- L2P DMA master
-----------------------------------------------------------------------------
--l2p_dma_stall_s <= '0';
l2p_dma : l2p_dma_master
port map
(
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_l2p_i => dma_ctrl_start_l2p_s,
dma_ctrl_done_o => dma_ctrl_l2p_done_s,
dma_ctrl_error_o => dma_ctrl_l2p_error_s,
dma_ctrl_byte_swap_i => "000", --TODO
dma_ctrl_abort_i => dma_ctrl_abort_s,
ldm_arb_tvalid_o => ldm_arb_tvalid_s,
ldm_arb_tlast_o => ldm_arb_tlast_s,
ldm_arb_tdata_o => ldm_arb_tdata_s,
ldm_arb_tkeep_o => ldm_arb_tkeep_s,
ldm_arb_req_o => ldm_arb_req_s,
arb_ldm_gnt_i => ldm_arb_tready_s,
l2p_edb_o => open,
ldm_arb_tready_i => ldm_arb_tready_s,
l2p_rdy_i => '1',
tx_error_i => '0',
l2p_dma_clk_i => clk_i,
l2p_dma_adr_o => l2p_dma_adr_s,
l2p_dma_dat_i => l2p_dma_dat_s2m_s,
l2p_dma_dat_o => l2p_dma_dat_m2s_s,
l2p_dma_sel_o => l2p_dma_sel_s,
l2p_dma_cyc_o => l2p_dma_cyc_s,
l2p_dma_stb_o => l2p_dma_stb_s,
l2p_dma_we_o => l2p_dma_we_s,
l2p_dma_ack_i => l2p_dma_ack_s,
l2p_dma_stall_i => l2p_dma_stall_s,
p2l_dma_cyc_i => p2l_dma_cyc_s,
--DMA Debug
l2p_current_state_do => l2p_current_state_ds,
l2p_data_cnt_do => l2p_data_cnt_ds,
l2p_len_cnt_do => l2p_len_cnt_ds,
l2p_timeout_cnt_do => l2p_timeout_cnt_ds,
wb_timeout_cnt_do => wb_timeout_cnt_ds,
-- Data FIFO
data_fifo_rd_do => data_fifo_rd_ds,
data_fifo_wr_do => data_fifo_wr_ds,
data_fifo_empty_do => data_fifo_empty_ds,
data_fifo_full_do => data_fifo_full_ds,
data_fifo_dout_do => data_fifo_dout_ds,
data_fifo_din_do => data_fifo_din_ds,
-- Addr FIFO
addr_fifo_rd_do => addr_fifo_rd_ds,
addr_fifo_wr_do => addr_fifo_wr_ds,
addr_fifo_empty_do => addr_fifo_empty_ds,
addr_fifo_full_do => addr_fifo_full_ds,
addr_fifo_dout_do => addr_fifo_dout_ds,
addr_fifo_din_do => addr_fifo_din_ds
);
arbiter:l2p_arbiter
generic map(
axis_data_width_c => axis_data_width_c
)
port map(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i => wbm_arb_tdata_s,
wbm_arb_tkeep_i => wbm_arb_tkeep_s,
wbm_arb_tlast_i => wbm_arb_tlast_s,
wbm_arb_tvalid_i => wbm_arb_tvalid_s,
wbm_arb_req_i => wbm_arb_req_s,
wbm_arb_tready_o => wbm_arb_tready_s,
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i => pdm_arb_tdata_s,
pdm_arb_tkeep_i => pdm_arb_tkeep_s,
pdm_arb_tlast_i => pdm_arb_tlast_s,
pdm_arb_tvalid_i => pdm_arb_tvalid_s,
pdm_arb_req_i => pdm_arb_req_s,
pdm_arb_tready_o => pdm_arb_tready_s,
arb_pdm_gnt_o => open,
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i => ldm_arb_tdata_s,
ldm_arb_tkeep_i => ldm_arb_tkeep_s,
ldm_arb_tlast_i => ldm_arb_tlast_s,
ldm_arb_tvalid_i => ldm_arb_tvalid_s,
ldm_arb_req_i => ldm_arb_req_s,
ldm_arb_tready_o => ldm_arb_tready_s,
arb_ldm_gnt_o => open,
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o => m_axis_tx_tdata_s,
axis_tx_tkeep_o => m_axis_tx_tkeep_s,
axis_tx_tuser_o => m_axis_tx_tuser_s,
axis_tx_tlast_o => m_axis_tx_tlast_s,
axis_tx_tvalid_o => m_axis_tx_tvalid_s,
axis_tx_tready_i => m_axis_tx_tready_s,
eop_do => eop_s
);
dma_bram_gen : if DMA_MEMORY_SELECTED = "DEMUX" or DMA_MEMORY_SELECTED = "BRAM" generate
dma_ram:k_bram
generic map (
ADDR_WIDTH => 9+4,
DATA_WIDTH => 64
)
port map (
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => dma_bram_adr_s(9+4 - 1 downto 0),
wb_dat_i => dma_bram_dat_m2s_s,
wb_we_i => dma_bram_we_s,
wb_stb_i => dma_bram_stb_s,
wb_cyc_i => dma_bram_cyc_s,
wb_lock_i => dma_bram_stb_s,
-- Wishbone Slave out
wb_dat_o => dma_bram_dat_s2m_s,
wb_ack_o => dma_bram_ack_s
);
end generate dma_bram_gen;
clk200_gen : if DMA_MEMORY_SELECTED = "BRAM" generate
--LVDS input to internal single
CLK_IBUFDS : IBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map(
I => sys_clk_p_i,
IB => sys_clk_n_i,
O => open
);
end generate clk200_gen;
dma_ddr3_gen : if DMA_MEMORY_SELECTED = "DEMUX" or DMA_MEMORY_SELECTED = "DDR3" generate
cmp_ddr3_ctrl_wb : ddr3_ctrl_wb
port map(
rst_n_i => rst_n_s,
ddr_addr_o => ddr_app_addr_s,
ddr_cmd_o => ddr_app_cmd_s,
ddr_cmd_en_o => ddr_app_cmd_en_s,
ddr_wdf_data_o => ddr_app_wdf_data_s,
ddr_wdf_end_o => ddr_app_wdf_end_s,
ddr_wdf_mask_o => ddr_app_wdf_mask_s,
ddr_wdf_wren_o => ddr_app_wdf_wren_s,
ddr_rd_data_i => ddr_app_rd_data_s,
ddr_rd_data_end_i => ddr_app_rd_data_end_s,
ddr_rd_data_valid_i => ddr_app_rd_data_valid_s,
ddr_rdy_i => ddr_app_rdy_s,
ddr_wdf_rdy_i => ddr_app_wdf_rdy_s,
ddr_ui_clk_i => ddr_app_ui_clk_s,
ddr_ui_clk_sync_rst_i => ddr_app_ui_clk_sync_rst_s,
ddr_sr_req_o => open,
ddr_ref_req_o => open,
ddr_zq_req_o => open,
ddr_sr_active_i => '1',
ddr_ref_ack_i => '1',
ddr_zq_ack_i => '1',
ddr_init_calib_complete_i => '1',
wb_clk_i => clk_i,
wb_sel_i => dma_ddr_sel_s,
wb_cyc_i => dma_ddr_cyc_s,
wb_stb_i => dma_ddr_stb_s,
wb_we_i => dma_ddr_we_s,
wb_addr_i => dma_ddr_addr_s,
wb_data_i => dma_ddr_dat_m2s_s,
wb_data_o => dma_ddr_dat_s2m_s,
wb_ack_o => dma_ddr_ack_s,
wb_stall_o => dma_ddr_stall_s,
ddr_wb_rd_mask_dout_do => ddr_wb_rd_mask_dout_ds,
ddr_wb_rd_mask_addr_dout_do => ddr_wb_rd_mask_addr_dout_ds,
ddr_rd_mask_rd_data_count_do => ddr_rd_mask_rd_data_count_ds,
ddr_rd_data_rd_data_count_do => ddr_rd_data_rd_data_count_ds,
ddr_rd_fifo_full_do => ddr_rd_fifo_full_ds,
ddr_rd_fifo_empty_do => ddr_rd_fifo_empty_ds,
ddr_rd_fifo_rd_do => ddr_rd_fifo_rd_ds
);
dma_ddr_sel_s <= (others => '1');
u_mig_7series_0 : mig_7series_0
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr_s,
ddr3_ba => ddr3_ba_s,
ddr3_cas_n => ddr3_cas_n_s,
ddr3_ck_n => ddr3_ck_n_s,
ddr3_ck_p => ddr3_ck_p_s,
ddr3_cke => ddr3_cke_s,
ddr3_ras_n => ddr3_ras_n_s,
ddr3_reset_n => ddr3_reset_n_s,
ddr3_we_n => ddr3_we_n_s,
ddr3_dq => ddr3_dq_s,
ddr3_dqs_n => ddr3_dqs_n_s,
ddr3_dqs_p => ddr3_dqs_p_s,
init_calib_complete => init_calib_complete_s,
ddr3_cs_n => ddr3_cs_n_s,
ddr3_dm => ddr3_dm_s,
ddr3_odt => ddr3_odt_s,
-- Application interface ports
app_addr => ddr_app_addr_s,
app_cmd => ddr_app_cmd_s,
app_en => ddr_app_cmd_en_s,
app_wdf_data => ddr_app_wdf_data_s,
app_wdf_end => ddr_app_wdf_end_s,
app_wdf_wren => ddr_app_wdf_wren_s,
app_rd_data => ddr_app_rd_data_s,
app_rd_data_end => ddr_app_rd_data_end_s,
app_rd_data_valid => ddr_app_rd_data_valid_s,
app_rdy => ddr_app_rdy_s,
app_wdf_rdy => ddr_app_wdf_rdy_s,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ddr_app_ui_clk_s,
ui_clk_sync_rst => ddr_app_ui_clk_sync_rst_s,
app_wdf_mask => ddr_app_wdf_mask_s,
-- System Clock Ports
sys_clk_p => sys_clk_p_i,
sys_clk_n => sys_clk_n_i,
sys_rst => rst_i
);
--DDR3
ddr3_dq_io <= ddr3_dq_s;
ddr3_dqs_p_io <= ddr3_dqs_p_s;
ddr3_dqs_n_io <= ddr3_dqs_n_s;
--init_calib_complete_o <= init_calib_complete_s;
ddr3_addr_o <= ddr3_addr_s;
ddr3_ba_o <= ddr3_ba_s;
ddr3_ras_n_o <= ddr3_ras_n_s;
ddr3_cas_n_o <= ddr3_cas_n_s;
ddr3_we_n_o <= ddr3_we_n_s;
ddr3_reset_n_o <= ddr3_reset_n_s;
ddr3_ck_p_o <= ddr3_ck_p_s;
ddr3_ck_n_o <= ddr3_ck_n_s;
ddr3_cke_o <= ddr3_cke_s;
ddr3_cs_n_o <= ddr3_cs_n_s;
ddr3_dm_o <= ddr3_dm_s;
ddr3_odt_o <= ddr3_odt_s;
end generate dma_ddr3_gen;
-- BRAM Wishbone Slave in
dma_bram_adr_s <= dma_adr_s;
dma_bram_dat_m2s_s <= dma_dat_m2s_s;
dma_bram_we_s <= dma_we_s;
dma_bram_stb_s <= dma_stb_s;
-- DDR CTRL Wishbone Slave in
dma_ddr_addr_s <= dma_adr_s;
dma_ddr_dat_m2s_s <= dma_dat_m2s_s;
dma_ddr_we_s <= dma_we_s;
dma_ddr_stb_s <= dma_stb_s;
dma_demux_gen : if DMA_MEMORY_SELECTED = "DEMUX" generate
dma_sel : process(clk_i,dummyram_sel_s, ddr3ram_sel_s, dummyaddress_sel_s, dummydeadbeef_sel_s,
dma_bram_dat_s2m_s,dma_bram_ack_s,dma_cyc_s,
dma_ddr_dat_s2m_s,dma_ddr_ack_s,
dma_ddr_dat_s2m_s,dma_ddr_ack_s)
begin
dma_dat_s2m_s <= (others => '0');
dma_ack_s <= '0';
dma_bram_cyc_s <= '0';
dma_ddr_cyc_s <= '0';
if(dummyram_sel_s = '1') then
dma_dat_s2m_s <= dma_bram_dat_s2m_s;
dma_ack_s <= dma_bram_ack_s;
dma_bram_cyc_s <= dma_cyc_s;
end if;
if (ddr3ram_sel_s = '1') then
dma_dat_s2m_s <= dma_ddr_dat_s2m_s;
dma_ack_s <= dma_ddr_ack_s;
dma_ddr_cyc_s <= dma_cyc_s;
end if;
if(dummyaddress_sel_s = '1') then
end if;
if(dummyaddress_sel_s = '1') then
end if;
end process dma_sel;
end generate dma_demux_gen;
dma_bramonly_gen : if DMA_MEMORY_SELECTED = "BRAM" generate
dma_dat_s2m_s <= dma_bram_dat_s2m_s;
dma_ack_s <= dma_bram_ack_s;
dma_bram_cyc_s <= dma_cyc_s;
end generate dma_bramonly_gen;
dma_ddr3only_gen : if DMA_MEMORY_SELECTED = "DDR3" generate
dma_dat_s2m_s <= dma_ddr_dat_s2m_s;
dma_ack_s <= dma_ddr_ack_s;
dma_ddr_cyc_s <= dma_cyc_s;
end generate dma_ddr3only_gen;
dma_mux: process(
l2p_dma_adr_s,l2p_dma_dat_m2s_s,l2p_dma_sel_s,l2p_dma_cyc_s,l2p_dma_stb_s,l2p_dma_we_s,
p2l_dma_adr_s,p2l_dma_dat_m2s_s,p2l_dma_sel_s,p2l_dma_cyc_s,p2l_dma_stb_s,p2l_dma_we_s)
begin
if l2p_dma_cyc_s = '1' then
dma_adr_s <= l2p_dma_adr_s(31 downto 0);
dma_dat_m2s_s <= l2p_dma_dat_m2s_s;
dma_sel_s <= l2p_dma_sel_s & l2p_dma_sel_s;
dma_cyc_s <= l2p_dma_cyc_s;
dma_stb_s <= l2p_dma_stb_s;
dma_we_s <= l2p_dma_we_s;
elsif p2l_dma_cyc_s = '1' then
dma_adr_s <= p2l_dma_adr_s;
dma_dat_m2s_s <= p2l_dma_dat_m2s_s;
dma_sel_s <= p2l_dma_sel_s;
dma_cyc_s <= p2l_dma_cyc_s;
dma_stb_s <= p2l_dma_stb_s;
dma_we_s <= p2l_dma_we_s;
else
dma_adr_s <= (others => '0');
dma_dat_m2s_s <= (others => '0');
dma_sel_s <= (others => '0');
dma_cyc_s <= '0';
dma_stb_s <= '0';
dma_we_s <= '0';
end if;
end process dma_mux;
l2p_dma_dat_s2m_s <= dma_dat_s2m_s;
p2l_dma_dat_s2m_s <= dma_dat_s2m_s;
l2p_dma_ack_s <= dma_ack_s;
p2l_dma_ack_s <= dma_ack_s;
l2p_dma_stall_s <= dma_stall_s;
p2l_dma_stall_s <= dma_stall_s;
dma_stall_s <= '0';
front_led_o <= count_s(28 downto 25);
--usr_led_o <= '1' & usr_sw_i;
dbg_0 : if DEBUG_C(0) = '1' generate
axis_debug : ila_axis
PORT MAP (
clk => clk_i,
probe0 => s_axis_rx_tdata_s,
probe1 => s_axis_rx_tkeep_s,
probe2(0) => s_axis_rx_tlast_s,
probe3(0) => s_axis_rx_tvalid_s,
probe4(0) => s_axis_rx_tready_s,
probe5 => m_axis_tx_tdata_s,
probe6 => m_axis_tx_tkeep_s,
probe7(0) => m_axis_tx_tlast_s,
probe8(0) => m_axis_tx_tvalid_s,
probe9(0) => m_axis_tx_tready_s,
probe10 => s_axis_rx_tuser_i,
probe11(0) => dma_ctrl_start_l2p_s,
probe12(0) => dma_ctrl_start_p2l_s,
probe13(0) => dma_ctrl_start_next_s,
probe14(0) => dma_ctrl_abort_s,
probe15(0) => dma_ctrl_done_s,
probe16(0) => dma_ctrl_error_s,
probe17(0) => user_lnk_up_i,
probe18(0) => cfg_interrupt_s,
probe19(0) => cfg_interrupt_rdy_i,
probe20(0) => dma_ctrl_done_s,
probe21 => wbm_arb_tready_s & wbm_arb_tready_s & ldm_arb_tready_s,--dma_ctrl_current_state_ds,
probe22(0) => tx_err_drop_i,--next_item_valid_s
probe23 => count_s
);
end generate dbg_0;
dbg_1 : if DEBUG_C(1) = '1' generate
dma_ctrl_debug : ila_dma_ctrl_reg
PORT MAP (
clk => clk_i,
probe0 => dma_ctrl_carrier_addr_s,
probe1 => dma_ctrl_host_addr_h_s,
probe2 => dma_ctrl_host_addr_l_s,
probe3 => dma_ctrl_len_s,
probe4(0) => dma_ctrl_start_l2p_s,
probe5(0) => dma_ctrl_start_p2l_s,
probe6(0) => dma_ctrl_start_next_s,
probe7 => dma_ctrl_byte_swap_s,
probe8(0) => dma_ctrl_abort_s,
probe9(0) => dma_ctrl_done_s,
probe10(0) => dma_ctrl_error_s,
probe11 => dma_ctrl_current_state_ds,
probe12 => next_item_carrier_addr_s,
probe13 => next_item_host_addr_h_s,
probe14 => next_item_host_addr_l_s,
probe15 => next_item_len_s,
probe16 => next_item_next_l_s,
probe17 => next_item_next_h_s,
probe18 => next_item_attrib_s,
probe19(0) => next_item_valid_s,
probe20 => dma_ctrl_irq_s
);
end generate dbg_1;
dbg_2 : if DEBUG_C(2) = '1' generate
pipelined_wishbone_debug : ila_wsh_pipe
PORT MAP (
clk => clk_i,
probe0 => dma_adr_s,
probe1 => dma_dat_s2m_s,
probe2 => dma_dat_m2s_s,
probe3 => dma_sel_s,
probe4(0) => dma_cyc_s,
probe5(0) => dma_stb_s,
probe6(0) => dma_we_s,
probe7(0) => dma_ack_s,
probe8(0) => dma_stall_s,
probe9(0) => l2p_dma_cyc_s,
probe10(0) => p2l_dma_cyc_s,
probe11(0) => dma_ctrl_start_l2p_s,
probe12(0) => dma_ctrl_start_p2l_s,
probe13(0) => dma_ctrl_start_next_s,
probe14 => ddr_rd_mask_rd_data_count_ds,
probe15 => ddr_rd_data_rd_data_count_ds,
probe16 => ddr_wb_rd_mask_addr_dout_ds & ddr_wb_rd_mask_dout_ds,
probe17 => count_s
);
end generate dbg_2;
dbg_3 : if DEBUG_C(3) = '1' generate
wbm_to_p2l_debug : ila_pd_pdm
PORT MAP (
clk => clk_i,
probe0 => pd_pdm_data_s,
probe1(0) => pd_pdm_data_last_s,
probe2(0) => pd_pdm_data_valid_s,
probe3 => s_axis_rx_tdata_s,
probe4 => s_axis_rx_tkeep_s,
probe5(0) => s_axis_rx_tlast_s,
probe6(0) => s_axis_rx_tvalid_s,
probe7(0) => ldm_arb_tready_s,
probe8 => l2p_current_state_ds,
probe9 => dma_ctrl_current_state_ds,
probe10 => pd_pdm_data_valid_w_s,
probe11(1) => next_item_valid_s
);
end generate dbg_3;
dbg_4 : if DEBUG_C(4) = '1' generate
l2p_debug : ila_l2p_dma
PORT MAP (
clk => clk_i,
probe0 => dma_ctrl_carrier_addr_s,
probe1 => dma_ctrl_host_addr_h_s,
probe2 => dma_ctrl_host_addr_l_s,
probe3 => dma_ctrl_len_s,
probe4(0) => dma_ctrl_start_l2p_s,
probe5(0) => dma_ctrl_done_s ,
probe6(0) => dma_ctrl_l2p_error_s ,
probe7(0) => dma_ctrl_abort_s,
probe8(0) => ldm_arb_tvalid_s,
probe9(0) => ldm_arb_tlast_s,
probe10 => ldm_arb_tdata_s,
probe11 => ldm_arb_tkeep_s,
probe12(0) => ldm_arb_tready_s,
probe13(0) => ldm_arb_req_s,
probe14(0) => pdm_arb_tready_s,
probe15(0) => '0',
probe16 => l2p_dma_adr_s(31 downto 0),
probe17 => l2p_dma_dat_m2s_s,
probe18 => l2p_dma_dat_s2m_s,
probe19(0) => l2p_dma_cyc_s,
probe20(0) => l2p_dma_stb_s,
probe21(0) => l2p_dma_we_s,
probe22(0) => l2p_dma_ack_s,
probe23(0) => l2p_dma_stall_s,
probe24(0) => p2l_dma_cyc_s,
probe25 => l2p_current_state_ds,
probe26 => std_logic_vector(l2p_data_cnt_ds),
probe27 => std_logic_vector(l2p_len_cnt_ds),
probe28(0) => data_fifo_rd_ds,
probe29(0) => data_fifo_wr_ds,
probe30(0) => data_fifo_empty_ds,
probe31(0) => data_fifo_full_ds,
probe32 => data_fifo_dout_ds,
probe33 => data_fifo_din_ds,
probe34(0) => addr_fifo_rd_ds,
probe35(0) => addr_fifo_wr_ds,
probe36(0) => addr_fifo_empty_ds,
probe37(0) => addr_fifo_full_ds,
probe38 => addr_fifo_dout_ds,
probe39 => addr_fifo_din_ds,
probe40 => std_logic_vector(wb_timeout_cnt_ds),
probe41 => std_logic_vector(l2p_timeout_cnt_ds),
probe42 => count_s
);
end generate dbg_4;
dbg_5 : if DEBUG_C(5) = '1' generate
ddr_debug : ila_ddr
PORT MAP (
clk => ddr_app_ui_clk_s,
probe0 => ddr_app_addr_s,
probe1 => ddr_app_cmd_s,
probe2(0) => ddr_app_cmd_en_s,
probe3 => ddr_app_wdf_data_s,
probe4(0) => ddr_app_wdf_end_s,
probe5 => ddr_app_wdf_mask_s,
probe6(0) => ddr_app_wdf_wren_s,
probe7 => ddr_app_rd_data_s,
probe8(0) => ddr_app_rd_data_end_s,
probe9(0) => ddr_app_rd_data_valid_s,
probe10(0) => ddr_app_rdy_s,
probe11(0) => ddr_app_wdf_rdy_s,
probe12(0) => ddr_app_ui_clk_sync_rst_s,
probe13(0) => init_calib_complete_s,
probe14 => ddr_count_s
);
end generate dbg_5;
end Behavioral;
| gpl-3.0 |
cretingame/Yarr-fw | ip-cores/spartan6/fifo_64x512.vhd | 2 | 7679 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fifo_generator:6.2
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_64x512 IS
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(63 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(8 downto 0);
prog_full_thresh_negate: in std_logic_vector(8 downto 0);
dout: out std_logic_vector(63 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
END fifo_64x512;
ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
-- synthesis translate_off
component wrapped_fifo_64x512
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(63 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(8 downto 0);
prog_full_thresh_negate: in std_logic_vector(8 downto 0);
dout: out std_logic_vector(63 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_64x512_a;
| gpl-3.0 |
Project-Bonfire/Bonfire | RTL/virtual_channel/LBDR.vhd | 1 | 3026 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
N1 <= '1' when dst_addr_y < cur_addr_y else '0';
E1 <= '1' when cur_addr_x < dst_addr_x else '0';
W1 <= '1' when dst_addr_x < cur_addr_x else '0';
S1 <= '1' when cur_addr_y < dst_addr_y else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END;
| gpl-3.0 |
Candyroot/Floating-Point-Addition | pda/@mux_5/_primary.vhd | 4 | 401 | library verilog;
use verilog.vl_types.all;
entity Mux_5 is
port(
clk : in vl_logic;
res : in vl_logic;
en : in vl_logic;
mux : in vl_logic_vector(7 downto 0);
rounding : in vl_logic_vector(7 downto 0);
outp : out vl_logic_vector(7 downto 0)
);
end Mux_5;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | tb_mdio.vhd | 1 | 2782 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mdio IS
END tb_mdio;
ARCHITECTURE behavior OF tb_mdio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mdio
PORT(
clk : IN std_logic;
rst : IN std_logic;
cnt_5 : in STD_LOGIC;
cnt_23 : IN std_logic;
mdc : OUT std_logic;
mdio_i : IN std_logic;
mdio_o : OUT std_logic;
mdio_t : OUT std_logic;
data : IN std_logic_vector(7 downto 0);
digit : OUT std_logic_vector(15 downto 0);
trgr : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal cnt64 : std_logic_vector(63 downto 0) := ( others => '0' );
signal mdio_i : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal trgr : std_logic := '0';
--Outputs
signal mdc : std_logic;
signal mdio_o : std_logic;
signal mdio_t : std_logic;
signal digit : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mdio PORT MAP (
clk => clk,
rst => rst,
cnt_5 => cnt64(5),
cnt_23 => cnt64(8),
mdc => mdc,
mdio_i => mdio_i,
mdio_o => mdio_o,
mdio_t => mdio_t,
data => data,
digit => digit,
trgr => trgr
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
cnt_64_p :process
begin
cnt64 <= cnt64 + 1;
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0';
wait for 10 us;
trgr <= '1';
wait for 1 us;
trgr <= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
kuba-moo/VHDL-precise-packet-generator | tb_mem_reader.vhd | 1 | 2463 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mem_reader IS
END tb_mem_reader;
ARCHITECTURE behavior OF tb_mem_reader IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem_reader
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FrameLen : IN std_logic_vector(10 downto 0);
FrameIval : IN std_logic_vector(27 downto 0);
BusPkt : OUT std_logic;
BusData : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal FrameLen : std_logic_vector(10 downto 0) := (others => '0');
signal FrameIval : std_logic_vector(27 downto 0) := (others => '0');
--Outputs
signal BusPkt : std_logic;
signal BusData : std_logic_vector(7 downto 0);
signal Clk_o : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
Clk_o <= transport Clk after 8 ns;
-- Instantiate the Unit Under Test (UUT)
uut: mem_reader PORT MAP (
Clk => Clk,
Rst => Rst,
FrameLen => FrameLen,
FrameIval => FrameIval,
BusPkt => BusPkt,
BusData => BusData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
FrameLen <= b"000" & X"4c";
FrameIval <= ( 7 => '1', others => '0' );
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
cretingame/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/read_data_path.vhd | 20 | 24605 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
| gpl-3.0 |
metaspace/ghdl_extra | ghdl_env/ghdl_env.vhdl | 2 | 1778 | -- fichier ghdl_env.vhdl (C) Yann Guidon 2010
-- version jeu. sept. 2 06:38:43 CEST 2010
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
package ghdl_env is
function getenv(s : string; d : integer) return integer;
function getenvC2(s : string; d : integer) return integer;
attribute foreign of getenvC2 :
function is "VHPIDIRECT ghdl_envC2";
function getenv(s : string) return string;
function getenvS2(s : string) return string;
attribute foreign of getenvS2 :
function is "VHPIDIRECT ghdl_env_string";
end ghdl_env;
package body ghdl_env is
-- fonction relais :
function getenv(s : string; d : integer)
return integer is
begin -- ajoute le 0 terminal :
return getenvC2(s & NUL, d);
end getenv;
function getenvC2(s : string; d : integer)
return integer is
begin
assert false report "VHPI" severity failure;
end getenvC2;
-- fonction relais :
function getenv(s : string) return string is
begin -- ajoute le 0 terminal :
return getenvS2(s & NUL);
end getenv;
function getenvS2(s : string) return string is
begin
assert false report "VHPI" severity failure;
end getenvS2;
end ghdl_env;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab01/lab01/ipcore_dir/ROM_D/simulation/ROM_D_tb_stim_gen.vhd | 8 | 10537 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END ROM_D_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF ROM_D_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"ROM_D.mif",
DEFAULT_DATA,
32,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.ROM_D_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.ROM_D_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/mux_5bits.vhd | 2 | 582 | --Mux de 3 entradas de 5 bits e uma saida de 5 bits. Usado para endereços de registradores
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux_5bits is
port (sel : in std_logic_vector(1 downto 0) := "00";
dataIn1, dataIn2, dataIn3 : in std_logic_vector (4 downto 0);
dataOut : out std_logic_vector(4 downto 0));
end entity mux_5bits;
architecture Behavioral of mux_5bits is
begin
WITH sel SELECT
dataOut <= dataIn1 when "00",
dataIn2 when "01",
dataIn3 when "10",
(others => '0') when others;
end Behavioral;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab05/lab05/ipcore_dir/ROM_D/example_design/ROM_D_prod_exdes.vhd | 8 | 5117 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab01/lab01/ipcore_dir/ROM_D/example_design/ROM_D_prod_exdes.vhd | 8 | 5117 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab01/lab01/ipcore_dir/ROM_D/simulation/ROM_D_tb.vhd | 8 | 4201 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM_D_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_tb IS
END ENTITY;
ARCHITECTURE ROM_D_tb_ARCH OF ROM_D_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM_D_tb_synth_inst:ENTITY work.ROM_D_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/ipcore_dir/ROM_D/simulation/ROM_D_tb.vhd | 8 | 4201 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM_D_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_tb IS
END ENTITY;
ARCHITECTURE ROM_D_tb_ARCH OF ROM_D_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM_D_tb_synth_inst:ENTITY work.ROM_D_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab01/lab01/ipcore_dir/RAM_B/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab09/lab09/ipcore_dir/RAM_B/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb_synth.vhd | 8 | 6921 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_D_tb_synth;
ARCHITECTURE ROM_D_synth_ARCH OF ROM_D_tb_synth IS
COMPONENT ROM_D_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_D_TB_STIM_GEN_INST:ENTITY work.ROM_D_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_D_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/ipcore_dir/ROM_D/simulation/ROM_D_tb_synth.vhd | 8 | 6921 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_D_tb_synth;
ARCHITECTURE ROM_D_synth_ARCH OF ROM_D_tb_synth IS
COMPONENT ROM_D_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_D_TB_STIM_GEN_INST:ENTITY work.ROM_D_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_D_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab07/lab07/ipcore_dir/RAM_B/simulation/RAM_B_synth.vhd | 12 | 7867 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_B_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_B_synth_ARCH OF RAM_B_synth IS
COMPONENT RAM_B_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_B_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab05/lab05/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd | 10 | 10063 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : RAM_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab09/lab09/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd | 10 | 10063 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : RAM_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/Banco Registradores/Registrador_Nbits.vhd | 1 | 1336 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Registrador
-- Descrição: Registrador com largura de palavra parametrizável
-- e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------
-- Definiçao da entidade:
-- N - controle da palavra
-- clk - clock
-- D - dado de entrada
-- Q - saida
----------------------------------
entity Registrador_Nbits is
Generic (N : integer := 16);
Port (clk : in std_logic;
D : in std_logic_vector(N - 1 downto 0) := (others => '0');
Q : out std_logic_vector(N - 1 downto 0) := (others => '0'));
end Registrador_Nbits;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture Comportamental of Registrador_Nbits is
begin
process (clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
end architecture Comportamental;
| gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificacao-Principal/dec_mi.vhd | 2 | 1978 | --Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mi is
generic(N: integer := 7; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_VECTOR(N-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_mi_arch of dec_mi is
-- signals
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
i1 : entity work.mi
generic map(N => N, M => M)
port map (
address => SW,
clk => clk,
instruction => dout
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab07/lab07/ipcore_dir/RAM_B/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/ipcore_dir/RAM_B/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab09/lab09/ipcore_dir/RAM_B/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab03/lab03/ipcore_dir/RAM_B/simulation/data_gen.vhd | 69 | 5024 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/ipcore_dir/RAM_B/simulation/data_gen.vhd | 69 | 5024 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-3.0 |
manosaloscables/vhdl | generador_pixeles/gen_obj_tb.vhd | 1 | 1896 | -- ****************************************************
-- * Banco de prueba para el generador de objetos VGA *
-- ****************************************************
-- Recordar que durante la simulación se deben incluir
-- las constantes para que obj_on funcione.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_obj_bp is
end gen_obj_bp;
architecture arq_bp of gen_obj_bp is
signal px_x, px_y: std_logic_vector(9 downto 0); -- Entradas
signal pared_on, bar_on, bola_on: std_logic; -- Salidas
signal pared_rgb, bar_rgb, bola_rgb: std_logic_vector(2 downto 0);
signal x, y: unsigned(9 downto 0); -- Estímulos
begin
-- Instanciar un generador de objetos con pared
unidad_gen_obj: entity work.gen_obj(pared)
port map(
obj_on => pared_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => pared_rgb
);
-- Instanciar un generador de objetos con barra
u2_gen_obj: entity work.gen_obj(barra)
port map(
obj_on => bar_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => bar_rgb
);
-- Instanciar un generador de objetos con bola
u3_gen_obj: entity work.gen_obj(bola)
port map(
obj_on => bola_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => bola_rgb
);
-- Otros estímulos
process begin
x <= to_unsigned(0, 10);
y <= to_unsigned(0, 10);
wait for 200 ns;
for j in 1 to 525 loop
y <= to_unsigned(j-1, 10);
px_y <= Std_logic_vector(y);
for i in 1 to 800 loop
x <= to_unsigned(i-1, 10);
px_x <= std_logic_vector(x);
wait for 200 ns;
end loop;
end loop;
-- Terminar simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp; | gpl-3.0 |
rafa-jfet/OFM | ARCHIVOS VHDL/IfftControl.vhd | 1 | 2473 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:54:31 06/24/2015
-- Design Name:
-- Module Name: asd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IfftControl is
generic(
CARRIERS : INTEGER :=128 --
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
IfftEnable: in STD_LOGIC;
start : out STD_LOGIC;
cp_len : out STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we : out STD_LOGIC;
unload : out STD_LOGIC;
fwd_inv : out STD_LOGIC;
fwd_inv_we : out STD_LOGIC;
rfd : in STD_LOGIC);
end IfftControl;
architecture Behavioral of IfftControl is
--declaracion de estados
type estado is (reposo,
-- leyendo,
inicio,
activo);
--señales
signal estado_actual, estado_nuevo: estado;
-- signal datoIn : STD_LOGIC_VECTOR (15 downto 0);
-- signal outReal, outImag : STD_LOGIC_VECTOR (7 downto 0);
-- signal dire_actual, dire_nuevo: STD_LOGIC_VECTOR(6 downto 0);
-- signal addra, p_addra : INTEGER RANGE 0 to CARRIERS; -- deberia ser carriers -1 pero sino no detectamos que es mayor por que desborda
begin
cp_len<="0001100"; --configuracion prefijo ciclico
fwd_inv <='0'; -- inversa ifft
--proceso sincrono
sinc: process(reset, clk)
begin
if(reset='1') then
estado_actual <= reposo;
elsif (clk='1' and clk'event) then
estado_actual <= estado_nuevo;
end if;
end process;
comb: process (estado_actual, ifftEnable, rfd)
begin
estado_nuevo<= estado_actual;
start <='0';
cp_len_we <='0';
unload <='1';
fwd_inv_we<='0';
case estado_actual is
when reposo =>
if ifftEnable='1' then
estado_nuevo<= inicio;
else
estado_nuevo <=reposo;
end if;
when inicio =>
--Conexiones con el core de FFT
start <='1';
cp_len_we <='1';
fwd_inv_we<='1';
--saltamos a otro estado
estado_nuevo<= activo;
when activo =>
start <='0';
--saltamos a otro estado
if rfd='1' then
estado_nuevo<= activo;
else
estado_nuevo <= reposo;
end if;
end case;
end process;
end Behavioral;
| gpl-3.0 |
hacklabmikkeli/rough-boy | preset_selector.vhdl | 2 | 5513 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity preset_selector is
port (EN: in std_logic
;CLK: in std_logic
;KEY_CODE: in keys_signal
;KEY_EVENT: in key_event_t
;PARAMS: out synthesis_params
);
end entity;
architecture preset_selector_impl of preset_selector is
subtype quantized_t is unsigned(2 downto 0);
function time_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"01";
when "001" => return x"02";
when "010" => return x"04";
when "011" => return x"08";
when "100" => return x"10";
when "101" => return x"20";
when "110" => return x"80";
when "111" => return x"F0";
when others => return x"FF";
end case;
end function;
function level_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"00";
when "001" => return x"20";
when "010" => return x"40";
when "011" => return x"60";
when "100" => return x"80";
when "101" => return x"A0";
when "110" => return x"C0";
when "111" => return x"E0";
when others => return x"FF";
end case;
end function;
signal mode: mode_t := mode_saw;
signal transform: voice_transform_t := voice_transform_none;
signal q_cutoff_base: quantized_t := "000";
signal q_cutoff_env: quantized_t := "111";
signal q_cutoff_attack: quantized_t := "111";
signal q_cutoff_decay: quantized_t := "000";
signal q_cutoff_sustain: quantized_t := "111";
signal q_cutoff_rel: quantized_t := "111";
signal q_gain_attack: quantized_t := "111";
signal q_gain_decay: quantized_t := "111";
signal q_gain_sustain: quantized_t := "111";
signal q_gain_rel: quantized_t := "111";
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
if KEY_EVENT = key_event_make then
case KEY_CODE is
-- Preset editing
when "001100" => mode <= mode - 1;
when "001101" => mode <= mode + 1;
when "001001" => transform <= transform - 1;
when "001010" => transform <= transform + 1;
when "001111" => q_cutoff_base <= q_cutoff_base - 1;
when "001110" => q_cutoff_base <= q_cutoff_base + 1;
when "100010" => q_cutoff_env <= q_cutoff_env - 1;
when "001000" => q_cutoff_env <= q_cutoff_env + 1;
when "000010" => q_cutoff_attack <= q_cutoff_attack + 1;
when "000011" => q_cutoff_attack <= q_cutoff_attack - 1;
when "000001" => q_cutoff_decay <= q_cutoff_decay + 1;
when "000000" => q_cutoff_decay <= q_cutoff_decay - 1;
when "000111" => q_cutoff_sustain <= q_cutoff_sustain - 1;
when "000110" => q_cutoff_sustain <= q_cutoff_sustain + 1;
when "000101" => q_cutoff_rel <= q_cutoff_rel + 1;
when "000100" => q_cutoff_rel <= q_cutoff_rel - 1;
when "010000" => q_gain_attack <= q_gain_attack + 1;
when "010001" => q_gain_attack <= q_gain_attack - 1;
when "010010" => q_gain_decay <= q_gain_decay + 1;
when "010011" => q_gain_decay <= q_gain_decay - 1;
when "010111" => q_gain_sustain <= q_gain_sustain - 1;
when "010110" => q_gain_sustain <= q_gain_sustain + 1;
when "010101" => q_gain_rel <= q_gain_rel + 1;
when "010100" => q_gain_rel <= q_gain_rel - 1;
when others => null;
end case;
end if;
end if;
end process;
PARAMS <= (mode
,transform
,level_unquantize(q_cutoff_base)
,level_unquantize(q_cutoff_env)
,time_unquantize(q_cutoff_attack)
,time_unquantize(q_cutoff_decay)
,level_unquantize(q_cutoff_sustain)
,time_unquantize(q_cutoff_rel)
,time_unquantize(q_gain_attack)
,time_unquantize(q_gain_decay)
,level_unquantize(q_gain_sustain)
,time_unquantize(q_gain_rel)
);
end architecture;
| gpl-3.0 |
rafa-jfet/OFM | ARCHIVOS VHDL/intlv.vhd | 1 | 4425 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:38:07 07/01/2015
-- Design Name:
-- Module Name: intlv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity intlv is
Generic ( bits_BPSK : integer := 96;
bits_QPSK : integer := 192;
bits_8PSK : integer := 288;
col_BPSK : integer := 12;
col_QPSK : integer := 12;
col_8PSK : integer := 18;
fil_BPSK : integer := 8;
fil_QPSK : integer := 16;
fil_8PSK : integer := 16);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC_VECTOR (0 downto 0);
dir_bit : out STD_LOGIC_VECTOR (8 downto 0);
write_mem : out STD_LOGIC_VECTOR (0 downto 0);
ok_bit_out : out STD_LOGIC
);
end intlv;
architecture Behavioral of intlv is
type estado is ( reposo,
inicio,
escribe,
salida,
salida_ok
);
signal estado_actual, estado_nuevo : estado;
signal dir, p_dir : STD_LOGIC_VECTOR(8 downto 0);
signal NUM_BITS : integer range 0 to bits_8PSK := 0;
signal NUM_COL : integer range 0 to col_8PSK := 0;
signal BITS_FILA : integer range 0 to 4;
begin
dir_bit <= dir;
bit_out(0) <= bit_in;
initialization : process ( modulation)
begin
case modulation is
when "100" =>
NUM_BITS <= bits_BPSK;
NUM_COL <= col_BPSK;
BITS_FILA <= 3;
when "010" =>
NUM_BITS <= bits_QPSK;
NUM_COL <= col_QPSK;
BITS_FILA <= 4;
when OTHERS =>
NUM_BITS <= bits_8PSK;
NUM_COL <= col_8PSK;
BITS_FILA <= 4;
end case;
end process;
comb : process ( estado_actual, button, modulation, dir, ok_bit_in, NUM_BITS, BITS_FILA )
--variable BITS_FILA : integer := 0; --bits necesarios para direccionar las filas
begin
write_mem(0) <= '0';
ok_bit_out <= '0';
p_dir <= dir;
estado_nuevo <= estado_actual;
case estado_actual is
when reposo =>
if ( button = '1' ) then
p_dir <= (others => '0');
estado_nuevo <= inicio;
end if;
-- case modulation is
--
-- when "100" =>
-- NUM_BITS <= bits_BPSK;
-- NUM_COL <= col_BPSK;
-- BITS_FILA := 3;
--
-- when "010" =>
-- NUM_BITS <= bits_QPSK;
-- NUM_COL <= col_QPSK;
-- BITS_FILA := 4;
--
-- when OTHERS =>
-- NUM_BITS <= bits_8PSK;
-- NUM_COL <= col_8PSK;
-- BITS_FILA := 4;
--
-- end case;
when inicio =>
if ( ok_bit_in = '1' ) then
write_mem(0) <= '1';
estado_nuevo <= escribe;
end if;
if (dir = NUM_BITS) then
estado_nuevo <= salida;
p_dir <= (others => '0');
end if;
when escribe =>
p_dir <= dir +1;
estado_nuevo <= inicio;
when salida =>
estado_nuevo <= salida_ok;
when salida_ok =>
estado_nuevo <= salida;
ok_bit_out <= '1';
if ( dir = NUM_BITS -1) then -- comprueba si se ha completado un simbolo
estado_nuevo <= inicio;
p_dir <= (others => '0');
elsif ( dir(8 downto BITS_FILA) = NUM_COL -1) then -- comprueba si se ha completado una fila
p_dir(8 downto BITS_FILA) <= (others => '0');
p_dir(BITS_FILA -1 downto 0) <= dir (BITS_FILA -1 downto 0) +1;
else
p_dir (8 downto BITS_FILA) <= dir(8 downto BITS_FILA) +1; --pasa a la siguiente columna
end if;
end case;
end process;
sinc : process (reset, clk)
begin
if ( reset = '1' ) then
dir <= ( others=>'0' );
estado_actual <= reposo;
elsif ( rising_edge(clk) ) then
dir <= p_dir;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 |
makestuff/spi-master | vhdl/tb_suppress/spi_master_tb.vhdl | 1 | 5405 | --
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_master_tb is
end entity;
architecture behavioural of spi_master_tb is
-- Clocks, etc
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal sendData : std_logic_vector(7 downto 0); -- data to send
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0); -- data we receive
signal recvValid : std_logic;
signal recvReady : std_logic;
-- External interface
signal spiClk : std_logic; -- serial clock
signal spiDataOut : std_logic; -- send serial data
signal spiDataIn : std_logic; -- receive serial data
begin
-- Instantiate the unit under test
uut: entity work.spi_master
generic map(
--FAST_COUNT => "000011"
FAST_COUNT => "000000",
BIT_ORDER => '1'
)
port map(
reset_in => reset,
clk_in => sysClk,
turbo_in => '1',
suppress_in => '1',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus/send.sim";
file outFile : text open write_mode is "results/recv.sim";
begin
sendData <= (others => 'X');
sendValid <= '0';
wait until falling_edge(reset);
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
sendData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
sendValid <= to_1(inLine.all(4));
recvReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(sendData(7 downto 4)) & from_4(sendData(3 downto 0)));
write(outLine, ' ');
write(outLine, sendValid);
write(outLine, ' ');
write(outLine, sendReady);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
sendData <= (others => 'X');
sendValid <= '0';
wait;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.sim and receive into r/send.sim
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.sim";
file outFile : text open write_mode is "results/send.sim";
begin
spiDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until spiClk = '0';
spiDataIn <= inData(7);
wait until spiClk = '1';
outData(7) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(6);
wait until spiClk = '1';
outData(6) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(5);
wait until spiClk = '1';
outData(5) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(4);
wait until spiClk = '1';
outData(4) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(3);
wait until spiClk = '1';
outData(3) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(2);
wait until spiClk = '1';
outData(2) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(1);
wait until spiClk = '1';
outData(1) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(0);
wait until spiClk = '1';
outData(0) := spiDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
spiDataIn <= 'X';
wait;
end process;
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_016_test_input.fixed_last_paren_new_line_false.vhd | 1 | 2595 |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
));
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_021_test_input.fixed.vhd | 1 | 558 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_100_test_input.fixed.vhd | 1 | 758 |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
-- Fixes follow
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
begin
end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd | 10 | 90302 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.
-- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic ;
MCB_UIDQLOWERINC : out std_logic ;
MCB_UIDQUPPERDEC : out std_logic ;
MCB_UIDQUPPERINC : out std_logic ;
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010";
constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011";
constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100";
constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101";
constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110";
constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111";
constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000";
constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001";
constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010";
constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011";
constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100";
constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101";
constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110";
constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111";
constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000";
constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010";
constant WAIT7 : std_logic_vector(5 downto 0) := "100011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100";
constant WAIT8 : std_logic_vector(5 downto 0) := "100101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "100110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010";
constant WAIT9 : std_logic_vector(5 downto 0) := "110011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100";
constant WAIT10 : std_logic_vector(5 downto 0) := "110101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111";
constant INCREMENT : std_logic_vector(5 downto 0) := "111000";
constant DECREMENT : std_logic_vector(5 downto 0) := "111001";
constant DONE : std_logic_vector(5 downto 0) := "111010";
--constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PNSKEWDQS : std_logic := '1';
constant MULT_S : integer := 9;
constant DIV_S : integer := 8;
constant MULT_W : integer := 7;
constant DIV_W : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT;
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_s : std_logic_vector(5 downto 0) := "000000";
signal N_Term_s : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_w : std_logic_vector(5 downto 0) := "000000";
signal N_Term_w : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0);
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_int : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
--signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
signal WaitTimer : std_logic_vector(7 downto 0);
signal WarmEnough : std_logic;
signal WaitCountEnable : std_logic;
signal State_Start_DynCal_R1 : std_logic;
signal State_Start_DynCal : std_logic;
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_s : signal is TRUE;
attribute syn_preserve of N_Term_s : signal is TRUE;
attribute syn_preserve of P_Term_w : signal is TRUE;
attribute syn_preserve of N_Term_w : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
-- move the default assignment here to make FORMALITY happy.
START_BROADCAST <= '1';
MCB_RECAL <= '0';
MCB_UIDQLOWERDEC <= '0';
MCB_UIADDR <= MCB_UIADDR_int;
MCB_UIDQLOWERINC <= '0';
MCB_UIDQUPPERDEC <= '0';
MCB_UIDQUPPERINC <= '0';
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_int,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
process (UI_CLK, RST) begin
if (RST = '1') then
if (C_SIMULATION = "TRUE") then
WAIT_200us_COUNTER <= X"7FF0";
else
WAIT_200us_COUNTER <= (others => '0');
end if;
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
-- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
-- WAIT_200us_COUNTER <= X"FFFF";
-- process
-- begin
-- report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
-- wait;
-- end process;
-- end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
else
CKE_Train <= '0';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
--MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, RST) begin
if (RST = '1') then
--Block_Reset <= '0';
--RstCounter <= (others => '0');
--elsif (UI_CLK'event and UI_CLK = '1') then
-- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
--end if;
end process;
-- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
non_violating_rst <= RST and Rst_condition1;
MCB_SYSRST <= Pre_SYSRST;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process.
-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
-- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which
-- will cause MCB to reset and reinitialize the memory afterwards.
-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at
-- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
-- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration
-- state machine will not reset during SUSPEND.
-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to
-- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST.
-- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT
-- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
--process (UI_CLK) begin
-- if (UI_CLK'event and UI_CLK = '1') then
--
-- if (RstCounter < RST_CNT) then
-- Rst_condition2 <= '1';
-- else
-- Rst_condition2 <= '0';
-- end if;
-- end if;
--end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
--RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK,RST)
begin
if (RST = '1') then
SELFREFRESH_MCB_MODE_R1 <= '0';
SELFREFRESH_MCB_MODE_R2 <= '0';
SELFREFRESH_MCB_MODE_R3 <= '0';
SELFREFRESH_REQ_R1 <= '0';
SELFREFRESH_REQ_R2 <= '0';
SELFREFRESH_REQ_R3 <= '0';
PLL_LOCK_R1 <= '0';
PLL_LOCK_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before
-- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before
-- user logic sending new commands to MCB.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif (WarmEnough = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitCountEnable <= '0';
elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then
WaitCountEnable <= '0';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
WaitCountEnable <= '1';
else
WaitCountEnable <= WaitCountEnable;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal <= '0';
elsif (STATE = START_DYN_CAL) then
State_Start_DynCal <= '1';
else
State_Start_DynCal <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal_R1 <= '0';
else
State_Start_DynCal_R1 <= State_Start_DynCal;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitTimer <= (others => '0');
WarmEnough <= '1';
elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then
WaitTimer <= (others => '0');
WarmEnough <= '0';
elsif (WaitTimer = X"04") then
WaitTimer <= WaitTimer ;
WarmEnough <= '1';
elsif (WaitCountEnable = '1') then
WaitTimer <= WaitTimer + '1';
else
WaitTimer <= WaitTimer ;
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_int <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_s <= "000000";
N_Term_w <= "0000000";
P_Term_w <= "000000";
N_Term_s <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
STATE <= WRITE_CALIBRATE;
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
-- 13/4/2011 compensate the added sync FF
P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0);
P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if (P_Term /= P_Term_Prev) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
-- if (PNSKEWDQS = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
-- else
-- STATE <= OFF_RZQ_PTERM;
-- end if;
end if;
-- *********************
when LDQS_CLK_WRITE_P_TERM => -- h12
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
else
STATE <= LDQS_CLK_P_TERM_WAIT;
end if;
when LDQS_CLK_P_TERM_WAIT => --7'h13
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_P_TERM_WAIT;
else
STATE <= LDQS_CLK_WRITE_N_TERM;
end if;
when LDQS_CLK_WRITE_N_TERM => --7'h14
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_N_TERM;
else
STATE <= LDQS_CLK_N_TERM_WAIT;
end if;
--**
when LDQS_CLK_N_TERM_WAIT => --7'h15
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_N_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_P_TERM;
end if;
when LDQS_PIN_WRITE_P_TERM => --7'h16
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_P_TERM;
else
STATE <= LDQS_PIN_P_TERM_WAIT;
end if;
when LDQS_PIN_P_TERM_WAIT => --7'h17
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_P_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_N_TERM;
end if;
when LDQS_PIN_WRITE_N_TERM => --7'h18
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_N_TERM;
else
STATE <= LDQS_PIN_N_TERM_WAIT;
end if;
when LDQS_PIN_N_TERM_WAIT => --7'h19
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_N_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_P_TERM;
end if;
when UDQS_CLK_WRITE_P_TERM => --7'h1A
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_P_TERM;
else
STATE <= UDQS_CLK_P_TERM_WAIT;
end if;
when UDQS_CLK_P_TERM_WAIT => --7'h1B
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_P_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_N_TERM;
end if;
when UDQS_CLK_WRITE_N_TERM => --7'h1C
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_N_TERM;
else
STATE <= UDQS_CLK_N_TERM_WAIT;
end if;
when UDQS_CLK_N_TERM_WAIT => --7'h1D
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_N_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_P_TERM;
end if;
when UDQS_PIN_WRITE_P_TERM => --7'h1E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_P_TERM;
else
STATE <= UDQS_PIN_P_TERM_WAIT;
end if;
when UDQS_PIN_P_TERM_WAIT => --7'h1F
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_P_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_N_TERM;
end if;
when UDQS_PIN_WRITE_N_TERM => --7'h20
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_N_TERM;
else
STATE <= UDQS_PIN_N_TERM_WAIT;
end if;
when UDQS_PIN_N_TERM_WAIT => --7'h21
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_N_TERM_WAIT;
else
STATE <= OFF_RZQ_PTERM;
end if;
-- *********************
when OFF_RZQ_PTERM => -- h22
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h23
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h24
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h26
MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h27
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
else
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h28
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h29
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h2A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h2B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h2C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h2D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h2E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h30
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h31
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h32
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h33
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h34
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h35
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h37
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h38
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h39
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h3A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable/rule_001_test_input.vhd | 1 | 411 |
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
variable var1 : integer;
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_010_test_input.fixed.vhd | 1 | 665 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- loop statements
if a = '1' then
loop
end loop;
else
end if;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_500_test_input.fixed_lower.vhd | 1 | 69 |
entity FIFO is
begin
end entity;
entity FIFO is
begin
end entity;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/rtl/traffic_gen/afifo.vhd | 20 | 9200 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_017_test_input.fixed_seperate_generic.vhd | 1 | 705 |
architecture RTl of FIFO is
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_008_test_input.vhd | 1 | 424 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_018_test_input.vhd | 1 | 636 |
entity FIFO is
port (
I_PORT1 : in integer;
I_PORT2 : in std_logic;
I_PORTA : in t_user2;
I_PORT3 : in std_logic_vector(3 downto 0);
I_PORT4 : in signed(15 downto 0);
I_PORT5 : in unsigned(7 downto 0);
I_PORT6 : in std_ulogic;
I_PORT7 : in t_user1
);
end entity FIFO;
-- Violation below
entity FIFO is
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/process_statement/classification_test_input.vhd | 1 | 551 |
architecture RTL of FIFO is
begin
process_and_or : process(a,b,d,e) is
begin
end process process_and_or;
process_and_or : postponed process(a,b,d,e) is
begin
end postponed process process_and_or;
process_and_or : postponed process is
begin
end postponed process process_and_or;
process_and_or : postponed process
begin
end postponed process process_and_or;
process_and_or : process
begin
end process process_and_or;
process
begin
end process;
process is
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_201_test_input.fixed.vhd | 1 | 475 |
architecture ARCH of ENTITY is
begin
PROC_1 : process
begin
case boolean_1 is
when STATE_1 =>
-- Comment
when STATE_2 =>
end case;
end process PROC_1;
-- Violations below
PROC_1 : process
begin
case boolean_1 is
when STATE_1 =>
-- Comment
when STATE_2 =>
end case;
case boolean_2 is
-- Comment
when STATE_1 =>
end case;
end process PROC_1;
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_011_test_input.fixed_upper.vhd | 1 | 221 |
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/mcb_flow_control.vhd | 20 | 18501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/library_clause/classification_test_input.vhd | 1 | 45 |
library ieee;
library ieee, lib2, lib3;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_024_test_input.fixed.vhd | 2 | 224 |
architecture RTL of FIFO is
begin
PROC_LABEL : process
begin
end process;
-- Violations below
PROC_LABEL : process
begin
end process;
PROC_LABEL : process
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/context_ref/rule_005_test_input.fixed.vhd | 1 | 98 |
library ieee;
context c1, c1a, c1b;
library ieee;
context con1;
context con2;
context con3;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_009_test_input.vhd | 1 | 62 |
entity FIFO is
end entity;
entity FIFO is
end entity;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd | 2 | 22920 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_clk_pll_s2_diff is
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s2_diff;
architecture arch_serdes_1_to_n_clk_pll_s2_diff of serdes_1_to_n_clk_pll_s2_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0); --
signal cascade : std_logic; --
signal pd_edge : std_logic; --
signal busys : std_logic; --
signal busym : std_logic; --
signal rx_clk_in : std_logic; --
signal feedback : std_logic; --
signal buf_P_clk : std_logic; --
signal iob_data_in : std_logic; --
signal rx_bufg_pll_x1_int : std_logic;
signal rxioclk_int : std_logic;
signal rx_serdesstrobe_int : std_logic;
signal rx_pllout_xs_int : std_logic;
signal rx_pllout_x1 : std_logic;
signal rx_pll_lckd_int : std_logic;
signal state : integer range 0 to 9;
signal bslip : std_logic;
signal count : std_logic_vector(2 downto 0);
signal busyd : std_logic;
signal counter : std_logic_vector(11 downto 0);
signal clk_iserdes_data : std_logic_vector(S-1 downto 0);
signal cal_clk : std_logic;
signal rst_clk : std_logic;
signal rx_bufplllckd : std_logic;
signal not_rx_bufpll_lckd : std_logic;
signal busy_clk : std_logic;
signal enable : std_logic;
constant RX_SWAP_CLK : std_logic := '0'; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int;
rxioclk <= rxioclk_int;
rx_serdesstrobe <= rx_serdesstrobe_int;
rx_pllout_xs <= rx_pllout_xs_int;
rx_pll_lckd <= rx_pll_lckd_int;
bitslip <= bslip;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK; -- Invert clock as required
busy_clk <= busym;
datain <= clk_iserdes_data;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0;
enable <= '0';
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk;
if counter(5) = '1' then
enable <= '1';
end if;
if counter(11) = '1' then
state <= 0;
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
else
counter <= counter + 1;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1;
elsif state = 1 then -- cal high
cal_clk <= '1'; state <= 2;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0'; state <= 3; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1'; state <= 4; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0'; state <= 5;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6;
count <= "000";
elsif state = 6 then -- hang around
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 7 then
if BS = true and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1'; -- bitslip needed
state <= 8;
count <= "000";
else
state <= 9;
end if;
elsif state = 8 then
bslip <= '0'; -- bitslip low
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 9 then -- repeat after a delay
state <= 9;
end if;
end if;
end if;
end process;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S);
end generate;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 90.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int);
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd);
end arch_serdes_1_to_n_clk_pll_s2_diff;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/signal/rule_006_test_input.fixed.vhd | 1 | 196 |
architecture RTL of FIFO is
signal sig1 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_016_test_input.vhd | 1 | 341 |
architecture RTl of FIFO is
component fifo is
port (
a : in std_logic
);
end component fifo;
-- Failures below
component fifo is
port (
a : in std_logic
);
end component fifo;
component fifo is
port (
a : in std_logic
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vsg/syntastic/syntastic.vhd | 1 | 60 |
ARCHITECTURE RTL OF FIFO IS
BEGIN
END ARCHITECTURE RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/type_definition/rule_400_test_input.vhd | 1 | 535 |
architecture rtl of fifo is
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
--Violations below
type t_some_record is record
element_1: natural;
some_other_element: natural;
yet_another_element: natural;
end record;
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
begin
end architecture rtl;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/ddr3k7-core/ddr3_write_core.vhd | 1 | 15010 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: ddr3k7-core
-- Module Name: ddr3_write_core - Behavioral
-- Project Name: YARR
-- Target Devices: xc7k160t
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ddr3_write_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end ddr3_write_core;
architecture Behavioral of ddr3_write_core is
--------------------------------------
-- Components
--------------------------------------
COMPONENT fifo_605x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(604 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(604 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
--------------------------------------
-- Constants
--------------------------------------
constant c_write_wait_time : unsigned(7 downto 0) := TO_UNSIGNED(15, 8);
constant c_register_shift_size : integer := 8;
--------------------------------------
-- Types
--------------------------------------
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal wb_cyc_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_we_s : std_logic;
signal wb_adr_s : std_logic_vector(32 - 1 downto 0);
signal wb_dat_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_wr_data_shift_a : data_array;
signal wb_wr_data_shift_next_a : data_array;
signal wb_wr_data_shift_s : std_logic_vector(511 downto 0);
signal wb_wr_mask_shift_a : mask_array;
signal wb_wr_mask_shift_next_a : mask_array;
signal wb_wr_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_addr_shift_a : addr_array;
signal wb_wr_addr_shift_next_a : addr_array;
signal wb_wr_shifting_s : std_logic;
signal wb_wr_aligned : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_row_a : row_array;
signal wb_wr_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_several_row_s : std_logic;
signal wb_wr_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_shift_flush_s : std_logic;
signal wb_wr_shift_flush_1_s : std_logic;
signal fifo_wb_wr_mask_s : std_logic_vector(63 downto 0);
signal fifo_wb_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_wr_din_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_wr_s : std_logic;
signal fifo_wb_wr_rd_s : std_logic;
signal fifo_wb_wr_rd_d : std_logic;
signal fifo_wb_wr_dout_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_full_s : std_logic;
signal fifo_wb_wr_empty_s : std_logic;
--------------------------------------
-- Counter
--------------------------------------
signal wb_write_wait_cnt : unsigned(7 downto 0);
begin
rst_s <= not rst_n_i;
--------------------------------------
-- Wishbone input delay
--------------------------------------
p_wb_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_sel_s <= (others =>'0');
wb_cyc_s <= '0';
wb_stb_s <= '0';
wb_we_s <= '0';
wb_adr_s <= (others =>'0');
wb_dat_s <= (others =>'0');
elsif rising_edge(wb_clk_i) then
wb_sel_s <= wb_sel_i;
wb_cyc_s <= wb_cyc_i;
wb_stb_s <= wb_stb_i;
wb_we_s <= wb_we_i;
wb_adr_s <= wb_adr_i;
wb_dat_s <= wb_dat_i;
end if;
end process p_wb_in;
--------------------------------------
-- Wishbone ouput
--------------------------------------
wb_ack_o <= wb_ack_s;
wb_dat_o <= (others => '0');
detection_gen : if (g_NOT_CONSECUTIVE_DETECTION = true) generate
wb_stall_s <= fifo_wb_wr_full_s or wb_wr_several_row_s;
end generate;
no_dectection_gen : if (g_NOT_CONSECUTIVE_DETECTION = false) generate
wb_stall_s <= fifo_wb_wr_full_s;
end generate;
wb_stall_o <= wb_stall_s;
--------------------------------------
-- Wishbone write process
--------------------------------------
p_wb_write : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_write_wait_cnt <= c_write_wait_time;
wb_wr_shift_flush_1_s <= '0';
wb_wr_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_a(i) <= (others => '1');
wb_wr_data_shift_a(i) <= (others => '0');
wb_wr_mask_shift_a(i) <= (others => '0');
end loop;
wb_ack_s <= '0';
elsif rising_edge(wb_clk_i) then
wb_wr_shift_flush_1_s <= wb_wr_shift_flush_s;
if (wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '1') then
wb_ack_s <= '1';
wb_write_wait_cnt <= c_write_wait_time;
else
wb_ack_s <= '0';
if(wb_wr_valid_shift_s /= (wb_wr_valid_shift_s'range => '0')) then
if (wb_write_wait_cnt /= 0) then
wb_write_wait_cnt <= wb_write_wait_cnt - 1;
end if;
end if;
end if;
if(wb_wr_shift_flush_s = '1') then
wb_write_wait_cnt <= c_write_wait_time;
end if;
wb_wr_addr_shift_a <= wb_wr_addr_shift_next_a;
wb_wr_data_shift_a <= wb_wr_data_shift_next_a;
wb_wr_mask_shift_a <= wb_wr_mask_shift_next_a;
wb_wr_valid_shift_s <= wb_wr_valid_shift_next_s;
end if;
end process p_wb_write;
p_wb_write_rtl : process (wb_write_wait_cnt,wb_wr_addr_shift_a,wb_wr_valid_shift_s,wb_wr_shift_flush_s,wb_wr_first_row_s,wb_wr_row_a,wb_wr_aligned,wb_wr_global_row_s)
begin
fifo_wb_wr_addr_s <= (others => '0');
wb_wr_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_wr_global_row_s(i) = '1' then
fifo_wb_wr_addr_s <= wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_wr_first_row_s <= wb_wr_row_a(i);
end if;
end loop;
if((wb_wr_global_row_s /= wb_wr_first_row_s) and (wb_wr_global_row_s /= (wb_wr_global_row_s'range => '0'))) then
wb_wr_several_row_s <= '1';
else
wb_wr_several_row_s <= '0';
end if;
end process p_wb_write_rtl;
p_wb_write_shift: process (wb_wr_shifting_s,wb_wr_addr_shift_a,wb_wr_data_shift_a,wb_wr_mask_shift_a,wb_wr_valid_shift_s,wb_adr_s,wb_dat_s,wb_sel_s,wb_wr_flush_v_s)
begin
if(wb_wr_shifting_s = '1') then
wb_wr_addr_shift_next_a(c_register_shift_size-1) <= wb_adr_s(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_wr_data_shift_next_a(c_register_shift_size-1) <= wb_dat_s;
wb_wr_mask_shift_next_a(c_register_shift_size-1) <= wb_sel_s;
wb_wr_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_s and wb_stb_s and wb_we_s;
for i in 1 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i-1) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i-1) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i-1) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i-1) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_write_shift;
wb_wr_shifting_s <= --'0' when wb_wr_several_row_s = '1' else
'1' when wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '1' else --and wb_stall_s = '0' else
'1' when wb_write_wait_cnt = 0 else
'0';
wb_wr_global_row_s <= wb_wr_aligned and wb_wr_valid_shift_s;
wb_wr_flush_v_s <= wb_wr_first_row_s;
wb_wr_shift_flush_s <= '1' when wb_wr_flush_v_s /= (wb_wr_flush_v_s'range => '0') else
'0';
wr_mask_match_g:for i in 0 to c_register_shift_size-1 generate
wb_wr_aligned(i) <= '1' when wb_wr_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
wr_row_g:for j in 0 to c_register_shift_size-1 generate
wb_wr_row_a(i)(j) <= '1' when wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_wr_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_wr_aligned(i) = '1' and wb_wr_aligned(j) = '1' and wb_wr_valid_shift_s(i) = '1' and wb_wr_valid_shift_s(j) = '1' else
'0';
end generate;
fifo_wb_wr_mask_s((i)*8+7 downto (i)*8) <= wb_wr_mask_shift_a(i) when wb_wr_flush_v_s(i) = '1' else (others=>'0');
end generate;
wb_wr_data_shift_s <= wb_wr_data_shift_a(7) &
wb_wr_data_shift_a(6) &
wb_wr_data_shift_a(5) &
wb_wr_data_shift_a(4) &
wb_wr_data_shift_a(3) &
wb_wr_data_shift_a(2) &
wb_wr_data_shift_a(1) &
wb_wr_data_shift_a(0);
fifo_wr_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_wr_din_s <= (others => '0');
fifo_wb_wr_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_wr_din_s <= fifo_wb_wr_addr_s &
fifo_wb_wr_mask_s &
wb_wr_data_shift_s;
fifo_wb_wr_wr_s <= wb_wr_shift_flush_s;
end if;
end process;
fifo_wb_write : fifo_605x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_wr_din_s,
wr_en => fifo_wb_wr_wr_s,
rd_en => fifo_wb_wr_rd_s,
dout => fifo_wb_wr_dout_s,
full => fifo_wb_wr_full_s,
empty => fifo_wb_wr_empty_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
ddr_cmd_en_o <= fifo_wb_wr_rd_s;
ddr_addr_o <= fifo_wb_wr_dout_s(604 downto 576);
ddr_cmd_o <= "000";
--------------------------------------
-- DDR Data out
--------------------------------------
ddr_wdf_wren_o <= fifo_wb_wr_rd_s;
ddr_wdf_end_o <= fifo_wb_wr_rd_s;
ddr_wdf_data_o <= fifo_wb_wr_dout_s(511 downto 0);
ddr_wdf_mask_o <= not fifo_wb_wr_dout_s(575 downto 512);
ddr_req_o <= not fifo_wb_wr_empty_s;
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_wr_rd_s <= ddr_wdf_rdy_i and ddr_rdy_i and ddr_gnt_i and (not fifo_wb_wr_empty_s);
end Behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_004_test_input.fixed.vhd | 1 | 1041 |
architecture ARCH of ENTITY is
begin
-- Passing
PROC_2 : process (a) is
begin
a := b or -- c = '2';
c or
d = '1';
c1 := d;
e12 := f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a := b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 := d or e or
f and g;
e1 := f and x or y;
end if;
end case;
a :=
b;
end process PROC_2;
-- Violations
PROC_2 : process (a) is
begin
a := b or -- c = '2';
c or
d = '1';
c1 := d;
e12 := f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a := b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 := d or e or
f and g;
e1 := f and x or y;
end if;
end case;
a :=
b;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_012_test_input.fixed_lower.vhd | 1 | 446 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate for_label;
IF_LABEL : if a = '1' generate
end generate if_label;
CASE_LABEL : case data generate
end generate case_label;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate for_label;
IF_LABEL : if a = '1' generate
end generate if_label1;
CASE_LABEL : case data generate
end generate case_label;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_506_test_input.fixed_lower.vhd | 1 | 240 |
architecture RTL of FIFO is
function func1 return integer is begin end function f_func1_f;
FUNCTION FUNC1 RETURN INTEGER IS BEGIN END FUNCTION f_func1_f;
procedure proc1 is begin end procedure Proc1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/enumeration_type_definition/classification_test_input.vhd | 1 | 226 |
architecture RTL of FIFO is
type NotGood is (X, '0', '1', X); -- illegal
type MyBit is (L, H);
type Test is ('0', '1', L, H);
type FSM_States is (Init, Read, Decode, Execute, Write);
begin
end architecture RTL;
| gpl-3.0 |
Jorge9314/ElectronicaDigital | Impresora2D/TB_Transmission_8bits.vhd | 1 | 1777 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Transmission_8bits IS
END TB_Transmission_8bits;
ARCHITECTURE behavior OF TB_Transmission_8bits IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Transmission_8bits
PORT(
Divisor_Frecuencia : IN std_logic;
Entrada : IN std_logic_vector(7 downto 0);
Activo : IN std_logic;
Salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal Divisor_Frecuencia : std_logic := '0';
signal Entrada : std_logic_vector(7 downto 0) := (others => '0');
signal Activo : std_logic := '0';
--Outputs
signal Salida : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant Divisor_Frecuencia_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Transmission_8bits PORT MAP (
Divisor_Frecuencia => Divisor_Frecuencia,
Entrada => Entrada,
Activo => Activo,
Salida => Salida
);
-- Clock process definitions
Divisor_Frecuencia_process :process
begin
Divisor_Frecuencia <= '0';
wait for Divisor_Frecuencia_period/2;
Divisor_Frecuencia <= '1';
wait for Divisor_Frecuencia_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Entrada <= "11111111";
-- IDLE --
Activo <= '1';
wait for 20 ns;
Activo <= '0';
wait for 300 ns;
Entrada <= "01010101";
Activo <= '1';
wait for 20 ns;
Activo <= '0';
wait for 300 ns;
Entrada <= "10010001";
Activo <= '1';
wait for 20 ns;
Activo <= '0';
wait for 300 ns;
end process;
END;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/signal/rule_002_test_input.fixed_lower.vhd | 2 | 193 |
architecture RTL of FIFO is
signal sig1 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
| gpl-3.0 |
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