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jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_012_test_input.fixed.vhd | 1 | 569 |
architecture RTL of FIFO is
begin
-- These are passing
ret <=
(
data => (others => '-'),
valid => '0',
sop => '0',
eop => '0',
empty => (others => '0'),
error => (others => '0')
);
-- These are failing
ret <=
(
data => (others => '-'),
valid => '0',
sop => '0',
eop => '0',
empty => (others => '0'),
error => (others => '0')
);
-- This is not an array and should not be "fixed"
d <=
(d2 xor to_stdulogic(gen2)) &
(d1 xor to_stdulogic(gen1));
end architecture RTL;
| gpl-3.0 |
Jorge9314/ElectronicaDigital | Impresora2D/Transmission_8bits.vhd | 1 | 3092 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Transmission_8bits is
Port ( Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC_VECTOR (7 downto 0);
Activo : in STD_LOGIC;
Salida : out STD_LOGIC := '1');
end Transmission_8bits;
architecture arq_Transmission_8bits of Transmission_8bits is
signal ParidadPAR : boolean := True;
-- Significa que el estado par es VERDADERO o que es PAR
signal estado : std_logic_vector(3 downto 0) := "0000";
-- El estado va a ser de la siguiente manera
-- "0000" o estado 0 significa el estado de IDLE hasta que Activo sea 1
-- Si Activo es 1 se envia el BIT DE INICIO ('0')
-- "0001" o estado 1 significa que envia el primer bit de información
-- "0010" o estado 2 significa que envia el segundo bit de información
-- ................. significa que envia los demas bits de información
-- "1011" o estado 11 significa que envia el BIT DE PARIDAD PAR '0' para par y '1' para impar
-- "1100" o estado 12 significa que envia el primer BIT DE FINALIZACION '1'
-- "1101" o estado 13 significa que envia el segundo BIT DE FINALIZACION '1'
-- "0000" o estado 14 significa que vuelve a estar en IDLE hasta que
-- El proximo activo sea igual a '1'
begin
process begin
wait until rising_edge(Divisor_Frecuencia);
case(estado) is
when "0000" =>
if Activo = '1' then
Salida <= '0';
ParidadPAR <= False; -- En este caso decimos que si no hay 1s es PAR
estado <= "0001";
end if;
when "0001" =>
if Entrada(7) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(7);
estado <= "0010";
when "0010" =>
if Entrada(6) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(6);
estado <= "0011";
when "0011" =>
if Entrada(5) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(5);
estado <= "0100";
when "0100" =>
if Entrada(4) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(4);
estado <= "0101";
when "0101" =>
if Entrada(3) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(3);
estado <= "0111";
when "0111" =>
if Entrada(2) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(2);
estado <= "1000";
when "1000" =>
if Entrada(1) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(1);
estado <= "1001";
when "1001" =>
if Entrada(0) = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Salida <= Entrada(0);
estado <= "1011";
when "1011" =>
if ParidadPAR then
Salida <= '1';
else
Salida <= '0';
end if;
estado <= "1100";
when "1100" =>
Salida <= '1';
estado <= "1101";
when others =>
Salida <= '1';
estado <= "0000";
end case;
end process;
end arq_Transmission_8bits;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_010_test_input.fixed_add.vhd | 1 | 331 |
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end architecture;
architecture RTL of ENT is
begin
end architecture;
architecture RTL of ENT is
begin
end architecture
;
architecture RTL of ENT is
begin
end architecture--Comment
;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/subprogram_body/rule_400_test_input.fixed.vhd | 1 | 1478 | architecture arc of ent is
signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
proc_p : process (clk_i, rst_n_i)
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
if rst_n_i = '0' then
rst_procedure;
elsif rising_edge(clk_i) then
a <= (others => '1');
b <= (others => '1');
c := d;
end if;
end process proc_p;
end architecture arc;
package body my_package is
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
end package body;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_503_test_input.fixed_upper.vhd | 1 | 169 |
architecture RTL of FIFO is
begin
block_label : block is BEGIN end block block_label;
BLOCK_LABEL : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_010_test_input.fixed.vhd | 1 | 442 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_010_test_input.fixed.vhd | 1 | 221 |
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is
begin
end process;
process
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/report_statement/rule_100_test_input.fixed.vhd | 3 | 134 |
architecture rtl of fifo is
begin
process begin
report "hello";
report "hello";
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_yes.vhd | 1 | 1548 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_yes_align_paren_yes_align_when_no_wrap_at_when_yes_align_else_yes.vhd | 1 | 2190 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_032_test_input.fixed.vhd | 2 | 545 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/architecture_body/classification_test_input.vhd | 1 | 231 |
architecture RTL of ENTITY1 is
begin
end architecture RTL;
architecture RTL of ENTITY1 is
begin
end;
architecture RTL of ENTITY1 is
begin
end architecture;
architecture
RTL
of
ENTITY1
is
begin
end
architecture
RTL
;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_005_test_input.vhd | 1 | 245 |
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
FUNCTION func1 return integer is begin end function func1;
Function func1 return integer is begin end function func1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/concurrent_assertion_statement/classification_test_input.vhd | 1 | 420 |
architecture RTL of FIFO is
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
assert TRUE
report "This is a string"
severity WARNING;
LABEL : assert TRUE
report "This is a string";
LABEL : assert TRUE
severity WARNING;
postponed assert TRUE
report "This is a string";
LABEL : postponed assert TRUE
report "This is a string";
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/VGA_Top.vhd | 1 | 5460 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VGA_Top is
Port ( R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
Clk : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
button : in STD_LOGIC;
reset : in STD_LOGIC;
LED : out STD_LOGIC;
Enables : out STD_LOGIC_VECTOR(3 downto 0);
Segments : out STD_LOGIC_VECTOR(6 downto 0);
inColor : in STD_LOGIC_VECTOR (2 downto 0);
MoveUp : in STD_LOGIC;
MoveDown : in STD_LOGIC;
MoveLeft : in STD_LOGIC;
MoveRight : in STD_LOGIC;
MoveP1 : in STD_LOGIC;
MoveP2 : in STD_LOGIC);
end VGA_Top;
architecture Behavioral of VGA_Top is
COMPONENT Debouncer
PORT(
Clk : IN std_logic;
Button : IN std_logic;
Dout : OUT std_logic);
END COMPONENT;
COMPONENT Bresenhamer
PORT(
X1 : IN std_logic_vector(9 downto 0);
Y1 : IN std_logic_vector(8 downto 0);
X2 : IN std_logic_vector(9 downto 0);
Y2 : IN std_logic_vector(8 downto 0);
Clk : IN std_logic;
StartDraw : IN std_logic;
WriteEnable : OUT std_logic;
SS : OUT STD_LOGIC_VECTOR (3 downto 0);
X : OUT std_logic_vector(9 downto 0);
Y : OUT std_logic_vector(8 downto 0);
Reset : in STD_LOGIC);
END COMPONENT;
Component Synchronizer is
Port ( R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
Clk : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (2 downto 0);
AddressX : out STD_LOGIC_VECTOR (9 downto 0);
AddressY : out STD_LOGIC_VECTOR (8 downto 0));
end Component;
Component FrameBuffer is
Port ( inX : in STD_LOGIC_VECTOR (9 downto 0);
inY : in STD_LOGIC_VECTOR (8 downto 0);
outX : in STD_LOGIC_VECTOR (9 downto 0);
outY : in STD_LOGIC_VECTOR (8 downto 0);
outColor : out STD_LOGIC_VECTOR (2 downto 0);
inColor : in STD_LOGIC_VECTOR (2 downto 0);
BufferWrite : in STD_LOGIC;
Clk : in STD_LOGIC);
end Component;
COMPONENT SevenSegment
PORT( Clk : IN std_logic;
data : IN std_logic_vector(15 downto 0);
Enables : OUT std_logic_vector(3 downto 0);
Segments : OUT std_logic_vector(6 downto 0));
END COMPONENT;
COMPONENT Pointer
Generic (initX : STD_LOGIC_VECTOR (9 downto 0);
initY : STD_LOGIC_VECTOR (8 downto 0));
PORT( MoveUp : IN std_logic;
MoveDown : IN std_logic;
MoveLeft : IN std_logic;
MoveRight : IN std_logic;
Move : IN std_logic;
Clk : IN std_logic;
X : OUT std_logic_vector(9 downto 0);
Y : OUT std_logic_vector(8 downto 0);
syncX : IN std_logic_vector(9 downto 0);
syncY : IN std_logic_vector(8 downto 0);
Here : OUT std_logic);
END COMPONENT;
COMPONENT FreqDiv
PORT( Clk : IN std_logic;
Clk2 : OUT std_logic);
END COMPONENT;
signal Adx,GPU_X : STD_LOGIC_VECTOR (9 downto 0);
signal Ady,GPU_Y : STD_LOGIC_VECTOR (8 downto 0);
signal data : STD_LOGIC_VECTOR (2 downto 0);
signal GIM : STD_LOGIC_VECTOR (22 downto 0);
signal GPU_COLOR_TO_BUFFER : STD_LOGIC_VECTOR (2 downto 0);
signal BufferWrite : STD_LOGIC;
signal Dout : STD_LOGIC;
signal SS : STD_LOGIC_VECTOR (3 downto 0);
signal Clk2 : STD_LOGIC;
signal P1Region,p2Region : STD_LOGIC;
signal Rt,Gt,Bt : STD_LOGIC;
signal X1,X2 : STD_LOGIC_VECTOR (9 downto 0);
signal Y1,Y2 : STD_LOGIC_VECTOR (8 downto 0);
begin
ins_FrameBuffer : FrameBuffer PORT MAP (
inX => GPU_X,
inY => GPU_Y,
outX => Adx,
outY => Ady,
outColor => data,
inColor => inColor,
BufferWrite => BufferWrite,
Clk => Clk);
ins_Synchronizer : Synchronizer PORT MAP (
R => Rt,
G => Gt,
B => Bt,
HS => HS,
VS => VS,
Clk => Clk,
dataIn => data,
AddressX => Adx,
AddressY => Ady);
Inst_Debouncer: Debouncer PORT MAP(
Clk => Clk,
Button => Button,
Dout => Dout);
Inst_Bresenhamer: Bresenhamer PORT MAP(
WriteEnable => BufferWrite,
X => GPU_X,
Y => GPU_Y,
X1 => X1,
Y1 => Y1,
X2 => X2,
Y2 => Y2,
Clk => Clk,
SS => SS,
Reset => reset,
StartDraw => Dout);
LED <= BufferWrite;
R <= Rt when (P1Region='0' and P2Region='0') else not Rt;
G <= Gt when (P1Region='0' and P2Region='0') else not Gt;
B <= Bt when (P1Region='0' and P2Region='0') else not Bt;
Inst_SevenSegment: SevenSegment PORT MAP(
Clk => Clk,
Enables => Enables,
Segments => Segments,
data(3 downto 0) => SS,
data(15 downto 4) => "000000000000");
Inst_Pointer1: Pointer
GENERIC MAP (initX => "0000000100",
initY => "011110000")
PORT MAP(
MoveUp => MoveUp,
MoveDown => MoveDown,
MoveLeft => MoveLeft,
MoveRight => MoveRight,
Move => MoveP1,
Clk => Clk2,
Here => P1Region,
X => X1,
Y => Y1,
syncX => Adx,
syncY => Ady);
Inst_FreqDiv: FreqDiv PORT MAP(
Clk => Clk,
Clk2 => Clk2);
Inst_Pointer2: Pointer
GENERIC MAP (InitX => "1001111000",
InitY => "011110000")
PORT MAP(
MoveUp => MoveUp,
MoveDown => MoveDown,
MoveLeft => MoveLeft,
MoveRight => MoveRight,
Move => MoveP2,
Clk => Clk2,
Here => P2Region,
X => X2,
Y => Y2,
syncX => Adx,
syncY => Ady);
end Behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_003_test_input.fixed.vhd | 2 | 525 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_401_test_input.fixed.vhd | 1 | 1702 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_003_test_input.vhd | 1 | 228 |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1<= sig2;
sig2<= sig3;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_015_test_input.vhd | 1 | 168 |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant x_depth : integer := 512;
constant word : integer := 1024;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_006_test_input.fixed_lower.vhd | 4 | 88 |
entity FIFO is
end entity;
entity FIFO is
end entity;
entity FIFO is
end entity;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_010_test_input.fixed_lower.vhd | 4 | 88 |
entity FIFO is
end entity;
entity FIFO is
end entity;
entity FIFO is
end entity;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_501_test_input.fixed_upper.vhd | 1 | 109 |
package BODY fifo_pkg is
end package body fifo_pkg;
package BODY fifo_pkg is
end package body fifo_pkg;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/rtl/mcb_soft_calibration_top.vhd | 19 | 21926 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
| gpl-3.0 |
rjarzmik/mips_processor | Caches/DualPort_Cache.vhd | 1 | 5353 | -------------------------------------------------------------------------------
-- Title : Dual port cache
-- Project :
-------------------------------------------------------------------------------
-- File : DualPort_Cache.vhd
-- Author : Robert Jarzmik (Intel) <[email protected]>
-- Company :
-- Created : 2016-11-15
-- Last update: 2016-11-18
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Cache with 2 input ports and one port towards memory/next cache
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-15 1.0 rjarzmik Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity DualPort_Cache is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
i_porta_req : in std_logic;
i_porta_we : in std_logic;
i_porta_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_porta_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_valid : out std_logic;
i_portb_req : in std_logic;
i_portb_we : in std_logic;
i_portb_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_portb_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_portb_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_portb_valid : out std_logic;
o_memory_req : out std_logic;
o_memory_we : out std_logic;
o_memory_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_memory_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_valid : in std_logic
);
end entity DualPort_Cache;
-------------------------------------------------------------------------------
architecture passthrough of DualPort_Cache is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
-- access handling
signal cache_valid : boolean;
signal cache_acquiring_porta : boolean;
signal cache_acquiring_portb : boolean;
signal cache_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal cache_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
process(rst, clk) is
begin
if rst = '1' then
o_porta_valid <= '0';
o_portb_valid <= '0';
o_memory_we <= '0';
cache_valid <= false;
cache_acquiring_porta <= false;
cache_acquiring_portb <= false;
elsif rising_edge(clk) then
if cache_valid and cache_acquiring_porta then
o_porta_read_data <= cache_data;
o_porta_valid <= '1';
cache_addr <= (others => 'X');
cache_acquiring_porta <= false;
else
o_porta_valid <= '0';
o_porta_read_data <= (others => 'X');
end if;
if cache_valid and cache_acquiring_portb then
o_portb_read_data <= cache_data;
o_portb_valid <= '1';
cache_addr <= (others => 'X');
cache_acquiring_portb <= false;
else
o_portb_valid <= '0';
o_portb_read_data <= (others => 'X');
end if;
if not (cache_acquiring_porta or cache_acquiring_portb) and
(not cache_valid or (cache_addr /= i_porta_addr and cache_addr /= i_portb_addr)) then
if i_porta_req = '1' then
cache_valid <= false;
cache_data <= (others => 'X');
o_memory_addr <= i_porta_addr;
o_memory_write_data <= i_porta_write_data;
cache_addr <= i_porta_addr;
o_memory_we <= i_porta_we;
cache_acquiring_porta <= true;
elsif i_portb_req = '1' then
cache_valid <= false;
cache_data <= (others => 'X');
o_memory_addr <= i_portb_addr;
o_memory_write_data <= i_portb_write_data;
cache_addr <= i_portb_addr;
o_memory_we <= i_portb_we;
cache_acquiring_portb <= true;
end if;
end if;
if i_memory_valid = '1' then
cache_data <= i_memory_read_data;
cache_valid <= true;
end if;
end if;
end process;
o_memory_req <= '1' when cache_acquiring_porta or cache_acquiring_portb else '0';
end architecture passthrough;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/loop_statement/rule_501_test_input.vhd | 3 | 115 |
architecture rtl of fifo is
begin
process begin
loop end loop;
LOOP END LOOP;
end process;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_013_test_input.vhd | 1 | 216 |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/context/rule_015_test_input.fixed_upper.vhd | 1 | 145 |
--This should pass
context con1 is
end CONTEXT con1;
--These should fail
context con1 is
end CONTEXT con1;
context co1 is
end CONTEXT con1;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity_specification/rule_501_test_input.vhd | 1 | 176 |
architecture RTL of FIFO is
attribute coordinate of all : component is (0.0, 17.5);
attribute coordinate of ALL :component is (0.0, 17.5);
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_605_test_input.vhd | 3 | 407 |
entity FIFO is
port (
WR_EN_I : in std_logic;
DATA_O : out std_logic_vector(31 downto 0);
RD_EN_IO : inout std_logic;
DATA_O : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN : inout std_logic;
DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_013_test_input.fixed_upper.vhd | 1 | 157 |
architecture RTL of FIFO is
begin
process IS
begin
end process;
-- Violations below
process IS
begin
end process;
end architecture RTL;
| gpl-3.0 |
lvd2/zxevo | fpga/base_trdemu/sd_iface_contention_test/sim_models/T80_Reg.vhd | 15 | 4020 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_007_test_input.fixed_before_1_after_4.vhd | 1 | 419 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/attribute_declaration/rule_500_test_input.fixed_upper.vhd | 1 | 121 |
architecture RTL of FIFO is
ATTRIBUTE max_delay : time;
ATTRIBUTE MAX_DELAY : TIME;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_010_test_input.fixed.vhd | 1 | 172 |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_016_test_input.vhd | 1 | 487 |
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is -- Comment
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is-- Comment
signal a : std_logic;
begin end architecture RTL;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/code_examples/graphicsaccelerator/Synchronizer.vhd | 2 | 3132 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in std_logic;
DATAIN : in std_logic_vector(2 downto 0);
ADDRESSX : out std_logic_vector(9 downto 0);
ADDRESSY : out std_logic_vector(8 downto 0)
);
end entity SYNCHRONIZER;
architecture BEHAVIORAL of SYNCHRONIZER is
signal x, nx : std_logic_vector(10 downto 0) := (others=>'0');
signal y, ny : std_logic_vector(20 downto 0) := (others=>'0');
constant tpw : std_logic_vector(1 downto 0) := "00";
constant tbp : std_logic_vector(1 downto 0) := "01";
constant tdp : std_logic_vector(1 downto 0) := "10";
constant tfp : std_logic_vector(1 downto 0) := "11";
signal xstate : std_logic_vector(1 downto 0) := tpw;
signal ystate : std_logic_vector(1 downto 0) := tpw;
signal enabledisplay : std_logic;
signal addressofy, naddressofy : std_logic_vector(8 downto 0);
begin
nx <= x + 1;
ny <= y + 1;
naddressofy <= addressofy + 1;
HS <= '0' when xstate=tpw else
'1';
VS <= '0' when ystate=tpw else
'1';
enabledisplay <= '1' when xstate=tdp and ystate=tdp else
'0';
R <= dataIn(0) when enabledisplay='1' else
'0';
B <= dataIn(1) when enabledisplay='1' else
'0';
G <= dataIn(2) when enabledisplay='1' else
'0';
AddressX <= x(10 downto 1);
AddressY <= addressofy - 30;
process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (xstate=tpw and x(7 downto 1)="1100000") then
x <= (others=>'0');
xstate <= tbp;
elsif (xstate=tbp and x(6 downto 1)="110000") then
x <= (others=>'0');
xstate <= tdp;
elsif (xstate=tdp and x(10 downto 1)="1010000000") then
x <= (others=>'0');
xstate <= tfp;
elsif (xstate=tfp and x(5 downto 1)="10000") then
x <= (others=>'0');
xstate <= tpw;
addressofy <= naddressofy;
else
x <= nx;
end if;
if (ystate=tpw and y(12 downto 1)="11001000000") then
y <= (others=>'0');
ystate <= tbp;
elsif (ystate=tbp and y(16 downto 1)="101101010100000") then
y <= (others=>'0');
ystate <= tdp;
elsif (ystate=tdp and y(20 downto 1)="1011101110000000000") then
y <= (others=>'0');
ystate <= tfp;
elsif (ystate=tfp and y(14 downto 1)="1111101000000") then
y <= (others=>'0');
x <= (others=>'0');
ystate <= tpw;
xstate <= tpw;
addressofy <= (others=>'0');
else
y <= ny;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block_comment/rule_001_test_input.align_left.vhd | 1 | 1031 |
------------------------------<- 80 chars ->------------------------------
--| Comment
--| Comment
--------------------------------------------------------------------------------
architecture rtl of fifo is
------------------------------<- 80 chars ->------------------------------
--| Comment
--| Comment
--------------------------------------------------------------------------------
begin
process
------------------------------<- 80 chars ->------------------------------
--| Comment
--| Comment
--------------------------------------------------------------------------------
begin
------------------------------<- 80 chars ->------------------------------
--| Comment
--| Comment
--------------------------------------------------------------------------------
end process;
end architecture rtl;
------------------------------<- 80 chars ->------------------------------
--| Comment
--| Comment
--------------------------------------------------------------------------------
| gpl-3.0 |
Yarr/Yarr-fw | syn/kintex7/xpressk7_160_type.vhd | 1 | 175 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package hw_type_pkg is
constant c_HW_IDENT : std_logic_vector(7 downto 0) := x"03";
end hw_type_pkg;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/use_clause/rule_503_test_input.vhd | 1 | 61 |
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.ALL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_004_test_input.fixed_lower.vhd | 1 | 294 |
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
procedure proc1 is Begin end procedure proc1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package/rule_010_test_input.fixed_lower.vhd | 7 | 71 |
package fifo_pkg is
end package;
package fifo_pkg is
end package;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_033_test_input.fixed_add.vhd | 1 | 589 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : component INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_ENTITY_INST : entity FIFO(rtl);
-- Violations below
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1:component INST
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_004_test_input.fixed.vhd | 1 | 422 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
c <= d;
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a = '1' generate
end generate;
b <= c;
CASE_LABEL : case data generate
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_401_test_input.vhd | 1 | 500 |
architecture rtl of fifo is
begin
-- Valid formatting
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
-- Invalid formatting
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
connect_ports(
port_1=> data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/iteration_scheme/rule_501_test_input.vhd | 1 | 161 |
architecture rtl of fifo is
begin
process begin
for x in (31 downto 0) loop end loop;
FOR x in (31 downto 0) loop end loop;
end process;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_026_test_input.fixed_no_blank.vhd | 1 | 515 |
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
process
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_022_test_input.fixed.vhd | 6 | 405 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_009_test_input.vhd | 1 | 151 |
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end PROCESS;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_017_test_input.fixed_record_constraint_comma__remove_new_line.vhd | 1 | 579 | architecture rtl of fifo is
constant sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)
(6
downto 0),
elementF(7 downto 0)
),
element6(4 downto
0),
element7(7 downto 0));
constant sig9 : t_data_struct(data(7 downto 0));
constant sig9 : t_data_struct(
data(7 downto 0)
);
begin
end architecture rtl;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/spartan6/serdes_n_to_1_s2_diff.vhd | 2 | 11029 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_n_to_1_s2_diff is
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_s2_diff;
architecture arch_serdes_n_to_1_s2_diff of serdes_n_to_1_s2_diff is
signal cascade_di : std_logic_vector(D-1 downto 0);
signal cascade_do : std_logic_vector(D-1 downto 0);
signal cascade_ti : std_logic_vector(D-1 downto 0);
signal cascade_to : std_logic_vector(D-1 downto 0);
signal mdataina : std_logic_vector(D*8 downto 0);
signal mdatainb : std_logic_vector(D*4 downto 0);
signal tx_data_out : std_logic_vector(D-1 downto 0);
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0'); -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i);
end generate;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i);
end generate;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate;
end generate;
end arch_serdes_n_to_1_s2_diff;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package/rule_402_test_input.fixed.vhd | 1 | 214 |
package fifo_pkg is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
end package;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_506_test_input.vhd | 1 | 109 |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package BODY fifo_pkg;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_503_test_input.fixed_lower.vhd | 1 | 169 |
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
BLOCK_LABEL : BLOCK IS begin END BLOCK BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_007_test_input.vhd | 1 | 431 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN :in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN :in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/FrameBuffer2.vhd | 1 | 1393 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity FrameBuffer is
Port ( inX : in STD_LOGIC_VECTOR (9 downto 0);
inY : in STD_LOGIC_VECTOR (8 downto 0);
outX : in STD_LOGIC_VECTOR (9 downto 0);
outY : in STD_LOGIC_VECTOR (8 downto 0);
outColor : out STD_LOGIC_VECTOR (2 downto 0);
inColor : in STD_LOGIC_VECTOR (2 downto 0);
BufferWrite : in STD_LOGIC;
Clk : in STD_LOGIC);
end FrameBuffer;
architecture Behavioral of FrameBuffer is
type FBuffer is array (0 to 524288/16-1) of std_logic_vector (2 downto 0);
impure function initFB return FBuffer is
variable temp : FBuffer;
variable i : integer;
begin
for i in 0 to 524288/16-1 loop
temp(i) := "000";
end loop;
return temp;
end initFB;
signal mybuffer : FBuffer := initFB;
signal addressWrite,addressRead : STD_LOGIC_VECTOR (14 downto 0);
signal temp : STD_LOGIC_VECTOR (2 downto 0);
begin
addressWrite <= inX(9 downto 2) & inY(8 downto 2);
addressRead <= outX(9 downto 2) & outY(8 downto 2);
outColor <= temp;
process (clk) begin
if (rising_edge(Clk)) then
if (BufferWrite = '1') then
mybuffer(conv_integer(addressWrite)) <= inColor;
end if;
temp <= mybuffer(conv_integer(addressRead));
end if;
end process;
end Behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_201_test_input.vhd | 1 | 239 | library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
-- Comments are not allowed
end package body;
library ieee;
package body fifo_pkg is
constant a : std_logic;
end package body;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/use_clause/rule_501_test_input.vhd | 3 | 149 |
use My_Math_Stuff.MY_STRING_STUFF.my_math_stuff;
use My_Math_Stuff.My_Math_Stuff.my_math_stuff;
use My_Logic_Stuff.my_logic_stuff.MY_MATH_STUFF;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/dma_controller_wb_slave.vhd | 4 | 31222 | ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for GN4124 core DMA controller
---------------------------------------------------------------------------------------
-- File : async_regs.vhd
-- Author : auto-generated by wbgen2 from async_regs.wb
-- Created : Wed Oct 6 15:30:35 2010
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE async_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_controller_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_i : in std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA engine control' in reg: 'DMACTRLR'
dma_ctrl_o : out std_logic_vector(31 downto 0);
dma_ctrl_i : in std_logic_vector(31 downto 0);
dma_ctrl_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA engine status' in reg: 'DMASTATR'
dma_stat_o : out std_logic_vector(31 downto 0);
dma_stat_i : in std_logic_vector(31 downto 0);
dma_stat_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address in the carrier' in reg: 'DMACSTARTR'
dma_cstart_o : out std_logic_vector(31 downto 0);
dma_cstart_i : in std_logic_vector(31 downto 0);
dma_cstart_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address (low) in the host' in reg: 'DMAHSTARTLR'
dma_hstartl_o : out std_logic_vector(31 downto 0);
dma_hstartl_i : in std_logic_vector(31 downto 0);
dma_hstartl_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address (high) in the host' in reg: 'DMAHSTARTHR'
dma_hstarth_o : out std_logic_vector(31 downto 0);
dma_hstarth_i : in std_logic_vector(31 downto 0);
dma_hstarth_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA read length in bytes' in reg: 'DMALENR'
dma_len_o : out std_logic_vector(31 downto 0);
dma_len_i : in std_logic_vector(31 downto 0);
dma_len_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'Pointer (low) to next item in list' in reg: 'DMANEXTLR'
dma_nextl_o : out std_logic_vector(31 downto 0);
dma_nextl_i : in std_logic_vector(31 downto 0);
dma_nextl_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'Pointer (high) to next item in list' in reg: 'DMANEXTHR'
dma_nexth_o : out std_logic_vector(31 downto 0);
dma_nexth_i : in std_logic_vector(31 downto 0);
dma_nexth_load_o : out std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA chain control' in reg: 'DMAATTRIBR'
dma_attrib_o : out std_logic_vector(31 downto 0);
dma_attrib_i : in std_logic_vector(31 downto 0);
dma_attrib_load_o : out std_logic
);
end dma_controller_wb_slave;
architecture syn of dma_controller_wb_slave is
signal dma_ctrl_int_read : std_logic_vector(31 downto 0);
signal dma_ctrl_int_write : std_logic_vector(31 downto 0);
signal dma_ctrl_lw : std_logic ;
signal dma_ctrl_lw_delay : std_logic ;
signal dma_ctrl_lw_read_in_progress : std_logic ;
signal dma_ctrl_lw_s0 : std_logic ;
signal dma_ctrl_lw_s1 : std_logic ;
signal dma_ctrl_lw_s2 : std_logic ;
signal dma_ctrl_rwsel : std_logic ;
signal dma_stat_int_read : std_logic_vector(31 downto 0);
signal dma_stat_int_write : std_logic_vector(31 downto 0);
signal dma_stat_lw : std_logic ;
signal dma_stat_lw_delay : std_logic ;
signal dma_stat_lw_read_in_progress : std_logic ;
signal dma_stat_lw_s0 : std_logic ;
signal dma_stat_lw_s1 : std_logic ;
signal dma_stat_lw_s2 : std_logic ;
signal dma_stat_rwsel : std_logic ;
signal dma_cstart_int_read : std_logic_vector(31 downto 0);
signal dma_cstart_int_write : std_logic_vector(31 downto 0);
signal dma_cstart_lw : std_logic ;
signal dma_cstart_lw_delay : std_logic ;
signal dma_cstart_lw_read_in_progress : std_logic ;
signal dma_cstart_lw_s0 : std_logic ;
signal dma_cstart_lw_s1 : std_logic ;
signal dma_cstart_lw_s2 : std_logic ;
signal dma_cstart_rwsel : std_logic ;
signal dma_hstartl_int_read : std_logic_vector(31 downto 0);
signal dma_hstartl_int_write : std_logic_vector(31 downto 0);
signal dma_hstartl_lw : std_logic ;
signal dma_hstartl_lw_delay : std_logic ;
signal dma_hstartl_lw_read_in_progress : std_logic ;
signal dma_hstartl_lw_s0 : std_logic ;
signal dma_hstartl_lw_s1 : std_logic ;
signal dma_hstartl_lw_s2 : std_logic ;
signal dma_hstartl_rwsel : std_logic ;
signal dma_hstarth_int_read : std_logic_vector(31 downto 0);
signal dma_hstarth_int_write : std_logic_vector(31 downto 0);
signal dma_hstarth_lw : std_logic ;
signal dma_hstarth_lw_delay : std_logic ;
signal dma_hstarth_lw_read_in_progress : std_logic ;
signal dma_hstarth_lw_s0 : std_logic ;
signal dma_hstarth_lw_s1 : std_logic ;
signal dma_hstarth_lw_s2 : std_logic ;
signal dma_hstarth_rwsel : std_logic ;
signal dma_len_int_read : std_logic_vector(31 downto 0);
signal dma_len_int_write : std_logic_vector(31 downto 0);
signal dma_len_lw : std_logic ;
signal dma_len_lw_delay : std_logic ;
signal dma_len_lw_read_in_progress : std_logic ;
signal dma_len_lw_s0 : std_logic ;
signal dma_len_lw_s1 : std_logic ;
signal dma_len_lw_s2 : std_logic ;
signal dma_len_rwsel : std_logic ;
signal dma_nextl_int_read : std_logic_vector(31 downto 0);
signal dma_nextl_int_write : std_logic_vector(31 downto 0);
signal dma_nextl_lw : std_logic ;
signal dma_nextl_lw_delay : std_logic ;
signal dma_nextl_lw_read_in_progress : std_logic ;
signal dma_nextl_lw_s0 : std_logic ;
signal dma_nextl_lw_s1 : std_logic ;
signal dma_nextl_lw_s2 : std_logic ;
signal dma_nextl_rwsel : std_logic ;
signal dma_nexth_int_read : std_logic_vector(31 downto 0);
signal dma_nexth_int_write : std_logic_vector(31 downto 0);
signal dma_nexth_lw : std_logic ;
signal dma_nexth_lw_delay : std_logic ;
signal dma_nexth_lw_read_in_progress : std_logic ;
signal dma_nexth_lw_s0 : std_logic ;
signal dma_nexth_lw_s1 : std_logic ;
signal dma_nexth_lw_s2 : std_logic ;
signal dma_nexth_rwsel : std_logic ;
signal dma_attrib_int_read : std_logic_vector(31 downto 0);
signal dma_attrib_int_write : std_logic_vector(31 downto 0);
signal dma_attrib_lw : std_logic ;
signal dma_attrib_lw_delay : std_logic ;
signal dma_attrib_lw_read_in_progress : std_logic ;
signal dma_attrib_lw_s0 : std_logic ;
signal dma_attrib_lw_s1 : std_logic ;
signal dma_attrib_lw_s2 : std_logic ;
signal dma_attrib_rwsel : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dma_ctrl_lw <= '0';
dma_ctrl_lw_delay <= '0';
dma_ctrl_lw_read_in_progress <= '0';
dma_ctrl_rwsel <= '0';
dma_ctrl_int_write <= "00000000000000000000000000000000";
dma_stat_lw <= '0';
dma_stat_lw_delay <= '0';
dma_stat_lw_read_in_progress <= '0';
dma_stat_rwsel <= '0';
dma_stat_int_write <= "00000000000000000000000000000000";
dma_cstart_lw <= '0';
dma_cstart_lw_delay <= '0';
dma_cstart_lw_read_in_progress <= '0';
dma_cstart_rwsel <= '0';
dma_cstart_int_write <= "00000000000000000000000000000000";
dma_hstartl_lw <= '0';
dma_hstartl_lw_delay <= '0';
dma_hstartl_lw_read_in_progress <= '0';
dma_hstartl_rwsel <= '0';
dma_hstartl_int_write <= "00000000000000000000000000000000";
dma_hstarth_lw <= '0';
dma_hstarth_lw_delay <= '0';
dma_hstarth_lw_read_in_progress <= '0';
dma_hstarth_rwsel <= '0';
dma_hstarth_int_write <= "00000000000000000000000000000000";
dma_len_lw <= '0';
dma_len_lw_delay <= '0';
dma_len_lw_read_in_progress <= '0';
dma_len_rwsel <= '0';
dma_len_int_write <= "00000000000000000000000000000000";
dma_nextl_lw <= '0';
dma_nextl_lw_delay <= '0';
dma_nextl_lw_read_in_progress <= '0';
dma_nextl_rwsel <= '0';
dma_nextl_int_write <= "00000000000000000000000000000000";
dma_nexth_lw <= '0';
dma_nexth_lw_delay <= '0';
dma_nexth_lw_read_in_progress <= '0';
dma_nexth_rwsel <= '0';
dma_nexth_int_write <= "00000000000000000000000000000000";
dma_attrib_lw <= '0';
dma_attrib_lw_delay <= '0';
dma_attrib_lw_read_in_progress <= '0';
dma_attrib_rwsel <= '0';
dma_attrib_int_write <= "00000000000000000000000000000000";
elsif rising_edge(wb_clk_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
dma_ctrl_lw <= dma_ctrl_lw_delay;
dma_ctrl_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_ctrl_lw_read_in_progress = '1')) then
dma_ctrl_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_ctrl_int_read;
end if;
dma_stat_lw <= dma_stat_lw_delay;
dma_stat_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_stat_lw_read_in_progress = '1')) then
dma_stat_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_stat_int_read;
end if;
dma_cstart_lw <= dma_cstart_lw_delay;
dma_cstart_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_cstart_lw_read_in_progress = '1')) then
dma_cstart_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_cstart_int_read;
end if;
dma_hstartl_lw <= dma_hstartl_lw_delay;
dma_hstartl_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_hstartl_lw_read_in_progress = '1')) then
dma_hstartl_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_hstartl_int_read;
end if;
dma_hstarth_lw <= dma_hstarth_lw_delay;
dma_hstarth_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_hstarth_lw_read_in_progress = '1')) then
dma_hstarth_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_hstarth_int_read;
end if;
dma_len_lw <= dma_len_lw_delay;
dma_len_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_len_lw_read_in_progress = '1')) then
dma_len_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_len_int_read;
end if;
dma_nextl_lw <= dma_nextl_lw_delay;
dma_nextl_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_nextl_lw_read_in_progress = '1')) then
dma_nextl_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_nextl_int_read;
end if;
dma_nexth_lw <= dma_nexth_lw_delay;
dma_nexth_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_nexth_lw_read_in_progress = '1')) then
dma_nexth_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_nexth_int_read;
end if;
dma_attrib_lw <= dma_attrib_lw_delay;
dma_attrib_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (dma_attrib_lw_read_in_progress = '1')) then
dma_attrib_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= dma_attrib_int_read;
end if;
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
dma_ctrl_int_write <= wrdata_reg(31 downto 0);
dma_ctrl_lw <= '1';
dma_ctrl_lw_delay <= '1';
dma_ctrl_lw_read_in_progress <= '0';
dma_ctrl_rwsel <= '1';
else
dma_ctrl_lw <= '1';
dma_ctrl_lw_delay <= '1';
dma_ctrl_lw_read_in_progress <= '1';
dma_ctrl_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
dma_stat_int_write <= wrdata_reg(31 downto 0);
dma_stat_lw <= '1';
dma_stat_lw_delay <= '1';
dma_stat_lw_read_in_progress <= '0';
dma_stat_rwsel <= '1';
else
dma_stat_lw <= '1';
dma_stat_lw_delay <= '1';
dma_stat_lw_read_in_progress <= '1';
dma_stat_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
dma_cstart_int_write <= wrdata_reg(31 downto 0);
dma_cstart_lw <= '1';
dma_cstart_lw_delay <= '1';
dma_cstart_lw_read_in_progress <= '0';
dma_cstart_rwsel <= '1';
else
dma_cstart_lw <= '1';
dma_cstart_lw_delay <= '1';
dma_cstart_lw_read_in_progress <= '1';
dma_cstart_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
dma_hstartl_int_write <= wrdata_reg(31 downto 0);
dma_hstartl_lw <= '1';
dma_hstartl_lw_delay <= '1';
dma_hstartl_lw_read_in_progress <= '0';
dma_hstartl_rwsel <= '1';
else
dma_hstartl_lw <= '1';
dma_hstartl_lw_delay <= '1';
dma_hstartl_lw_read_in_progress <= '1';
dma_hstartl_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
dma_hstarth_int_write <= wrdata_reg(31 downto 0);
dma_hstarth_lw <= '1';
dma_hstarth_lw_delay <= '1';
dma_hstarth_lw_read_in_progress <= '0';
dma_hstarth_rwsel <= '1';
else
dma_hstarth_lw <= '1';
dma_hstarth_lw_delay <= '1';
dma_hstarth_lw_read_in_progress <= '1';
dma_hstarth_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
dma_len_int_write <= wrdata_reg(31 downto 0);
dma_len_lw <= '1';
dma_len_lw_delay <= '1';
dma_len_lw_read_in_progress <= '0';
dma_len_rwsel <= '1';
else
dma_len_lw <= '1';
dma_len_lw_delay <= '1';
dma_len_lw_read_in_progress <= '1';
dma_len_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
dma_nextl_int_write <= wrdata_reg(31 downto 0);
dma_nextl_lw <= '1';
dma_nextl_lw_delay <= '1';
dma_nextl_lw_read_in_progress <= '0';
dma_nextl_rwsel <= '1';
else
dma_nextl_lw <= '1';
dma_nextl_lw_delay <= '1';
dma_nextl_lw_read_in_progress <= '1';
dma_nextl_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
dma_nexth_int_write <= wrdata_reg(31 downto 0);
dma_nexth_lw <= '1';
dma_nexth_lw_delay <= '1';
dma_nexth_lw_read_in_progress <= '0';
dma_nexth_rwsel <= '1';
else
dma_nexth_lw <= '1';
dma_nexth_lw_delay <= '1';
dma_nexth_lw_read_in_progress <= '1';
dma_nexth_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
dma_attrib_int_write <= wrdata_reg(31 downto 0);
dma_attrib_lw <= '1';
dma_attrib_lw_delay <= '1';
dma_attrib_lw_read_in_progress <= '0';
dma_attrib_rwsel <= '1';
else
dma_attrib_lw <= '1';
dma_attrib_lw_delay <= '1';
dma_attrib_lw_read_in_progress <= '1';
dma_attrib_rwsel <= '0';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- DMA engine control
-- asynchronous std_logic_vector register : DMA engine control (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_ctrl_lw_s0 <= '0';
dma_ctrl_lw_s1 <= '0';
dma_ctrl_lw_s2 <= '0';
dma_ctrl_o <= "00000000000000000000000000000000";
dma_ctrl_load_o <= '0';
dma_ctrl_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_ctrl_lw_s0 <= dma_ctrl_lw;
dma_ctrl_lw_s1 <= dma_ctrl_lw_s0;
dma_ctrl_lw_s2 <= dma_ctrl_lw_s1;
if ((dma_ctrl_lw_s2 = '0') and (dma_ctrl_lw_s1 = '1')) then
if (dma_ctrl_rwsel = '1') then
dma_ctrl_o <= dma_ctrl_int_write;
dma_ctrl_load_o <= '1';
else
dma_ctrl_load_o <= '0';
dma_ctrl_int_read <= dma_ctrl_i;
end if;
else
dma_ctrl_load_o <= '0';
end if;
end if;
end process;
-- DMA engine status
-- asynchronous std_logic_vector register : DMA engine status (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_stat_lw_s0 <= '0';
dma_stat_lw_s1 <= '0';
dma_stat_lw_s2 <= '0';
dma_stat_o <= "00000000000000000000000000000000";
dma_stat_load_o <= '0';
dma_stat_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_stat_lw_s0 <= dma_stat_lw;
dma_stat_lw_s1 <= dma_stat_lw_s0;
dma_stat_lw_s2 <= dma_stat_lw_s1;
if ((dma_stat_lw_s2 = '0') and (dma_stat_lw_s1 = '1')) then
if (dma_stat_rwsel = '1') then
dma_stat_o <= dma_stat_int_write;
dma_stat_load_o <= '1';
else
dma_stat_load_o <= '0';
dma_stat_int_read <= dma_stat_i;
end if;
else
dma_stat_load_o <= '0';
end if;
end if;
end process;
-- DMA start address in the carrier
-- asynchronous std_logic_vector register : DMA start address in the carrier (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_cstart_lw_s0 <= '0';
dma_cstart_lw_s1 <= '0';
dma_cstart_lw_s2 <= '0';
dma_cstart_o <= "00000000000000000000000000000000";
dma_cstart_load_o <= '0';
dma_cstart_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_cstart_lw_s0 <= dma_cstart_lw;
dma_cstart_lw_s1 <= dma_cstart_lw_s0;
dma_cstart_lw_s2 <= dma_cstart_lw_s1;
if ((dma_cstart_lw_s2 = '0') and (dma_cstart_lw_s1 = '1')) then
if (dma_cstart_rwsel = '1') then
dma_cstart_o <= dma_cstart_int_write;
dma_cstart_load_o <= '1';
else
dma_cstart_load_o <= '0';
dma_cstart_int_read <= dma_cstart_i;
end if;
else
dma_cstart_load_o <= '0';
end if;
end if;
end process;
-- DMA start address (low) in the host
-- asynchronous std_logic_vector register : DMA start address (low) in the host (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_hstartl_lw_s0 <= '0';
dma_hstartl_lw_s1 <= '0';
dma_hstartl_lw_s2 <= '0';
dma_hstartl_o <= "00000000000000000000000000000000";
dma_hstartl_load_o <= '0';
dma_hstartl_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_hstartl_lw_s0 <= dma_hstartl_lw;
dma_hstartl_lw_s1 <= dma_hstartl_lw_s0;
dma_hstartl_lw_s2 <= dma_hstartl_lw_s1;
if ((dma_hstartl_lw_s2 = '0') and (dma_hstartl_lw_s1 = '1')) then
if (dma_hstartl_rwsel = '1') then
dma_hstartl_o <= dma_hstartl_int_write;
dma_hstartl_load_o <= '1';
else
dma_hstartl_load_o <= '0';
dma_hstartl_int_read <= dma_hstartl_i;
end if;
else
dma_hstartl_load_o <= '0';
end if;
end if;
end process;
-- DMA start address (high) in the host
-- asynchronous std_logic_vector register : DMA start address (high) in the host (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_hstarth_lw_s0 <= '0';
dma_hstarth_lw_s1 <= '0';
dma_hstarth_lw_s2 <= '0';
dma_hstarth_o <= "00000000000000000000000000000000";
dma_hstarth_load_o <= '0';
dma_hstarth_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_hstarth_lw_s0 <= dma_hstarth_lw;
dma_hstarth_lw_s1 <= dma_hstarth_lw_s0;
dma_hstarth_lw_s2 <= dma_hstarth_lw_s1;
if ((dma_hstarth_lw_s2 = '0') and (dma_hstarth_lw_s1 = '1')) then
if (dma_hstarth_rwsel = '1') then
dma_hstarth_o <= dma_hstarth_int_write;
dma_hstarth_load_o <= '1';
else
dma_hstarth_load_o <= '0';
dma_hstarth_int_read <= dma_hstarth_i;
end if;
else
dma_hstarth_load_o <= '0';
end if;
end if;
end process;
-- DMA read length in bytes
-- asynchronous std_logic_vector register : DMA read length in bytes (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_len_lw_s0 <= '0';
dma_len_lw_s1 <= '0';
dma_len_lw_s2 <= '0';
dma_len_o <= "00000000000000000000000000000000";
dma_len_load_o <= '0';
dma_len_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_len_lw_s0 <= dma_len_lw;
dma_len_lw_s1 <= dma_len_lw_s0;
dma_len_lw_s2 <= dma_len_lw_s1;
if ((dma_len_lw_s2 = '0') and (dma_len_lw_s1 = '1')) then
if (dma_len_rwsel = '1') then
dma_len_o <= dma_len_int_write;
dma_len_load_o <= '1';
else
dma_len_load_o <= '0';
dma_len_int_read <= dma_len_i;
end if;
else
dma_len_load_o <= '0';
end if;
end if;
end process;
-- Pointer (low) to next item in list
-- asynchronous std_logic_vector register : Pointer (low) to next item in list (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_nextl_lw_s0 <= '0';
dma_nextl_lw_s1 <= '0';
dma_nextl_lw_s2 <= '0';
dma_nextl_o <= "00000000000000000000000000000000";
dma_nextl_load_o <= '0';
dma_nextl_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_nextl_lw_s0 <= dma_nextl_lw;
dma_nextl_lw_s1 <= dma_nextl_lw_s0;
dma_nextl_lw_s2 <= dma_nextl_lw_s1;
if ((dma_nextl_lw_s2 = '0') and (dma_nextl_lw_s1 = '1')) then
if (dma_nextl_rwsel = '1') then
dma_nextl_o <= dma_nextl_int_write;
dma_nextl_load_o <= '1';
else
dma_nextl_load_o <= '0';
dma_nextl_int_read <= dma_nextl_i;
end if;
else
dma_nextl_load_o <= '0';
end if;
end if;
end process;
-- Pointer (high) to next item in list
-- asynchronous std_logic_vector register : Pointer (high) to next item in list (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_nexth_lw_s0 <= '0';
dma_nexth_lw_s1 <= '0';
dma_nexth_lw_s2 <= '0';
dma_nexth_o <= "00000000000000000000000000000000";
dma_nexth_load_o <= '0';
dma_nexth_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_nexth_lw_s0 <= dma_nexth_lw;
dma_nexth_lw_s1 <= dma_nexth_lw_s0;
dma_nexth_lw_s2 <= dma_nexth_lw_s1;
if ((dma_nexth_lw_s2 = '0') and (dma_nexth_lw_s1 = '1')) then
if (dma_nexth_rwsel = '1') then
dma_nexth_o <= dma_nexth_int_write;
dma_nexth_load_o <= '1';
else
dma_nexth_load_o <= '0';
dma_nexth_int_read <= dma_nexth_i;
end if;
else
dma_nexth_load_o <= '0';
end if;
end if;
end process;
-- DMA chain control
-- asynchronous std_logic_vector register : DMA chain control (type RW/WO, clk_i <-> wb_clk_i)
process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_attrib_lw_s0 <= '0';
dma_attrib_lw_s1 <= '0';
dma_attrib_lw_s2 <= '0';
dma_attrib_o <= "00000000000000000000000000000000";
dma_attrib_load_o <= '0';
dma_attrib_int_read <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
dma_attrib_lw_s0 <= dma_attrib_lw;
dma_attrib_lw_s1 <= dma_attrib_lw_s0;
dma_attrib_lw_s2 <= dma_attrib_lw_s1;
if ((dma_attrib_lw_s2 = '0') and (dma_attrib_lw_s1 = '1')) then
if (dma_attrib_rwsel = '1') then
dma_attrib_o <= dma_attrib_int_write;
dma_attrib_load_o <= '1';
else
dma_attrib_load_o <= '0';
dma_attrib_int_read <= dma_attrib_i;
end if;
else
dma_attrib_load_o <= '0';
end if;
end if;
end process;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/component_instantiation_statement/classification_test_input.vhd | 1 | 3385 |
architecture ARCH of ENTITY is
begin
-- Component instantiation without component keyword.
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : INST1;
-- Component instantiation with component keyword.
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : component INST1;
-- entity without architecture identifier
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1;
-- entity without architecture identifier and with library identifier
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity my_lib.INST1;
-- entity with architecture identifier
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1 (rtl);
-- configuration
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : configuration INST1;
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_002_test_input.fixed_w_0_spaces.vhd | 1 | 379 |
architecture RTL of FIFO is
begin
FOR_LABEL: for i in 0 to 7 generate
end generate;
IF_LABEL: if a = '1' generate
end generate;
CASE_LABEL: case data generate
end generate;
-- Violations below
FOR_LABEL: for i in 0 to 7 generate
end generate;
IF_LABEL: if a = '1' generate
end generate;
CASE_LABEL: case data generate
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_029_test_input.vhd | 1 | 421 |
architecture RTL of FIFO is
begin
process
begin
if (rst = c_asserted) then
elsif (clk'event and clk = '1') then
end if;
if (rst = c_asserted) then
elsif (clk'event and clk = '0') then
end if;
if (rst = c_asserted) then
elsif (rising_edge(clk)) then
end if;
if (rst = c_asserted) then
elsif (falling_edge(clk)) then
end if;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_004_test_input.fixed_upper.vhd | 1 | 88 |
ENTITY FIFO is
end entity;
ENTITY FIFO is
end entity;
ENTITY FIFO is
end entity;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_012_test_input.vhd | 1 | 4020 |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_012_test_input.fixed.vhd | 1 | 403 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
when STATE_1 => -- This is okay
a <= b;
when STATE_1 =>-- This is okay
a <= b;
when STATE_2 =>
a <= b;
when STATE_3 =>
a <= b;
when STATE_4 =>
null;
end case;
end process PROC_1;
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/report_statement/rule_002_test_input.vhd | 1 | 174 |
architecture rtl of fifo is
begin
process begin
report "hello" severity FAILURE;
report "hello"
severity FAILURE;
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_014_test_input.fixed_lower.vhd | 2 | 245 |
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/record_type_definition/rule_200_test_input.vhd | 1 | 307 |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_009_test_input.fixed_lower.vhd | 4 | 151 |
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/trigger-logic/eudet_tlu.vhd | 1 | 5789 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eudet_tlu is
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
deadtime_i : IN std_logic_vector(15 downto 0);
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end eudet_tlu;
architecture rtl of eudet_tlu is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
-- constants
signal C_DEADTIME : integer := 2000; -- clk_i cycles
signal C_CLKDIVIDER : integer := 16; -- 160 MHz -> 10Mhz
-- State machine
type state_type is (IDLE, TRIGGER, RECEIVE, DEAD);
signal state : state_type;
-- Sync inputs
signal sync_eudet_trig_t : std_logic;
signal sync_eudet_rst_i : std_logic;
signal trig_tag_t : std_logic_vector(15 downto 0); -- only 15:1 good
signal eudet_busy_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_bust_t : std_logic;
signal clk_counter : unsigned (7 downto 0);
signal bit_counter : unsigned (4 downto 0);
signal dead_counter : unsigned (15 downto 0);
signal deadtime_t : std_logic_vector(15 downto 0);
begin
-- Sync async inputs
trig_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_trig_i, sync_out => sync_eudet_trig_t);
rst_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_rst_i, sync_out => sync_eudet_rst_i);
eudet_busy_o <= eudet_busy_t;
eudet_clk_o <= eudet_clk_t;
rst_o <= '0';
state_machine: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
state <= IDLE;
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
dead_counter <= (others => '0');
deadtime_t <= (others => '0');
trig_tag_t <= (others => '0');
trig_tag_o <= (others => '0');
trig_o <= '0';
elsif rising_edge(clk_i) then
case state is
when IDLE =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_o <= '0';
if (sync_eudet_trig_t = '1') then
state <= TRIGGER;
end if;
when TRIGGER =>
-- Raise busy and wait until trigger is negated
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_tag_t <= (others => '0');
dead_counter <= (others => '0');
if (sync_eudet_trig_t = '0' and simple_mode_i = '0') then
state <= RECEIVE;
elsif (sync_eudet_trig_t = '0' and simple_mode_i = '1') then
state <= DEAD;
end if;
when RECEIVE =>
eudet_busy_t <= '1';
trig_o <= '0';
clk_counter <= clk_counter + 1;
dead_counter <= (others => '0');
if (clk_counter = (C_CLKDIVIDER-1)) then
clk_counter <= (others => '0');
eudet_clk_t <= not eudet_clk_t;
if (eudet_clk_t = '1') then --sampling on negative edge
bit_counter <= bit_counter + 1;
trig_tag_t <= eudet_trig_i & trig_tag_t(15 downto 1); -- do not need synced vers here
end if;
end if;
if (bit_counter = "10000") then
state <= DEAD;
trig_tag_o <= '0' & trig_tag_t(14 downto 0);
end if;
when DEAD =>
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
if (dead_counter = 0) then
trig_o <= '1'; -- Trigger now (16 clock cycles after the initial trigger?)
end if;
dead_counter <= dead_counter + 1;
if (dead_counter >= unsigned(deadtime_t) and busy_i = '0') then
state <= IDLE;
end if;
when others =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
state <= IDLE;
end case;
deadtime_t <= deadtime_i;
end if;
end process state_machine;
end rtl;
| gpl-3.0 |
rjarzmik/mips_processor | Caches/cache_defs.vhd | 1 | 8140 | -------------------------------------------------------------------------------
-- Title : Cache definitions
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : cache_defs.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-15
-- Last update: 2017-01-01
-- Platform :
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-15 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
package cache_defs is
-- Constants for Singleport_Associative_Cache_tb
constant ADDR_WIDTH : natural := 32;
constant DATA_WIDTH : natural := 32;
constant DATAS_PER_LINE_WIDTH : natural := 1;
constant INDEX_WIDTH : natural := 1;
constant WAYS_WIDTH : natural := 1;
--constant ADDR_WIDTH : natural := 32;
--constant DATA_WIDTH : natural := 32;
--constant DATAS_PER_LINE_WIDTH : natural := 4;
--constant INDEX_WIDTH : natural := 7;
--constant WAYS_WIDTH : natural := 2;
-- Infered constants
constant NB_LINES : natural := 2**INDEX_WIDTH;
constant DATAS_PER_LINE : natural := 2**DATAS_PER_LINE_WIDTH;
constant NB_WAYS : natural := 2**WAYS_WIDTH;
constant ADDR_DATA_NBITS : natural := integer(log2(real(DATA_WIDTH / 8)));
constant ADDR_DATALINE_NBITS : natural :=
ADDR_DATA_NBITS + DATAS_PER_LINE_WIDTH + INDEX_WIDTH;
constant TAG_WIDTH : natural := ADDR_WIDTH - ADDR_DATALINE_NBITS;
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
subtype data_t is std_logic_vector(DATA_WIDTH - 1 downto 0);
type data_vector is array(natural range <>) of data_t;
subtype cache_line_selector_t is std_logic_vector(0 to DATAS_PER_LINE - 1);
subtype way_selector_t is std_logic_vector(0 to NB_WAYS - 1);
subtype cache_line_t is data_vector(0 to DATAS_PER_LINE - 1);
subtype flat_cache_line_t is
std_logic_vector(DATAS_PER_LINE * DATA_WIDTH - 1 downto 0);
type cache_line_vector is array (natural range <>) of cache_line_t;
type flat_cache_line_vector is array (natural range <>) of flat_cache_line_t;
type cls_op is (cls_none, cls_refill, cls_flush);
type cache_request_t is record
req : cls_op;
addr : addr_t;
sel : cache_line_selector_t;
cline : cache_line_t;
end record;
type cache_response_t is record
cline : cache_line_t;
sel : cache_line_selector_t;
rdy : std_logic;
done : std_logic;
end record;
-- Tag entry
--- entry = [ [valid_bits_of_line] [dirty_bits_of_line] [tag_context] [tag]
--- +-------------------------------------------------------+
--- | Tag context | Dirty line bits | Valid line bits | Tag |
--- +-------------------------------------------------------+
subtype tag_t is std_logic_vector(TAG_WIDTH - 1 downto 0);
subtype tag_context_t is std_logic_vector(1 downto 0);
type tag_entry_t is record
ctxt : tag_context_t;
valids : cache_line_selector_t;
dirtys : cache_line_selector_t;
tag : tag_t;
end record;
type tag_entry_vector is array(natural range <>) of tag_entry_t;
constant TAG_ENTRY_EMPTY : tag_entry_t := (
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
-- Eviction types
--- eviction_entry = [ [alloc_counter] ]
constant alloc_entry_len : natural := ((WAYS_WIDTH * NB_WAYS + 7) / 8) * 8;
subtype alloc_entry_t is std_logic_vector(0 to alloc_entry_len - 1);
type mem_tag_status_t is record
valid : std_logic;
dirty : std_logic;
end record;
type cache_state is (s_idle, s_searching,
s_prepare_flushing, s_flush_outer, s_flushing,
s_refill_memory, s_refill_cache,
s_writethrough, s_write_allocate);
-- Cache statistics
type cache_stats_t is record
read_hits : natural;
write_hits : natural;
read_misses : natural;
write_misses : natural;
write_throughs : natural;
write_backs : natural;
flushes : natural;
refills : natural;
end record cache_stats_t;
function get_address_index(i_address : std_logic_vector) return natural;
function get_address_tag(i_address : std_logic_vector)
return std_logic_vector;
function get_data_set_index(i_address : std_logic_vector)
return natural;
function get_address(tag : tag_t; index : natural range 0 to NB_LINES - 1;
data_in_line : natural range 0 to DATAS_PER_LINE - 1)
return addr_t;
function data_is_valid(addr : addr_t; te : tag_entry_t) return std_logic;
function dataline_is_dirty(te : tag_entry_t) return boolean;
function to_way_selector(way : natural range 0 to NB_WAYS - 1)
return way_selector_t;
function to_cacheline_selector(addr : addr_t) return cache_line_selector_t;
end package cache_defs;
package body cache_defs is
function get_address_index(i_address : std_logic_vector) return natural is
variable idx : natural;
begin
idx := to_integer(unsigned(i_address(
ADDR_DATALINE_NBITS - 1 downto DATAS_PER_LINE_WIDTH + ADDR_DATA_NBITS)));
return idx;
end function get_address_index;
function get_address_tag(i_address : std_logic_vector)
return std_logic_vector is
variable tag : tag_t;
begin
tag :=
i_address(i_address'length - 1 downto i_address'length - TAG_WIDTH);
return tag;
end function get_address_tag;
function get_data_set_index(i_address : std_logic_vector)
return natural is
variable set_index : natural range 0 to DATAS_PER_LINE - 1;
begin
if DATAS_PER_LINE = 1 then
set_index := 0;
else
set_index := to_integer(unsigned(i_address(
DATAS_PER_LINE_WIDTH + ADDR_DATA_NBITS - 1 downto ADDR_DATA_NBITS)));
end if;
return set_index;
end function get_data_set_index;
function get_address(tag : tag_t; index : natural range 0 to NB_LINES - 1;
data_in_line : natural range 0 to DATAS_PER_LINE - 1)
return addr_t is
begin
return tag & std_logic_vector(to_unsigned(index, INDEX_WIDTH) &
to_unsigned(data_in_line, DATAS_PER_LINE_WIDTH) &
to_unsigned(0, ADDR_DATA_NBITS));
end function get_address;
function data_is_valid(addr : addr_t; te : tag_entry_t) return std_logic is
variable data_in_line : natural range 0 to DATAS_PER_LINE - 1;
begin
data_in_line := get_data_set_index(addr);
return te.valids(data_in_line);
end function data_is_valid;
function dataline_is_dirty(te : tag_entry_t) return boolean is
constant z : cache_line_selector_t := (others => '0');
variable o : boolean;
begin
o := te.dirtys /= z;
return o;
end function dataline_is_dirty;
function to_way_selector(way : natural range 0 to NB_WAYS - 1)
return way_selector_t is
variable ws : way_selector_t := (others => '0');
begin
for i in ws'range loop
if i = way then
ws(i) := '1';
end if;
end loop;
return ws;
end function to_way_selector;
function to_cacheline_selector(addr : addr_t) return cache_line_selector_t is
variable clsel : cache_line_selector_t := (others => '0');
variable data_in_line : natural range 0 to DATAS_PER_LINE - 1;
begin
data_in_line := get_data_set_index(addr);
clsel(data_in_line) := '1';
return clsel;
end function to_cacheline_selector;
end package body cache_defs;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/library/rule_004_test_input.fixed_upper.vhd | 1 | 30 |
LIBRARY ieee;
LIBRARY ieee;
| gpl-3.0 |
rjarzmik/mips_processor | IF/Fetch_tb.vhd | 1 | 4914 | -------------------------------------------------------------------------------
-- Title : Testbench for design "Fetch"
-- Project :
-------------------------------------------------------------------------------
-- File : Fetch_tb.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-11
-- Last update: 2016-12-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-11 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity Fetch_tb is
end entity Fetch_tb;
-------------------------------------------------------------------------------
architecture rtl of Fetch_tb is
-- component generics
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 16;
constant MEMORY_LATENCY : integer := 3;
-- component ports
-- clock
signal Clk : std_logic := '1';
-- reset
signal Rst : std_logic := '1';
signal instruction : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(0, ADDR_WIDTH));
signal next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH));
signal next_next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH));
signal stall_req : std_logic := '0';
signal stall_pc : std_logic := '0';
signal jump_pc : std_logic;
signal jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- L2 connections
signal o_L2c_req : std_logic;
signal o_L2c_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i_L2c_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal i_L2c_valid : std_logic;
-- Debug signals
signal dbg_if_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
begin -- architecture rtl
-- component instantiation
dut : entity work.Fetch(rtl3)
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => Clk,
rst => Rst,
stall_req => '0',
kill_req => '0',
i_pc => pc,
i_next_pc => next_pc,
i_next_next_pc => next_next_pc,
o_instruction => instruction,
o_do_stall_pc => stall_pc,
o_L2c_req => o_L2c_req,
o_L2c_addr => o_L2c_addr,
i_L2c_read_data => i_L2c_read_data,
i_L2c_valid => i_L2c_valid,
o_dbg_if_fetching_pc => dbg_if_pc);
Simulated_Memory_1 : entity work.Simulated_Memory
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
MEMORY_LATENCY => MEMORY_LATENCY)
port map (
clk => Clk,
rst => Rst,
i_memory_req => o_L2c_req,
i_memory_we => '0',
i_memory_addr => o_L2c_addr,
i_memory_write_data => (others => 'X'),
o_memory_read_data => i_L2c_read_data,
o_memory_valid => i_L2c_valid);
PC_Register_1 : entity work.PC_Register
generic map (
ADDR_WIDTH => ADDR_WIDTH,
STEP => 4)
port map (
clk => Clk,
rst => Rst,
stall_pc => stall_pc,
jump_pc => jump_pc,
jump_target => jump_target,
o_current_pc => pc,
o_next_pc => next_pc,
o_next_next_pc => next_next_pc);
-- reset
Rst <= '0' after 12 ps;
-- clock generation
Clk <= not Clk after 5 ps;
-- waveform generation
WaveGen_Proc : process
variable nb_clks : integer := 0;
begin
-- insert signal assignments here
wait until Clk = '1';
nb_clks := nb_clks + 1;
if unsigned(pc) = to_unsigned(16 + 4, ADDR_WIDTH) then
jump_pc <= '1';
jump_target <= std_logic_vector(to_unsigned(8, ADDR_WIDTH));
else
jump_pc <= '0';
jump_target <= (others => 'X');
end if;
end process WaveGen_Proc;
end architecture rtl;
-------------------------------------------------------------------------------
configuration Fetch_tb_test_cfg of Fetch_tb is
for rtl
end for;
end Fetch_tb_test_cfg;
-------------------------------------------------------------------------------
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_401_test_input.fixed.vhd | 1 | 488 |
architecture rtl of fifo is
begin
-- Valid formatting
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
-- Invalid formatting
process
begin
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
end process;
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package/rule_008_test_input.fixed_lower.vhd | 1 | 89 |
package fifo_pkg is
end package fifo_pkg;
package fifo_pkg is
end package fifo_pkg;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/library/rule_008_test_input.fixed_with_indent_size_0.vhd | 1 | 170 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/alias_declaration/rule_300_test_input.vhd | 1 | 147 |
architecture rtl of fifo is
alias designator is name;
alias designator is name;
alias designator is name;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_024_test_input.vhd | 1 | 409 |
architecture RTL of FIFO is begin end architecture;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/sim/functional/sim_tb_top.vhd | 2 | 16400 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 8;
constant C3_P0_DATA_PORT_SIZE : integer := 64;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_reset_n : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/context/rule_004_test_input.fixed_lower.vhd | 1 | 134 |
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context c1;
context c1 is
end context c1;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/rx-core/data_alignment.vhd | 3 | 4097 | -- word alignment
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_alignment is
port
(
clk : in std_logic := '0';
reset : in std_logic := '0';
din : in std_logic_vector(1 downto 0) := "00";
din_valid : in std_logic_vector(1 downto 0) := "00";
dout : out std_logic_vector(9 downto 0) := (others => '0');
dout_valid : out std_logic := '0';
dout_sync : out std_logic := '0'
);
end data_alignment;
architecture Behavioral of data_alignment is
-- FE-I4 Encoded Komma Words used for Alignment of the Decoder
constant idle_word : std_logic_vector(9 downto 0) := "0011111001";
constant sof_word : std_logic_vector(9 downto 0) := "0011111000";
constant eof_word : std_logic_vector(9 downto 0) := "0011111010";
-- Count of Bits before a new sync word is necessary (currently arbitrary)
constant fei4syncPeriod: integer := 160000000;
signal data_sr : std_logic_vector(10 downto 0) := (others => '0');
signal dcnt : integer range 0 to 11 := 0;
signal scnt : integer range 0 to fei4syncPeriod := 0;
signal sync : std_logic := '0';
signal sync_word : std_logic_vector(1 downto 0) := (others => '0');
signal sync_holdoff : std_logic := '0';
begin
-- search for sync words
process (reset, data_sr) begin
if reset = '1' then
sync_word <= "00";
else
if sync_holdoff = '0' then
if (data_sr(9 downto 0) = idle_word) or (data_sr(9 downto 0) = not idle_word) or
(data_sr(9 downto 0) = sof_word) or (data_sr(9 downto 0) = not sof_word) or
(data_sr(9 downto 0) = eof_word) or (data_sr(9 downto 0) = not eof_word) then
sync_word <= "01";
elsif (data_sr(10 downto 1) = idle_word) or (data_sr(10 downto 1) = not idle_word) or
(data_sr(10 downto 1) = sof_word) or (data_sr(10 downto 1) = not sof_word) or
(data_sr(10 downto 1) = eof_word) or (data_sr(10 downto 1) = not eof_word) then
sync_word <= "10";
else
sync_word <= "00";
end if;
else
sync_word <= "00";
end if;
end if;
end process;
-- data alignment
process begin
wait until rising_edge(clk);
if reset = '1' then
dout <= (others => '0');
dout_valid <= '0';
sync <= '0';
data_sr <= (others => '0');
dcnt <= 0;
scnt <= 0;
else
-- clear sync flag
if scnt = fei4syncPeriod then
sync <= '0';
scnt <= 0;
else
scnt <= scnt + 1;
end if;
-- shift in new data
if din_valid = "01" then
data_sr <= data_sr(9 downto 0) & din(0);
if sync_word = "01" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
sync_holdoff <= '1';
elsif sync_word = "10" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
sync_holdoff <= '1';
else
dcnt <= dcnt + 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 1;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 2;
else
dout_valid <= '0';
end if;
elsif din_valid = "11" then
data_sr <= data_sr(8 downto 0) & din(0) & din(1);
if sync_word = "01" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
elsif sync_word = "10" then
sync <= '1';
scnt <= 3;
dcnt <= 3;
else
dcnt <= dcnt + 2;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 2;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 3;
else
dout_valid <= '0';
end if;
else
if sync_word = "01" then
sync <= '1';
scnt <= 0;
dcnt <= 0;
elsif sync_word = "10" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 0;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 1;
else
dout_valid <= '0';
end if;
end if;
end if;
end process;
dout_sync <= sync;
end Behavioral;
| gpl-3.0 |
rjarzmik/mips_processor | Caches/tags_data_mem.vhd | 1 | 8821 | -------------------------------------------------------------------------------
-- Title : Cache tags data memory
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : tags_data_mem.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-15
-- Last update: 2017-01-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-15 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity tags_data_mem is
generic
(
DEBUG : boolean := false
);
port (
clk : in std_logic;
-- Reader
i_re : in std_logic;
i_raddr : in addr_t;
o_tag_found : out boolean;
o_way_found : out natural range 0 to NB_WAYS - 1;
--- Combinational : read_tag_entries(i_raddr)(way)
o_tag_entry : out tag_entry_t;
o_data_valid : out std_logic;
o_way_evict : out natural range 0 to NB_WAYS - 1;
o_evict_dirty : out boolean;
o_evict_tag_entry : out tag_entry_t;
-- Writer
--- i_update_addr will be the one latched when i_prepare_we = 1
--- base data for update will be the one latched from mem_read_data the
--- cycle _after_ i_prepare_we = 1
i_waddr : in addr_t;
i_we : in std_logic;
i_update_way : in natural range 0 to NB_WAYS - 1;
i_wtag_entry : in tag_entry_t;
--- i_way_alloc triggers a new election of the next to evict line
i_evict_compute : in std_logic
);
end entity tags_data_mem;
architecture str of tags_data_mem is
-- Entry anatomy, ie. entry for a given address index
subtype counter_t is natural range 0 to NB_WAYS - 1;
-- Tag Data Memory interface
subtype mem_addr_t is std_logic_vector(INDEX_WIDTH - 1 downto 0);
signal mem_raddr : mem_addr_t := (others => '0');
signal mem_read_data : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
signal mem_bypassed_rdata : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
signal mem_rren : way_selector_t := (others => '0');
signal mem_waddr : mem_addr_t;
signal mem_we : std_logic;
signal mem_wway : natural range 0 to NB_WAYS - 1;
signal mem_wren : way_selector_t := (others => '0');
signal mem_write_data : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
-- Tag Allocate interface
signal evict_rdata : alloc_entry_t := (others => '0');
signal evict_wdata : alloc_entry_t := (others => '0');
signal evict_bypassed_rdata : alloc_entry_t := (others => '0');
signal evict_wren : std_logic := '0';
signal evict_way : natural range 0 to NB_WAYS - 1;
signal mem_read_alloc_counter : alloc_entry_t;
-- Debug signals
-- Latched data for memory read + search
signal searched_addr : addr_t := (others => '0');
signal mem_w_bypass : boolean := false;
signal mem_te : tag_entry_t := TAG_ENTRY_EMPTY;
signal mem_searched_addr : mem_addr_t := (others => '0');
signal mem_way_found : natural range 0 to NB_WAYS - 1;
----------------------------------------------
-- Functions for combinational memory logic --
----------------------------------------------
function get_is_way_found(addr : addr_t;
tev : tag_entry_vector(0 to NB_WAYS - 1))
return boolean is
variable needle : tag_t;
variable way_found : boolean := false;
begin
needle := get_address_tag(addr);
for way in tev'range loop
if tev(way).tag = needle and tev(way).valids /= TAG_ENTRY_EMPTY.valids then
way_found := true;
end if;
end loop;
return way_found;
end function get_is_way_found;
function get_way_found(addr : addr_t;
tev : tag_entry_vector(0 to NB_WAYS - 1))
return natural is
variable needle : tag_t;
variable oway : natural range 0 to NB_WAYS - 1 := 0;
begin
needle := get_address_tag(addr);
for way in tev'range loop
if tev(way).tag = needle and tev(way).valids /= TAG_ENTRY_EMPTY.valids then
oway := way;
end if;
end loop;
return oway;
end function get_way_found;
function get_alloc_counter(ae : alloc_entry_t; step : natural)
return natural is
variable ac : natural;
begin
ac := to_integer(unsigned(ae));
ac := (ac + step) mod NB_WAYS;
return ac;
end function get_alloc_counter;
function get_updated_tag_entry(addr : addr_t;
a : tag_entry_t;
data_in_line : natural range 0 to DATAS_PER_LINE;
valid : std_ulogic;
dirty : std_ulogic;
ctxt : tag_context_t)
return tag_entry_t is
variable te : tag_entry_t;
begin
te.ctxt := ctxt;
te.valids(data_in_line) := valid;
te.dirtys(data_in_line) := dirty;
return te;
end function get_updated_tag_entry;
begin -- architecture str
-- Memories instances
tmem : for i in 0 to NB_WAYS - 1 generate
tdata : entity work.memory_tagmem_internal
generic map (ADDR_WIDTH => INDEX_WIDTH, DEBUG_IDX => i, DEBUG => DEBUG)
port map (clk, mem_raddr, mem_waddr, mem_write_data(i), i_re,
mem_wren(i), mem_read_data(i));
end generate tmem;
evictm : entity work.memory_eviction_internal
generic map (ADDR_WIDTH => INDEX_WIDTH, DEBUG => DEBUG)
port map (clk, mem_raddr, mem_waddr, evict_wdata, i_re,
evict_wren, evict_rdata);
mem_raddr <= std_logic_vector(to_unsigned(get_address_index(i_raddr), mem_raddr'length));
reader : process(clk, i_raddr)
begin
if rising_edge(clk) then
searched_addr <= i_raddr;
mem_searched_addr <= mem_raddr;
end if;
end process reader;
mem_w_bypass <= mem_searched_addr = mem_waddr and mem_we = '1';
gmbypassrdata : for way in mem_bypassed_rdata'range generate
mem_bypassed_rdata(way) <= mem_write_data(way) when mem_w_bypass and way = mem_wway
else mem_read_data(way);
end generate;
evict_bypassed_rdata <= evict_wdata when evict_wren = '1' and mem_waddr = mem_searched_addr else evict_rdata;
-- mem_way_found <= get_way_found(searched_addr, mem_read_data);
mem_way_found <= get_way_found(searched_addr, mem_bypassed_rdata);
mem_te <= mem_bypassed_rdata(mem_way_found);
evict_way <= get_alloc_counter(evict_bypassed_rdata, 0);
o_tag_found <= get_is_way_found(searched_addr, mem_bypassed_rdata);
o_way_found <= mem_way_found;
o_way_evict <= evict_way;
o_data_valid <= data_is_valid(searched_addr, mem_te);
o_tag_entry_mux : entity work.tag_entry_mux
generic map (NB => NB_WAYS)
port map (mem_way_found, mem_bypassed_rdata, o_tag_entry);
o_evict_dirty <= dataline_is_dirty(mem_bypassed_rdata(evict_way));
o_evict_tag_entry_mux : entity work.tag_entry_mux
generic map (NB => NB_WAYS)
port map (evict_way, mem_bypassed_rdata, o_evict_tag_entry);
writer : process(clk, mem_searched_addr, i_we, i_update_way, i_waddr)
begin
if rising_edge(clk) then
mem_waddr <= std_logic_vector(to_unsigned(get_address_index(i_waddr), mem_waddr'length));
mem_we <= i_we;
mem_wway <= i_update_way;
for way in mem_wren'range loop
if i_we = '1' and i_update_way = way then
mem_wren(way) <= '1';
else
mem_wren(way) <= '0';
end if;
end loop;
for way in mem_write_data'range loop
mem_write_data(way) <= i_wtag_entry;
end loop;
end if;
end process writer;
evicter : process(clk, mem_searched_addr, i_evict_compute)
begin
if rising_edge(clk) then
evict_wren <= i_evict_compute;
evict_wdata <=
std_logic_vector(to_unsigned(get_alloc_counter(evict_rdata, 1), evict_wdata'length));
end if;
end process evicter;
end architecture str;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/tg_status.vhd | 20 | 5700 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: tg_status.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
-- Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity tg_status is
generic (
TCQ : TIME := 100 ps;
DWIDTH : integer := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
manual_clear_error : in std_logic;
data_error_i : in std_logic;
cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
cmp_addr_i : in std_logic_vector(31 downto 0);
cmp_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
mcb_wr_full_i : in std_logic;
mcb_rd_empty_i : in std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
error : out std_logic
);
end entity tg_status;
architecture trans of tg_status is
signal data_error_r : std_logic;
signal error_set : std_logic;
begin
error <= error_set;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_error_r <= data_error_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i or manual_clear_error) = '1') then
-- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
error_status <= (others => '0');
error_set <= '0';
else
-- latch the first error only
if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
error_status(31 downto 0) <= cmp_addr_i;
error_status(37 downto 32) <= cmp_bl_i;
error_status(40) <= mcb_cmd_full_i;
error_status(41) <= mcb_wr_full_i;
error_status(42) <= mcb_rd_empty_i;
error_set <= '1';
error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
end if;
error_status(39 downto 38) <= "00"; -- reserved
error_status(63 downto 43) <= "000000000000000000000"; -- reserved
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_029_test_input.vhd | 1 | 3274 |
architecture RTL of ENTITY1 is
-- These should fail
variable v_var1 : std_logic;
signal s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias1 is name;
-- These should pass
variable v_var1 : std_logic;
signal s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias1 is name;
-- Test with different spacing
variable v_var1 : std_logic;
signal s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias1 is name;
-- Test with shorter combinations
signal s_sig1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
alias a_alias1 is name;
-- Test with comments
variable v_var1 : std_logic;
signal s_sig1 : std_logic;
-- some comment
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
-- some comment
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
-- Test multiline declarations
type state_type is (
state1, state2,
state3, state4
);
signal sig1 : std_logic;
-- This should not error
type state_type2 is (
state1, state2,
state3, state4
);
signal sig1 : std_logic;
begin
end architecture RTL;
-- Test functions and procedures defined in architectures
architecture RTL of ENTITY1 is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
-- Violations below this line
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
variable var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant x : in integer;
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : something;
variable var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
function func_1 (
constant a : integer;
signal b : integer;
signal c : unsigned(3 downto 0);
signal d : std_logic_vector(7 downto 0);
constant e : std_logic) return integer is
file file1 : load_file_type open read_mode is load_file_name;
variable con1 : integer := 0;
variable sig1 : std_logic_vector;
begin
end;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_waveforms/rule_501_test_input.vhd | 2 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_expressions/rule_501_test_input.vhd | 2 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/read_posted_fifo.vhd | 20 | 11980 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_posted_fifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module instantiated by read_data_path module and sits between
-- mcb_flow_control module and read_data_gen module to buffer up the
-- commands that has sent to memory controller.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity read_posted_fifo is
generic (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
data_valid_i : in std_logic;
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1 : in std_logic;
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
gen_rdy_i : in std_logic;
gen_valid_o : out std_logic;
gen_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
gen_bl_o : out std_logic_vector(BL_WIDTH - 1 downto 0);
rd_buff_avail_o : out std_logic_vector(6 downto 0);
rd_mdata_fifo_empty : in std_logic;
rd_mdata_en : out std_logic
);
end entity read_posted_fifo;
architecture trans of read_posted_fifo is
component afifo is
generic (
DSIZE : integer := 32;
FIFO_DEPTH : integer := 16;
ASIZE : integer := 4;
SYNC : integer := 1
);
port (
wr_clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
wr_data : in std_logic_vector(DSIZE - 1 downto 0);
rd_en : in std_logic;
rd_clk : in std_logic;
rd_data : out std_logic_vector(DSIZE - 1 downto 0);
full : out std_logic;
empty : out std_logic;
almost_full : out std_logic
);
end component;
signal full : std_logic;
signal empty : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal data_valid_r : std_logic;
signal user_bl_cnt_not_1 : std_logic;
signal buf_avail_r : std_logic_vector(6 downto 0);
signal rd_data_received_counts : std_logic_vector(6 downto 0);
signal rd_data_counts_asked : std_logic_vector(6 downto 0);
signal dfifo_has_enough_room : std_logic;
signal wait_cnt : std_logic_vector(1 downto 0);
signal wait_done : std_logic;
signal dfifo_has_enough_room_d1 : std_logic;
signal empty_r : std_logic;
signal rd_first_data : std_logic;
-- current count is 1 and data_is_valie, then next cycle is not 1
-- calculate how many buf still available
-- assign buf_avail = 64 - (rd_data_counts_asked - rd_data_received_counts);
-- signal tmp_buf_avil : std_logic_vector(5 downto 0);
-- X-HDL generated signals
signal xhdl3 : std_logic;
signal xhdl4 : std_logic;
signal xhdl5 : std_logic_vector(37 downto 0);
signal xhdl6 : std_logic_vector(37 downto 0);
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal gen_addr_o_xhdl1 : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal gen_bl_o_xhdl2 : std_logic_vector(BL_WIDTH - 1 downto 0);
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
-- gen_addr_o <= gen_addr_o_xhdl1;
-- gen_bl_o <= gen_bl_o_xhdl2;
gen_bl_o <= xhdl6(BL_WIDTH+ADDR_WIDTH-1 downto ADDR_WIDTH);
gen_addr_o <= xhdl6(ADDR_WIDTH-1 downto 0);
rd_mdata_en <= rd_en;
rd_buff_avail_o <= buf_avail_r;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_rdy_o_xhdl0 <= not(full) and dfifo_has_enough_room and wait_done;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_cnt <= "00";
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_cnt <= "10";
elsif (wait_cnt > "00") then
wait_cnt <= wait_cnt - "01";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_done <= '1';
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_done <= '0';
elsif (wait_cnt = "00") then
wait_done <= '1';
else
wait_done <= '0';
end if;
end if;
end process;
xhdl3 <= '1' when (buf_avail_r >= "0111110") else
'0';
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
dfifo_has_enough_room <= xhdl3;
dfifo_has_enough_room_d1 <= dfifo_has_enough_room;
end if;
end process;
wr_en <= cmd_valid_i and not(full) and dfifo_has_enough_room_d1 and wait_done;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_valid_r <= data_valid_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((data_valid_i and user_bl_cnt_is_1) = '1') then
user_bl_cnt_not_1 <= '1';
else
user_bl_cnt_not_1 <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_counts_asked <= (others => '0');
elsif (cmd_en_i = '1' and cmd_sent(0) = '1') then
rd_data_counts_asked <= rd_data_counts_asked + (bl_sent + "0000001" );
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_received_counts <= "0000000";
elsif (data_valid_i = '1') then
rd_data_received_counts <= rd_data_received_counts + "0000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
buf_avail_r <= "1000000" - (rd_data_counts_asked - rd_data_received_counts);
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
empty_r <= empty;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_first_data <= '0';
elsif ( empty = '0' AND empty_r = '1') then
rd_first_data <= '1';
end if;
end if;
end process;
process (gen_rdy_i, empty,empty_r, data_valid_i, data_valid_r, user_bl_cnt_not_1,rd_mdata_fifo_empty,rd_first_data)
begin
if (FAMILY = "SPARTAN6") then
rd_en <= gen_rdy_i and not(empty);
else
IF (MEM_BURST_LEN = 4) then
rd_en <= (not(empty) and empty_r and not(rd_first_data)) or (not(rd_mdata_fifo_empty) and not(empty)) or
(user_bl_cnt_not_1 and data_valid_i);
ELSE
rd_en <= (data_valid_i and not(data_valid_r)) or (user_bl_cnt_not_1 and data_valid_i);
END IF;
end if;
end process;
gen_valid_o <= not(empty);
-- set the SYNC to 1 because rd_clk = wr_clk to reduce latency
-- xhdl4 <= to_integer(to_stdlogic(BL_WIDTH) + to_stdlogic(ADDR_WIDTH));
xhdl5 <= (bl_i & addr_i);
-- (gen_bl_o_xhdl2, gen_addr_o_xhdl1) <= xhdl6;
rd_fifo : afifo
GENERIC MAP (
DSIZE => (BL_WIDTH + ADDR_WIDTH),--xhdl4,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
port map (
wr_clk => clk_i,
rst => rst_i,
wr_en => wr_en,
wr_data => xhdl5,
rd_en => rd_en,
rd_clk => clk_i,
rd_data => xhdl6,
full => full,
empty => empty,
almost_full => open
);
end architecture trans;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/common/synchronizer.vhd | 2 | 1061 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal deglitch_t1 : std_logic;
signal deglitch_t2 : std_logic;
begin
deglitch_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_out <= '0';
deglitch_t1 <= '0';
deglitch_t2 <= '0';
elsif rising_edge(clk_i) then
deglitch_t1 <= async_in;
deglitch_t2 <= deglitch_t1;
sync_out <= deglitch_t2;
end if;
end process deglitch_proc;
end rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/report_statement/rule_101_test_input.vhd | 1 | 183 |
architecture rtl of fifo is
begin
process begin
report "hello"
severity FAILURE;
report "hello"
severity FAILURE;
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_500_test_input.fixed_lower.vhd | 1 | 169 |
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
block_label : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_008_test_input.fixed.vhd | 6 | 385 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port_map/rule_002_test_input.fixed_upper.vhd | 1 | 585 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/type_definition/rule_400_test_input.fixed.vhd | 1 | 534 |
architecture rtl of fifo is
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
--Violations below
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_502_test_input.vhd | 1 | 219 |
architecture RTL of FIFO is
procedure proc1 is begin end procedure proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
FUNCTION FUNC1 RETURN INTEGER Is BEGIN END FUNCTION FUNC1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/attribute_specification/rule_101_test_input.vhd | 1 | 212 |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_no_align_paren_yes_align_when_yes.vhd | 1 | 2232 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
lvd2/zxevo | fpga/baseconf/trunk/sim_models/T80.vhd | 5 | 32078 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
ResetPC : in std_logic_vector(15 downto 0);
ResetSP : in std_logic_vector(15 downto 0)
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= unsigned(ResetPC);
-- (others => '0') -- Program Counter
A <= ResetPC; -- (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= unsigned(ResetSP);
-- (others => '1')
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 |
lvd2/zxevo | fpga/sdload/trunk/sim_models/T80.vhd | 5 | 32078 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
ResetPC : in std_logic_vector(15 downto 0);
ResetSP : in std_logic_vector(15 downto 0)
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= unsigned(ResetPC);
-- (others => '0') -- Program Counter
A <= ResetPC; -- (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= unsigned(ResetSP);
-- (others => '1')
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/code_examples/nested_generates.vhd | 1 | 335 |
architecture rtl of e is
begin
g_0 : if true generate
g_1 : if true generate
signal Sig0 : bit;
signal Sig00 : bit;
begin
g_2 : for i in 0 to 0 generate
end generate g_2;
end generate g_1;
end generate g_0;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/component_declaration/classification_test_input.vhd | 1 | 937 |
architecture RTL of FIFO is
component COMP is
end component COMP;
component COMP
end component COMP;
component COMP
end component;
-- test with generics
component COMP is
generic (
G_GEN1 : integer := 1;
G_GEN2 : integer := 0
);
end component COMP;
-- test with ports
component COMP is
port (
I_PORT : in integer := 1;
O_PORT : out integer := 0
);
end component COMP;
-- test with both
component COMP is
generic (
G_GEN1 : integer := 1;
G_GEN2 : integer := 0
);
port (
I_PORT : in integer := 1;
O_PORT : out integer := 0
);
end component COMP;
-- test with range in generic
component COMP is
generic (
G_GEN1 : integer := 1;
G_GEN2 : integer range 0 to 3
);
port (
I_PORT : in integer := 1;
O_PORT : out integer := 0
);
end component COMP;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_020_test_input.vhd | 1 | 403 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA: out std_logic_vector(31 downto 0);
I_RD_EN: in std_logic;
O_DATA: out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
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