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Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/allocator_logic_pseudo_checkers.vhd | 12 | 24829 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_checkers;
architecture behavior of allocator_logic_pseudo_checkers is
begin
-- The combionational part
-- Checkers
-- Grant_N checkers
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if (grant_N_N_sig = '1' and empty_N = '0' and grant_N_N = '0') then
err_grant_N_N_sig_not_empty_N_grant_N_N <= '1';
else
err_grant_N_N_sig_not_empty_N_grant_N_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if ( (grant_N_N_sig = '0' or empty_N = '1') and grant_N_N = '1') then
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '1';
else
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if (grant_N_E_sig = '1' and empty_E = '0' and grant_N_E = '0') then
err_grant_N_E_sig_not_empty_E_grant_N_E <= '1';
else
err_grant_N_E_sig_not_empty_E_grant_N_E <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if ( (grant_N_E_sig = '0' or empty_E = '1') and grant_N_E = '1') then
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '1';
else
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if (grant_N_W_sig = '1' and empty_W = '0' and grant_N_W = '0') then
err_grant_N_W_sig_not_empty_W_grant_N_W <= '1';
else
err_grant_N_W_sig_not_empty_W_grant_N_W <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if ( (grant_N_W_sig = '0' or empty_W = '1') and grant_N_W = '1') then
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '1';
else
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if (grant_N_S_sig = '1' and empty_S = '0' and grant_N_S = '0') then
err_grant_N_S_sig_not_empty_S_grant_N_S <= '1';
else
err_grant_N_S_sig_not_empty_S_grant_N_S <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if ( (grant_N_S_sig = '0' or empty_S = '1') and grant_N_S = '1') then
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '1';
else
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if (grant_N_L_sig = '1' and empty_L = '0' and grant_N_L = '0') then
err_grant_N_L_sig_not_empty_L_grant_N_L <= '1';
else
err_grant_N_L_sig_not_empty_L_grant_N_L <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if ( (grant_N_L_sig = '0' or empty_L = '1') and grant_N_L = '1') then
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '1';
else
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_E checkers
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if (grant_E_N_sig = '1' and empty_N = '0' and grant_E_N = '0') then
err_grant_E_N_sig_not_empty_N_grant_E_N <= '1';
else
err_grant_E_N_sig_not_empty_N_grant_E_N <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if ( (grant_E_N_sig = '0' or empty_N = '1') and grant_E_N = '1') then
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '1';
else
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if (grant_E_E_sig = '1' and empty_E = '0' and grant_E_E = '0') then
err_grant_E_E_sig_not_empty_E_grant_E_E <= '1';
else
err_grant_E_E_sig_not_empty_E_grant_E_E <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if ( (grant_E_E_sig = '0' or empty_E = '1') and grant_E_E = '1') then
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '1';
else
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if (grant_E_W_sig = '1' and empty_W = '0' and grant_E_W = '0') then
err_grant_E_W_sig_not_empty_W_grant_E_W <= '1';
else
err_grant_E_W_sig_not_empty_W_grant_E_W <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if ( (grant_E_W_sig = '0' or empty_W = '1') and grant_E_W = '1') then
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '1';
else
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if (grant_E_S_sig = '1' and empty_S = '0' and grant_E_S = '0') then
err_grant_E_S_sig_not_empty_S_grant_E_S <= '1';
else
err_grant_E_S_sig_not_empty_S_grant_E_S <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if ( (grant_E_S_sig = '0' or empty_S = '1') and grant_E_S = '1') then
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '1';
else
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if (grant_E_L_sig = '1' and empty_L = '0' and grant_E_L = '0') then
err_grant_E_L_sig_not_empty_L_grant_E_L <= '1';
else
err_grant_E_L_sig_not_empty_L_grant_E_L <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if ( (grant_E_L_sig = '0' or empty_L = '1') and grant_E_L = '1') then
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '1';
else
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_W checkers
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if (grant_W_N_sig = '1' and empty_N = '0' and grant_W_N = '0') then
err_grant_W_N_sig_not_empty_N_grant_W_N <= '1';
else
err_grant_W_N_sig_not_empty_N_grant_W_N <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if ( (grant_W_N_sig = '0' or empty_N = '1') and grant_W_N = '1') then
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '1';
else
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if (grant_W_E_sig = '1' and empty_E = '0' and grant_W_E = '0') then
err_grant_W_E_sig_not_empty_E_grant_W_E <= '1';
else
err_grant_W_E_sig_not_empty_E_grant_W_E <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if ( (grant_W_E_sig = '0' or empty_E = '1') and grant_W_E = '1') then
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '1';
else
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if (grant_W_W_sig = '1' and empty_W = '0' and grant_W_W = '0') then
err_grant_W_W_sig_not_empty_W_grant_W_W <= '1';
else
err_grant_W_W_sig_not_empty_W_grant_W_W <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if ( (grant_W_W_sig = '0' or empty_W = '1') and grant_W_W = '1') then
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '1';
else
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if (grant_W_S_sig = '1' and empty_S = '0' and grant_W_S = '0') then
err_grant_W_S_sig_not_empty_S_grant_W_S <= '1';
else
err_grant_W_S_sig_not_empty_S_grant_W_S <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if ( (grant_W_S_sig = '0' or empty_S = '1') and grant_W_S = '1') then
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '1';
else
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if (grant_W_L_sig = '1' and empty_L = '0' and grant_W_L = '0') then
err_grant_W_L_sig_not_empty_L_grant_W_L <= '1';
else
err_grant_W_L_sig_not_empty_L_grant_W_L <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if ( (grant_W_L_sig = '0' or empty_L = '1') and grant_W_L = '1') then
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '1';
else
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_S checkers
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if (grant_S_N_sig = '1' and empty_N = '0' and grant_S_N = '0') then
err_grant_S_N_sig_not_empty_N_grant_S_N <= '1';
else
err_grant_S_N_sig_not_empty_N_grant_S_N <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if ( (grant_S_N_sig = '0' or empty_N = '1') and grant_S_N = '1') then
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '1';
else
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if (grant_S_E_sig = '1' and empty_E = '0' and grant_S_E = '0') then
err_grant_S_E_sig_not_empty_E_grant_S_E <= '1';
else
err_grant_S_E_sig_not_empty_E_grant_S_E <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if ( (grant_S_E_sig = '0' or empty_E = '1') and grant_S_E = '1') then
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '1';
else
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if (grant_S_W_sig = '1' and empty_W = '0' and grant_S_W = '0') then
err_grant_S_W_sig_not_empty_W_grant_S_W <= '1';
else
err_grant_S_W_sig_not_empty_W_grant_S_W <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if ( (grant_S_W_sig = '0' or empty_W = '1') and grant_S_W = '1') then
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '1';
else
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if (grant_S_S_sig = '1' and empty_S = '0' and grant_S_S = '0') then
err_grant_S_S_sig_not_empty_S_grant_S_S <= '1';
else
err_grant_S_S_sig_not_empty_S_grant_S_S <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if ( (grant_S_S_sig = '0' or empty_S = '1') and grant_S_S = '1') then
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '1';
else
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if (grant_S_L_sig = '1' and empty_L = '0' and grant_S_L = '0') then
err_grant_S_L_sig_not_empty_L_grant_S_L <= '1';
else
err_grant_S_L_sig_not_empty_L_grant_S_L <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if ( (grant_S_L_sig = '0' or empty_L = '1') and grant_S_L = '1') then
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '1';
else
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_L checkers
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if (grant_L_N_sig = '1' and empty_N = '0' and grant_L_N = '0') then
err_grant_L_N_sig_not_empty_N_grant_L_N <= '1';
else
err_grant_L_N_sig_not_empty_N_grant_L_N <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if ( (grant_L_N_sig = '0' or empty_N = '1') and grant_L_N = '1') then
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '1';
else
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if (grant_L_E_sig = '1' and empty_E = '0' and grant_L_E = '0') then
err_grant_L_E_sig_not_empty_E_grant_L_E <= '1';
else
err_grant_L_E_sig_not_empty_E_grant_L_E <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if ( (grant_L_E_sig = '0' or empty_E = '1') and grant_L_E = '1') then
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '1';
else
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if (grant_L_W_sig = '1' and empty_W = '0' and grant_L_W = '0') then
err_grant_L_W_sig_not_empty_W_grant_L_W <= '1';
else
err_grant_L_W_sig_not_empty_W_grant_L_W <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if ( (grant_L_W_sig = '0' or empty_W = '1') and grant_L_W = '1') then
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '1';
else
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if (grant_L_S_sig = '1' and empty_S = '0' and grant_L_S = '0') then
err_grant_L_S_sig_not_empty_S_grant_L_S <= '1';
else
err_grant_L_S_sig_not_empty_S_grant_L_S <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if ( (grant_L_S_sig = '0' or empty_S = '1') and grant_L_S = '1') then
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '1';
else
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if (grant_L_L_sig = '1' and empty_L = '0' and grant_L_L = '0') then
err_grant_L_L_sig_not_empty_L_grant_L_L <= '1';
else
err_grant_L_L_sig_not_empty_L_grant_L_L <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if ( (grant_L_L_sig = '0' or empty_L = '1') and grant_L_L = '1') then
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '1';
else
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Final Grant output checkers
-- North
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '1' and empty_N = '0' ) or (grant_N_E_sig = '1' and empty_E = '0') or (grant_N_W_sig = '1' and empty_W = '0') or
(grant_N_S_sig = '1' and empty_S = '0') or (grant_N_L_sig = '1' and empty_L = '0') ) and grant_N = '0' ) then
err_grant_signals_not_empty_grant_N <= '1';
else
err_grant_signals_not_empty_grant_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '0' or empty_N = '1' ) and (grant_N_E_sig = '0' and empty_E = '1') and (grant_N_W_sig = '0' or empty_W = '1') and
(grant_N_S_sig = '0' or empty_S = '1') and (grant_N_L_sig = '0' or empty_L = '1') ) and grant_N /= '0' ) then
err_not_grant_signals_empty_not_grant_N <= '1';
else
err_not_grant_signals_empty_not_grant_N <= '0';
end if;
end process;
-- East
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '1' and empty_N = '0' ) or (grant_E_E_sig = '1' and empty_E = '0') or (grant_E_W_sig = '1' and empty_W = '0') or
(grant_E_S_sig = '1' and empty_S = '0') or (grant_E_L_sig = '1' and empty_L = '0') ) and grant_E = '0' ) then
err_grant_signals_not_empty_grant_E <= '1';
else
err_grant_signals_not_empty_grant_E <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '0' or empty_N = '1' ) and (grant_E_E_sig = '0' and empty_E = '1') and (grant_E_W_sig = '0' or empty_W = '1') and
(grant_E_S_sig = '0' or empty_S = '1') and (grant_E_L_sig = '0' or empty_L = '1') ) and grant_E /= '0' ) then
err_not_grant_signals_empty_not_grant_E <= '1';
else
err_not_grant_signals_empty_not_grant_E <= '0';
end if;
end process;
-- West
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '1' and empty_N = '0' ) or (grant_W_E_sig = '1' and empty_E = '0') or (grant_W_W_sig = '1' and empty_W = '0') or
(grant_W_S_sig = '1' and empty_S = '0') or (grant_W_L_sig = '1' and empty_L = '0') ) and grant_W = '0' ) then
err_grant_signals_not_empty_grant_W <= '1';
else
err_grant_signals_not_empty_grant_W <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '0' or empty_N = '1' ) and (grant_W_E_sig = '0' and empty_E = '1') and (grant_W_W_sig = '0' or empty_W = '1') and
(grant_W_S_sig = '0' or empty_S = '1') and (grant_W_L_sig = '0' or empty_L = '1') ) and grant_W /= '0' ) then
err_not_grant_signals_empty_not_grant_W <= '1';
else
err_not_grant_signals_empty_not_grant_W <= '0';
end if;
end process;
-- South
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '1' and empty_N = '0' ) or (grant_S_E_sig = '1' and empty_E = '0') or (grant_S_W_sig = '1' and empty_W = '0') or
(grant_S_S_sig = '1' and empty_S = '0') or (grant_S_L_sig = '1' and empty_L = '0') ) and grant_S = '0' ) then
err_grant_signals_not_empty_grant_S <= '1';
else
err_grant_signals_not_empty_grant_S <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '0' or empty_N = '1' ) and (grant_S_E_sig = '0' and empty_E = '1') and (grant_S_W_sig = '0' or empty_W = '1') and
(grant_S_S_sig = '0' or empty_S = '1') and (grant_S_L_sig = '0' or empty_L = '1') ) and grant_S /= '0' ) then
err_not_grant_signals_empty_not_grant_S <= '1';
else
err_not_grant_signals_empty_not_grant_S <= '0';
end if;
end process;
-- Local
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '1' and empty_N = '0' ) or (grant_L_E_sig = '1' and empty_E = '0') or (grant_L_W_sig = '1' and empty_W = '0') or
(grant_L_S_sig = '1' and empty_S = '0') or (grant_L_L_sig = '1' and empty_L = '0') ) and grant_L = '0' ) then
err_grant_signals_not_empty_grant_L <= '1';
else
err_grant_signals_not_empty_grant_L <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '0' or empty_N = '1' ) and (grant_L_E_sig = '0' and empty_E = '1') and (grant_L_W_sig = '0' or empty_W = '1') and
(grant_L_S_sig = '0' or empty_S = '1') and (grant_L_L_sig = '0' or empty_L = '1') ) and grant_L /= '0' ) then
err_not_grant_signals_empty_not_grant_L <= '1';
else
err_not_grant_signals_empty_not_grant_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Valid output checkers
process (valid_N, valid_E, valid_W, valid_S, valid_L, grant_N, grant_E, grant_W, grant_S, grant_L)
begin
if (valid_N /= grant_N or valid_E /= grant_E or valid_W /= grant_W or valid_S /= grant_S or valid_L /= grant_L) then
err_grants_valid_not_match <= '1';
else
err_grants_valid_not_match <= '0';
end if;
end process;
END;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_routing_part_pseudo_checkers.vhd | 12 | 13914 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
--process (flit_type, empty, Requests_in)
--begin
-- if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and
-- Requests_in /= "00100" and Requests_in /= "01000" and Requests_in /= "10000") then
-- err_header_not_empty_Requests_in_onehot <= '1';
-- else
-- err_header_not_empty_Requests_in_onehot <= '0';
-- end if;
--end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, cur_addr, dst_addr, Req_L_in, Req_L_FF)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in /= Req_L_FF) then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if (flit_type = "001" and empty = '0' and ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='0' ) and dst_addr /= cur_addr and packet_drop_in <= '0' ) then
err_header_not_empty_packet_drop_in <= '1';
else
err_header_not_empty_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '0' and ( ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='1' ) or (dst_addr = cur_addr) ) and packet_drop_in /= packet_drop ) then
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '1';
else
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; | gpl-3.0 |
rogerioag/gcg | tutorial/ula/testbench/inversor_tb.vhd | 1 | 1791 | -- Testebench gerado via script.
-- Data: Sex,30/12/2011-23:36:18
-- Autor: rogerio
-- Comentario: Teste da entidade inversor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity inversor_tb is
end inversor_tb;
architecture logica of inversor_tb is
-- Declaração do componente.
component inversor
port (a: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for inversor_0: inversor use entity work.inversor;
signal s_t_a, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
inversor_0: inversor port map ( a=>s_t_a, y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
('0', '1'),
('1', '0'),
('0', '1'),
('0', '1'),
('1', '0'),
('1', '0')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
| gpl-3.0 |
os-cillation/easyfpga-soc | easy_cores/uart16750/slib_clock_div.vhd | 5 | 2036 | --
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/ScanRegister_for_SIBFCX.vhd | 3 | 2121 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister_for_SIBFCX;
architecture ScanRegister_arch of ScanRegister_for_SIBFCX is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
ue_mux_out <= ue_mux;
end ScanRegister_arch; | gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support.vhd | 3 | 16854 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info <= '0';
health_info <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
health_info <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' and flit_type = "001" then
fault_info <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Processor_NI/alu.vhd | 13 | 2633 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
do_add <= '1' when alu_function = ALU_ADD else '0';
sum <= bv_adder(a_in, b_in, do_add);
less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
else a_in(31);
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else
ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
a_in or b_in when alu_function=ALU_OR else
a_in and b_in when alu_function=ALU_AND else
a_in xor b_in when alu_function=ALU_XOR else
a_in nor b_in when alu_function=ALU_NOR else
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else (others => 'Z');
c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
(others => 'Z');
c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 |
rogerioag/gcg | tutorial/ula/src/or3.vhd | 1 | 348 | -- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: or3.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity or3 is
port(a,b,c:in std_logic; y:out std_logic);
end or3;
architecture estrutural of or3 is
begin
y <= a or b or c;
end estrutural;
| gpl-3.0 |
adelapie/noekeon_inner_round | noekeon_pipelining_inner_k_1/tb_noekeon.vhd | 1 | 5032 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*32;-- + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
-- wait for clk_period + clk_period/2;
-- rst <= '1';
-- enc <= '1';
--
-- a_0_in <= X"e2f687e0";
-- a_1_in <= X"7b75660f";
-- a_2_in <= X"fc372233";
-- a_3_in <= X"bc47532c";
--
-- k_0_in <= X"b1656851";
-- k_1_in <= X"699e29fa";
-- k_2_in <= X"24b70148";
-- k_3_in <= X"503d2dfc";
--
-- wait for clk_period;
-- rst <= '0';
--
-- wait for clk_period*15 + clk_period/2;
--
-- assert a_0_out = X"2a78421b"
-- report "DECRYPT ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"87c7d092"
-- report "DECRYPT ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"4f26113f"
-- report "DECRYPT ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"1d1349b2"
-- report "DECRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 |
rogerioag/gcg | samples/unidade_a2/templates/decl_components_instances.vhd | 5 | 139 | -- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
| gpl-3.0 |
rogerioag/gcg | samples/or2/templates/decl_components_instances.vhd | 5 | 139 | -- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/ddr_ctrl.vhd | 12 | 13365 | ---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
| gpl-3.0 |
os-cillation/easyfpga-soc | easy_cores/pwm/pwm16.vhd | 1 | 3873 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- 16-bit PWM using two-process design pattern
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Type and component definition package
-------------------------------------------------------------------------------
package pwm16_comp is
type pwm16_in_type is record
duty_cycle : std_logic_vector(15 downto 0);
end record;
component pwm16
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm16_in_type;
pwm : out std_logic
);
end component;
end package;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pwm16_comp.all;
-------------------------------------------------------------------------------
ENTITY pwm16 is
-------------------------------------------------------------------------------
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm16_in_type;
pwm : out std_logic
);
end pwm16;
-------------------------------------------------------------------------------
ARCHITECTURE two_proc of pwm16 is
-------------------------------------------------------------------------------
type reg_type is record
pwm_cnt : unsigned(15 downto 0); -- pwm counter
end record;
signal reg_out, reg_in : reg_type;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(d, reg_out)
-------------------------------------------------------------------------------
variable tmp_var : reg_type;
begin
tmp_var := reg_out; -- default assignments
---algorithm-------------------------------------------------------------
-- PWM: reset on overflow, increment otherwise
if (tmp_var.pwm_cnt = 2**16-1) then
tmp_var.pwm_cnt := (others => '0');
else
tmp_var.pwm_cnt := reg_out.pwm_cnt + 1;
end if;
-- compare and drive output
if (tmp_var.pwm_cnt >= unsigned(d.duty_cycle)) then
pwm <= '0';
else
pwm <= '1';
end if;
-------------------------------------------------------------------------
reg_in <= tmp_var; -- drive register inputs
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk,rst)
-------------------------------------------------------------------------------
begin
if rising_edge(clk) then
if (rst = '1') then
reg_out.pwm_cnt <= (others => '0');
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
| gpl-3.0 |
hdlguy/vivado_tcl | source/testbench/chirp_gen_tb.vhd | 1 | 944 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity chirp_gen_tb is
generic(
in_width : natural := 8);
end entity chirp_gen_tb;
architecture rtl of chirp_gen_tb is
--
signal clk : std_logic;
signal reset : std_logic;
signal cos : std_logic_vector(7 downto 0);
signal sin : std_logic_vector(7 downto 0);
--
constant clk_period : time := 10 ns;
--
begin
stim_proc:process
begin
reset <= '1';
wait for clk_period*4;
reset <= '0';
wait;
end process;
uut: entity work.chirp_gen
port map (
clk => clk,
reset => reset,
cos => cos,
sin => sin);
clk_proc:process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end architecture rtl;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre.vhd | 3 | 3021 | --Copyright (C) 2017 Dmitri Mihhailov
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC); -- ScanOutPort
end SIB_mux_pre;
architecture SIB_mux_pre_arch of SIB_mux_pre is
component ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (0 downto 0);
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(0); -- SEL & SR.DO
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR : ScanRegister
Generic map (Size => 1,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0") -- ResetValue 1'b0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_do, -- CaptureSource SR
ScanRegister_out => SR_do);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do, --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_arch; | gpl-3.0 |
Project-Bonfire/KOIT | RTL/Processor_NI/bus_mux.vhd | 16 | 4157 | ---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/bus_mux.vhd | 16 | 4157 | ---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_checkers.vhd | 3 | 22792 | --Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_Req_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_IDLE_grant_N <= '0';
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_Req_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_North_grant_N <= '0';
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_Req_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
end if;
end process;
process (state, req_X_E, X_E)
begin
err_East_grant_E <= '0';
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_Req_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
end if;
end process;
process (state, req_X_W, X_W)
begin
err_West_grant_W <= '0';
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_Req_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
end if;
end process;
process (state, req_X_S, X_S)
begin
err_South_grant_S <= '0';
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_Req_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
end if;
end process;
process (state, req_X_L, X_L)
begin
err_Local_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_Req_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_IDLE_grant_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
err_North_Req_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_North_grant_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
err_East_Req_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
err_East_grant_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
err_West_Req_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
err_West_grant_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_Req_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
err_South_grant_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_Req_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
err_Local_grant_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_Req_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_IDLE_grant_W <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_Req_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_North_grant_W <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_Req_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
err_East_grant_S <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_Req_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
err_West_grant_L <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_Req_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
err_South_grant_N <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_Req_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
err_Local_grant_E <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_Req_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_IDLE_grant_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_Req_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_North_grant_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_Req_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_East_grant_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_Req_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_West_grant_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_Req_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_South_grant_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_Req_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_Local_grant_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_Req_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_IDLE_grant_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_Req_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_North_grant_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_Req_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_East_grant_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_Req_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_West_grant_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_Req_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_South_grant_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_Req_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_Local_grant_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_request_no_grants <= '0';
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
end if;
end process;
process (req_X_N, X_N)
begin
err_no_Req_N_grant_N <= '0';
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
end if;
end process;
process (req_X_E, X_E)
begin
err_no_Req_E_grant_E <= '0';
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
end if;
end process;
process (req_X_W, X_W)
begin
err_no_Req_W_grant_W <= '0';
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
end if;
end process;
process (req_X_S, X_S)
begin
err_no_Req_S_grant_S <= '0';
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
end if;
end process;
process (req_X_L, X_L)
begin
err_no_Req_L_grant_L <= '0';
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
end if;
end process;
end behavior; | gpl-3.0 |
rogerioag/gcg | tutorial/ula/testbench/xnor2_tb.vhd | 1 | 1808 | -- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:19:09
-- Autor: rogerio
-- Comentario: Teste da entidade xnor2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xnor2_tb is
end xnor2_tb;
architecture logica of xnor2_tb is
-- Declaração do componente.
component xnor2
port (a, b: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for xnor2_0: xnor2 use entity work.xnor2;
signal s_t_a, s_t_b, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
xnor2_0: xnor2 port map ( a=>s_t_a, b=>s_t_b, y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a, vi_b: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
('0', '0', '1'),
('0', '1', '0'),
('1', '0', '0'),
('1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop.vhd | 3 | 16426 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if (read_en ='1' or fake_credit = '1') then
credit_in <= '1';
end if;
if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/shifter.vhd | 16 | 3063 | ---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 |
rogerioag/gcg | tutorial/ula/testbench/somador_tb.vhd | 1 | 2382 | -- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: somador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador_tb is
end somador_tb;
architecture estrutural of somador_tb is
-- Declaração do componente.
component somador
port(a, b, cin, opSomador:in std_logic; s, cout: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for somador_0: somador use entity work.somador;
signal t_a, t_b, t_cin, t_opSomador, t_s, t_cout: std_logic;
begin
-- Instanciação do Componente.
somador_0: somador port map (a=>t_a, b=>t_b, cin=>t_cin, opSomador=>t_opSomador, s=>t_s, cout=>t_cout);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
type pattern_type is record
-- entradas.
vi_a, vi_b, vi_cin, vi_opSomador: std_logic;
-- saídas.
vo_s, vo_cout : std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '1', '0', '0'),
('0', '0', '1', '1', '1', '0'),
('0', '1', '0', '1', '1', '0'),
('0', '1', '1', '1', '0', '1'),
('1', '0', '0', '1', '1', '0'),
('1', '0', '1', '1', '0', '1'),
('1', '1', '0', '1', '0', '1'),
('1', '1', '1', '1', '1', '1'),
('1', '1', '1', '0', '0', '0')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
t_a <= patterns(i).vi_a;
t_b <= patterns(i).vi_b;
t_cin <= patterns(i).vi_cin;
t_opSomador <= patterns(i).vi_opSomador;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert t_s = patterns(i).vo_s
report "Valor de t_s não confere com o resultado esperado." severity error;
assert t_cout = patterns(i).vo_cout
report "Valor de t_cout não confere com o resultado esperado."severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end estrutural;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/mem_wrap_tb.vhd | 3 | 2401 | --Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.TB_Package.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity mem_wrap_tb is
end mem_wrap_tb;
architecture behavior of mem_wrap_tb is
-- Declaring network component
constant clk_period : time := 10 ns;
signal clk, reset, enable: std_logic := '0';
signal write_byte_enable: std_logic_vector(3 downto 0);
signal address: std_logic_vector(31 downto 2);
signal data_write, data_read: std_logic_vector(31 downto 0);
component ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --entity ram
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after clk_period;
ram_unit: ram port map(clk, reset, enable, write_byte_enable, address, data_write, data_read);
process(clk)
variable counter: integer := 0;
begin
if reset = '0' then
counter := 0;
enable <= '0';
write_byte_enable <= "0000";
address <= (others => '0');
data_write <= (others => '0');
elsif falling_edge(clk) then
if counter < 10 then
enable <= '1';
address <= address + 1;
write_byte_enable <= "1111";
data_write <= data_write + 1;
counter := counter +1;
else
if counter < 20 then
address <= address - 1;
enable <= '1';
write_byte_enable <= "0000";
counter := counter +1;
else
enable <= '0';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 |
rogerioag/gcg | tutorial/ula/testbench/and2_tb.vhd | 1 | 1834 | -- Testebench gerado via script.
-- Data: Qua,20/07/2011-14:18:43
-- Autor: rogerio
-- Comentario: Teste da entidade and2.
library ieee;
use ieee.std_logic_1164.all;
entity and2_tb is
end and2_tb;
architecture logica of and2_tb is
-- Declaração do componente.
component and2
port (a,b: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for and2_0: and2 use entity work.and2;
signal s_t_a, s_t_b, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
and2_0: and2 port map (a=>s_t_a,b=>s_t_b,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a,vi_b: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0'),
('0', '1', '0'),
('1', '0', '0'),
('1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
| gpl-3.0 |
iocoder/graduation | hardware/tlc.vhd | 1 | 9470 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TLC is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- LED:
LED : out STD_LOGIC_VECTOR ( 7 downto 0);
-- VGA Connector
R : out STD_LOGIC_VECTOR ( 2 downto 0);
G : out STD_LOGIC_VECTOR ( 2 downto 0);
B : out STD_LOGIC_VECTOR ( 1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC := '0';
ST_STS : in STD_LOGIC := '0';
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC := '0';
PS2DATA : in STD_LOGIC := '0'
);
end TLC;
architecture Structural of TLC is
component cpu is
Port (
CLK : in STD_LOGIC;
IRQ : in STD_LOGIC;
NMI : in STD_LOGIC;
IAK : out STD_LOGIC;
NAK : out STD_LOGIC;
-- system bus
MEME : out STD_LOGIC;
RW : out STD_LOGIC;
ADDR : out STD_LOGIC_VECTOR (31 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : out STD_LOGIC_VECTOR ( 2 downto 0);
RDY : in STD_LOGIC
);
end component;
component memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : in STD_LOGIC; -- 0: read, 1: write
A : in STD_LOGIC_VECTOR (23 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC;
-- External Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1'; -- active low
WE : out STD_LOGIC := '1'; -- active low
MT_ADV : out STD_LOGIC := '0'; -- active low
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1'; -- active low
MT_LB : out STD_LOGIC := '1'; -- active low
MT_CE : out STD_LOGIC := '1'; -- active low
MT_CRE : out STD_LOGIC := '0'; -- active high
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1'; -- active low
ST_CE : out STD_LOGIC := '1' -- active low
);
end component;
component vga is
Port ( CLK : in STD_LOGIC; -- 50MHz clock input
-- System Bus
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
RDY : out STD_LOGIC := '0';
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
-- VGA Port
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end component;
component kbdctl is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Output:
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- System bus interface:
EN : in STD_LOGIC;
RW : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
RDY : out STD_LOGIC;
-- Interrupt Logic:
INT : out STD_LOGIC;
IAK : in STD_LOGIC
);
end component;
component pit is
Port (
CLK : in STD_LOGIC;
IRQ : out STD_LOGIC;
IAK : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1');
end component;
component pic is
Port (
CLK : in STD_LOGIC;
IRQ_in : in STD_LOGIC_VECTOR (7 downto 0);
IAK_out : out STD_LOGIC_VECTOR (7 downto 0);
IRQ_out : out STD_LOGIC := '0';
IAK_in : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1'
);
end component;
-- CPU signals
signal IRQ : STD_LOGIC := '0';
signal NMI : STD_LOGIC := '0';
signal IAK : STD_LOGIC := '0';
signal NAK : STD_LOGIC := '0';
-- System bus:
signal MEME : STD_LOGIC := '0';
signal RW : STD_LOGIC := '0';
signal Address : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataCPUToMem : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataMemToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataRAMToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataVGAToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataKBDToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPITToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPICToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DTYPE : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
signal RAM_CS : STD_LOGIC := '0';
signal ROM_CS : STD_LOGIC := '0';
signal VGA_CS : STD_LOGIC := '0';
signal KBD_CS : STD_LOGIC := '0';
signal PIT_CS : STD_LOGIC := '0';
signal PIC_CS : STD_LOGIC := '0';
signal MEM_RDY : STD_LOGIC := '0';
signal VGA_RDY : STD_LOGIC := '0';
signal KBD_RDY : STD_LOGIC := '0';
signal PIT_RDY : STD_LOGIC := '0';
signal PIC_RDY : STD_LOGIC := '0';
signal RDY : STD_LOGIC := '0';
signal IRQ_to_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal IAK_from_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
begin
------------- memory map -------------
-- 0x00000000 - 0x00FFFFFF : RAM
-- 0x1E000000 - 0x1E003FFF : VGA
-- 0x1E800000 - 0x1E800FFF : KBD
-- 0x1E801000 - 0x1E801FFF : PIT
-- 0x1E802000 - 0x1E802FFF : PIC
-- 0x1EC02000 - 0x1EC02007 : PPU
-- 0x1F000000 - 0x1FFFFFFF : ROM
-- memory decoding
RAM_CS <= MEME when Address(31 downto 24) = x"00" else '0';
ROM_CS <= MEME when Address(31 downto 24) = x"1F" else '0';
VGA_CS <= MEME when Address(31 downto 14) = x"1E00"&"00" or
Address(31 downto 12) = x"1EC02" else '0';
KBD_CS <= MEME when Address(31 downto 12) = x"1E800" else '0';
PIT_CS <= MEME when Address(31 downto 12) = x"1E801" else '0';
PIC_CS <= MEME when Address(31 downto 12) = x"1E802" else '0';
DataMemToCPU <= DataRAMToCPU when ROM_CS = '1' or RAM_CS = '1' else
DataVGAToCPU when VGA_CS = '1' else
DataKBDToCPU when KBD_CS = '1' else
DataPITToCPU when PIT_CS = '1' else
DataPICToCPU when PIC_CS = '1' else
x"00000000";
RDY <= MEM_RDY when ROM_CS = '1' or RAM_CS = '1' else
VGA_RDY when VGA_CS = '1' else
KBD_RDY when KBD_CS = '1' else
PIT_RDY when PIT_CS = '1' else
PIC_RDY when PIC_CS = '1' else
'0';
-- subblocks
U1: cpu port map (CLK, IRQ, NMI, IAK, NAK,
MEME, RW, Address, DataMemToCPU, DataCPUToMem, DTYPE, RDY);
U2: memif port map (CLK,
RAM_CS, ROM_CS, RW, Address(23 downto 0),
DataCPUToMem(31 downto 0), DataRAMToCPU(31 downto 0),
DTYPE, MEM_RDY, ADDR, DATA, OE, WE,
MT_ADV, MT_CLK, MT_UB, MT_LB, MT_CE, MT_CRE, MT_WAIT,
ST_STS, RP, ST_CE);
U3: vga port map (CLK, VGA_CS, RW,
Address(13 downto 0), DataCPUToMem(15 downto 0),
DataVGAToCPU(15 downto 0), VGA_RDY,
IRQ_to_PIC(3), IAK_from_PIC(3),
R, G, B, HS, VS);
U4: kbdctl port map (CLK, PS2CLK, PS2DATA, LED,
KBD_CS, RW, DataKBDToCPU(7 downto 0), KBD_RDY,
IRQ_to_PIC(1), IAK_from_PIC(1));
U5: pit port map (CLK, IRQ_to_PIC(0), IAK_from_PIC(0),
PIT_CS, RW, DataCPUToMem, DataPITToCPU, DTYPE, PIT_RDY);
U6: pic port map (CLK, IRQ_to_PIC, IAK_from_PIC, IRQ, IAK,
PIC_CS, RW, DataCPUToMem, DataPICToCPU, DTYPE, PIC_RDY);
end Structural;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_au.vhd | 1 | 17905 | --------------------------------------------------------------------------------
-- Title : DMA adress unit
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_au.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module provides the adresses and byte enables for the
-- dma operation.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_au
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_dma_au.vhd,v $
-- Revision 1.3 2013/09/12 08:45:28 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.2 2012/08/27 12:57:18 MMiehling
-- removed dma_size_counter instance and implemented as common source code
-- adopted tga logic
--
-- Revision 1.1 2012/03/29 10:14:45 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:02:20 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:23 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:19:38 mmiehling
-- improved timing
-- fixed boundary errors
-- changed dma_size_cnt to lpm
--
-- Revision 1.3 2004/08/13 15:41:10 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:20 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:48 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY vme_dma_au IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_signals
adr_o : OUT std_logic_vector(31 DOWNTO 0); -- adress for wb-bus
sel_o : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for wb_bus
we_o : OUT std_logic; -- write/read
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
cyc_o_sram : OUT std_logic; -- chip select for sram
cyc_o_pci : OUT std_logic; -- chip select for pci
cyc_o_vme : OUT std_logic; -- chip select for vme
stb_o : IN std_logic; -- request signal for cyc switching
-- fifo
fifo_empty : in std_logic;
fifo_full : in std_logic;
-- vme_dma_mstr
sour_dest : IN std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : IN std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : IN std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : OUT std_logic; -- if all data from one bd was read and stored in the fifo
load_cnt : IN std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : OUT std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : out std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : out std_logic; -- if all data from one bd was read and stored in the fifo
clr_dma_act_bd : IN std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
dma_act_bd : OUT std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
dma_dest_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : IN std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : IN std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : IN std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : IN std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0) -- size of data package
);
END vme_dma_au;
ARCHITECTURE vme_dma_au_arch OF vme_dma_au IS
CONSTANT dma_size_cnt_val : std_logic_vector(15 DOWNTO 0):= x"0001";
SIGNAL dma_act_bd_int : std_logic_vector(7 DOWNTO 2);
SIGNAL blk_int : std_logic;
SIGNAL dma_size_int : std_logic_vector(15 DOWNTO 0);
SIGNAL dma_sour_adr_int : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_dest_adr_int : std_logic_vector(31 DOWNTO 2);
signal dma_sour_adr_blt : std_logic_vector(31 downto 2);
signal dma_dest_adr_blt : std_logic_vector(31 downto 2);
SIGNAL cyc_o_sram_int : std_logic;
SIGNAL cyc_o_pci_int : std_logic;
SIGNAL cyc_o_vme_int : std_logic;
SIGNAL adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL reached_size_int : std_logic;
SIGNAL almost_reached_size_int : std_logic;
SIGNAL boundary_blt : std_logic;
SIGNAL boundary_blt_d1 : std_logic;
SIGNAL boundary_mblt : std_logic;
SIGNAL almost_boundary_blt : std_logic;
SIGNAL almost_boundary_mblt : std_logic;
SIGNAL dma_size_en : std_logic;
signal tga_int : std_logic_vector(8 DOWNTO 0);
signal dma_vme_am_conv : std_logic_vector(1 DOWNTO 0);
signal trans_blt_src : std_logic;
signal trans_blt_dst : std_logic;
signal fifo_empty_d1 : std_logic;
signal fifo_full_d1 : std_logic;
signal boundary_blt_edge : std_logic;
signal fifo_empty_edge : std_logic;
signal fifo_full_edge : std_logic;
BEGIN
cyc_o_sram <= cyc_o_sram_int WHEN stb_o = '1' ELSE '0';
cyc_o_pci <= cyc_o_pci_int WHEN stb_o = '1' ELSE '0';
cyc_o_vme <= cyc_o_vme_int WHEN stb_o = '1' ELSE '0';
-- perform VME block transfer when
-- 1. block transfer configured and access to source selected and source address shall be incremented
-- 2. block transfer configured and access to destination selected and destination address shall be incremented
-- 3. else single transfer
blk_int <= '1' when blk_sgl = '0' and sour_dest = '0' and inc_sour = '0' else
'1' when blk_sgl = '0' and sour_dest = '1' and inc_dest = '0' else
'0';
dma_act_bd <= dma_act_bd_int;
reached_size_int <= '1' WHEN dma_size_int = dma_size ELSE '0';
almost_reached_size_int <= '1' WHEN (dma_size_int + 1) = dma_size ELSE '0';
adr_o_int(31 DOWNTO 2) <= x"000f_f9" & dma_act_bd_int WHEN get_bd = '1' ELSE -- switch iram adress [10:2] to adr_o
dma_sour_adr when (sour_dest = '1' and inc_sour = '1') else -- keep src address from the descriptor
dma_sour_adr_blt when (sour_dest = '1' and inc_sour = '0' and trans_blt_src = '1') else
dma_sour_adr_int when (sour_dest = '1' and inc_sour = '0') else -- switch source adress to adr_o & dma_access & swap
dma_dest_adr when (sour_dest = '0' and inc_dest = '1') else -- keep dst address from the descriptor
dma_dest_adr_blt when (sour_dest = '0' and inc_sour = '0' and trans_blt_dst = '1') else
dma_dest_adr_int ; -- switch destination adress to adr_o & dma_access & swap
adr_o_int(1 DOWNTO 0) <= "00";
boundary <= boundary_blt OR boundary_mblt;
almost_boundary <= almost_boundary_blt OR almost_boundary_mblt;
-- rising edge pulses
boundary_blt_edge <= boundary_blt and (not boundary_blt_d1);
fifo_empty_edge <= fifo_empty and (not fifo_empty_d1);
fifo_full_edge <= fifo_full and (not fifo_full_d1);
sel_o <= (OTHERS => '1'); -- always longword accessess
dma_vme_am_conv <= "10" when dma_vme_am(1 DOWNTO 0) = "01" else -- A32
"01" when dma_vme_am(1 DOWNTO 0) = "10" else -- A16
"00"; -- A24
-- (1:0) : 00=A24, 01=A32, 10=A16
-- (3:2) : 00=D16, 01=D32, 10=D64
-- (4) : if increment enabled the burst else single
-- (5) : swapped(1) or non swapped (0)
-- (6) : =0 always VME bus access (no register access)
-- (7) : =1 indicates access to vme_ctrl by DMA
-- (8) : 0= non-privileged 1= supervisory
tga_int <= dma_vme_am(4) & "10" & NOT dma_vme_am(0) & blk_int & dma_vme_am(3 DOWNTO 2) & dma_vme_am_conv;
-- A32D32 BLT transfer
trans_blt_src <= '1' when (dma_sour_device(1) = '1' and dma_vme_am(3 downto 2) = "01" and blk_int = '1') else
'0';
trans_blt_dst <= '1' when (dma_dest_device(1) = '1' and dma_vme_am(3 downto 2) = "01" and blk_int = '1') else
'0';
adr_o_proc : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
adr_o <= (OTHERS => '0');
dma_sour_adr_int <= (OTHERS => '0');
dma_dest_adr_int <= (OTHERS => '0');
dma_act_bd_int <= (OTHERS => '0');
cyc_o_sram_int <= '0';
cyc_o_pci_int <= '0';
cyc_o_vme_int <= '0';
we_o <= '0';
reached_size <= '0';
almost_reached_size <= '0';
tga_o <= (OTHERS => '0');
boundary_blt <= '0';
boundary_blt_d1 <= '0';
boundary_mblt <= '0';
almost_boundary_blt <= '0';
almost_boundary_mblt <= '0';
dma_sour_adr_blt <= (others=>'0');
dma_dest_adr_blt <= (others=>'0');
ELSIF clk'EVENT AND clk = '1' THEN
-- rule of vmebus: do not cross 256 byte boundaries (0x100)
IF dma_vme_am(3) = '0' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "000000" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "000000" AND sour_dest = '1')) THEN
boundary_blt <= '1';
ELSE
boundary_blt <= '0';
END IF;
IF dma_vme_am(3) = '0' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "111111" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "111111" AND sour_dest = '1')) THEN
almost_boundary_blt <= '1';
ELSE
almost_boundary_blt <= '0';
END IF;
-- for mblt-d64: do not cross 2k byte boundaries (0x800)
IF dma_vme_am(3) = '1' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "000000" AND dma_dest_adr_int(10 DOWNTO 8) = "000" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "000000" AND dma_sour_adr_int(10 DOWNTO 8) = "000" AND sour_dest = '1')) THEN
boundary_mblt <= '1';
ELSE
boundary_mblt <= '0';
END IF;
IF dma_vme_am(3) = '1' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(10 DOWNTO 2) = "111111111" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(10 DOWNTO 2) = "111111111" AND sour_dest = '1')) THEN
almost_boundary_mblt <= '1';
ELSE
almost_boundary_mblt <= '0';
END IF;
IF inc_adr = '1' OR get_bd = '1' THEN
adr_o <= adr_o_int;
END IF;
IF load_cnt = '1' THEN
reached_size <= '0';
if dma_size = conv_std_logic_vector(0, 16) then -- if just one longword shall be transfered, indicate almost reached
almost_reached_size <= '1';
else
almost_reached_size <= '0';
end if;
ELSIF inc_adr = '1' AND sour_dest = '1' THEN
reached_size <= reached_size_int;
almost_reached_size <= almost_reached_size_int;
END IF;
IF get_bd = '1' THEN
cyc_o_sram_int <= '1';
cyc_o_pci_int <= '0';
cyc_o_vme_int <= '0';
we_o <= '0'; -- only reading from sram
tga_o <= (OTHERS => '0');
ELSIF sour_dest = '1' THEN -- SOURCE
cyc_o_sram_int <= dma_sour_device(0);
cyc_o_vme_int <= dma_sour_device(1);
cyc_o_pci_int <= dma_sour_device(2);
we_o <= '0'; -- read from source
if dma_sour_device(1) = '1' then -- if access to vme range, use tga for space selection
tga_o <= tga_int;
else -- if access to SRAM or PCI => no special tga setting
tga_o <= (OTHERS => '0');
end if;
ELSE -- DESTINATION
cyc_o_sram_int <= dma_dest_device(0);
cyc_o_vme_int <= dma_dest_device(1);
cyc_o_pci_int <= dma_dest_device(2);
we_o <= '1'; -- write to destination
if dma_dest_device(1) = '1' then -- if access to vme range, use tga for space selection
tga_o <= tga_int;
else -- if access to SRAM or PCI => no special tga setting
tga_o <= (OTHERS => '0');
end if;
END IF;
IF load_cnt = '1' THEN
dma_sour_adr_int <= dma_sour_adr;
ELSIF get_bd = '0' AND sour_dest = '1' AND inc_adr = '1' THEN
dma_sour_adr_int <= dma_sour_adr_int + 1;
END IF;
IF load_cnt = '1' THEN
dma_dest_adr_int <= dma_dest_adr;
ELSIF get_bd = '0' AND sour_dest = '0' AND inc_adr = '1' THEN
dma_dest_adr_int <= dma_dest_adr_int + 1;
END IF;
boundary_blt_d1 <= boundary_blt;
fifo_empty_d1 <= fifo_empty;
fifo_full_d1 <= fifo_full;
-- address regiters for BLT
if load_cnt = '1' then
dma_sour_adr_blt <= dma_sour_adr;
elsif sour_dest = '1' and (boundary_blt_edge = '1' or fifo_full_edge = '1') then
-- remember address value for new BLT transfer
dma_sour_adr_blt <= dma_sour_adr_int;
end if;
if load_cnt = '1' then
dma_dest_adr_blt <= dma_dest_adr;
elsif sour_dest = '0' and (boundary_blt_edge = '1' or fifo_empty_edge = '1') then
-- remember address value for new BLT transfer
dma_dest_adr_blt <= dma_dest_adr_int;
end if;
IF start_dma = '1' OR clr_dma_act_bd = '1' THEN
dma_act_bd_int <= (OTHERS => '0');
ELSIF get_bd = '1' AND inc_adr = '1' THEN
dma_act_bd_int <= dma_act_bd_int + 1;
END IF;
END IF;
END PROCESS adr_o_proc;
dma_size_en <= '1' WHEN sour_dest = '1' AND inc_adr = '1' ELSE '0';
size_cnt: PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
dma_size_int <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF load_cnt = '1' THEN
dma_size_int <= (OTHERS => '0');
ELSIF dma_size_en = '1' THEN
dma_size_int <= dma_size_int + 1;
END IF;
END IF;
END PROCESS size_cnt;
END vme_dma_au_arch;
| gpl-3.0 |
chiwanpark/flamingo2 | flamingo2-web/src/main/webapp/resources/build/production/Flamingo2/resources/lib/aceeditor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/fpga_pkg_2_16zxxx.vhd | 1 | 2791 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for IP-Core top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_16zxxx.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_16zxxx.vhd
-- - one_device.vhd
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_16zxxx.vhd,v $
-- Revision 1.2 2009/02/17 11:37:40 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:56 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/24 16:39:57 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_16zxxx IS
GENERIC (
FPGA_FAMILY : family_type := CYCLONE
);
PORT(
dummy : OUT std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_16zxxx_arch OF fpga_pkg_2_16zxxx IS
CONSTANT SUPPORTED_DEVICES : supported_family_type := (CYCLONE);
COMPONENT one_device
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
BEGIN
-- coverage off
ASSERT NOT NO_VALID_DEVICE(supported_device => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "No valid DEVICE!" SEVERITY failure;
-- coverage on
the_one_device : one_device
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy
);
END ARCHITECTURE fpga_pkg_2_16zxxx_arch;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z100-00_src/Source/wbmon.vhd | 1 | 23976 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.8 $
--
-- $Log: wbmon.vhd,v $
-- Revision 1.8 2015/06/15 16:40:04 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.7 2010/03/01 09:28:34 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.6 2008/10/27 08:42:22 skrieger
-- R: The wrong address is displayed during an access (lower than 32 bit) to a not 32-bit-alligned address. Example: 8-bit access to address 0x00000001
-- is displayed as 8-bit access to address 0x00000000 but with the same data.
-- M: Changed data output that a 32-bit-alligned address will be output but with the correct data and with the corresponding select-lines.
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
);
END wbmon;
ARCHITECTURE wbmon_arch OF wbmon IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT bitaccess : IN natural;
CONSTANT val : in std_logic_vector--(7 DOWNTO 0)
) RETURN string is
VARIABLE reglen : natural := 1;
VARIABLE result_str : string(1 to (bitaccess / 4));
VARIABLE slv : std_logic_vector(bitaccess-1 DOWNTO 0);-- := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
slv := val;
IF bitaccess = 8 THEN
reglen := 1;
ELSIF bitaccess = 16 THEN
reglen := 3;
ELSIF bitaccess = 32 THEN
reglen := 7;
ELSIF bitaccess = 64 THEN
reglen := 15;
ELSE
END IF;
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(reglen + 1 - i) := '0';
WHEN "0001" => result_str(reglen + 1 - i) := '1';
WHEN "0010" => result_str(reglen + 1 - i) := '2';
WHEN "0011" => result_str(reglen + 1 - i) := '3';
WHEN "0100" => result_str(reglen + 1 - i) := '4';
WHEN "0101" => result_str(reglen + 1 - i) := '5';
WHEN "0110" => result_str(reglen + 1 - i) := '6';
WHEN "0111" => result_str(reglen + 1 - i) := '7';
WHEN "1000" => result_str(reglen + 1 - i) := '8';
WHEN "1001" => result_str(reglen + 1 - i) := '9';
WHEN "1010" => result_str(reglen + 1 - i) := 'A';
WHEN "1011" => result_str(reglen + 1 - i) := 'B';
WHEN "1100" => result_str(reglen + 1 - i) := 'C';
WHEN "1101" => result_str(reglen + 1 - i) := 'D';
WHEN "1110" => result_str(reglen + 1 - i) := 'E';
WHEN "1111" => result_str(reglen + 1 - i) := 'F';
WHEN others => result_str(reglen + 1 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION data_out (sel : std_logic_vector(3 downto 0); dat : std_logic_vector(31 downto 0)) RETURN string IS
variable byte0 : string(1 to 2);
variable byte1 : string(1 to 2);
variable byte2 : string(1 to 2);
variable byte3 : string(1 to 2);
BEGIN
if sel(0) = '1' then
byte0 := to_hstring(8,dat( 7 downto 0));
else
byte0 := "XX";
end if;
if sel(1) = '1' then
byte1 := to_hstring(8,dat(15 downto 8));
else
byte1 := "XX";
end if;
if sel(2) = '1' then
byte2 := to_hstring(8,dat(23 downto 16));
else
byte2 := "XX";
end if;
if sel(3) = '1' then
byte3 := to_hstring(8,dat(31 downto 24));
else
byte3 := "XX";
end if;
return (byte3 & byte2 & "_" & byte1 & byte0);
end data_out;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 4);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 8);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(31 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (3 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(31 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 4;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,"Master Data Out changed during burst cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_b)&")", x"02", enable , ERROR, sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 4;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb = '1' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon_arch; | gpl-3.0 |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_wbm.vhd | 1 | 10259 | --------------------------------------------------------------------------------
-- Title : Wishbone Master Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_wbm.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 11/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The module handles the wishbone master accesses to PCI or SRAM space. If a
-- VME access to the slave gets received, the vme_slave will forward this to
-- vme_wbm. All wishbone accesses are single read/write. If there is a
-- read-modify-write request, the cyc signal between the read and write access
-- on the wishbone bus will be keept asserted to prevent access to the same
-- location in between.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_wbm
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: vme_wbm.vhd,v $
-- Revision 1.4 2012/11/12 08:13:04 MMiehling
-- changed comments
--
-- Revision 1.3 2012/09/25 11:21:39 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:04 MMiehling
-- added sl_en_vma_dat_out_reg_high for d64 access
--
-- Revision 1.1 2012/03/29 10:14:29 MMiehling
-- Initial Revision
--
-- Revision 1.8 2004/11/02 11:29:40 mmiehling
-- removed iram access
--
-- Revision 1.7 2004/07/27 17:15:25 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.6 2003/12/17 15:51:35 MMiehling
-- optimized performance
--
-- Revision 1.5 2003/12/01 10:03:26 MMiehling
-- changed all
--
-- Revision 1.4 2003/06/24 13:46:47 MMiehling
-- removed burst; added loc_keep
--
-- Revision 1.3 2003/06/13 10:06:16 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/22 11:02:49 MMiehling
-- improved fsm
--
-- Revision 1.1 2003/04/01 13:04:27 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_wbm IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- mensb master
loc_keep : IN std_logic; -- if '1', csn remains active (keeps bus)
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : IN std_logic;
vme_cyc_sram : OUT std_logic; -- keeps bus arbitration to sram as long as active
vme_cyc_pci : OUT std_logic; -- keeps bus arbitration to pci as long as active
-- vme_slave
mensb_mstr_req : IN std_logic; -- mensb master request
mensb_mstr_ack : OUT std_logic; -- mensb master acknoledge
-- vme_du
sel_wbm_dat_o : OUT std_logic;
en_wbm_dat_o : OUT std_logic;
sl_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
sl_en_vme_data_out_reg_high : OUT std_logic; -- for d64 high
-- vme_au
inc_loc_adr_m_cnt : OUT std_logic;
sl_acc_wb : IN std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
pci_acc : IN std_logic; -- pci access is requested by vmebus
sram_acc : IN std_logic -- sram access is requested by vmebus
);
END vme_wbm;
ARCHITECTURE vme_wbm_arch OF vme_wbm IS
TYPE loc_mstr_states IS (idle, req_bus, req_bus2, wait_on_end);
SIGNAL loc_mstr_state : loc_mstr_states;
SIGNAL wbm_stb_o_int : std_logic;
SIGNAL inc_wbm_cnt : std_logic;
SIGNAL mensb_mstr_ack_int : std_logic;
SIGNAL d64_high : std_logic;
SIGNAL sl_en_vme_data_out_reg_int : std_logic;
BEGIN
wbm_stb_o <= wbm_stb_o_int;
inc_loc_adr_m_cnt <= inc_wbm_cnt;
mensb_mstr_ack <= mensb_mstr_ack_int;
-- the wb-bus arbitration will be released when a single vme-transaction is done (done when asn is deasserted)
-- in case of a rmw-cycle the asn-signal will be asserted between the two transactions => the wb-bus cyc-signal
-- will also be asserted between these two transactions
-- in case of a burst, the asn-signal is asserted all the time, but the wb-bus will be released after each
-- single transaction, in order to prevent bus errors on pci-bus
regs : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
vme_cyc_sram <= '0';
vme_cyc_pci <= '0';
d64_high <= '0';
ELSIF clk'EVENT AND clk = '1' then
IF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND (wbm_we_o = '1' OR sl_acc_wb(1) = '1' OR sl_acc_wb(0) = '1')) -- burst or write
OR (loc_keep = '1' AND wbm_we_o = '0') THEN -- read and not burst (read of rmw)
vme_cyc_sram <= '0';
vme_cyc_pci <= '0';
ELSIF mensb_mstr_req = '1' AND mensb_mstr_ack_int = '0' THEN
vme_cyc_sram <= sram_acc;
vme_cyc_pci <= pci_acc;
END IF;
IF d64_high = '0' AND sl_en_vme_data_out_reg_int = '1' AND sl_acc_wb(0) = '1' AND wbm_we_o = '0' THEN
d64_high <= '1';
ELSIF sl_en_vme_data_out_reg_int = '1' THEN
d64_high <= '0';
END IF;
END IF;
END PROCESS regs;
sl_en_vme_data_out_reg <= sl_en_vme_data_out_reg_int WHEN d64_high = '0' ELSE '0';
sl_en_vme_data_out_reg_high <= sl_en_vme_data_out_reg_int WHEN d64_high = '1' ELSE '0';
loc_mstr_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
loc_mstr_state <= idle;
wbm_stb_o_int <= '0';
mensb_mstr_ack_int <= '0';
en_wbm_dat_o <= '1';
sel_wbm_dat_o <= '0';
inc_wbm_cnt <= '0';
sl_en_vme_data_out_reg_int <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE loc_mstr_state IS
WHEN idle =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '0';
sel_wbm_dat_o <= '0';
IF mensb_mstr_req = '1' AND (sram_acc = '1' OR pci_acc = '1') THEN
loc_mstr_state <= req_bus;
wbm_stb_o_int <= '1';
en_wbm_dat_o <= '0'; -- stop loading wbm_dat_o
ELSE
loc_mstr_state <= idle;
wbm_stb_o_int <= '0';
en_wbm_dat_o <= '1'; -- always enable
END IF;
WHEN req_bus =>
IF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND sl_acc_wb(0) = '0') OR mensb_mstr_req = '0' THEN
sl_en_vme_data_out_reg_int <= '1';
loc_mstr_state <= wait_on_end;
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '1';
wbm_stb_o_int <= '0';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '0';
ELSIF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND sl_acc_wb(0) = '1') OR mensb_mstr_req = '0' THEN
sl_en_vme_data_out_reg_int <= '1';
inc_wbm_cnt <= '1'; -- increment wbm_cnt
IF wbm_we_o = '1' THEN
mensb_mstr_ack_int <= '0'; -- not yet ack, because two cycles has to be done
loc_mstr_state <= req_bus2;
ELSE
mensb_mstr_ack_int <= '1'; -- ack, because first d32 can be put to external driver
loc_mstr_state <= wait_on_end;
END IF;
wbm_stb_o_int <= '0'; -- one cycle break
en_wbm_dat_o <= '1'; -- put high d32 in wbm_dat_o
sel_wbm_dat_o <= '1';
ELSE
sl_en_vme_data_out_reg_int <= '0';
loc_mstr_state <= req_bus;
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '1';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '0';
END IF;
WHEN req_bus2 =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '1';
IF (wbm_ack_i = '1' OR wbm_err_i = '1') OR mensb_mstr_req = '0' THEN
loc_mstr_state <= wait_on_end;
mensb_mstr_ack_int <= '1';
wbm_stb_o_int <= '0';
ELSE
loc_mstr_state <= req_bus2;
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '1';
END IF;
WHEN wait_on_end =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
wbm_stb_o_int <= '0';
loc_mstr_state <= idle;
mensb_mstr_ack_int <= '0';
sel_wbm_dat_o <= '0';
WHEN OTHERS =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
loc_mstr_state <= idle;
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '0';
sel_wbm_dat_o <= '0';
END CASE;
END IF;
END PROCESS loc_mstr_fsm;
END vme_wbm_arch;
| gpl-3.0 |
michaelmiehling/A25_VME | Source/wb_adr_dec.vhd | 1 | 5389 |
---------------------------------------------------------------
-- Title : Adress decoder for whisbone bus
-- Project : <A025-00>
---------------------------------------------------------------
-- File : wb_adr_dec.vhd
-- Author : Chameleon_V2.exe
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2017/6/1 - 12:2:21
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description : Created with Chameleon_V2.exe
-- v1.18
-- 2016-06-14
--
--
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 10 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 200 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- | 16z002-01 VME CR/CSR | 9 | 0 | 1000000 | 4 |
-- +-------------------------------+-----+----------+----------+-----+
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2017, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
ENTITY wb_adr_dec IS
PORT (
pci_cyc_i : IN std_logic_vector(4 DOWNTO 0);
wbm_adr_o_q : IN std_logic_vector(31 DOWNTO 2);
wbm_cyc_o : OUT std_logic_vector(9 DOWNTO 0)
);
END wb_adr_dec;
ARCHITECTURE wb_adr_dec_arch OF wb_adr_dec IS
SIGNAL zero : std_logic_vector(4 DOWNTO 0);
BEGIN
zero <= (OTHERS => '0');
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(9 DOWNTO 0);
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 10 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 4) = "00000000100000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "010000000" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CR/CSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF pci_cyc_i /= zero AND wbm_cyc_o_int = "0000000000" THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
END wb_adr_dec_arch;
| gpl-3.0 |
iocoder/graduation | hardware/cpu/clkdiv.vhd | 1 | 2575 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.cpu_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clkdiv is
Port (
CLK : in STD_LOGIC;
-- CPU interface
CLK50MHz : out STD_LOGIC := '0';
CLK25MHz : out STD_LOGIC := '0';
CLK2MHz : out STD_LOGIC := '0';
CLK1MHz : out STD_LOGIC := '0';
CACHE_EN : out STD_LOGIC := '0'
);
end entity;
architecture Behavioral of clkdiv is
signal oCLK1MHz : STD_LOGIC := '0';
signal oCLK2MHz : STD_LOGIC := '0';
signal oCLK12_5MHz : STD_LOGIC := '0';
signal oCLK6_25MHz : STD_LOGIC := '0';
signal oCLK3_150MHz : STD_LOGIC := '0';
signal oCLK1_5MHz : STD_LOGIC := '0';
signal oCLK25MHz : STD_LOGIC := '0';
signal oCLK50MHz : STD_LOGIC := '0';
signal bCLK25MHz : STD_LOGIC := '0';
signal bCLK50MHz : STD_LOGIC := '0';
attribute clock_signal : string;
attribute clock_signal of oCLK50MHz : signal is "yes";
attribute clock_signal of oCLK25MHz : signal is "yes";
signal counter1MHz : integer := 24;
signal counter2MHz : integer := 11;
signal delay : integer := 3;
begin
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
if (delay /= 0) then
delay <= delay - 1;
end if;
end if;
end process;
oCLK50MHz <= CLK when delay = 0 else '0';
CACHE_EN <= '1' when delay = 0 else '0';
process (oCLK50MHz)
begin
if ( oCLK50MHz = '1' and oCLK50MHz'event ) then
oCLK25MHz <= NOT oCLK25MHz;
end if;
if ( oCLK25MHz = '1' and oCLK25MHz'event ) then
oCLK12_5MHz <= NOT oCLK12_5MHz;
end if;
if ( oCLK12_5MHz = '1' and oCLK12_5MHz'event ) then
oCLK6_25MHz <= NOT oCLK6_25MHz;
end if;
if ( oCLK6_25MHz = '1' and oCLK6_25MHz'event ) then
oCLK3_150MHz <= NOT oCLK3_150MHz;
end if;
if ( oCLK3_150MHz = '1' and oCLK3_150MHz'event ) then
oCLK1_5MHz <= NOT oCLK1_5MHz;
end if;
if ( oCLK50MHz = '1' and oCLK50MHz'event ) then
if (counter2MHz = 11) then
oCLK2MHz <= NOT oCLK2MHz;
counter2MHz <= 0;
else
counter2MHz <= counter2MHz + 1;
end if;
end if;
if ( oCLK2MHz = '1' and oCLK2MHz'event ) then
oCLK1MHz <= NOT oCLK1MHz;
end if;
end process;
bufg0 : bufg port map(i=>oCLK50MHz, o=>bCLK50MHz);
bufg1 : bufg port map(i=>oCLK25MHz, o=>bCLK25MHz);
CLK50MHz <= bCLK50MHz;
CLK25MHz <= bCLK25MHz;
CLK2MHz <= oCLK2MHz;
CLK1MHz <= oCLK1MHz;
end Behavioral;
| gpl-3.0 |
iocoder/graduation | hardware/cpu/cachearray.vhd | 1 | 1836 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.cpu_pkg.all;
entity cachearray is
Port (
CLK : in STD_LOGIC;
-- bus interface
RW : in STD_LOGIC;
RD_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
WR_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
-- inputs
Vin : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
TAGin : in STD_LOGIC_VECTOR (19 downto 0);
-- outputs
Vout : out STD_LOGIC;
Dout : out STD_LOGIC_VECTOR (31 downto 0);
TAGout : out STD_LOGIC_VECTOR (19 downto 0)
);
end entity;
architecture Behavioral of cachearray is
type cache_v_t is array (0 to 1023) of std_logic;
type cache_data_t is array (0 to 1023) of std_logic_vector(31 downto 0);
type cache_tag_t is array (0 to 1023) of std_logic_vector(19 downto 0);
signal cache_arr_v : cache_v_t := (others => '0');
signal cache_arr_data : cache_data_t;
signal cache_arr_tag : cache_tag_t;
attribute ram_style: string;
attribute ram_style of cache_arr_v : signal is "block";
attribute ram_style of cache_arr_data : signal is "block";
attribute ram_style of cache_arr_tag : signal is "block";
begin
process (CLK)
begin
if ( CLK = '0' and CLK'event ) then
if (RW = '1') then
cache_arr_v(conv_integer(WR_ADDR)) <= Vin;
cache_arr_data(conv_integer(WR_ADDR)) <= Din;
cache_arr_tag(conv_integer(WR_ADDR)) <= TAGin;
else
Vout <= cache_arr_v(conv_integer(RD_ADDR));
Dout <= cache_arr_data(conv_integer(RD_ADDR));
TAGout <= cache_arr_tag(conv_integer(RD_ADDR));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z024-01_src/Source/iram_dp_wb.vhd | 1 | 8167 | ---------------------------------------------------------------
-- Title : Dual Ported IRAM with Wishbone Interface
-- Project : -
---------------------------------------------------------------
-- File : iram_dp_wb.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/11/05
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: iram_dp_wb.vhd,v $
-- Revision 1.3 2007/11/21 13:46:06 FLenhardt
-- Added ERR output to Wishbone interfaces
--
-- Revision 1.2 2006/01/04 15:57:18 mmiehling
-- added generic usedw_width
--
-- Revision 1.1 2005/12/15 15:38:42 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_dp_wb IS
GENERIC
(
USEDW_WIDTH : positive := 6; -- width of address vector (6 = one M4K)
SAME_CLK : boolean:= TRUE -- true: sl0_clk = sl1_clk; false: sl0_clk /= sl1_clk
);
PORT
(
rst : IN std_logic; -- global async high active reset
-- Wishbone Bus #0
sl0_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl0_stb : IN std_logic; -- request
sl0_cyc : IN std_logic; -- chip select
sl0_ack : OUT std_logic; -- acknowledge
sl0_err : OUT std_logic; -- error
sl0_we : IN std_logic; -- write=1 read=0
sl0_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl0_adr : IN std_logic_vector(31 DOWNTO 0);
sl0_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl0_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
-- Wishbone Bus #0
sl1_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl1_stb : IN std_logic; -- request
sl1_cyc : IN std_logic; -- chip select
sl1_ack : OUT std_logic; -- acknowledge
sl1_err : OUT std_logic; -- error
sl1_we : IN std_logic; -- write=1 read=0
sl1_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl1_adr : IN std_logic_vector(31 DOWNTO 0);
sl1_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl1_dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_dp_wb;
ARCHITECTURE iram_dp_wb_arch OF iram_dp_wb IS
SIGNAL sl0_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl0_ack_o_int : std_logic;
SIGNAL sl0_clk_int : std_logic;
SIGNAL sl0_write : std_logic;
SIGNAL sl1_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl1_ack_o_int : std_logic;
SIGNAL sl1_clk_int : std_logic;
SIGNAL sl1_write : std_logic;
BEGIN
-------------------------------------------------------------------------------------------
-- WB #0 Interface
sl0_ack <= sl0_ack_o_int;
sl0_err <= '0';
sl0_write <= '1' WHEN sl0_ack_o_int = '1' AND sl0_we = '1' ELSE '0';
sl0: PROCESS(rst, sl0_clk_int)
BEGIN
IF(rst = '1') THEN
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
ELSIF(sl0_clk_int'EVENT AND sl0_clk_int = '1') THEN
IF((sl0_stb = '1' AND sl0_cyc = '1') AND sl0_ack_o_int = '0') THEN
IF(sl0_we = '1') THEN
sl0_loc_be <= sl0_sel;
ELSE
sl0_loc_be <= (OTHERS => '0');
END IF;
sl0_ack_o_int <= '1';
ELSE
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl0;
-------------------------------------------------------------------------------------------
-- WB #1 Interface
sl1_ack <= sl1_ack_o_int;
sl1_err <= '0';
sl1_write <= '1' WHEN sl1_ack_o_int = '1' AND sl1_we = '1' ELSE '0';
sl1: PROCESS(rst, sl1_clk_int)
BEGIN
IF(rst = '1') THEN
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
ELSIF(sl1_clk_int'EVENT AND sl1_clk_int = '1') THEN
IF((sl1_stb = '1' AND sl1_cyc = '1') AND sl1_ack_o_int = '0') THEN
IF(sl1_we = '1') THEN
sl1_loc_be <= sl1_sel;
ELSE
sl1_loc_be <= (OTHERS => '0');
END IF;
sl1_ack_o_int <= '1';
ELSE
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl1;
-------------------------------------------------------------------------------------------
gen_2clk: IF NOT SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl1_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK1",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK1",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
power_up_uninitialized => "FALSE",
init_file => "iram.hex"
)
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
clock1 => sl1_clk,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_2clk;
gen_1clk: IF SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl0_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
ram_block_type => "M4K",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK0",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK0",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "iram.hex")
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_1clk;
END iram_dp_wb_arch;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z100-00_src/Source/switch_fab_3.vhd | 1 | 18172 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_3.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_3.vhd,v $
-- Revision 1.4 2015/06/15 16:39:57 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2007/08/13 10:14:21 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.2 2007/04/04 13:15:15 smahveen
-- cyc_x handling in SW_2 corrected.
-- (FSM state will not change after WB Master-3 access wishbone slave in SW_2 state)
--
-- Revision 1.1 2004/08/13 15:16:06 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:06:21 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_3 IS
GENERIC (
registered : IN boolean );
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_3;
ARCHITECTURE switch_fab_3_arch OF switch_fab_3 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
CONSTANT sw_2 : sw_states := "11";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL ack_2_int : std_logic;
SIGNAL sel : std_logic_vector(2 DOWNTO 0);
SIGNAL wbi_slave_stb : std_logic;
BEGIN
without_q : IF NOT registered GENERATE
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_2.stb;
ELSIF wbo_slave.ack = '1' AND wbo_2.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_2;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat, wbo_2.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN sw_2 => wbi_slave.dat <= wbo_2.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr, wbo_2.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN sw_2 => wbi_slave.adr <= wbo_2.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel, wbo_2.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN sw_2 => wbi_slave.sel <= wbo_2.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we, wbo_2.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN sw_2 => wbi_slave.we <= wbo_2.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti, wbo_2.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN sw_2 => wbi_slave.cti <= wbo_2.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga, wbo_2.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN sw_2 => wbi_slave.tga <= wbo_2.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') OR (sw_state = sw_2 AND cyc_2 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END GENERATE without_q;
---------------------------------------------------------------------
with_q : IF registered GENERATE
ack_0 <= ack_0_int;
ack_1 <= ack_1_int;
ack_2 <= ack_2_int;
wbi_slave.stb <= wbi_slave_stb;
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_state <= sw_0;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_0_int = '1') AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_0;
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_state <= sw_1;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- single
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_1_int = '1') AND wbo_1.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_1;
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_state <= sw_2;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- single
wbi_slave_stb <= wbo_2.stb;
ELSIF (wbo_slave.ack = '1' OR ack_2_int = '1') AND wbo_2.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSE
sw_state <= sw_2;
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
sw_state <= sw_0;
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN sel <= "001";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSE sel <= "000";
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN OTHERS => sel <= "000";
END CASE;
END PROCESS sw_fsm_sel;
data_sw : PROCESS( clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave.dat <= (OTHERS => '0');
wbi_slave.adr <= (OTHERS => '0');
wbi_slave.sel <= (OTHERS => '0');
wbi_slave.cti <= (OTHERS => '0');
wbi_slave.tga <= (OTHERS => '0');
wbi_slave.we <= '0';
wbi_slave_cyc <= '0';
ack_0_int <= '0';
err_0 <= '0';
ack_1_int <= '0';
err_1 <= '0';
ack_2_int <= '0';
err_2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
wbi_slave_cyc <= sel(0) OR sel(1) OR sel(2);
IF sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_0_int <= '1';
ELSE
ack_0_int <= '0';
END IF;
IF sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_0 <= '1';
ELSE
err_0 <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_1_int <= '1';
ELSE
ack_1_int <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_1 <= '1';
ELSE
err_1 <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_2_int <= '1';
ELSE
ack_2_int <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_2 <= '1';
ELSE
err_2 <= '0';
END IF;
CASE sel IS
WHEN "001" => wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
WHEN "010" => wbi_slave.dat <= wbo_1.dat;
wbi_slave.adr <= wbo_1.adr;
wbi_slave.sel <= wbo_1.sel;
wbi_slave.we <= wbo_1.we;
wbi_slave.cti <= wbo_1.cti;
wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.dat <= wbo_2.dat;
wbi_slave.adr <= wbo_2.adr;
wbi_slave.sel <= wbo_2.sel;
wbi_slave.we <= wbo_2.we;
wbi_slave.cti <= wbo_2.cti;
wbi_slave.tga <= wbo_2.tga;
END CASE;
END IF;
END PROCESS data_sw;
END GENERATE with_q;
END switch_fab_3_arch;
| gpl-3.0 |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/fpga_pkg_2_top_example.vhd | 1 | 3086 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_top.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_top.vhd
-- - fpga_pkg_2_16zxxx.vhd
-- - - one_device.vhd
-- - fpga_pkg_2_16zyyy.vhd
-- - - many_devices.vhd
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_top_example.vhd,v $
-- Revision 1.2 2009/02/17 11:37:37 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:55 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:55 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_top IS
PORT(
dummy_o : OUT std_logic;
dummy_i : IN std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_top_arch OF fpga_pkg_2_top IS
CONSTANT FPGA_FAMILY : family_type := CYCLONE;
COMPONENT fpga_pkg_2_16zxxx
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
COMPONENT fpga_pkg_2_16zyyy
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
the_one_device : fpga_pkg_2_16zxxx
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_o
);
the_fpga_pkg_2_16zyyy : fpga_pkg_2_16zyyy
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_i
);
END ARCHITECTURE fpga_pkg_2_top_arch;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_a/hdl/vhdl/sg_2d_fir_cw.vhd | 2 | 26710 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_logic_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_ce_logic: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
ce_logic_1 <= xlclockdriver_1_ce_logic;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
ce_logic => xlclockdriver_1_ce_logic,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_cw is
port (
active_video_i: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_2d_fir_cw;
architecture structural of sg_2d_fir_cw is
component block_memory_generator_spartan6_6_2_80846d0865f6122e
port (
addra: in std_logic_vector(4 downto 0);
addrb: in std_logic_vector(4 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(6 downto 0);
dinb: in std_logic_vector(6 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic_vector(0 downto 0);
web: in std_logic_vector(0 downto 0);
douta: out std_logic_vector(6 downto 0);
doutb: out std_logic_vector(6 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
attribute box_type: string;
attribute box_type of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
attribute optimize_primitives of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is false;
attribute dont_touch of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal addr_net: std_logic_vector(4 downto 0);
signal addr_x0_net: std_logic_vector(4 downto 0);
signal ce_1_sg_x54: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x54: signal is "REDUCE";
signal ce_logic_1_sg_x25: std_logic;
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x54: std_logic;
signal coef_gain_reg_ce: std_logic;
signal coef_update_reg_ce: std_logic;
signal data_in_net: std_logic_vector(6 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x1_net: std_logic_vector(19 downto 0);
signal data_in_x2_net: std_logic_vector(6 downto 0);
signal data_out_net: std_logic_vector(19 downto 0);
signal data_out_x0_net: std_logic;
signal data_out_x1_net: std_logic_vector(6 downto 0);
signal data_out_x2_net: std_logic_vector(6 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
begin
active_video_i_net <= active_video_i;
clkNet <= clk;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
clkNet_x0 <= xps_clk;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
coef_buffer: block_memory_generator_spartan6_6_2_80846d0865f6122e
port map (
addra => addr_net,
addrb => addr_x0_net,
clka => clk_1_sg_x54,
clkb => plb_clk_1_sg_x1,
dina => data_in_net,
dinb => data_in_x2_net,
ena => ce_1_sg_x54,
enb => plb_ce_1_sg_x1,
wea(0) => we_net,
web(0) => we_x0_net,
douta => data_out_x1_net,
doutb => data_out_x2_net
);
coef_gain: entity work.synth_reg_w_init
generic map (
width => 20,
init_index => 2,
init_value => b"11111111111111111111",
latency => 1
)
port map (
ce => coef_gain_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i => data_in_x1_net,
o => data_out_net
);
coef_gain_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_x0_net,
dout => coef_gain_reg_ce
);
coef_update: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"1",
latency => 1
)
port map (
ce => coef_update_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i(0) => data_in_x0_net,
o(0) => data_out_x0_net
);
coef_update_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_net,
dout => coef_update_reg_ce
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x54,
ce_logic_1 => ce_logic_1_sg_x25,
clk_1 => clk_1_sg_x54
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_2d_fir_x0: entity work.sg_2d_fir
port map (
active_video_i => active_video_i_net,
ce_1 => ce_1_sg_x54,
ce_logic_1 => ce_logic_1_sg_x25,
clk_1 => clk_1_sg_x54,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x2 => data_out_x2_net,
dout => data_out_x0_net,
dout_x0 => data_out_net,
hblank_i => hblank_i_net,
hsync_i => hsync_i_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
reset => reset_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
vblank_i => vblank_i_net,
video_data_i => video_data_i_net,
vsync_i => vsync_i_net,
active_video_o => active_video_o_net,
addr => addr_net,
addr_x0 => addr_x0_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x2 => data_in_x2_net,
en => en_net,
en_x0 => en_x0_net,
hblank_o => hblank_o_net,
hsync_o => hsync_o_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
vblank_o => vblank_o_net,
video_data_o => video_data_o_net,
vsync_o => vsync_o_net,
we => we_net,
we_x0 => we_x0_net
);
end structural;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/fir_2d_trn_load.vhd | 2 | 9103 | -------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: 2D 5x5-FIR filter in transposed form with loadable coefficients
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_2d_trn_load is
port (ce_1 : in std_logic;
clk_1 : in std_logic;
coef : in std_logic_vector (6 downto 0);
gain : in std_logic_vector (19 downto 0);
line1 : in std_logic_vector (7 downto 0);
line2 : in std_logic_vector (7 downto 0);
line3 : in std_logic_vector (7 downto 0);
line4 : in std_logic_vector (7 downto 0);
line5 : in std_logic_vector (7 downto 0);
load_1 : in std_logic;
load_2 : in std_logic;
load_3 : in std_logic;
load_4 : in std_logic;
load_5 : in std_logic;
dout : out std_logic_vector (7 downto 0)
);
end fir_2d_trn_load;
architecture Behavioral of fir_2d_trn_load is
constant len_inData_vec : integer := line1'length * 5;
constant len_inLoad_vec : integer := 5;
constant number_of_firs : integer := 5;
constant DW_OUT_FIR_5x5 : integer := 8;
constant binary_Point_Gain : integer := 17;
signal fir_data_in : std_logic_vector(len_inData_vec-1 downto 0) := (others => '0');
signal fir_load_in : std_logic_vector(len_inLoad_vec-1 downto 0) := (others => '0');
signal fir_dout : std_logic_vector(number_of_firs*19-1 downto 0) := (others => '0');
signal fir_1_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_2_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_3_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_4_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_5_dout : std_logic_vector(18 downto 0) := (others => '0');
signal adder_1_dout : std_logic_vector(19 downto 0) := (others => '0');
signal adder_2_dout : std_logic_vector(19 downto 0) := (others => '0');
signal adder_3_dout : std_logic_vector(20 downto 0) := (others => '0');
signal adder_4_dout : std_logic_vector(21 downto 0) := (others => '0');
signal reg1_dout : std_logic_vector(18 downto 0) := (others => '0');
signal reg2_dout : std_logic_vector(18 downto 0) := (others => '0');
signal reg2_dout_ext : std_logic_vector(20 downto 0) := (others => '0');
signal reg3_dout : std_logic_vector(19 downto 0) := (others => '0');
signal abs_dout : std_logic_vector(21 downto 0) := (others => '0');
signal mult_dout : std_logic_vector(41 downto 0) := (others => '0');
component fir_1d_trn_load is
generic(
IN_DW : integer; -- Input word width
OUT_DW : integer; -- Output word width
COEF_DW : integer; -- coefficient word width
TAPS : integer; -- # of taps + 1 output register
DELAY : integer -- output delay line
-- (to adapt latency to system architecture)
);
port(
ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end component;
component MULT is
generic(
DW_IN_1 : integer;
DW_IN_2 : integer;
DELAY : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
FACTOR_IN_1 : in std_logic_vector(DW_IN_1-1 downto 0);
FACTOR_IN_2 : in std_logic_vector(DW_IN_2-1 downto 0);
PRODUCT_OUT : out std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0)
);
end component;
component ADDER is
generic(
DW_IN : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
S_IN_1 : in std_logic_vector(DW_IN-1 downto 0);
S_IN_2 : in std_logic_vector(DW_IN-1 downto 0);
SUM_OUT : out std_logic_vector(DW_IN downto 0)
);
end component;
component ABS_VAL is
generic(
DW : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
VAL_IN : in std_logic_vector(DW-1 downto 0);
VAL_OUT : out std_logic_vector(DW-1 downto 0)
);
end component;
component Pipeline_Reg is
generic(
DW_IN : integer
);
port(
clk_1 : in std_logic;
en : in std_logic;
D : in std_logic_vector(DW_IN-1 downto 0);
Q : out std_logic_vector(DW_IN-1 downto 0)
);
end component;
component CONVERT is
generic(
DW_IN : integer;
DW_OUT : integer;
BIN_PNT : integer
);
port(
clk_1 : in std_logic;
ce_1 : in std_logic;
din : in std_logic_vector(DW_IN-1 downto 0);
dout : out std_logic_vector(DW_OUT-1 downto 0)
);
end component;
begin
-- Concatenate input signals to enable 1D-FIR instantiation
-- line
fir_data_in(1*8-1 downto 0) <= line1;
fir_data_in(2*8-1 downto 1*7+1) <= line2;
fir_data_in(3*8-1 downto 2*7+2) <= line3;
fir_data_in(4*8-1 downto 3*7+3) <= line4;
fir_data_in(5*8-1 downto 4*7+4) <= line5;
-- load
fir_load_in(0) <= load_1;
fir_load_in(1) <= load_2;
fir_load_in(2) <= load_3;
fir_load_in(3) <= load_4;
fir_load_in(4) <= load_5;
-- De-concatenate 1D-FIR outpus
fir_1_dout <= fir_dout(1*19-1 downto 0);
fir_2_dout <= fir_dout(2*19-1 downto 1*18+1);
fir_3_dout <= fir_dout(3*19-1 downto 2*18+2);
fir_4_dout <= fir_dout(4*19-1 downto 3*18+3);
fir_5_dout <= fir_dout(5*19-1 downto 4*18+4);
-- instantiate 5 1D-FIR filter
FIR_5x5 : for N in 0 to 4 generate
fir_N : fir_1d_trn_load
generic map(
IN_DW => 8,
OUT_DW => 19,
COEF_DW => 7,
TAPS => 5,
DELAY => 8
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
load => fir_load_in(N),
coef => coef,
din => fir_data_in((N+1)*8-1 downto N*7+N),
out_data => fir_dout((N+1)*19-1 downto N*18+N)
);
end generate;
-- instantiate adder tree
ADDER_1 : ADDER
generic map(
DW_IN => fir_1_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => fir_1_dout,
S_IN_2 => fir_2_dout,
SUM_OUT => adder_1_dout
);
ADDER_2 : ADDER
generic map(
DW_IN => fir_3_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => fir_3_dout,
S_IN_2 => fir_4_dout,
SUM_OUT => adder_2_dout
);
ADDER_3 : ADDER
generic map(
DW_IN => adder_1_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => adder_1_dout,
S_IN_2 => adder_2_dout,
SUM_OUT => adder_3_dout
);
reg2_dout_ext <= "00" & reg2_dout;
ADDER_4 : ADDER
generic map(
DW_IN => adder_3_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => adder_3_dout,
S_IN_2 => reg2_dout_ext,
SUM_OUT => adder_4_dout
);
REG_1 : Pipeline_Reg
generic map(
DW_IN => fir_5_dout'length
)
port map(
clk_1 => clk_1,
en => '1',
D => fir_5_dout,
Q => reg1_dout
);
REG_2 : Pipeline_Reg
generic map(
DW_IN => reg1_dout'length
)
port map(
clk_1 => clk_1,
en => '1',
D => reg1_dout,
Q => reg2_dout
);
-- instantiate components for output scaling
REG_GAIN : Pipeline_Reg
generic map(
DW_IN => gain'length
)
port map(
clk_1 => clk_1,
en => load_5,
D => gain,
Q => reg3_dout
);
ABS_1 : ABS_VAL
generic map(
DW => adder_4_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
VAL_IN => adder_4_dout,
VAL_OUT => abs_dout
);
MULT_1 : MULT
generic map(
DW_IN_1 => abs_dout'length,
DW_IN_2 => reg3_dout'length,
DELAY => 3
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
FACTOR_IN_1 => abs_dout,
FACTOR_IN_2 => reg3_dout,
PRODUCT_OUT => mult_dout
);
CONV_1 : CONVERT
generic map(
DW_IN => mult_dout'length,
DW_OUT => DW_OUT_FIR_5x5,
BIN_PNT => binary_Point_Gain
)
port map(
clk_1 => clk_1,
ce_1 => ce_1,
din => mult_dout,
dout => dout
);
end Behavioral;
| gpl-3.0 |
tghaefli/ADD | ISE/FMC/tb_mcu.vhd | 1 | 804 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal Switch : std_logic_vector(3 downto 0);
signal LED : std_logic_vector(7 downto 0);
constant SIM_CF : natural := CF/10; -- 50 MHz/10 for simulation
begin
-- instantiate MUT
MUT : entity work.mcu
--generic map(CLK_FRQ => SIM_CF)
port map(
rst => rst,
clk => clk,
LED => LED,
Switch => Switch
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / SIM_CF/2;
clk <= not clk;
end process;
end TB;
| gpl-3.0 |
tghaefli/ADD | ISE/FMC/cpu_prc.vhd | 3 | 2652 | -------------------------------------------------------------------------------
-- Entity: cpu_prc
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Program Counter unit for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 + 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_prc is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
ctr_in : in t_ctr2prc;
ctr_out : out t_prc2ctr
);
end cpu_prc;
architecture rtl of cpu_prc is
-- program counter and exception signals
signal pc : std_logic_vector(AW-1 downto 0);
signal exc : t_addr_exc;
begin
-- assign outputs
ctr_out.pc <= pc;
ctr_out.exc <= exc;
-----------------------------------------------------------------------------
-- Program Counter
-----------------------------------------------------------------------------
P_pc: process(clk, rst)
variable v_pc : std_logic_vector(AW-1 downto 0);
variable v_addr : std_logic_vector(AW downto 0);
begin
if rst = '1' then
pc <= (others => '0');
exc <= no_err;
elsif rising_edge(clk) then
if ctr_in.enb = '1' then
exc <= no_err; -- default assignment
case ctr_in.mode is
when linear =>
-- PC := PC + 1
v_pc := std_logic_vector(unsigned(pc) + 1);
if v_pc(AW-1) /= BA(ROM)(AW-1) then -- NOT NICE! Find better solution!!!!!!!!!!!!!!!!!!!!!!!
-- PC would leave ROM address space
-- do not increment and issue error
exc <= lin_err;
else
pc <= v_pc;
end if;
when abs_jump =>
-- PC := addr
pc <= ctr_in.addr;
when rel_offset =>
-- PC := PC + addr
v_addr := std_logic_vector(unsigned('0' & pc) + unsigned(ctr_in.addr));
pc <= v_addr(AW-1 downto 0);
if v_addr(AW) = '1' and ctr_in.addr(AW-1) = '0' then
-- overflow with addition of positive relative offset
exc <= rel_err;
elsif v_addr(AW) = '0' and ctr_in.addr(AW-1) = '1' then
-- underflow with addition of negative relative offset
exc <= rel_err;
end if;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
| gpl-3.0 |
EXEM-OSS/Flamingo2 | flamingo2-web/src/main/webapp/resources/build/production/Flamingo2/resources/lib/aceeditor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-3.0 |
Geenie-Lee/flamingo2 | flamingo2-web/src/main/webapp/resources/build/production/Flamingo2/resources/lib/aceeditor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_01_a/hdl/vhdl/sg_2d_fir_cw.vhd | 1 | 26710 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_logic_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_ce_logic: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
ce_logic_1 <= xlclockdriver_1_ce_logic;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
ce_logic => xlclockdriver_1_ce_logic,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_cw is
port (
active_video_i: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_2d_fir_cw;
architecture structural of sg_2d_fir_cw is
component block_memory_generator_spartan6_6_2_80846d0865f6122e
port (
addra: in std_logic_vector(4 downto 0);
addrb: in std_logic_vector(4 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(6 downto 0);
dinb: in std_logic_vector(6 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic_vector(0 downto 0);
web: in std_logic_vector(0 downto 0);
douta: out std_logic_vector(6 downto 0);
doutb: out std_logic_vector(6 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
attribute box_type: string;
attribute box_type of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
attribute optimize_primitives of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is false;
attribute dont_touch of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal addr_net: std_logic_vector(4 downto 0);
signal addr_x0_net: std_logic_vector(4 downto 0);
signal ce_1_sg_x51: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x51: signal is "REDUCE";
signal ce_logic_1_sg_x22: std_logic;
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x51: std_logic;
signal coef_gain_reg_ce: std_logic;
signal coef_update_reg_ce: std_logic;
signal data_in_net: std_logic_vector(6 downto 0);
signal data_in_x0_net: std_logic_vector(6 downto 0);
signal data_in_x1_net: std_logic;
signal data_in_x2_net: std_logic_vector(19 downto 0);
signal data_out_net: std_logic_vector(19 downto 0);
signal data_out_x0_net: std_logic;
signal data_out_x1_net: std_logic_vector(6 downto 0);
signal data_out_x2_net: std_logic_vector(6 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
begin
active_video_i_net <= active_video_i;
clkNet <= clk;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
clkNet_x0 <= xps_clk;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x2;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
coef_buffer: block_memory_generator_spartan6_6_2_80846d0865f6122e
port map (
addra => addr_net,
addrb => addr_x0_net,
clka => clk_1_sg_x51,
clkb => plb_clk_1_sg_x1,
dina => data_in_net,
dinb => data_in_x0_net,
ena => ce_1_sg_x51,
enb => plb_ce_1_sg_x1,
wea(0) => we_net,
web(0) => we_x0_net,
douta => data_out_x1_net,
doutb => data_out_x2_net
);
coef_gain: entity work.synth_reg_w_init
generic map (
width => 20,
init_index => 2,
init_value => b"11111111111111111111",
latency => 1
)
port map (
ce => coef_gain_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i => data_in_x2_net,
o => data_out_net
);
coef_gain_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_x0_net,
dout => coef_gain_reg_ce
);
coef_update: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"1",
latency => 1
)
port map (
ce => coef_update_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i(0) => data_in_x1_net,
o(0) => data_out_x0_net
);
coef_update_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_net,
dout => coef_update_reg_ce
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x51,
ce_logic_1 => ce_logic_1_sg_x22,
clk_1 => clk_1_sg_x51
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_2d_fir_x0: entity work.sg_2d_fir
port map (
active_video_i => active_video_i_net,
ce_1 => ce_1_sg_x51,
ce_logic_1 => ce_logic_1_sg_x22,
clk_1 => clk_1_sg_x51,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x2 => data_out_x2_net,
dout => data_out_x0_net,
dout_x0 => data_out_net,
hblank_i => hblank_i_net,
hsync_i => hsync_i_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
reset => reset_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
vblank_i => vblank_i_net,
video_data_i => video_data_i_net,
vsync_i => vsync_i_net,
active_video_o => active_video_o_net,
addr => addr_net,
addr_x0 => addr_x0_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x2 => data_in_x2_net,
en => en_net,
en_x0 => en_x0_net,
hblank_o => hblank_o_net,
hsync_o => hsync_o_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x1,
sl_wrdack => sl_wrdack_x2,
vblank_o => vblank_o_net,
video_data_o => video_data_o_net,
vsync_o => vsync_o_net,
we => we_net,
we_x0 => we_x0_net
);
end structural;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd | 3 | 6752 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd when simulating
-- the core, block_memory_generator_spartan6_6_2_80846d0865f6122e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY block_memory_generator_spartan6_6_2_80846d0865f6122e IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END block_memory_generator_spartan6_6_2_80846d0865f6122e;
ARCHITECTURE block_memory_generator_spartan6_6_2_80846d0865f6122e_a OF block_memory_generator_spartan6_6_2_80846d0865f6122e IS
-- synthesis translate_off
COMPONENT wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 1,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "block_memory_generator_spartan6_6_2_80846d0865f6122e.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 7,
c_read_width_b => 7,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "READ_FIRST",
c_write_width_a => 7,
c_write_width_b => 7,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END block_memory_generator_spartan6_6_2_80846d0865f6122e_a;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_a/hdl/vhdl/block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd | 3 | 6752 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd when simulating
-- the core, block_memory_generator_spartan6_6_2_80846d0865f6122e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY block_memory_generator_spartan6_6_2_80846d0865f6122e IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END block_memory_generator_spartan6_6_2_80846d0865f6122e;
ARCHITECTURE block_memory_generator_spartan6_6_2_80846d0865f6122e_a OF block_memory_generator_spartan6_6_2_80846d0865f6122e IS
-- synthesis translate_off
COMPONENT wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 1,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "block_memory_generator_spartan6_6_2_80846d0865f6122e.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 7,
c_read_width_b => 7,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "READ_FIRST",
c_write_width_a => 7,
c_write_width_b => 7,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END block_memory_generator_spartan6_6_2_80846d0865f6122e_a;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout.vhd | 1 | 102280 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_f4d0462e0e is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_f4d0462e0e;
architecture behavior of mcode_block_f4d0462e0e is
signal plbrst_1_110: unsigned((1 - 1) downto 0);
signal plbabus_1_118: unsigned((32 - 1) downto 0);
signal plbpavalid_1_127: unsigned((1 - 1) downto 0);
signal plbrnw_1_139: unsigned((1 - 1) downto 0);
signal plbwrdbus_1_147: unsigned((32 - 1) downto 0);
signal rddata_1_158: unsigned((32 - 1) downto 0);
signal addrpref_1_166: unsigned((20 - 1) downto 0);
signal plbrstreg_12_24_next: boolean;
signal plbrstreg_12_24: boolean := false;
signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_14_28_next: boolean;
signal plbpavalidreg_14_28: boolean := false;
signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_28_23_next: boolean;
signal avalidreg_28_23: boolean := false;
signal ps1reg_39_20_next: boolean;
signal ps1reg_39_20: boolean := false;
signal psreg_47_19_next: boolean;
signal psreg_47_19: boolean := false;
type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := (
"0",
"0",
"0");
signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_push_front_pop_back_en: std_logic;
signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_66_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0);
signal rel_33_4: boolean;
signal ps1_join_33_1: boolean;
signal ps_42_1_bit: boolean;
signal bitnot_49_49: boolean;
signal bitnot_49_73: boolean;
signal bit_49_49: boolean;
signal addrack_49_1_convert: unsigned((1 - 1) downto 0);
signal bit_55_43: unsigned((1 - 1) downto 0);
signal bitnot_72_35: unsigned((1 - 1) downto 0);
signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_76_1_bit: unsigned((1 - 1) downto 0);
signal rel_78_4: boolean;
signal rddbus1_join_78_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_12_24_next_x_000000: boolean;
signal plbpavalidreg_14_28_next_x_000000: boolean;
begin
plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst);
plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_1_158 <= std_logic_vector_to_unsigned(rddata);
addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_12_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_12_24 <= plbrstreg_12_24_next;
end if;
end if;
end process proc_plbrstreg_12_24;
proc_plbabusreg_13_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_13_25 <= plbabusreg_13_25_next;
end if;
end if;
end process proc_plbabusreg_13_25;
proc_plbpavalidreg_14_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_14_28 <= plbpavalidreg_14_28_next;
end if;
end if;
end process proc_plbpavalidreg_14_28;
proc_plbrnwreg_15_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_15_24 <= plbrnwreg_15_24_next;
end if;
end if;
end process proc_plbrnwreg_15_24;
proc_plbwrdbusreg_16_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next;
end if;
end if;
end process proc_plbwrdbusreg_16_27;
proc_avalidreg_28_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_28_23 <= avalidreg_28_23_next;
end if;
end if;
end process proc_avalidreg_28_23;
proc_ps1reg_39_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_39_20 <= ps1reg_39_20_next;
end if;
end if;
end process proc_ps1reg_39_20;
proc_psreg_47_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_47_19 <= psreg_47_19_next;
end if;
end if;
end process proc_psreg_47_19;
rdcompdelay_58_25_back <= rdcompdelay_58_25(2);
proc_rdcompdelay_58_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1);
end loop;
rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din;
end if;
end if;
end process proc_rdcompdelay_58_25;
proc_rdcompreg_62_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_62_23 <= rdcompreg_62_23_next;
end if;
end if;
end process proc_rdcompreg_62_23;
proc_rddackreg_66_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_66_23 <= rddackreg_66_23_next;
end if;
end if;
end process proc_rddackreg_66_23;
proc_wrdackreg_70_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_70_23 <= wrdackreg_70_23_next;
end if;
end if;
end process proc_wrdackreg_70_23;
proc_rddbusreg_84_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_84_23 <= rddbusreg_84_23_next;
end if;
end if;
end process proc_rddbusreg_84_23;
bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10);
linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2);
addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12);
rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166;
proc_if_33_1: process (rel_33_4)
is
begin
if rel_33_4 then
ps1_join_33_1 <= true;
else
ps1_join_33_1 <= false;
end if;
end process proc_if_33_1;
ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1");
bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1");
bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1");
bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1");
addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0);
bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24));
bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24));
wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35));
rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23));
rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1");
proc_if_78_1: process (rddata_1_158, rel_78_4)
is
begin
if rel_78_4 then
rddbus1_join_78_1 <= rddata_1_158;
else
rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_78_1;
plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0);
plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0");
plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000;
plbabusreg_13_25_next <= plbabus_1_118;
plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0");
plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000;
plbrnwreg_15_24_next <= plbrnw_1_139;
plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice;
avalidreg_28_23_next <= plbpavalidreg_14_28;
ps1reg_39_20_next <= ps1_join_33_1;
psreg_47_19_next <= ps_42_1_bit;
rdcompdelay_58_25_front_din <= bit_55_43;
rdcompdelay_58_25_push_front_pop_back_en <= '1';
rdcompreg_62_23_next <= rdcompdelay_58_25_back;
rddackreg_66_23_next <= rdcompreg_62_23;
wrdackreg_70_23_next <= wrdackreg_72_1_bit;
rddbusreg_84_23_next <= rddbus1_join_78_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27);
addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_66_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_189a35de81 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_189a35de81;
architecture behavior of mcode_block_189a35de81 is
signal wrdbus_1_39: unsigned((32 - 1) downto 0);
signal bankaddr_1_47: unsigned((2 - 1) downto 0);
signal linearaddr_1_57: unsigned((8 - 1) downto 0);
signal rnwreg_1_69: unsigned((1 - 1) downto 0);
signal addrack_1_77: unsigned((1 - 1) downto 0);
signal read_bank_out_reg_53_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_53_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_56_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_56_26: unsigned((2 - 1) downto 0) := "00";
signal opcode_21_1_concat: unsigned((12 - 1) downto 0);
signal rel_58_4: boolean;
signal rel_61_8: boolean;
signal rel_64_8: boolean;
signal rel_67_8: boolean;
signal read_bank_out_reg_join_58_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_39 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_47 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_57 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_69 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_77 <= std_logic_vector_to_unsigned(addrack);
proc_read_bank_out_reg_53_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_53_31 <= read_bank_out_reg_53_31_next;
end if;
end if;
end process proc_read_bank_out_reg_53_31;
proc_bankaddr_reg_56_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_56_26 <= bankaddr_reg_56_26_next;
end if;
end if;
end process proc_bankaddr_reg_56_26;
opcode_21_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_77) & unsigned_to_std_logic_vector(rnwreg_1_69) & unsigned_to_std_logic_vector(bankaddr_1_47) & unsigned_to_std_logic_vector(linearaddr_1_57));
rel_58_4 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("00");
rel_61_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("01");
rel_64_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("10");
rel_67_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("11");
proc_if_58_1: process (read_bank_out_reg_53_31, rel_58_4, rel_61_8, rel_64_8, rel_67_8)
is
begin
if rel_58_4 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_61_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_64_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_67_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_58_1 <= read_bank_out_reg_53_31;
end if;
end process proc_if_58_1;
read_bank_out_reg_53_31_next <= read_bank_out_reg_join_58_1;
bankaddr_reg_56_26_next <= bankaddr_1_47;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_53_31);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d0d1b9533e is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_d0d1b9533e;
architecture behavior of concat_d0d1b9533e is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_xsvi_fanout/EDK Processor"
entity edk_processor_entity_0cfccb8238 is
port (
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0)
);
end edk_processor_entity_0cfccb8238;
architecture structural of edk_processor_entity_0cfccb8238 is
signal bankaddr: std_logic_vector(1 downto 0);
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x0: std_logic;
signal plb_clk_1_sg_x0: std_logic;
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
plb_abus_net_x0 <= plb_abus;
plb_ce_1_sg_x0 <= plb_ce_1;
plb_clk_1_sg_x0 <= plb_clk_1;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_f4d0462e0e
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_189a35de81
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
wrdbus => wrdbusreg,
read_bank_out => rddata
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_xsvi_fanout"
entity sg_xsvi_fanout is
port (
active_video_i: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_xsvi_fanout;
architecture structural of sg_xsvi_fanout is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "sg_xsvi_fanout,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=102,xilinx_bit_slice_extractor_block=3,xilinx_bus_concatenator_block=1,xilinx_constant_block_block=1,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=13,xilinx_mcode_block_block=2,xilinx_register_block=8,xilinx_system_generator_block=1,}";
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal blue: std_logic_vector(7 downto 0);
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal green: std_logic_vector(7 downto 0);
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal red: std_logic_vector(7 downto 0);
signal register5_q_net: std_logic_vector(7 downto 0);
signal register6_q_net: std_logic_vector(7 downto 0);
signal register7_q_net: std_logic_vector(7 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_ce_1_sg_x1 <= plb_ce_1;
plb_clk_1_sg_x1 <= plb_clk_1;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
concat: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => register5_q_net,
in1 => register6_q_net,
in2 => register7_q_net,
y => video_data_o_net
);
edk_processor_0cfccb8238: entity work.edk_processor_entity_0cfccb8238
port map (
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => vsync_i_net,
en => "1",
rst => "0",
q(0) => vsync_o_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => hsync_i_net,
en => "1",
rst => "0",
q(0) => hsync_o_net
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => vblank_i_net,
en => "1",
rst => "0",
q(0) => vblank_o_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => hblank_i_net,
en => "1",
rst => "0",
q(0) => hblank_o_net
);
register5: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => red,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => green,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => blue,
en => "1",
rst => "0",
q => register7_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => active_video_i_net,
en => "1",
rst => "0",
q(0) => active_video_o_net
);
slice15downto8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => green
);
slice23downto16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => red
);
slice7downto0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => blue
);
end structural;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout_cw.vhd | 1 | 20514 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_xsvi_fanout_cw is
port (
active_video_i: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_xsvi_fanout_cw;
architecture structural of sg_xsvi_fanout_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal ce_1_sg_x0: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x0: signal is "REDUCE";
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
clkNet <= clk;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
clkNet_x0 <= xps_clk;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x0,
clk_1 => clk_1_sg_x0
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_xsvi_fanout_x0: entity work.sg_xsvi_fanout
port map (
active_video_i => active_video_i_net,
ce_1 => ce_1_sg_x0,
clk_1 => clk_1_sg_x0,
hblank_i => hblank_i_net,
hsync_i => hsync_i_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
vblank_i => vblank_i_net,
video_data_i => video_data_i_net,
vsync_i => vsync_i_net,
active_video_o => active_video_o_net,
hblank_o => hblank_o_net,
hsync_o => hsync_o_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
vblank_o => vblank_o_net,
video_data_o => video_data_o_net,
vsync_o => vsync_o_net
);
end structural;
| gpl-3.0 |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/fifo_generator_spartan6_6_1_ba61a4be12cec537.vhd | 1 | 6195 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_generator_spartan6_6_1_ba61a4be12cec537.vhd when simulating
-- the core, fifo_generator_spartan6_6_1_ba61a4be12cec537. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_generator_spartan6_6_1_ba61a4be12cec537 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(0 downto 0));
END fifo_generator_spartan6_6_1_ba61a4be12cec537;
ARCHITECTURE fifo_generator_spartan6_6_1_ba61a4be12cec537_a OF fifo_generator_spartan6_6_1_ba61a4be12cec537 IS
-- synthesis translate_off
component wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(0 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537 use entity XilinxCoreLib.fifo_generator_v6_1(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 1,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 32,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 5,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 5,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 5,
c_enable_rlocs => 0,
c_wr_pntr_width => 5,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 1,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 28,
c_wr_depth => 32,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 29,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_generator_spartan6_6_1_ba61a4be12cec537_a;
| gpl-3.0 |
Feuerwerk/fpgaNES | vga_pll.vhd | 1 | 17827 | -- megafunction wizard: %PLL Intel FPGA IP v18.0%
-- GENERATION: XML
-- vga_pll.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vga_pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end entity vga_pll;
architecture rtl of vga_pll is
component vga_pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component vga_pll_0002;
begin
vga_pll_inst : component vga_pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => locked -- locked.export
);
end architecture rtl; -- of vga_pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="2" />
-- Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="25.175" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : vga_pll.vho
-- RELATED_FILES: vga_pll.vhd, vga_pll_0002.v
| gpl-3.0 |
MartinCura/SistDig-TP4 | old/External_RAM/buffer_almacenamiento.vhd | 1 | 2469 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity buffer_almacenamiento is
generic (
N,M : natural
);
port (
clk : in std_logic;
rst : in std_logic;
flag_rotar : in std_logic;--flag que indica cuando mandar los datos al cordic
data_in_rdy : in std_logic;
data_in : in std_logic_vector (N-1 downto 0);
datax_out : out std_logic_vector (N-1 downto 0);
datay_out : out std_logic_vector (N-1 downto 0);
dataz_out : out std_logic_vector (N-1 downto 0);
data_out_rdy : out std_logic
);
end;
architecture beh of buffer_almacenamiento is
type memo is array (0 to M-1) of std_logic_vector(N-1 downto 0); --M = 300
signal posicion : memo;
signal contador_carga : unsigned(8 downto 0):= (others => '0');
signal contador_salida : unsigned(8 downto 0):= (others => '0');
--variable flag_aux_rotar is std_logic;--flag auxiliar para que no cambie una vez que cambia el flag de afuera
begin
--Process carga de datos--
process(clk,rst)
begin
if rst='1' then
contador_carga <= (others => '0');
elsif rising_edge(clk) then
if data_in_rdy = '1' then
posicion(to_integer(contador_carga)) <= data_in;
contador_carga <= contador_carga + 1;
end if;
end if;
end process;
--Process salida de datos--
process(clk,rst)
variable flag_aux_rotar,aux_data_out_rdy : std_logic;
variable aux_data_buffer : unsigned(3 downto 0) := "0000";
begin
if rst='1' then
contador_salida <= (others => '0');
elsif rising_edge(clk) then
--aux_data_out_rdy := '0';
if flag_rotar = '1' then
flag_aux_rotar := '1';
aux_data_buffer := "0000";
end if;
if flag_aux_rotar = '1' then
if to_integer(contador_salida) >= M then -- M=300
contador_salida <= (others => '0');
flag_aux_rotar := '0';
aux_data_buffer := "0000";
aux_data_out_rdy := '0';
elsif aux_data_buffer > "0000" then
aux_data_buffer := aux_data_buffer +1;
if aux_data_buffer = "1111" then
aux_data_out_rdy := '1';
aux_data_buffer := "0000";
end if;
else
datax_out <= posicion(to_integer(contador_salida));
datay_out <= posicion(to_integer(contador_salida + 1));
dataz_out <= posicion(to_integer(contador_salida + 2));
contador_salida <= contador_salida + 3;
aux_data_buffer := "0001";
aux_data_out_rdy := '0';
end if;
end if;
end if;
data_out_rdy <= aux_data_out_rdy;
end process;
end beh;
| gpl-3.0 |
MartinCura/SistDig-TP4 | src/ctrl_global.vhd | 1 | 5024 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_ctrl is
generic (
Nangle : natural := 16
);
port (
clock : in std_logic;
write_rst_i: in std_logic;
read_rst_i : in std_logic;
sw_x_pos, sw_x_neg: in std_logic;
sw_y_pos, sw_y_neg: in std_logic;
sw_z_pos, sw_z_neg: in std_logic;
delta_angle: in std_logic_vector(Nangle-1 downto 0);
alfa, beta, gama: out std_logic_vector(Nangle-1 downto 0);
clear_reset, clear_enable: out std_logic;
clear_stop: in std_logic;
read_start: out std_logic;
read_stop: in std_logic;
read_reset_out, write_reset_out: out std_logic;
vga_start, vga_stop: in std_logic
);
end;
architecture global_ctrl_arq of global_ctrl is
type t_estado is (IDLE, CLEARING, READING, REFRESHING);
signal estado : t_estado := IDLE;
type t_subestado is (WAITING, REFRESHING);
signal refresh_subestado : t_subestado := WAITING;
signal ctrl_alfa, ctrl_beta, ctrl_gama : std_logic_vector(1 downto 0) := (others => '0');
signal alfa_aux, beta_aux, gama_aux: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal delta_alfa, delta_beta, delta_gama: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal minus_delta_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal button_down : std_logic := '0';
begin
button_down <= (sw_x_pos or sw_x_neg or
sw_y_pos or sw_y_neg or
sw_z_pos or sw_z_neg or
write_rst_i or read_rst_i);
--button_down <= ( (sw_x_pos XOR sw_x_neg) OR (sw_y_pos XOR sw_y_neg) OR (sw_z_pos XOR sw_z_neg)
-- OR write_rst_i OR read_rst_i );
clear_enable <= '1' when (estado = CLEARING) else '0';
read_reset_out <= '1' when (estado = CLEARING) else '0';
read_start <= '1' when (estado = READING) else '0';
write_reset_out <= write_rst_i;
process(clock, button_down)
begin
if rising_edge(clock) then
case estado is
when IDLE =>
refresh_subestado <= WAITING;
if button_down = '1' then
estado <= CLEARING;
clear_reset <= '0';
end if;
-- Borro la memoria de video
when CLEARING =>
if clear_stop = '1' then
clear_reset <= '1';
estado <= READING;
end if;
-- Leo los nuevos datos
when READING =>
clear_reset <= '0';
if read_stop = '1' then
estado <= REFRESHING;
end if;
-- Espero a que refresque la pantalla con los nuevos datos leídos
when REFRESHING =>
clear_reset <= '0';
case refresh_subestado is
when WAITING =>
if vga_start = '1' then
refresh_subestado <= REFRESHING;
-- else refresh_subestado <= WAITING;
end if;
when REFRESHING =>
if vga_stop = '1' then
estado <= IDLE;
refresh_subestado <= WAITING;
-- else
-- refresh_subestado <= REFRESHING;
end if;
end case;
end case;
end if;
end process;
-- Ángulos
-- Ctrl +/- (selector del mux)
ctrl_alfa <= sw_x_pos & sw_x_neg;
ctrl_beta <= sw_y_pos & sw_y_neg;
ctrl_gama <= sw_z_pos & sw_z_neg;
-- Menos delta (-delta)
minus_delta_angle <= std_logic_vector(unsigned(not delta_angle) + 1);
-- Mux
delta_alfa <= delta_angle when ctrl_alfa = "10" else
minus_delta_angle when ctrl_alfa = "01" else
(others => '0');
delta_beta <= delta_angle when ctrl_beta = "10" else
minus_delta_angle when ctrl_beta = "01" else
(others => '0');
delta_gama <= delta_angle when ctrl_gama = "10" else
minus_delta_angle when ctrl_gama = "01" else
(others => '0');
alfa <= alfa_aux;
beta <= beta_aux;
gama <= gama_aux;
-- Acumulador de ángulos
process(clock, estado)
begin
if rising_edge(clock) then
if estado = IDLE then
alfa_aux <= std_logic_vector( unsigned(alfa_aux) + unsigned(delta_alfa) );
beta_aux <= std_logic_vector( unsigned(beta_aux) + unsigned(delta_beta) );
gama_aux <= std_logic_vector( unsigned(gama_aux) + unsigned(delta_gama) );
end if;
end if;
end process;
end;
| gpl-3.0 |
MartinCura/SistDig-TP4 | src/ext_ram/pos_loader.vhd | 1 | 2174 | -- Loader de posiciones (x,y,z) desde la RAM externa
library ieee;
use ieee.std_logic_1164.all;
entity pos_loader is
port (
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
start: in std_logic;
data_in: in std_logic_vector(15 downto 0);
go_ram: out std_logic;
busy_ram: in std_logic;
RxRdy_ram: in std_logic;
RxRdy_out: out std_logic;
x, y, z: out std_logic_vector(15 downto 0)
);
end;
architecture pos_loader_arq of pos_loader is
-- Para indicar qué coordenada se está cargando
type t_estado is (IDLE, X_st, Y_st, Z_st);
signal estado : t_estado := IDLE;
begin
process(clock, reset, start, RxRdy_ram, busy_ram)
begin
-- reset
if reset = '1' then
go_ram <= '0';
estado <= IDLE;
elsif rising_edge(clock) then
RxRdy_out <= '0';
go_ram <= '0';
if enable = '1' then
case estado is
when IDLE =>
if start = '1' and busy_ram = '0' then -- pido X
go_ram <= '1';
estado <= X_st;
end if;
when X_st =>
if RxRdy_ram = '1' then -- Ya X, pido Y
x <= data_in;
go_ram <= '1';
estado <= Y_st;
end if;
when Y_st =>
if RxRdy_ram = '1' then -- Ya Y, pido Z
y <= data_in;
go_ram <= '1';
estado <= Z_st;
end if;
when Z_st =>
if RxRdy_ram = '1' then -- Ya Z, vuelvo a IDLE
z <= data_in;
RxRdy_out <= '1'; -- Posición lista
go_ram <= '1';
estado <= X_st;---
end if;
end case;
end if;
end if;
end process;
end;
| gpl-3.0 |
MartinCura/SistDig-TP4 | old/testers/rotador3d_tb.vhd | 1 | 3904 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity rotador3d_tb is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
port(
vec_pos_pixel: out t_vec := (others => CERO)
);
end;
architecture rotador3d_tb_arq of rotador3d_tb is
type memo_t is array(0 to 39) of std_logic_vector(15 downto 0);
constant testmemo : memo_t := (
"0000000000000000",
"0000000000000100",
"0000000000001100",
"0000000001100000",
"0000000000000010",
"0000000000000001",
"1000001100000000",
"1000000000010000",
"0100000000010000",
"1111111111111111",
"1111110111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000010",
"0000000000000001",
"1000001100000000",
"1000000000010000",
"0100000000010000",
"1111111101111111",
"1111111111111110",
"1111111111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000010",
"0100000000010000",
"1111111111111111",
"1111111111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000001",
"0000000000000010"
);
constant c1 : t_float := PI_PF * to_float( 0.703125) / 180;
constant c2 : t_float := PI_PF * to_float( 1.406250) / 180;
constant c_1 : t_float := PI_PF * to_float(-0.703125) / 180;
constant c_2 : t_float := PI_PF * to_float(-1.406250) / 180;
signal clk_t : std_logic := '1';
signal ena_o: std_logic := '0'; -- Enable de rotar
signal pos_mem_leida: t_pos_mem := (others => (others => '0'));
signal alfa, beta, gama: t_float := CERO;
signal pos_leida, pos_rotada: t_pos := (others => CERO);
begin
clk_t <= not clk_t after 5 ns;
ena_o <= '1' after 10 ns;
pos_mem_leida(1) <= (15 downto 1 => '0') & '1';
pos_mem_leida(2) <= (15 downto 1 => '0') & '1';
pos_mem_leida(3) <= (15 downto 1 => '0') & '1';
---pos_mem_leida(1) <= testmemo(3) after 0 ns;---, testmemo(10) after 100 ns, testmemo(20) after 200 ns;
---pos_mem_leida(2) <= testmemo(4) after 0 ns;---, testmemo(11) after 100 ns, testmemo(21) after 200 ns;
---pos_mem_leida(3) <= testmemo(5) after 0 ns;---, testmemo(12) after 100 ns, testmemo(22) after 200 ns;
-- Paso a formato punto flotante
---process(pos_mem_leida)
---begin
--- pos_leida(1) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_mem_leida(1))),N_BITS_COORD)));
--- pos_leida(2) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_mem_leida(2))),N_BITS_COORD)));
--- pos_leida(3) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_mem_leida(3))),N_BITS_COORD)));
---end process;
pos_leida(1) <= to_float(1);
pos_leida(2) <= to_float(2);
pos_leida(3) <= to_float(3);
alfa <= c1 after 20 ns, (PI_PF/2) after 100 ns;
beta <= c1 after 20 ns, CERO after 100 ns;
gama <= c1 after 20 ns, (PI_PF/2) after 100 ns, (PI_PF) after 600 ns;
-- Roto la posición leída según los ángulos de rotación
rotador: entity work.rotador3d
port map(
--- clk => clk_t,
ena => ena_o, ---ena => rot_ena,
pos_in => pos_leida,
alfa => alfa,
beta => beta,
gama => gama,
pos_rotada => pos_rotada
);
-- Aplano a ejes (y,z)
vec_pos_pixel(1) <= pos_rotada(2);
vec_pos_pixel(2) <= pos_rotada(3);
process(clk_t, pos_rotada)
begin
if falling_edge(clk_t) then
report "pos x: " & integer'image(to_integer(to_signed(pos_rotada(1)*(1000000),32)))
& " pos y: " & integer'image(to_integer(to_signed(pos_rotada(2)*(1000000),32)))
& " pos z: " & integer'image(to_integer(to_signed(pos_rotada(3)*(1000000),32)))
severity note;
end if;
end process;
end;
| gpl-3.0 |
kuba-moo/VHDL-lib | test/tb_bus_tail_strip.vhd | 1 | 2956 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity tb_bus_tail_strip is
end tb_bus_tail_strip;
architecture behavior of tb_bus_tail_strip is
-- Component Declaration for the Unit Under Test (UUT)
component bus_tail_strip
generic (N_BYTES : integer);
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector(7 downto 0));
end component;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut, PktOut_1 : std_logic;
signal DataOut, DataOut_1 : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
strip_3 : bus_tail_strip
generic map (N_BYTES => 3)
port map (
Clk => Clk,
Rst => Rst,
PktIn => PktIn,
DataIn => DataIn,
PktOut => PktOut_1,
DataOut => DataOut_1
);
strip_1 : bus_tail_strip
generic map (N_BYTES => 1)
port map (
Clk => Clk,
Rst => Rst,
PktIn => PktOut_1,
DataIn => DataOut_1,
PktOut => PktOut,
DataOut => DataOut
);
-- Clock process definitions
Clk_process : process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
PktIn <= '1';
for i in 1 to 10 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait;
end process;
end;
| gpl-3.0 |
MartinCura/SistDig-TP4 | old/rotador/gen_dirs.vhd | 1 | 1069 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- A partir de una posición 2D (x,y) mapea a una dirección de pantalla (i,j)
entity gen_dirs is
generic(
-- Bits por fila/columna
BR : integer := 10; -- n_bits_row
BC : integer := 10 -- n_bits_col
);
port(
pos_2d: in t_vec; -- Posición 2D
dir: out t_dir -- Dirección en pantalla de píxel correspondiente
);
end entity;
architecture gen_dirs_arq of gen_dirs is
constant SCR_W : integer := 640;
constant SCR_H : integer := 480;
constant SIZE : integer := 160;
begin
process(pos_2d)
variable x, y : integer := 0;
begin
x := SCR_W / 2 + to_integer( SIZE * pos_2d(1) );
y := SCR_H / 2 + to_integer( SIZE * pos_2d(2) );
---dir := x + SCR_W * y;
dir(1) <= std_logic_vector(to_unsigned(x, BR));
dir(2) <= std_logic_vector(to_unsigned(y, BC));
end process;
end;
| gpl-3.0 |
MartinCura/SistDig-TP4 | src/pos_rotator.vhd | 1 | 7375 | -- Rota posiciones (x,y,z) usando el algoritmo CORDIC iterativamente
library ieee;
use ieee.std_logic_1164.all;
entity pos_rotator is
generic(
Nxy : natural := 16;
Nangle : natural := 16;
Nits : natural := 16
);
port (
clock : in std_logic;
reset : in std_logic;
load : in std_logic;
RxRdy : out std_logic;
alfa, beta, gama : in std_logic_vector(Nangle-1 downto 0);
x0, y0, z0 : in std_logic_vector(Nxy-1 downto 0);
x1, y1, z1 : out std_logic_vector(Nxy-1 downto 0)
);
end;
architecture pos_rotator_arq of pos_rotator is
constant n_reg_in : natural := 1+3*Nxy+3*Nangle-1; -- tamaño de registro de entrada
-- Señales entre etapas
signal xrot_load : std_logic := '0';
signal xrot_RxRdy : std_logic := '0';
signal xrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal xrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_x1_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_load : std_logic := '0';
signal yrot_RxRdy : std_logic := '0';
signal yrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal yrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_x1_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_load : std_logic := '0';
signal zrot_RxRdy : std_logic := '0';
signal zrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal zrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal out_reg_in : std_logic_vector(1+3*Nxy-1 downto 0) := (others => '0');
signal out_reg_out : std_logic_vector(1+3*Nxy-1 downto 0) := (others => '0');
signal in_reg_in : std_logic_vector(n_reg_in downto 0) := (others => '0');
signal in_reg_out : std_logic_vector(n_reg_in downto 0) := (others => '0');
signal load_delay : std_logic := '0';
signal x0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal x0_delay_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal y0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal z0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal alfa_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal beta_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal gama_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
begin
-- Registro de entrada
in_reg_in <= load & x0 & y0 & z0 & alfa & beta & gama;
pipe_reg_in: entity work.registroNb
generic map(
N => 1 + 3*Nxy + 3*Nangle
) port map(
clk => clock,
rst => reset,
ena => '1',
d => in_reg_in,
q => in_reg_out
);
load_delay <= in_reg_out(n_reg_in);
x0_delay <= in_reg_out( n_reg_in -1 downto n_reg_in -Nxy);
y0_delay <= in_reg_out( n_reg_in -Nxy-1 downto n_reg_in -2*Nxy);
z0_delay <= in_reg_out( n_reg_in -2*Nxy-1 downto n_reg_in -3*Nxy);
alfa_delay <= in_reg_out(n_reg_in -3*Nxy -1 downto n_reg_in -3*Nxy -Nangle);
beta_delay <= in_reg_out(n_reg_in -3*Nxy -Nangle-1 downto n_reg_in -3*Nxy -2*Nangle);
gama_delay <= in_reg_out(n_reg_in -3*Nxy -2*Nangle-1 downto n_reg_in -3*Nxy -3*Nangle);
-------------------------------------
-- Rotador según eje X
-------------------------------------
xrot_load <= load_delay;
xrot_x0 <= y0_delay;
xrot_y0 <= z0_delay;
xrot_angle <= alfa_delay;
X_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => xrot_load,
x_in => xrot_x0,
y_in => xrot_y0,
angle => xrot_angle,
x_rot => xrot_x1,
y_rot => xrot_y1,
rotRdy => xrot_RxRdy
);
-------------------------------------
-- Delay para x
-------------------------------------
X_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits +1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => x0_delay,
B => x0_delay_delay
);
-------------------------------------
-- Rotador según eje Y
-------------------------------------
yrot_load <= xrot_RxRdy;
yrot_x0 <= xrot_y1;
yrot_y0 <= x0_delay_delay;
yrot_angle <= beta_delay;
Y_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => yrot_load,
x_in => yrot_x0,
y_in => yrot_y0,
angle => yrot_angle,
x_rot => yrot_x1,
y_rot => yrot_y1,
rotRdy => yrot_RxRdy
);
-------------------------------------
-- Delay para y
-------------------------------------
Y_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits+1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => xrot_x1,
B => xrot_x1_delay
);
-------------------------------------
-- Rotador según eje Z (plano XY)
-------------------------------------
zrot_load <= yrot_RxRdy;
zrot_x0 <= yrot_y1;
zrot_y0 <= xrot_x1_delay;
zrot_angle <= gama_delay;
Z_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => zrot_load,
x_in => zrot_x0,
y_in => zrot_y0,
angle => zrot_angle,
x_rot => zrot_x1,
y_rot => zrot_y1,
rotRdy => zrot_RxRdy
);
-------------------------------------
-- Delay para Z
-------------------------------------
Z_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits +1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => yrot_x1,
B => yrot_x1_delay
);
-- Registro de salida
out_reg_in <= zrot_RxRdy & zrot_x1 & zrot_y1 & yrot_x1_delay;
pipe_reg_out: entity work.registroNb
generic map(
N => 1 + 3*Nxy
)
port map(
clk => clock,
rst => reset,
ena => '1',
d => out_reg_in,
q => out_reg_out
);
RxRdy <= out_reg_out(1+3*Nxy-1);
x1 <= out_reg_out(1+3*Nxy-1-1 downto 1+3*Nxy-1-Nxy);
y1 <= out_reg_out(1+3*Nxy-1-Nxy-1 downto 1+3*Nxy-1-2*Nxy);
z1 <= out_reg_out(1+3*Nxy-1-2*Nxy-1 downto 0);
end;
| gpl-3.0 |
kuba-moo/VHDL-lib | reg_master_uart.vhd | 2 | 5493 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- UART interface for registers
entity reg_master_uart is
generic (REQ_SIZE : integer); -- #bytes per req
port (Clk : in std_logic;
Rst : in std_logic;
RxByte : in byte_t;
RxValid : in std_logic;
TxByte : out byte_t;
TxKick : out std_logic;
TxBusy : in std_logic;
BusO : out reg_bus_t;
BusI : in reg_bus_t);
end reg_master_uart;
-- Operation:
-- 1. receive Request from UART;
-- 2. convert Request to reg_bus_t format;
-- 3. send Request onto bus;
-- 4. read Response from the bus (bus is looped);
-- 5. convert Response to Request format;
-- 6. send Response to UART.
--
-- All UART frames have identical format.
-- - in read requests data is treated as default value (value which will
-- be returned if no register matches the address
-- - in write responses data is just an echo of the request and should NOT
-- be treated as new value of the register
--
-- Request bit format:
-- offset | field
-- ---------------+------------------------------
-- 0 | read(0)/write(1)
-- 1 - REG_ADDR_W | address
-- ------------align-to-byte-boundary------------
-- REQ_SIZE * 8 | data (default value for read)
--
--
-- WARNING: generating ny operation targeting invalid address (read or write
-- that encompasses address with all 1's) will HUNG the bus master!!!
architecture Behavioral of reg_master_uart is
constant REQ_HDR_LEN : integer := integer(ceil(real(1 + REG_ADDR_W)/8.0));
constant REQ_MAX_LEN : integer := REQ_HDR_LEN + REQ_SIZE;
type state_t is (WAIT_REQ, EMIT, WAIT_LOOP, RESPOND, WAIT_UART);
subtype req_buffer_t is std_logic_vector(REQ_MAX_LEN*8 - 1 downto 0);
constant ReqRWBit : integer := 0;
subtype ReqAddr is natural range REG_ADDR_W downto 1;
signal state, NEXT_state : state_t;
signal cnt, NEXT_cnt : integer range 0 to REQ_MAX_LEN := 0;
signal req_buf, NEXT_req_buf : req_buffer_t;
signal res_cnt, NEXT_res_cnt : integer range 0 to REQ_MAX_LEN;
begin
NEXT_fsm : process (state, cnt, req_buf, res_cnt, RxValid, RxByte, TxBusy, BusI, NEXT_cnt)
begin
NEXT_state <= state;
NEXT_cnt <= cnt;
NEXT_req_buf <= req_buf;
NEXT_res_cnt <= res_cnt;
TxByte <= req_buf(cnt*8 + 7 downto cnt*8);
TxKick <= '0';
BusO.wr <= req_buf(ReqRWBit);
BusO.addr <= reg_addr_invl;
BusO.data <= (others => '0');
if BusI.addr /= reg_addr_invl then -- data coming back
NEXT_req_buf((res_cnt + REQ_HDR_LEN)*8 + 7 downto
(res_cnt + REQ_HDR_LEN)*8) <= BusI.data;
NEXT_res_cnt <= res_cnt + 1;
end if;
case state is
when WAIT_REQ =>
if RxValid = '1' then
NEXT_req_buf(cnt*8 + 7 downto cnt*8) <= RxByte;
NEXT_cnt <= cnt + 1;
end if;
if cnt = REQ_MAX_LEN then
NEXT_state <= EMIT;
NEXT_cnt <= 0;
NEXT_res_cnt <= 0;
end if;
when EMIT =>
NEXT_cnt <= cnt + 1;
BusO.addr <= CONV_std_logic_vector(cnt + CONV_integer(req_buf(ReqAddr)), REG_ADDR_W);
BusO.data <= req_buf((cnt + REQ_HDR_LEN)*8 + 7 downto (cnt + REQ_HDR_LEN)*8);
if NEXT_cnt = REQ_SIZE then -- wait until data loops back
NEXT_state <= WAIT_LOOP;
end if;
when WAIT_LOOP =>
if res_cnt = REQ_SIZE then
NEXT_state <= RESPOND;
NEXT_cnt <= 0;
end if;
when RESPOND =>
NEXT_state <= WAIT_UART;
NEXT_cnt <= cnt + 1;
TxKick <= '1';
when WAIT_UART =>
if TxBusy = '0' then
NEXT_state <= RESPOND;
end if;
if cnt = REQ_MAX_LEN then
NEXT_state <= WAIT_REQ;
NEXT_cnt <= 0;
end if;
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
cnt <= NEXT_cnt;
req_buf <= NEXT_req_buf;
res_cnt <= NEXT_res_cnt;
if Rst = '1' then
state <= WAIT_REQ;
cnt <= 0;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
MartinCura/SistDig-TP4 | old/testers/cordic_tb.vhd | 1 | 1145 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity cordic_tb is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
end;
architecture cordic_tb_arq of cordic_tb is
signal clk_i : std_logic := '1';
signal ang : t_float := CERO;
signal x, y, z : t_coordenada := CERO;
signal vec_i, vec_o : t_vec;
begin
clk_i <= not clk_i after 5 ns;
ang <= PI_PF/4 after 49 ns, PI_PF/2 after 100 ns, 3*PI_PF/4 after 150 ns, PI_PF after 200 ns, 3*PI_PF/2 after 250 ns, -PI_PF/2 after 300 ns, 2*PI_PF after 350 ns, to_float(0.5) after 400 ns;
x <= to_float(1);
y <= to_float(2);
z <= to_float(3);
vec_i(1) <= x;
vec_i(2) <= y;
process(vec_i, ang)
begin
vec_o <= cordic(vec_i, ang);
end process;
process(clk_i, vec_o)
begin
if rising_edge(clk_i) then
report "pos x: " & integer'image(to_integer(to_signed(vec_o(1)*(1000),32)))
& " pos y: " & integer'image(to_integer(to_signed(vec_o(2)*(1000),32)))
severity note;
end if;
end process;
end;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rdmux.vhd | 18 | 69394 | -------------------------------------------------------------------------------
-- axi_datamover_rdmux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rdmux.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_rdmux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the width of the AXI Stream Data Channel
);
port (
-- AXI MMap Data Channel Input -----------------------------------------------
--
mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
-------------------------------------------------------------------------------
-- AXI Master Stream ---------------------------------------------------------
--
mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
--Mux data output --
-------------------------------------------------------------------------------
-- Command Calculator Interface -----------------------------------------------
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
-------------------------------------------------------------------------------
);
end entity axi_datamover_rdmux;
architecture implementation of axi_datamover_rdmux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (channel_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case channel_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- 1024-bit channel case
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH;
Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
mux_data_out <= sig_rdmux_dout;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate
begin
sig_rdmux_dout <= mmap_read_data_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel input mux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_NUX
--
-- Process Description:
-- Implement the 2XN Mux
--
-------------------------------------------------------------
DO_2XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when others => -- 1 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
end case;
end process DO_2XN_NUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel input mux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_NUX
--
-- Process Description:
-- Implement the 4XN Mux
--
-------------------------------------------------------------
DO_4XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when others => -- 3 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
end case;
end process DO_4XN_NUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel input mux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_NUX
--
-- Process Description:
-- Implement the 8XN Mux
--
-------------------------------------------------------------
DO_8XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when others => -- 7 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
end case;
end process DO_8XN_NUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel input mux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_NUX
--
-- Process Description:
-- Implement the 16XN Mux
--
-------------------------------------------------------------
DO_16XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when others => -- 15 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
end case;
end process DO_16XN_NUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel input mux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_NUX
--
-- Process Description:
-- Implement the 32XN Mux
--
-------------------------------------------------------------
DO_32XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when others => -- 31 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
end case;
end process DO_32XN_NUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel input mux case
--
--
------------------------------------------------------------
GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_64XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when others => -- 63 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
end case;
end process DO_64XN_NUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel input mux case
--
--
------------------------------------------------------------
GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_128XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when 63 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
when 64 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*65)-1 downto CHANNEL_DWIDTH*64) ;
when 65 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*66)-1 downto CHANNEL_DWIDTH*65) ;
when 66 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*67)-1 downto CHANNEL_DWIDTH*66) ;
when 67 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*68)-1 downto CHANNEL_DWIDTH*67) ;
when 68 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*69)-1 downto CHANNEL_DWIDTH*68) ;
when 69 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*70)-1 downto CHANNEL_DWIDTH*69) ;
when 70 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*71)-1 downto CHANNEL_DWIDTH*70) ;
when 71 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*72)-1 downto CHANNEL_DWIDTH*71) ;
when 72 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*73)-1 downto CHANNEL_DWIDTH*72) ;
when 73 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*74)-1 downto CHANNEL_DWIDTH*73) ;
when 74 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*75)-1 downto CHANNEL_DWIDTH*74) ;
when 75 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*76)-1 downto CHANNEL_DWIDTH*75) ;
when 76 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*77)-1 downto CHANNEL_DWIDTH*76) ;
when 77 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*78)-1 downto CHANNEL_DWIDTH*77) ;
when 78 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*79)-1 downto CHANNEL_DWIDTH*78) ;
when 79 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*80)-1 downto CHANNEL_DWIDTH*79) ;
when 80 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*81)-1 downto CHANNEL_DWIDTH*80) ;
when 81 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*82)-1 downto CHANNEL_DWIDTH*81) ;
when 82 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*83)-1 downto CHANNEL_DWIDTH*82) ;
when 83 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*84)-1 downto CHANNEL_DWIDTH*83) ;
when 84 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*85)-1 downto CHANNEL_DWIDTH*84) ;
when 85 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*86)-1 downto CHANNEL_DWIDTH*85) ;
when 86 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*87)-1 downto CHANNEL_DWIDTH*86) ;
when 87 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*88)-1 downto CHANNEL_DWIDTH*87) ;
when 88 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*89)-1 downto CHANNEL_DWIDTH*88) ;
when 89 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*90)-1 downto CHANNEL_DWIDTH*89) ;
when 90 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*91)-1 downto CHANNEL_DWIDTH*90) ;
when 91 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*92)-1 downto CHANNEL_DWIDTH*91) ;
when 92 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*93)-1 downto CHANNEL_DWIDTH*92) ;
when 93 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*94)-1 downto CHANNEL_DWIDTH*93) ;
when 94 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*95)-1 downto CHANNEL_DWIDTH*94) ;
when 95 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*96)-1 downto CHANNEL_DWIDTH*95) ;
when 96 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*97 )-1 downto CHANNEL_DWIDTH*96 ) ;
when 97 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*98 )-1 downto CHANNEL_DWIDTH*97 ) ;
when 98 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*99 )-1 downto CHANNEL_DWIDTH*98 ) ;
when 99 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*100)-1 downto CHANNEL_DWIDTH*99 ) ;
when 100 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*101)-1 downto CHANNEL_DWIDTH*100) ;
when 101 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*102)-1 downto CHANNEL_DWIDTH*101) ;
when 102 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*103)-1 downto CHANNEL_DWIDTH*102) ;
when 103 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*104)-1 downto CHANNEL_DWIDTH*103) ;
when 104 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*105)-1 downto CHANNEL_DWIDTH*104) ;
when 105 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*106)-1 downto CHANNEL_DWIDTH*105) ;
when 106 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*107)-1 downto CHANNEL_DWIDTH*106) ;
when 107 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*108)-1 downto CHANNEL_DWIDTH*107) ;
when 108 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*109)-1 downto CHANNEL_DWIDTH*108) ;
when 109 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*110)-1 downto CHANNEL_DWIDTH*109) ;
when 110 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*111)-1 downto CHANNEL_DWIDTH*110) ;
when 111 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*112)-1 downto CHANNEL_DWIDTH*111) ;
when 112 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*113)-1 downto CHANNEL_DWIDTH*112) ;
when 113 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*114)-1 downto CHANNEL_DWIDTH*113) ;
when 114 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*115)-1 downto CHANNEL_DWIDTH*114) ;
when 115 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*116)-1 downto CHANNEL_DWIDTH*115) ;
when 116 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*117)-1 downto CHANNEL_DWIDTH*116) ;
when 117 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*118)-1 downto CHANNEL_DWIDTH*117) ;
when 118 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*119)-1 downto CHANNEL_DWIDTH*118) ;
when 119 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*120)-1 downto CHANNEL_DWIDTH*119) ;
when 120 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*121)-1 downto CHANNEL_DWIDTH*120) ;
when 121 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*122)-1 downto CHANNEL_DWIDTH*121) ;
when 122 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*123)-1 downto CHANNEL_DWIDTH*122) ;
when 123 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*124)-1 downto CHANNEL_DWIDTH*123) ;
when 124 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*125)-1 downto CHANNEL_DWIDTH*124) ;
when 125 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*126)-1 downto CHANNEL_DWIDTH*125) ;
when 126 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*127)-1 downto CHANNEL_DWIDTH*126) ;
when others => -- 127 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*128)-1 downto CHANNEL_DWIDTH*127) ;
end case;
end process DO_128XN_NUX;
end generate GEN_128XN;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd | 4 | 87948 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd | 4 | 174357 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register_s2mm.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register_s2mm is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
tdest_in : in std_logic_vector (5 downto 0) ;
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register_s2mm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant SGCTL_INDEX : integer := 0;
constant DMACR_INDEX : integer := 1; -- DMACR Register index
constant DMASR_INDEX : integer := 2; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index
constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index
constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index
constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index
constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index
constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index
constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index
constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index
constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index
constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index
constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index
constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index
constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index
constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index
constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index
constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index
constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index
constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index
constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index
constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index
constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index
constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index
constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index
constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index
constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index
constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index
constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index
constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index
constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index
constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index
constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index
constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index
constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index
constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index
constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index
constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index
constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index
constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index
constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index
constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index
constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index
constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index
constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index
constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index
constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index
constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index
constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index
constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index
constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index
constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index
constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index
constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index
constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index
constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index
constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index
constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index
constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index
constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index
constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index
constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index
constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 7;
constant BUFF_ADDRESS_MSB_INDEX : integer := 8;
constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_64_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal update_curdesc1 : std_logic := '0';
signal update_curdesc2 : std_logic := '0';
signal update_curdesc3 : std_logic := '0';
signal update_curdesc4 : std_logic := '0';
signal update_curdesc5 : std_logic := '0';
signal update_curdesc6 : std_logic := '0';
signal update_curdesc7 : std_logic := '0';
signal update_curdesc8 : std_logic := '0';
signal update_curdesc9 : std_logic := '0';
signal update_curdesc10 : std_logic := '0';
signal update_curdesc11 : std_logic := '0';
signal update_curdesc12 : std_logic := '0';
signal update_curdesc13 : std_logic := '0';
signal update_curdesc14 : std_logic := '0';
signal update_curdesc15 : std_logic := '0';
signal dest0 : std_logic := '0';
signal dest1 : std_logic := '0';
signal dest2 : std_logic := '0';
signal dest3 : std_logic := '0';
signal dest4 : std_logic := '0';
signal dest5 : std_logic := '0';
signal dest6 : std_logic := '0';
signal dest7 : std_logic := '0';
signal dest8 : std_logic := '0';
signal dest9 : std_logic := '0';
signal dest10 : std_logic := '0';
signal dest11 : std_logic := '0';
signal dest12 : std_logic := '0';
signal dest13 : std_logic := '0';
signal dest14 : std_logic := '0';
signal dest15 : std_logic := '0';
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal error_pointer_set1 : std_logic := '0';
signal error_pointer_set2 : std_logic := '0';
signal error_pointer_set3 : std_logic := '0';
signal error_pointer_set4 : std_logic := '0';
signal error_pointer_set5 : std_logic := '0';
signal error_pointer_set6 : std_logic := '0';
signal error_pointer_set7 : std_logic := '0';
signal error_pointer_set8 : std_logic := '0';
signal error_pointer_set9 : std_logic := '0';
signal error_pointer_set10 : std_logic := '0';
signal error_pointer_set11 : std_logic := '0';
signal error_pointer_set12 : std_logic := '0';
signal error_pointer_set13 : std_logic := '0';
signal error_pointer_set14 : std_logic := '0';
signal error_pointer_set15 : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal tail_update_lsb : std_logic := '0';
signal tail_update_msb : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal halt_free : std_logic := '0';
signal tmp11 : std_logic := '0';
signal sig_cur_updated : std_logic := '0';
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
halt_free <= '1';
end generate GEN_MULTI_CH;
GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
halt_free <= dmasr_i(DMASR_HALTED_BIT);
end generate GEN_NOMULTI_CH;
GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate
begin
update_curdesc1 <= '0';
update_curdesc2 <= '0';
update_curdesc3 <= '0';
update_curdesc4 <= '0';
update_curdesc5 <= '0';
update_curdesc6 <= '0';
update_curdesc7 <= '0';
update_curdesc8 <= '0';
update_curdesc9 <= '0';
update_curdesc10 <= '0';
update_curdesc11 <= '0';
update_curdesc12 <= '0';
update_curdesc13 <= '0';
update_curdesc14 <= '0';
update_curdesc15 <= '0';
end generate GEN_DESC_UPDATE_FOR_SG;
dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0';
dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0';
dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0';
dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0';
dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0';
dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0';
dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0';
dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0';
dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0';
dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0';
dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0';
dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0';
dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0';
dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0';
dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0';
dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0';
GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate
update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0';
update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0';
update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0';
update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0';
update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0';
update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0';
update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0';
update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0';
update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0';
update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0';
update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0';
update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0';
update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0';
update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0';
update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0';
end generate GEN_DESC_UPDATE_FOR_SG_CH;
GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_64_i & buffer_address_i ;
end generate GEN_DA_ADDR_EQL64;
GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate GEN_DA_ADDR_EQL32;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_length <= buffer_length_i ;
curdesc1_lsb <= curdesc1_lsb_i ;
curdesc1_msb <= curdesc1_msb_i ;
taildesc1_lsb <= taildesc1_lsb_i ;
taildesc1_msb <= taildesc1_msb_i ;
curdesc2_lsb <= curdesc2_lsb_i ;
curdesc2_msb <= curdesc2_msb_i ;
taildesc2_lsb <= taildesc2_lsb_i ;
taildesc2_msb <= taildesc2_msb_i ;
curdesc3_lsb <= curdesc3_lsb_i ;
curdesc3_msb <= curdesc3_msb_i ;
taildesc3_lsb <= taildesc3_lsb_i ;
taildesc3_msb <= taildesc3_msb_i ;
curdesc4_lsb <= curdesc4_lsb_i ;
curdesc4_msb <= curdesc4_msb_i ;
taildesc4_lsb <= taildesc4_lsb_i ;
taildesc4_msb <= taildesc4_msb_i ;
curdesc5_lsb <= curdesc5_lsb_i ;
curdesc5_msb <= curdesc5_msb_i ;
taildesc5_lsb <= taildesc5_lsb_i ;
taildesc5_msb <= taildesc5_msb_i ;
curdesc6_lsb <= curdesc6_lsb_i ;
curdesc6_msb <= curdesc6_msb_i ;
taildesc6_lsb <= taildesc6_lsb_i ;
taildesc6_msb <= taildesc6_msb_i ;
curdesc7_lsb <= curdesc7_lsb_i ;
curdesc7_msb <= curdesc7_msb_i ;
taildesc7_lsb <= taildesc7_lsb_i ;
taildesc7_msb <= taildesc7_msb_i ;
curdesc8_lsb <= curdesc8_lsb_i ;
curdesc8_msb <= curdesc8_msb_i ;
taildesc8_lsb <= taildesc8_lsb_i ;
taildesc8_msb <= taildesc8_msb_i ;
curdesc9_lsb <= curdesc9_lsb_i ;
curdesc9_msb <= curdesc9_msb_i ;
taildesc9_lsb <= taildesc9_lsb_i ;
taildesc9_msb <= taildesc9_msb_i ;
curdesc10_lsb <= curdesc10_lsb_i ;
curdesc10_msb <= curdesc10_msb_i ;
taildesc10_lsb <= taildesc10_lsb_i ;
taildesc10_msb <= taildesc10_msb_i ;
curdesc11_lsb <= curdesc11_lsb_i ;
curdesc11_msb <= curdesc11_msb_i ;
taildesc11_lsb <= taildesc11_lsb_i ;
taildesc11_msb <= taildesc11_msb_i ;
curdesc12_lsb <= curdesc12_lsb_i ;
curdesc12_msb <= curdesc12_msb_i ;
taildesc12_lsb <= taildesc12_lsb_i ;
taildesc12_msb <= taildesc12_msb_i ;
curdesc13_lsb <= curdesc13_lsb_i ;
curdesc13_msb <= curdesc13_msb_i ;
taildesc13_lsb <= taildesc13_lsb_i ;
taildesc13_msb <= taildesc13_msb_i ;
curdesc14_lsb <= curdesc14_lsb_i ;
curdesc14_msb <= curdesc14_msb_i ;
taildesc14_lsb <= taildesc14_lsb_i ;
taildesc14_msb <= taildesc14_msb_i ;
curdesc15_lsb <= curdesc15_lsb_i ;
curdesc15_msb <= curdesc15_msb_i ;
taildesc15_lsb <= taildesc15_lsb_i ;
taildesc15_msb <= taildesc15_msb_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Key Hole write bit (3)
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest0 = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_lsb_i <= (others => '0');
error_pointer_set1 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set1 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then
curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set1 <= '0';
end if;
end if;
end if;
end process CURDESC1_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then
taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC1_LSB_REGISTER;
end generate GEN_DESC1_REG_FOR_SG;
GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_lsb_i <= (others => '0');
error_pointer_set2 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set2 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then
curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set2 <= '0';
end if;
end if;
end if;
end process CURDESC2_LSB_REGISTER;
TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then
taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC2_LSB_REGISTER;
end generate GEN_DESC2_REG_FOR_SG;
GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_lsb_i <= (others => '0');
error_pointer_set3 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set3 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then
curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set3 <= '0';
end if;
end if;
end if;
end process CURDESC3_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then
taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC3_LSB_REGISTER;
end generate GEN_DESC3_REG_FOR_SG;
GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_lsb_i <= (others => '0');
error_pointer_set4 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set4 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then
curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set4 <= '0';
end if;
end if;
end if;
end process CURDESC4_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then
taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC4_LSB_REGISTER;
end generate GEN_DESC4_REG_FOR_SG;
GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_lsb_i <= (others => '0');
error_pointer_set5 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set5 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then
curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set5 <= '0';
end if;
end if;
end if;
end process CURDESC5_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then
taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC5_LSB_REGISTER;
end generate GEN_DESC5_REG_FOR_SG;
GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_lsb_i <= (others => '0');
error_pointer_set6 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set6 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then
curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set6 <= '0';
end if;
end if;
end if;
end process CURDESC6_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then
taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC6_LSB_REGISTER;
end generate GEN_DESC6_REG_FOR_SG;
GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_lsb_i <= (others => '0');
error_pointer_set7 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set7 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then
curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set7 <= '0';
end if;
end if;
end if;
end process CURDESC7_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then
taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC7_LSB_REGISTER;
end generate GEN_DESC7_REG_FOR_SG;
GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_lsb_i <= (others => '0');
error_pointer_set8 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set8 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then
curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set8 <= '0';
end if;
end if;
end if;
end process CURDESC8_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then
taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC8_LSB_REGISTER;
end generate GEN_DESC8_REG_FOR_SG;
GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_lsb_i <= (others => '0');
error_pointer_set9 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set9 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then
curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set9 <= '0';
end if;
end if;
end if;
end process CURDESC9_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then
taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC9_LSB_REGISTER;
end generate GEN_DESC9_REG_FOR_SG;
GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_lsb_i <= (others => '0');
error_pointer_set10 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set10 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then
curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set10 <= '0';
end if;
end if;
end if;
end process CURDESC10_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then
taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC10_LSB_REGISTER;
end generate GEN_DESC10_REG_FOR_SG;
GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_lsb_i <= (others => '0');
error_pointer_set11 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set11 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then
curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set11 <= '0';
end if;
end if;
end if;
end process CURDESC11_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then
taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC11_LSB_REGISTER;
end generate GEN_DESC11_REG_FOR_SG;
GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_lsb_i <= (others => '0');
error_pointer_set12 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set12 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then
curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set12 <= '0';
end if;
end if;
end if;
end process CURDESC12_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then
taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC12_LSB_REGISTER;
end generate GEN_DESC12_REG_FOR_SG;
GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_lsb_i <= (others => '0');
error_pointer_set13 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set13 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then
curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set13 <= '0';
end if;
end if;
end if;
end process CURDESC13_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then
taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC13_LSB_REGISTER;
end generate GEN_DESC13_REG_FOR_SG;
GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_lsb_i <= (others => '0');
error_pointer_set14 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set14 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then
curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set14 <= '0';
end if;
end if;
end if;
end process CURDESC14_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then
taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC14_LSB_REGISTER;
end generate GEN_DESC14_REG_FOR_SG;
GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_lsb_i <= (others => '0');
error_pointer_set15 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set15 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then
curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set15 <= '0';
end if;
end if;
end if;
end process CURDESC15_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then
taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC15_LSB_REGISTER;
end generate GEN_DESC15_REG_FOR_SG;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
elsif(sg_updt_error = '1' and dest0 = '1')then
curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_msb_i <= (others => '0');
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then
curdesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC1_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then
taildesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC1_MSB_REGISTER;
end generate GEN_DESC1_MSB_FOR_SG;
GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_msb_i <= (others => '0');
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then
curdesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC2_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then
taildesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC2_MSB_REGISTER;
end generate GEN_DESC2_MSB_FOR_SG;
GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_msb_i <= (others => '0');
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then
curdesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC3_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then
taildesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC3_MSB_REGISTER;
end generate GEN_DESC3_MSB_FOR_SG;
GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_msb_i <= (others => '0');
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then
curdesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC4_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then
taildesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC4_MSB_REGISTER;
end generate GEN_DESC4_MSB_FOR_SG;
GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_msb_i <= (others => '0');
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then
curdesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC5_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then
taildesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC5_MSB_REGISTER;
end generate GEN_DESC5_MSB_FOR_SG;
GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_msb_i <= (others => '0');
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then
curdesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC6_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then
taildesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC6_MSB_REGISTER;
end generate GEN_DESC6_MSB_FOR_SG;
GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_msb_i <= (others => '0');
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then
curdesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC7_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then
taildesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC7_MSB_REGISTER;
end generate GEN_DESC7_MSB_FOR_SG;
GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_msb_i <= (others => '0');
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then
curdesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC8_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then
taildesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC8_MSB_REGISTER;
end generate GEN_DESC8_MSB_FOR_SG;
GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_msb_i <= (others => '0');
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then
curdesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC9_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then
taildesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC9_MSB_REGISTER;
end generate GEN_DESC9_MSB_FOR_SG;
GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_msb_i <= (others => '0');
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then
curdesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC10_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then
taildesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC10_MSB_REGISTER;
end generate GEN_DESC10_MSB_FOR_SG;
GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_msb_i <= (others => '0');
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then
curdesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC11_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then
taildesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC11_MSB_REGISTER;
end generate GEN_DESC11_MSB_FOR_SG;
GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_msb_i <= (others => '0');
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then
curdesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC12_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then
taildesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC12_MSB_REGISTER;
end generate GEN_DESC12_MSB_FOR_SG;
GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_msb_i <= (others => '0');
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then
curdesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC13_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then
taildesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC13_MSB_REGISTER;
end generate GEN_DESC13_MSB_FOR_SG;
GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_msb_i <= (others => '0');
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then
curdesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC14_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then
taildesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC14_MSB_REGISTER;
end generate GEN_DESC14_MSB_FOR_SG;
GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_msb_i <= (others => '0');
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then
curdesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC15_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then
taildesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC15_MSB_REGISTER;
end generate GEN_DESC15_MSB_FOR_SG;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to the extra registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15);
end generate GENERATE_MULTI_CH;
GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15);
end generate GENERATE_NO_MULTI_CH1;
GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH2;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_msb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to new registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
curdesc1_lsb_i <= (others => '0');
taildesc1_lsb_i <= (others => '0');
curdesc2_lsb_i <= (others => '0');
taildesc2_lsb_i <= (others => '0');
curdesc3_lsb_i <= (others => '0');
taildesc3_lsb_i <= (others => '0');
curdesc4_lsb_i <= (others => '0');
taildesc4_lsb_i <= (others => '0');
curdesc5_lsb_i <= (others => '0');
taildesc5_lsb_i <= (others => '0');
curdesc6_lsb_i <= (others => '0');
taildesc6_lsb_i <= (others => '0');
curdesc7_lsb_i <= (others => '0');
taildesc7_lsb_i <= (others => '0');
curdesc8_lsb_i <= (others => '0');
taildesc8_lsb_i <= (others => '0');
curdesc9_lsb_i <= (others => '0');
taildesc9_lsb_i <= (others => '0');
curdesc10_lsb_i <= (others => '0');
taildesc10_lsb_i <= (others => '0');
curdesc11_lsb_i <= (others => '0');
taildesc11_lsb_i <= (others => '0');
curdesc12_lsb_i <= (others => '0');
taildesc12_lsb_i <= (others => '0');
curdesc13_lsb_i <= (others => '0');
taildesc13_lsb_i <= (others => '0');
curdesc14_lsb_i <= (others => '0');
taildesc14_lsb_i <= (others => '0');
curdesc15_lsb_i <= (others => '0');
taildesc15_lsb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_64_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_64_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then
buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd | 4 | 75293 | -------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_9.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/vhdl/ANN_ST_uOut.vhd | 7 | 4489 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 160
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 160;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_uOut is
component ANN_ST_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_uOut_ram_U : component ANN_ST_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 7 | 24940 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fadd_3_full_dsp_32/synth/ANN_ap_fadd_3_full_dsp_32.vhd | 6 | 12700 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fadd_3_full_dsp_32.vhd | 6 | 12700 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd | 7 | 41813 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd | 15 | 10256 | -- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library lib_srl_fifo_v1_0_2;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
-- constant COUNTER_PRIMS_AVAIL : boolean :=
-- supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
constant COUNTER_PRIMS_AVAIL : boolean := false;
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_fifo.vhd | 7 | 24380 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_sfifo_autord;
use axi_sg_v4_1_2.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1_2.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/vhdl/feedforward_mux_4to1_sel2_32_1.vhd | 3 | 1622 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3.vhd | 4 | 21293 | `protect begin_protected
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`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13632)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd | 4 | 33317 | -------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fdiv_14_no_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 24 | 73491 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 24 | 73491 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/synth/ANN_ap_fptrunc_0_no_dsp_64.vhd | 1 | 12159 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE ANN_ap_fptrunc_0_no_dsp_64_arch OF ANN_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fptrunc_0_no_dsp_64_arch;
| gpl-3.0 |
Rookfighter/aes-ss17 | ex03/i2c_slave_write_tb.vhd | 1 | 6507 | -- i2c_slave_tb.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave_write_tb is
end entity;
architecture behavior of i2c_slave_write_tb is
-- Component Declaration for the Unit Under Test (UUT)
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end component;
--Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
--Outputs
signal tx_sent: std_logic;
signal rx_data: std_logic_vector(7 downto 0);
signal rx_recv: std_logic;
signal busy: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave
generic map(RSTDEF => '0',
ADDRDEF => "0010111") -- address 0x17
port map(rst => rst,
clk => clk,
tx_data => tx_data,
tx_sent => tx_sent,
rx_data => rx_data,
rx_recv => rx_recv,
busy => busy,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
sda <= tosend;
-- wait for delay element to take over new value
wait for 24*clk_period;
-- allow slave to read
scl <= '1';
wait for clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for clk_period;
scl <= '1';
wait for clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
-- init transmission
send_start;
-- send correct address
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('1'); -- data bit 2
send_bit('0'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('1'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- rx_data should be "11001101"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('1'); -- data bit 7
send_bit('0'); -- data bit 8
-- rx_data should be "10100110"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- terminate transmission
send_stop;
-- init next transmission
send_start;
-- send wrong address 0x13
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('0'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send no ack and go back to idle mode
wait_ack;
-- send data
-- slave should not record it
send_bit('0'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- slave should send no ack and go back to idle mode
wait_ack;
-- terminate transmission
send_stop;
wait for clk_period*10;
wait;
end process;
end;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_sofeof_gen.vhd | 4 | 19880 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_dadd_64ns_64ns_64_5_full_dsp.vhd | 6 | 3340 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 7;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dadd_3_full_dsp_64_u : component ANN_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 7 | 41879 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 7 | 41879 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd | 4 | 103940 | -------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_1/hdl/ip/ANN_ap_fcmp_0_no_dsp_32.vhd | 6 | 12778 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ANN_ap_fcmp_0_no_dsp_32;
ARCHITECTURE ANN_ap_fcmp_0_no_dsp_32_arch OF ANN_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fcmp_0_no_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd | 7 | 41099 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
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-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- CRITICAL APPLICATIONS
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
--use axi_sg_v4_1_2.axi_sg_afifo_autord.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
-- Channel Control --
desc1_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
desc2_flush : in std_logic ; --
ftch1_active : in std_logic ; --
ftch2_active : in std_logic ; --
ftch1_queue_empty : out std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch1_queue_full : out std_logic ; --
ftch2_queue_full : out std_logic ; --
ftch1_pause : out std_logic ; --
ftch2_pause : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing1_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
sof_ftch_desc : in std_logic ;
m_axis1_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
--
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_64_cdma : in std_logic_vector --
(31 downto 0) ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
data_concat_tlast : in std_logic ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_aclk : in std_logic ; --
m_axis_ftch1_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch1_tvalid : out std_logic ; --
m_axis_ftch1_tready : in std_logic ; --
m_axis_ftch1_tlast : out std_logic ; --
m_axis_ftch1_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch1_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch1_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
m_axis_ftch2_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch2_tvalid : out std_logic ; --
m_axis_ftch2_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch2_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch2_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
m_axis_ftch2_tready : in std_logic ; --
m_axis_ftch2_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Number of words deep fifo needs to be
-- 6 is subtracted as BD address are always 16 word aligned
constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6);
constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL;
--constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
-- * C_SG_WORDS_TO_FETCH1));
constant FETCH_QUEUE_DEPTH : integer := 16;
-- Select between BRAM or Logic Memory Type
constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG_WORDS_TO_FETCH1 > 16);
constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1);
constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1;
constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461
constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH;
constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1));
-- Select between BRAM or Logic Memory Type
constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1 > 16);
constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1);
constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1;
constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant DESC2QUEUE_VECT_WIDTH : integer := 4;
--constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
--constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461
constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tvalid_new : std_logic := '0';
signal ftch_tdata : std_logic_vector
(31 downto 0) := (others => '0');
signal ftch_tdata_new, reg1, reg2 : std_logic_vector
(FIFO_WIDTH-1 downto 0) := (others => '0');
signal ftch_tdata_new_64, reg1_64, reg2_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal ftch_tdata_new_bd, reg2_bd_64, reg1_bd_64 : std_logic_vector (31 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tlast_new : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal ftch_tready_ch1 : std_logic := '0';
signal ftch_tready_ch2 : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-- FIFO signals
signal queue_rden2 : std_logic := '0';
signal queue_rden2_new : std_logic := '0';
signal queue_wren2 : std_logic := '0';
signal queue_wren2_new : std_logic := '0';
signal queue_empty2 : std_logic := '0';
signal queue_empty2_new : std_logic := '0';
signal queue_rden : std_logic := '0';
signal queue_rden_new : std_logic := '0';
signal queue_wren : std_logic := '0';
signal queue_wren_new : std_logic := '0';
signal queue_empty : std_logic := '0';
signal queue_empty_new : std_logic := '0';
signal queue_dout_valid : std_logic := '0';
signal queue_dout2_valid : std_logic := '0';
signal queue_full_new : std_logic := '0';
signal queue_full2_new : std_logic := '0';
signal queue_full, queue_full2 : std_logic := '0';
signal queue_din_new : std_logic_vector
(127 downto 0) := (others => '0');
signal queue_dout_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_dout2_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout2_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout2_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout2_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_din : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout2 : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_sinit : std_logic := '0';
signal queue_sinit2 : std_logic := '0';
signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal ftch_no_room : std_logic;
signal ftch_active : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal sof_ftch_desc_del : std_logic;
signal sof_ftch_desc_del1 : std_logic;
signal sof_ftch_desc_pulse : std_logic;
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal xfer_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1'))then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
ftch_active <= ftch1_active or ftch2_active;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
CURRENT_BD_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(32+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_64;
CURRENT_BD_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_32;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
m_axis_ftch1_tdata_mcdma_new <= (others => '0');
m_axis_ftch2_tdata_mcdma_new <= (others => '0');
COUNTER_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
counter <= (others => '0');
elsif (m_axis_mm2s_tvalid = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process COUNTER_PROCESS;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
CDMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (63 downto 0) <= data_concat_64_cdma & data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate CDMA_FIELDS_64;
ftch_tdata_new (95 downto 0) <= data_concat;
-- BD is always 16 word aligned
ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6);
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
DMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (31 downto 0) <= data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate DMA_FIELDS_64;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
-- BD is always 16 word aligned
ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6);
end generate DMA_FIELDS;
ftch_tvalid_new <= data_concat_valid and ftch_active;
ftch_tlast_new <= data_concat_tlast and ftch_active;
GEN_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_rden_new = '1') then
queue_empty_new <= '1';
queue_full_new <= '0';
elsif (queue_wren_new = '1') then
queue_empty_new <= '0';
queue_full_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
reg1 <= (others => '0');
reg1_64 <= (others => '0');
reg1_bd_64 <= (others => '0');
elsif (queue_wren_new = '1') then
reg1 <= ftch_tdata_new;
reg1_64 <= ftch_tdata_new_64;
reg1_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
queue_dout_new <= (others => '0');
queue_dout_new_64 <= (others => '0');
queue_dout_new_bd <= (others => '0');
elsif (queue_rden_new = '1') then
queue_dout_new <= reg1;
queue_dout_new_64 <= reg1_64;
queue_dout_new_bd <= reg1_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_dout_valid = '1') then
queue_dout_valid <= '0';
elsif (queue_rden_new = '1') then
queue_dout_valid <= '1';
end if;
end if;
end process;
MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH1_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren_new ,
Rd_en => queue_rden_new ,
Dout => queue_dout_mcdma_new ,
Full => open, --queue_full_new ,
Empty => open, --queue_empty_new ,
Almost_full => open ,
Data_count => open, --queue_dcount_new ,
Rd_ack => open, --queue_dout_valid, --open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new;
end generate MCDMA_MM2S;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate
begin
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
end generate GEN_MM2S;
GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_rden2_new = '1') then
queue_empty2_new <= '1';
queue_full2_new <= '0';
elsif (queue_wren2_new = '1') then
queue_empty2_new <= '0';
queue_full2_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
reg2 <= (others => '0');
reg2_64 <= (others => '0');
reg2_bd_64 <= (others => '0');
elsif (queue_wren2_new = '1') then
reg2 <= ftch_tdata_new;
reg2_64 <= ftch_tdata_new_64;
reg2_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
queue_dout2_new <= (others => '0');
queue_dout2_new_64 <= (others => '0');
queue_dout2_new_bd <= (others => '0');
elsif (queue_rden2_new = '1') then
queue_dout2_new <= reg2;
queue_dout2_new_64 <= reg2_64;
queue_dout2_new_bd <= reg2_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_dout2_valid = '1') then
queue_dout2_valid <= '0';
elsif (queue_rden2_new = '1') then
queue_dout2_valid <= '1';
end if;
end if;
end process;
MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH2_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit2 ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren2_new ,
Rd_en => queue_rden2_new ,
Dout => queue_dout2_new ,
Full => open, --queue_full2_new ,
Empty => open, --queue_empty2_new ,
Almost_full => open ,
Data_count => queue_dcount2_new ,
Rd_ack => open, --queue_dout2_valid ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new;
end generate MCDMA_S2MM;
end generate GEN_S2MM;
-----------------------------------------------------------------------
-- Internal Side
-----------------------------------------------------------------------
-- Drive tready with fifo not full
ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2;
-- Following is the APP data that goes into APP FIFO
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate
begin
--queue_full_new <= '1' when (queue_dcount_new = "00100") else '0';
queue_sinit <= desc1_flush or not m_axi_sg_aresetn;
ftch_tready_ch1 <= (not queue_full and ftch1_active);
m_axis1_mm2s_tready <= ftch_tready_ch1;
-- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched.
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch1_active;
-- Wr_en of BD FIFO
queue_wren_new <= not queue_full_new
and ftch_tvalid_new
and ftch1_active;
ftch1_queue_empty <= queue_empty_new;
ftch1_queue_full <= queue_full_new;
ftch1_pause <= queue_full_new;
-- RD_en of APP FIFO based on empty and tready
-- RD_EN of BD FIFO based on empty and tready
queue_rden_new <= not queue_empty_new
and m_axis_ftch1_tready;
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle);
-- below signal triggers the fetch of BD in MM2S Mngr
m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
FTCH_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new_bd & queue_dout_new_64 & queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64;
FTCH_FIELDS_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32;
writing1_curdesc_out <= writing_curdesc and ftch1_active;
NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NOCONTROL_STREAM_ASST;
end generate GEN_CH1_CTRL;
GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
ftch_tready_ch1 <= '0';
m_axis1_mm2s_tready <= '0';
-- Write to fifo if it is not full and data is valid
queue_wren <= '0';
ftch1_queue_empty <= '0';
ftch1_queue_full <= '0';
ftch1_pause <= '0';
queue_rden <= '0';
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
writing1_curdesc_out <= '0';
m_axis_ftch1_tdata_new <= (others => '0');
m_axis_ftch1_tvalid_new <= '0';
m_axis_ftch1_desc_available <= '0';
end generate GEN_NO_CH1_CTRL;
GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate
begin
queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn;
ftch_tready_ch2 <= (not queue_full2_new and ftch2_active);
m_axis2_mm2s_tready <= ftch_tready_ch2;
queue_wren2 <= '0';
-- Wr_en for S2MM BD FIFO
queue_wren2_new <= not queue_full2_new
and ftch_tvalid_new
and ftch2_active;
--queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
ftch2_queue_empty <= queue_empty2_new;
ftch2_queue_full <= queue_full2_new;
ftch2_pause <= queue_full2_new;
queue_rden2 <= '0';
-- Rd_en for S2MM BD FIFO
queue_rden2_new <= not queue_empty2_new
and m_axis_ftch2_tready;
m_axis_ftch2_tvalid <= '0';
m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle);
m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
FTCH_FIELDS_64_2 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new_bd & queue_dout2_new_64 & queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64_2;
FTCH_FIELDS_32_2 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32_2;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
end generate GEN_CH2_CTRL;
GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate
begin
ftch_tready_ch2 <= '0';
m_axis2_mm2s_tready <= '0';
queue_wren2 <= '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
--ftch_queue_empty <= queue_empty; CR 621600
ftch2_queue_empty <= '0';
ftch2_queue_full <= '0';
ftch2_pause <= '0';
queue_rden2 <= '0';
m_axis_ftch2_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
m_axis_ftch2_tdata_new <= (others => '0');
m_axis_ftch2_tvalid_new <= '0';
writing2_curdesc_out <= '0';
m_axis_ftch2_desc_available <= '0';
end generate GEN_NO_CH2_CTRL;
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/vhdl/feedforward_fptrunc_64ns_32_1.vhd | 4 | 1982 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fptrunc_64ns_32_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component feedforward_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fptrunc_0_no_dsp_64_u : component feedforward_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fptrunc_64ns_32_1.vhd | 4 | 1982 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fptrunc_64ns_32_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component feedforward_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fptrunc_0_no_dsp_64_u : component feedforward_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd | 18 | 6145 | -------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux8_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 8 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux8_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 8x Mux slice
);
port (
Sel : In std_logic_vector(2 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
I4 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 4 input
I5 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 5 input
I6 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 6 input
I7 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 7 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux8_1_x_n; --
Architecture implementation of axi_datamover_dre_mux8_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT8_1
--
-- Process Description:
-- This process implements an 8 to 1 mux.
--
-------------------------------------------------------------
SELECT8_1 : process (Sel, I0, I1, I2, I3,
I4, I5, I6, I7)
begin
case Sel is
when "000" =>
Y <= I0;
when "001" =>
Y <= I1;
when "010" =>
Y <= I2;
when "011" =>
Y <= I3;
when "100" =>
Y <= I4;
when "101" =>
Y <= I5;
when "110" =>
Y <= I6;
when "111" =>
Y <= I7;
when others =>
Y <= I0;
end case;
end process SELECT8_1;
end implementation; -- axi_datamover_dre_mux8_1_x_n
-------------------------------------------------------------------------------
-- End 8 to 1 xN Mux
-------------------------------------------------------------------------------
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd | 28 | 10116 | -- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_mm2s_basic_wrap.vhd | 7 | 43265 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd | 24 | 292074 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dexp_16_full_dsp_64/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd | 24 | 292074 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
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`protect end_protected
| gpl-3.0 |
makestuff/spi-talk | templates/fx2all/vhdl/top_level.vhdl | 1 | 5035 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Peripheral interface ----------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(NUM_DEVS-1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/ip/feedforward_ap_fmul_2_max_dsp_32.vhd | 4 | 12777 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fadd_32ns_32ns_32_5_full_dsp.vhd | 4 | 3380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fadd_32ns_32ns_32_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fadd_32ns_32ns_32_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fadd_3_full_dsp_32_u : component feedforward_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fpext_0_no_dsp_32.vhd | 6 | 12143 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_fpext_0_no_dsp_32;
ARCHITECTURE ANN_ap_fpext_0_no_dsp_32_arch OF ANN_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fpext_0_no_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wr_demux.vhd | 13 | 75458 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_sg_wr_demux;
architecture implementation of axi_sg_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_sitofp_32ns_32_6.vhd | 6 | 2642 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_sitofp_32ns_32_6 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_sitofp_32ns_32_6 is
--------------------- Component ---------------------
component ANN_ap_sitofp_4_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_sitofp_4_no_dsp_32_u : component ANN_ap_sitofp_4_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd | 24 | 157786 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
GK+B9PZwAQG0AijumSfbCugpYhcwULsoxpdEe41kJbdOvZ5J1nq4AhWPTePhNLqLZyBbfYmxsIZl
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd | 24 | 157786 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dexp_64ns_64ns_64_18_full_dsp.vhd | 2 | 2809 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 4;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_ibttcc.vhd | 18 | 112659 | -------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
| gpl-3.0 |
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