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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/ANN_ddiv_64ns_64ns_64_31.vhd | 6 | 3322 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd | 4 | 92853 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset ;
use axi_datamover_v5_1_9.axi_datamover_cmd_status ;
use axi_datamover_v5_1_9.axi_datamover_pcc ;
use axi_datamover_v5_1_9.axi_datamover_ibttcc ;
use axi_datamover_v5_1_9.axi_datamover_indet_btt ;
use axi_datamover_v5_1_9.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_9.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1_9.axi_datamover_skid_buf ;
Use axi_datamover_v5_1_9.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_9.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_9.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1_9.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1_9.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
| gpl-3.0 |
Rookfighter/aes-ss17 | ex01/whole_design.vhd | 1 | 2408 | -- whole_design.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Integrates ledblinker and freq_controller.
library ieee;
use ieee.std_logic_1164.all;
entity whole_design is
generic(RSTDEF: std_logic := '0'); -- reset button is low active
port(rst: in std_logic; -- reset, RESTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
led: out std_logic; -- LED status, active high
freq: out std_logic_vector(2 downto 0)); -- blinking frequency, 000 = stop, 111 = fast
end whole_design;
architecture behavioral of whole_design is
component ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
freq: in std_logic_vector(2 downto 0); -- blinking frequency, 000 = stop, 111 = fast
led: out std_logic); -- LED status, active high
end component;
component freq_controller is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
freq: out std_logic_vector(2 downto 0)); -- frequency, 000 = stop, 111 = fast
end component;
-- signal to connect freq, ledblinker and freq_controller
signal freq_tmp: std_logic_vector(2 downto 0) := (others => '0');
begin
-- connect freq_tmp to out port freq
freq <= freq_tmp;
-- connect freq of ledblinker to freq_tmp (read)
lblink: ledblinker
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
freq => freq_tmp,
led => led);
-- connect freq of freq_controlelr to freq_tmp (write)
fcontr : freq_controller
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
btn0 => btn0,
btn1 => btn1,
freq => freq_tmp);
end behavioral;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_mul_7ns_31ns_38_3.vhd | 3 | 2699 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(31 - 1 downto 0);
p: out std_logic_vector(38 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
signal tmp_product : std_logic_vector(38 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(31 - 1 downto 0);
signal p_tmp : std_logic_vector(38 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(31 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(38 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 38));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_31ns_38_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_31ns_38_3 is
component feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_31ns_38_3_Mul3S_0_U : component feedforward_mul_7ns_31ns_38_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd | 24 | 10054 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd | 24 | 10054 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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lgbORi9FkufyjC5h+qBXYo2MNb8GBJgrnk1MKQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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2s2Y/e1zmbUtpz3jQt4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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kGRTzk7UkhrDq3Oux/TeAQEkQ232IeceP94yxw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dadd_3_full_dsp_64/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd | 24 | 10054 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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50cQnibA9g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_cmd_split.vhd | 4 | 22816 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | tb_dramtest.vhd | 1 | 6002 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:29:26 12/18/2016
-- Design Name:
-- Module Name: tb_dramtest.vhd
-- Project Name: bonfire
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: papilio_pro_dram_toplevel
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dramtest IS
generic (
RamFileName : string := "compiled_code/monitor.hex";
--RamFileName : string :="../../../bonfire-soc/compiled_code/monitor.hex";
mode : string := "H"; -- only used when UseBRAMPrimitives is false
Swapbytes : boolean := false; -- SWAP Bytes in RAM word in low byte first order to use data2mem
FakeDRAM : boolean := false; -- Use Block RAM instead of DRAM
BurstSize : natural := 8;
CacheSizeWords : natural := 4096; -- 16KB Instruction Cache
EnableDCache : boolean := true;
DCacheSizeWords : natural := 2048;
MUL_ARCH: string := "spartandsp";
REG_RAM_STYLE : string := "block";
DRAM_INIT_FILE : string :=""
);
END tb_dramtest;
ARCHITECTURE behavior OF tb_dramtest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT papilio_pro_dram_toplevel
generic (
RamFileName : string;
mode : string;
Swapbytes : boolean := true;
FakeDRAM : boolean := false;
BurstSize : natural := 8;
CacheSizeWords : natural := 2048; -- 8KB Instruction Cache
EnableDCache : boolean := true;
DCacheSizeWords : natural := 2048;
MUL_ARCH: string := "spartandsp";
REG_RAM_STYLE : string := "block"
);
PORT(
sysclk_32m : IN std_logic;
I_RESET : IN std_logic;
uart0_rxd : IN std_logic;
flash_spi_miso : IN std_logic;
SDRAM_DATA : INOUT std_logic_vector(15 downto 0);
leds : OUT std_logic_vector(3 downto 0);
uart0_txd : OUT std_logic;
flash_spi_cs : OUT std_logic;
flash_spi_clk : OUT std_logic;
flash_spi_mosi : OUT std_logic;
led1 : OUT std_logic;
SDRAM_CLK : OUT std_logic;
SDRAM_CKE : OUT std_logic;
SDRAM_CS : OUT std_logic;
SDRAM_RAS : OUT std_logic;
SDRAM_CAS : OUT std_logic;
SDRAM_WE : OUT std_logic;
SDRAM_DQM : OUT std_logic_vector(1 downto 0);
SDRAM_ADDR : OUT std_logic_vector(12 downto 0);
SDRAM_BA : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT sdram_model
GENERIC (
mode : string := "H";
RamFileName : string
);
PORT(
CLK : IN std_logic;
CKE : IN std_logic;
CS_N : IN std_logic;
RAS_N : IN std_logic;
CAS_N : IN std_logic;
WE_N : IN std_logic;
BA : IN std_logic_vector(1 downto 0);
DQM : IN std_logic_vector(1 downto 0);
ADDR : IN std_logic_vector(12 downto 0);
DQ : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal sysclk_32m : std_logic := '0';
signal I_RESET : std_logic := '0';
signal uart0_rxd : std_logic := '0';
--BiDirs
signal SDRAM_DATA : std_logic_vector(15 downto 0);
--Outputs
signal leds : std_logic_vector(3 downto 0);
signal uart0_txd : std_logic;
signal led1 : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CS : std_logic;
signal SDRAM_RAS : std_logic;
signal SDRAM_CAS : std_logic;
signal SDRAM_WE : std_logic;
signal SDRAM_DQM : std_logic_vector(1 downto 0);
signal SDRAM_ADDR : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal flash_spi_cs,flash_spi_clk,flash_spi_loopback : std_logic;
-- Clock period definitions
constant clock_period : time := 31.25ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: papilio_pro_dram_toplevel
generic map (
RamFileName => RamFileName,
mode=>mode,
FakeDRAM=>FakeDRAM,
Swapbytes=>Swapbytes,
CacheSizeWords => CacheSizeWords,
BurstSize =>BurstSize,
EnableDCache => EnableDCache,
DCacheSizeWords=>DCacheSizeWords,
MUL_ARCH=>MUL_ARCH,
REG_RAM_STYLE=>REG_RAM_STYLE
)
PORT MAP (
sysclk_32m => sysclk_32m,
I_RESET => I_RESET,
leds => leds,
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
led1 => led1,
flash_spi_cs =>flash_spi_cs ,
flash_spi_clk => flash_spi_clk,
flash_spi_mosi => flash_spi_loopback,
flash_spi_miso => flash_spi_loopback,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS => SDRAM_CS,
SDRAM_RAS => SDRAM_RAS,
SDRAM_CAS => SDRAM_CAS,
SDRAM_WE => SDRAM_WE,
SDRAM_DQM => SDRAM_DQM,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_BA => SDRAM_BA,
SDRAM_DATA => SDRAM_DATA
);
Inst_sdram_model: sdram_model
GENERIC MAP (
mode=>"H",
RamFileName => DRAM_INIT_FILE
)
PORT MAP(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
CS_N => SDRAM_CS,
RAS_N => SDRAM_RAS,
CAS_N => SDRAM_CAS,
WE_N => SDRAM_WE,
BA => SDRAM_BA,
DQM => SDRAM_DQM,
ADDR => SDRAM_ADDR,
DQ => SDRAM_DATA
);
-- Clock process definitions
clock_process :process
begin
sysclk_32m <= '0';
wait for clock_period/2;
sysclk_32m <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sm.vhd | 4 | 28280 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/lib_fifo_v1_0/hdl/src/vhdl/async_fifo_fg.vhd | 4 | 124572 | -- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_1 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
--library lib_fifo_v1_0_4;
--use lib_fifo_v1_0_4.lib_fifo_pkg.all;
--use lib_fifo_v1_0_4.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd | 8 | 35419 | -------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fadd_3_full_dsp_32/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 24 | 24644 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dexp_16_full_dsp_64/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 24 | 24644 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_dadd_64ns_64ns_64_5_full_dsp.vhd | 4 | 3380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 6;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dadd_3_full_dsp_64_u : component feedforward_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/vhdl/feedforward_dadd_64ns_64ns_64_5_full_dsp.vhd | 4 | 3380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 6;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dadd_3_full_dsp_64_u : component feedforward_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wr_status_cntl.vhd | 7 | 57339 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd | 4 | 11936 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd | 7 | 25964 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd | 4 | 24259 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1_8.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1_8.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd | 18 | 16390 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_omit_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 0;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input --------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- MM2S Halt request input control-------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------------
-- Error discrete output ----------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-----------------------------------------------------------
-- Optional MM2S Command and Status clock and Reset -----------
-- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
---------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
----------------------------------------------------------------
-- Address Posting contols -------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
----------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_omit_wrap;
architecture implementation of axi_datamover_mm2s_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type
-- Just tie off output ports
mm2s_halt_cmplt <= mm2s_halt ;
mm2s_err <= '0' ;
mm2s_cmd_wready <= '0' ;
mm2s_sts_wvalid <= '0' ;
mm2s_sts_wdata <= (others => '0');
mm2s_sts_wstrb <= (others => '0');
mm2s_sts_wlast <= '0' ;
mm2s_arid <= (others => '0');
mm2s_araddr <= (others => '0');
mm2s_arlen <= (others => '0');
mm2s_arsize <= (others => '0');
mm2s_arburst <= (others => '0');
mm2s_arprot <= (others => '0');
mm2s_arcache <= (others => '0');
mm2s_aruser <= (others => '0');
mm2s_arvalid <= '0' ;
mm2s_rready <= '0' ;
mm2s_strm_wdata <= (others => '0');
mm2s_strm_wstrb <= (others => '0');
mm2s_strm_wlast <= '0' ;
mm2s_strm_wvalid <= '0' ;
mm2s_addr_req_posted <= '0' ;
mm2s_rd_xfer_cmplt <= '0' ;
-- Input ports are ignored
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_ddiv_29_no_dsp_64.vhd | 6 | 12779 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_ddiv_29_no_dsp_64;
ARCHITECTURE feedforward_ap_ddiv_29_no_dsp_64_arch OF feedforward_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_ddiv_29_no_dsp_64_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fadd_3_full_dsp_32/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd | 24 | 8323 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd | 24 | 8323 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd | 24 | 8323 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_sitofp_4_no_dsp_32/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd | 24 | 8323 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_1/hdl/vhdl/ANN_AXILiteS_s_axi.vhd | 6 | 17016 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
ap_return :in STD_LOGIC_VECTOR(31 downto 0);
P_mode :out STD_LOGIC_VECTOR(31 downto 0);
P_index1 :out STD_LOGIC_VECTOR(31 downto 0);
P_index2 :out STD_LOGIC_VECTOR(31 downto 0);
P_intIn_index3 :out STD_LOGIC_VECTOR(31 downto 0);
P_floatIn :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity ANN_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of ap_return
-- bit 31~0 - ap_return[31:0] (Read)
-- 0x18 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of P_index1
-- bit 31~0 - P_index1[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of P_index2
-- bit 31~0 - P_index2[31:0] (Read/Write)
-- 0x2c : reserved
-- 0x30 : Data signal of P_intIn_index3
-- bit 31~0 - P_intIn_index3[31:0] (Read/Write)
-- 0x34 : reserved
-- 0x38 : Data signal of P_floatIn
-- bit 31~0 - P_floatIn[31:0] (Read/Write)
-- 0x3c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of ANN_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_AP_RETURN_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#18#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#1c#;
constant ADDR_P_INDEX1_DATA_0 : INTEGER := 16#20#;
constant ADDR_P_INDEX1_CTRL : INTEGER := 16#24#;
constant ADDR_P_INDEX2_DATA_0 : INTEGER := 16#28#;
constant ADDR_P_INDEX2_CTRL : INTEGER := 16#2c#;
constant ADDR_P_INTIN_INDEX3_DATA_0 : INTEGER := 16#30#;
constant ADDR_P_INTIN_INDEX3_CTRL : INTEGER := 16#34#;
constant ADDR_P_FLOATIN_DATA_0 : INTEGER := 16#38#;
constant ADDR_P_FLOATIN_CTRL : INTEGER := 16#3c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_ap_return : UNSIGNED(31 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
signal int_P_index1 : UNSIGNED(31 downto 0);
signal int_P_index2 : UNSIGNED(31 downto 0);
signal int_P_intIn_index3 : UNSIGNED(31 downto 0);
signal int_P_floatIn : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_AP_RETURN_0 =>
rdata_data <= RESIZE(int_ap_return(31 downto 0), 32);
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when ADDR_P_INDEX1_DATA_0 =>
rdata_data <= RESIZE(int_P_index1(31 downto 0), 32);
when ADDR_P_INDEX2_DATA_0 =>
rdata_data <= RESIZE(int_P_index2(31 downto 0), 32);
when ADDR_P_INTIN_INDEX3_DATA_0 =>
rdata_data <= RESIZE(int_P_intIn_index3(31 downto 0), 32);
when ADDR_P_FLOATIN_DATA_0 =>
rdata_data <= RESIZE(int_P_floatIn(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
P_index1 <= STD_LOGIC_VECTOR(int_P_index1);
P_index2 <= STD_LOGIC_VECTOR(int_P_index2);
P_intIn_index3 <= STD_LOGIC_VECTOR(int_P_intIn_index3);
P_floatIn <= STD_LOGIC_VECTOR(int_P_floatIn);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_return <= (others => '0');
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_return <= UNSIGNED(ap_return);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX1_DATA_0) then
int_P_index1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index1(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX2_DATA_0) then
int_P_index2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index2(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INTIN_INDEX3_DATA_0) then
int_P_intIn_index3(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_intIn_index3(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_FLOATIN_DATA_0) then
int_P_floatIn(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_floatIn(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/vhdl/ANN_AXILiteS_s_axi.vhd | 6 | 17016 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
ap_return :in STD_LOGIC_VECTOR(31 downto 0);
P_mode :out STD_LOGIC_VECTOR(31 downto 0);
P_index1 :out STD_LOGIC_VECTOR(31 downto 0);
P_index2 :out STD_LOGIC_VECTOR(31 downto 0);
P_intIn_index3 :out STD_LOGIC_VECTOR(31 downto 0);
P_floatIn :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity ANN_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of ap_return
-- bit 31~0 - ap_return[31:0] (Read)
-- 0x18 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of P_index1
-- bit 31~0 - P_index1[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of P_index2
-- bit 31~0 - P_index2[31:0] (Read/Write)
-- 0x2c : reserved
-- 0x30 : Data signal of P_intIn_index3
-- bit 31~0 - P_intIn_index3[31:0] (Read/Write)
-- 0x34 : reserved
-- 0x38 : Data signal of P_floatIn
-- bit 31~0 - P_floatIn[31:0] (Read/Write)
-- 0x3c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of ANN_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_AP_RETURN_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#18#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#1c#;
constant ADDR_P_INDEX1_DATA_0 : INTEGER := 16#20#;
constant ADDR_P_INDEX1_CTRL : INTEGER := 16#24#;
constant ADDR_P_INDEX2_DATA_0 : INTEGER := 16#28#;
constant ADDR_P_INDEX2_CTRL : INTEGER := 16#2c#;
constant ADDR_P_INTIN_INDEX3_DATA_0 : INTEGER := 16#30#;
constant ADDR_P_INTIN_INDEX3_CTRL : INTEGER := 16#34#;
constant ADDR_P_FLOATIN_DATA_0 : INTEGER := 16#38#;
constant ADDR_P_FLOATIN_CTRL : INTEGER := 16#3c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_ap_return : UNSIGNED(31 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
signal int_P_index1 : UNSIGNED(31 downto 0);
signal int_P_index2 : UNSIGNED(31 downto 0);
signal int_P_intIn_index3 : UNSIGNED(31 downto 0);
signal int_P_floatIn : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_AP_RETURN_0 =>
rdata_data <= RESIZE(int_ap_return(31 downto 0), 32);
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when ADDR_P_INDEX1_DATA_0 =>
rdata_data <= RESIZE(int_P_index1(31 downto 0), 32);
when ADDR_P_INDEX2_DATA_0 =>
rdata_data <= RESIZE(int_P_index2(31 downto 0), 32);
when ADDR_P_INTIN_INDEX3_DATA_0 =>
rdata_data <= RESIZE(int_P_intIn_index3(31 downto 0), 32);
when ADDR_P_FLOATIN_DATA_0 =>
rdata_data <= RESIZE(int_P_floatIn(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
P_index1 <= STD_LOGIC_VECTOR(int_P_index1);
P_index2 <= STD_LOGIC_VECTOR(int_P_index2);
P_intIn_index3 <= STD_LOGIC_VECTOR(int_P_intIn_index3);
P_floatIn <= STD_LOGIC_VECTOR(int_P_floatIn);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_return <= (others => '0');
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_return <= UNSIGNED(ap_return);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX1_DATA_0) then
int_P_index1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index1(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX2_DATA_0) then
int_P_index2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index2(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INTIN_INDEX3_DATA_0) then
int_P_intIn_index3(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_intIn_index3(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_FLOATIN_DATA_0) then
int_P_floatIn(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_floatIn(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register.vhd | 4 | 49418 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd | 4 | 51651 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | obsolete/MainMemorySpartan6.vhd | 1 | 4916 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:54:55 10/16/2016
-- Design Name:
-- Module Name: MainMemorySpartan6 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.util.all;
entity MainMemorySpartan6 is
generic (
NUMBANKS: natural:=1 -- number of RAM16B Banks, each Bank has 4*2K*8 BRAMS
);
Port ( DBOut : out STD_LOGIC_VECTOR (31 downto 0);
DBIn : in STD_LOGIC_VECTOR (31 downto 0);
AdrBus : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
ENA : in STD_LOGIC;
WREN : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
-- Second Port ( read only)
CLKB : in STD_LOGIC;
ENB : in STD_LOGIC;
AdrBusB : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
DBOutB : out STD_LOGIC_VECTOR (31 downto 0)
);
end MainMemorySpartan6;
architecture Behavioral of MainMemorySpartan6 is
subtype word is STD_LOGIC_VECTOR (31 downto 0);
type tBusMux is array (0 to NUMBANKS-1) of STD_LOGIC_VECTOR (31 downto 0);
signal ena_v,enb_v : std_logic_vector (NUMBANKS-1 downto 0);
signal upper_adr_a,upper_adr_b : std_logic_vector (log2(NUMBANKS)-1 downto 0);
signal BusMuxA,BusMuxB : tBusMux;
COMPONENT ram2048x8
PORT(
DInA : IN std_logic_vector(7 downto 0);
AdrA : IN std_logic_vector(10 downto 0);
ENA : IN std_logic;
WRENA : IN std_logic;
CLKA : IN std_logic;
AdrB : IN std_logic_vector(10 downto 0);
ENB : IN std_logic;
CLKB : IN std_logic;
DOutA : OUT std_logic_vector(7 downto 0);
DoutB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
upper_adr_a <= AdrBus(AdrBus'length-1 downto 11);
upper_adr_b <= AdrBusB(AdrBusB'length-1 downto 11);
genmem: for i in 0 to NUMBANKS-1 generate
begin
Inst_ram2048x8_0: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(7 downto 0),
DInA => DBIn(7 downto 0),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(0),
CLKA => clk,
DoutB => BusMuxB(i)(7 downto 0),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_1: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(15 downto 8),
DInA => DBIn(15 downto 8),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(1),
CLKA => clk,
DoutB => BusMuxB(i)(15 downto 8),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_2: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(23 downto 16),
DInA => DBIn(23 downto 16),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(2),
CLKA => clk,
DoutB => BusMuxB(i)(23 downto 16),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_3: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(31 downto 24),
DInA => DBIn(31 downto 24),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(3),
CLKA => clk,
DoutB => BusMuxB(i)(31 downto 24),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
end generate;
MuxA: process(upper_adr_a,ena,BusMuxA)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_a=CONV_STD_LOGIC_VECTOR(i,upper_adr_a'length) and ena='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxA(i)(k) and env(i));
end loop;
end loop;
ena_v<=env;
DBOut<=mux;
end process;
MuxB: process(upper_adr_b,enb,BusMuxB)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_b=CONV_STD_LOGIC_VECTOR(i,upper_adr_b'length) and enb='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxB(i)(k) and env(i));
end loop;
end loop;
enb_v<=env;
DBOutB<=mux;
end process;
end Behavioral;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | dram_arbiter.vhd | 1 | 4342 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Wed May 10 21:03:18 2017
--
-- Configuration:
-- Number of masters: 2
-- Number of slaves: 1
-- Master address width: 26
-- Slave address width: 26
-- Port size: 32
-- Port granularity: 8
-- Entity name: dram_arbiter
-- Pipelined arbiter: no
-- Registered feedback: yes
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e dram_arbiter -r 2 1 26 26 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dram_arbiter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_cti_i: in std_logic_vector(2 downto 0);
s0_bte_i: in std_logic_vector(1 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(25 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
s1_cyc_i: in std_logic;
s1_stb_i: in std_logic;
s1_we_i: in std_logic;
s1_sel_i: in std_logic_vector(3 downto 0);
s1_cti_i: in std_logic_vector(2 downto 0);
s1_bte_i: in std_logic_vector(1 downto 0);
s1_ack_o: out std_logic;
s1_adr_i: in std_logic_vector(25 downto 2);
s1_dat_i: in std_logic_vector(31 downto 0);
s1_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_cti_o: out std_logic_vector(2 downto 0);
m0_bte_o: out std_logic_vector(1 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(25 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of dram_arbiter is
signal request: std_logic_vector(1 downto 0);
signal grant_next: std_logic_vector(1 downto 0);
signal grant: std_logic_vector(1 downto 0);
signal grant_reg: std_logic_vector(1 downto 0):=(others=>'0');
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal cti_mux: std_logic_vector(2 downto 0);
signal bte_mux: std_logic_vector(1 downto 0);
signal adr_mux: std_logic_vector(25 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- ARBITER
-- Selects the active master. Masters with lower port numbers
-- have higher priority. Ongoing cycles are not interrupted.
request<=s1_cyc_i&s0_cyc_i;
grant_next<="01" when request(0)='1' else
"10" when request(1)='1' else
(others=>'0');
grant<=grant_reg when (request and grant_reg)/="00" else grant_next;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
grant_reg<=(others=>'0');
else
grant_reg<=grant;
end if;
end if;
end process;
-- MASTER->SLAVE MUX
cyc_mux<=(s0_cyc_i and grant(0)) or
(s1_cyc_i and grant(1));
stb_mux<=(s0_stb_i and grant(0)) or
(s1_stb_i and grant(1));
we_mux<=(s0_we_i and grant(0)) or
(s1_we_i and grant(1));
sel_mux_gen: for i in sel_mux'range generate
sel_mux(i)<=(s0_sel_i(i) and grant(0)) or
(s1_sel_i(i) and grant(1));
end generate;
cti_mux_gen: for i in cti_mux'range generate
cti_mux(i)<=(s0_cti_i(i) and grant(0)) or
(s1_cti_i(i) and grant(1));
end generate;
bte_mux_gen: for i in bte_mux'range generate
bte_mux(i)<=(s0_bte_i(i) and grant(0)) or
(s1_bte_i(i) and grant(1));
end generate;
adr_mux_gen: for i in adr_mux'range generate
adr_mux(i)<=(s0_adr_i(i) and grant(0)) or
(s1_adr_i(i) and grant(1));
end generate;
wdata_mux_gen: for i in wdata_mux'range generate
wdata_mux(i)<=(s0_dat_i(i) and grant(0)) or
(s1_dat_i(i) and grant(1));
end generate;
-- MASTER->SLAVE DEMUX
m0_cyc_o<=cyc_mux;
m0_stb_o<=stb_mux;
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_cti_o<=cti_mux;
m0_bte_o<=bte_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=m0_ack_i;
rdata_mux<=m0_dat_i;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux and grant(0);
s0_dat_o<=rdata_mux;
s1_ack_o<=ack_mux and grant(1);
s1_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reg_module.vhd | 4 | 87143 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_8.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_8.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_8.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_ST_WandB.vhd | 4 | 3121 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/ANN_dexp_64ns_64ns_64_18_full_dsp.vhd | 6 | 2769 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 9;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dexp_16_full_dsp_64_u : component ANN_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd | 4 | 59962 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_s2mm_dre;
use axi_datamover_v5_1_9.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_9.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/vhdl/feedforward_fpext_32ns_64_1.vhd | 4 | 1972 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fpext_32ns_64_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fpext_32ns_64_1 is
--------------------- Component ---------------------
component feedforward_ap_fpext_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fpext_0_no_dsp_32_u : component feedforward_ap_fpext_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/interrupt_control_v3_1/hdl/src/vhdl/interrupt_control.vhd | 4 | 57397 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SW_standalone/ipshared/xilinx.com/interrupt_control_v3_1/hdl/src/vhdl/interrupt_control.vhd | 4 | 57397 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| gpl-3.0 |
Rookfighter/aes-ss17 | ex01/freq_controller.vhd | 1 | 3567 | -- freq_controller.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- Component that allows to set blinking frequency from user input (buttons).
-- Uses sync_buffer component to debounce buttons signals. Button signals
-- are sampled with ~732Hz (24MHz / 2**15).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity freq_controller is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
freq: out std_logic_vector(2 downto 0)); -- frequency, 000 = stop, 111 = fast
end entity freq_controller;
architecture behavioral of freq_controller is
-- debounce buffer component for buttons
component sync_buffer is
generic(RSTDEF: std_logic);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
en: in std_logic; -- enable, high active
din: in std_logic; -- data bit, input
dout: out std_logic; -- data bit, output
redge: out std_logic; -- rising edge on din detected
fedge: out std_logic); -- falling edge on din detected
end component;
-- frequency divider by 2**CNTLEN
constant CNTLEN: natural := 15;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
signal cnt_tmp: std_logic_vector(CNTLEN downto 0) := (others => '0');
signal cnt_en: std_logic := '0';
-- if set, increment frequency
signal inc: std_logic := '0';
-- if set, decrement frequency
signal dec: std_logic := '0';
-- signal for internal freq computation
signal freq_tmp: std_logic_vector(2 downto 0) :=(others => '0');
begin
-- carry bit defines enable for sync_buffers
cnt_en <= cnt_tmp(CNTLEN);
cnt <= cnt_tmp(CNTLEN-1 downto 0);
-- connect freq out port with internal freq_tmp
freq <= freq_tmp;
process(rst, clk)
begin
if rst = RSTDEF then
cnt_tmp <= (others => '0');
freq_tmp <= (others => '0');
elsif rising_edge(clk) then
-- increment frequency divider
cnt_tmp <= '0' & cnt + 1;
if inc = '1' then
-- increment frequency, overflow not handled
-- just start at 0 again
freq_tmp <= freq_tmp + 1;
elsif dec = '1' then
-- decrement frequency, overflow not handled
-- just start at full freq again
freq_tmp <= freq_tmp - 1;
end if;
end if;
end process;
-- map rising edge (release button) of btn0 to inc
-- connect frequency divider carry to enable
sbuf0: sync_buffer
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => cnt_en,
din => btn0,
dout => open,
redge => inc,
fedge => open);
-- map rising edge (release button) of btn1 to dec
-- connect frequency divider carry to enable
sbuf1: sync_buffer
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => cnt_en,
din => btn1,
dout => open,
redge => dec,
fedge => open);
end architecture behavioral;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | uart/fifo.vhd | 1 | 3755 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| FIFO implementation with high water mark. Could be improved; currently |--
--| it is impossible to use the last byte in the FIFO (because it cannot |--
--| distinguish completely-full from completely-empty) |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo is
generic(
depth_log2 : integer := 10; -- 5 gives 32 bytes, implements without a BRAM.
hwm_space : integer := 5; -- minimum bytes free in buffer before we assert flow control signals
width : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
write_en : in std_logic;
write_ready : out std_logic; -- is there space to write?
read_en : in std_logic;
read_ready : out std_logic; -- is there data waiting to read?
data_in : in std_logic_vector(width-1 downto 0);
data_out : out std_logic_vector(width-1 downto 0);
high_water_mark : out std_logic;
-- Debug outputs
dbg_read_ptr : out std_logic_vector(depth_log2-1 downto 0);
dbg_write_ptr : out std_logic_vector(depth_log2-1 downto 0)
);
end fifo;
architecture behaviour of fifo is
type fifo_entry is array (natural range <>) of std_logic_vector(width-1 downto 0);
signal fifo_contents : fifo_entry(0 to (2 ** depth_log2) - 1); -- this is the FIFO buffer memory
signal read_ptr : unsigned(depth_log2-1 downto 0) := (others => '0');
signal write_ptr : unsigned(depth_log2-1 downto 0) := (others => '0');
signal full : std_logic;
signal empty : std_logic;
begin
dbg_read_ptr <= std_logic_vector(read_ptr);
dbg_write_ptr <= std_logic_vector(write_ptr);
is_empty: process(read_ptr, write_ptr)
begin
if read_ptr = write_ptr then
empty <= '1';
else
empty <= '0';
end if;
if read_ptr = (write_ptr+1) then
full <= '1';
else
full <= '0';
end if;
if (write_ptr - read_ptr) >= ((2 ** depth_log2) - 1 - hwm_space) then
high_water_mark <= '1';
else
high_water_mark <= '0';
end if;
end process;
fifo_update: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset
read_ptr <= to_unsigned(0, depth_log2);
write_ptr <= to_unsigned(0, depth_log2);
else
-- normal operation
if write_en = '1' and full = '0' then
fifo_contents(to_integer(write_ptr)) <= data_in;
write_ptr <= write_ptr + 1;
end if;
if read_en = '1' and empty = '0' then
read_ptr <= read_ptr + 1;
end if;
data_out <= fifo_contents(to_integer(read_ptr));
end if;
end if;
end process;
write_ready <= not full;
read_ready <= not empty;
end;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 24 | 142613 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/8b10_dec_wrap.vhd | 4 | 4249 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
| gpl-3.0 |
rkrajnc/minimig-mist | rtl/tg68k/TG68K_ALU.vhd | 1 | 36854 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use IEEE.numeric_std.ALL;
use work.TG68K_Pack.ALL;
entity TG68K_ALU is
generic (
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port (
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic := '1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_width : in std_logic_vector(4 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
bf_offset : in std_logic_vector(31 downto 0);
set_V_Flag_out : out bit;
Flags_out : out std_logic_vector(7 downto 0);
c_out_out : out std_logic_vector(2 downto 0);
addsub_q_out : out std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU IS
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : BIT;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal pack_out : std_logic_vector(15 downto 0);
signal pack_a : std_logic_vector(15 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : BIT;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_loff_dir : std_logic_vector(4 downto 0);
signal bf_set2 : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_extu : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal index : std_logic_vector(4 downto 0);
signal bf_flag_z : std_logic;
signal bf_flag_n : std_logic;
signal set_V_Flag : BIT;
signal Flags : std_logic_vector(7 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
process (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
pack_out, bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_offset, bf_width,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
begin
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
if exec(opcBFwb) = '1' then
ALUout <= result(31 downto 0);
if bf_fffo = '1' then
ALUout <= bf_offset + bf_width + 1 - bf_firstbit;
end if;
end if;
OP1in <= addsub_q;
if exec(opcABCD) = '1' then
OP1in(7 downto 0) <= bcd_a(7 downto 0);
elsif exec(opcSBCD) = '1' then
OP1in(7 downto 0) <= bcd_s(7 downto 0);
elsif exec(opcMULU) = '1' and MUL_Mode /= 3 then
if exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then
OP1in <= result_mulu(31 downto 0);
else
OP1in <= result_mulu(63 downto 32);
end if;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
-- if exe_opcode(15)='1' then
OP1in <= result_div(47 downto 32) & result_div(15 downto 0);
else --64bit
if exec(write_reminder) = '1' then
OP1in <= result_div(63 downto 32);
else
OP1in <= result_div(31 downto 0);
end if;
end if;
elsif exec(opcOR) = '1' then
OP1in <= OP2out OR OP1out;
elsif exec(opcand) = '1' then
OP1in <= OP2out and OP1out;
elsif exec(opcScc) = '1' then
OP1in(7 downto 0) <= (others => exe_condition);
elsif exec(opcEOR) = '1' then
OP1in <= OP2out xor OP1out;
elsif exec(opcMOVE) = '1' OR exec(exg) = '1' then
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
elsif exec(opcROT) = '1' then
OP1in <= rot_out;
elsif exec(opcSWAP) = '1' then
OP1in <= OP1out(15 downto 0) & OP1out(31 downto 16);
elsif exec(opcBITS) = '1' then
OP1in <= bits_out;
elsif exec(opcBF) = '1' then
OP1in <= bf_datareg;
elsif exec(opcMOVECCR) = '1' then
OP1in(15 downto 8) <= "00000000";
OP1in( 7 downto 0) <= Flags;
elsif exec(opcMOVESR) = '1' then
OP1in(15 downto 8) <= FlagsSR;
OP1in( 7 downto 0) <= Flags;
elsif exec(opcPACK) = '1' then
OP1in(15 downto 0) <= pack_out;
end if;
end process;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
process (OP1out, OP2out, execOPC, datatype, Flags, long_start, non_aligned, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
begin
addsub_a <= OP1out;
if exec(get_bfoffset) = '1' then
if sndOPC(11) = '1' then
addsub_a <= OP1out(31) & OP1out(31) & OP1out(31) & OP1out(31 downto 3);
else
addsub_a <= "000000000000000000000000000000" & sndOPC(10 downto 9);
end if;
end if;
if exec(subidx) = '1' then
opaddsub <= '1';
else
opaddsub <= '0';
end if;
c_in(0) <= '0';
addsub_b <= OP2out;
if execOPC = '0' and exec(OP2out_one) = '0' and exec(get_bfoffset) = '0' then
if long_start = '0' and datatype = "00" and exec(use_SP) = '0' then
addsub_b <= "00000000000000000000000000000001";
elsif long_start = '0' and exe_datatype = "10" and (exec(presub) OR exec(postadd) OR movem_presub) = '1' then
if exec(movem_action) = '1' then -- used for initial offset / aligned case
addsub_b <= "00000000000000000000000000000110";
else
addsub_b <= "00000000000000000000000000000100";
end if;
else
addsub_b <= "00000000000000000000000000000010";
end if;
else
if (exec(use_XZFlag) = '1' and Flags(4) = '1') OR exec(opcCHK) = '1' then
c_in(0) <= '1';
end if;
opaddsub <= exec(addsub);
end if;
-- patch for un-aligned movem
if (exec(movem_action) = '1') then
if (movem_presub = '0') then -- up
if (non_aligned = '1') and (long_start = '0') then -- hold
addsub_b <= (others => '0');
end if;
else
if (non_aligned = '1') and (long_start = '0') then
if (exe_datatype = "10") then
addsub_b <= "00000000000000000000000000001000";
else
addsub_b <= "00000000000000000000000000000100";
end if;
end if;
end if;
end if;
if opaddsub = '0' OR long_start = '1' then --ADD
notaddsub_b <= '0' & addsub_b & c_in(0);
else --SUB
notaddsub_b <= not ('0' & addsub_b & c_in(0));
end if;
add_result <= (('0' & addsub_a & notaddsub_b(0)) + notaddsub_b);
c_in(1) <= add_result(9) xor addsub_a(8) xor addsub_b(8);
c_in(2) <= add_result(17) xor addsub_a(16) xor addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) xor add_result(8) xor addsub_a(7) xor addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) xor add_result(16) xor addsub_a(15) xor addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) xor add_result(32) xor addsub_a(31) xor addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
end process;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
process (OP1out, OP2out, pack_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
begin
if exe_opcode(7 downto 6) = "01" then
-- PACK
pack_a <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(OP2out(15 downto 0)));
pack_out <= "00000000" & pack_a(11 downto 8) & pack_a(3 downto 0);
else
-- UNPK
pack_a <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
pack_out <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(pack_a));
end if;
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc & (niba_h(4 downto 1) + ('0', niba_hc, niba_hc, '0')) & (niba_l(4 downto 1) + ('0', niba_lc, niba_lc, '0'));
niba_l <= ('0' & OP1out(3 downto 0) & '1') + ('0' & OP2out(3 downto 0) & Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) and niba_l(3)) OR (niba_l(4) and niba_l(2));
niba_h <= ('0' & OP1out(7 downto 4) & '1') + ('0' & OP2out(7 downto 4) & niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) and niba_h(3)) OR (niba_h(4) and niba_h(2));
--SBC
bcd_s <= nibs_hc & (nibs_h(4 downto 1) - ('0', nibs_hc, nibs_hc, '0')) & (nibs_l(4 downto 1) - ('0', nibs_lc, nibs_lc, '0'));
nibs_l <= ('0' & OP1out(3 downto 0) & '0') - ('0' & OP2out(3 downto 0) & Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0' & OP1out(7 downto 4) & '0') - ('0' & OP2out(7 downto 4) & nibs_lc);
nibs_hc <= nibs_h(5);
end process;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
process (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC, reg_QB)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bchg <= '0';
bset <= '0';
case opcode(7 downto 6) IS
when "01" => --bchg
bchg <= '1';
when "11" => --bset
bset <= '1';
when others => NULL;
end case;
end if;
end if;
if exe_opcode(8) = '0' then
if exe_opcode(5 downto 4) = "00" then
bit_number <= sndOPC(4 downto 0);
else
bit_number <= "00" & sndOPC(2 downto 0);
end if;
else
if exe_opcode(5 downto 4) = "00" then
bit_number <= reg_QB(4 downto 0);
else
bit_number <= "00" & reg_QB(2 downto 0);
end if;
end if;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg and not one_bit_in) OR bset;
end process;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
-- Bitfields can have up to four (register) operands, e.g. bfins d0,d1{d2,d3}
-- the width an offset operands are evaluated while the second opcode word is
-- evaluated. These values are latched, so the two other registers can be read
-- in the next cycle while the ALU is working since the tg68k can only read
-- from two registers at once.
--
-- All bitfield operations can operate on registers or memory. There are
-- two fundamental differences which make the shifters quite complex:
-- 1. Memory content is delivered byte aligned to the ALU. Thus all shifting
-- is 7 bits far at most. Registers are 32 bit in size and may require
-- shifting of up to 31 bit positions
-- 2. Memory operations can affect 5 bytes. Thus all shifting is 40 bit in that
-- case. Registers are 32 bit in size and bitfield operations wrap. Shifts
-- are actually rotations for that reason
--
-- The destination operand is transfered via op1out and bf_ext into the ALU.
--
-- bftst, bfset, bfclr and bfchg
--------------------------------
-- bftst, bfset, bfclr and bfchg work very similar. A "sign" vector is generated
-- having "width" right aligned 0-bits and the rest ones.
-- A "copy" vector is generated from this by shifting through copymux so
-- this contains a 1 for all bits in bf_ext_in & op1out that will not be
-- affected by the operation.
-- The result vector is either all 1's (bfset), all 0's(bfclr) or the inverse
-- of bf_ext_in & op1out. Those bits in result that have a 1 in the copy
-- vector are overwritten with the original value from bf_ext_in & op1out
-- The result is returned through bf_ext_out and ALUout
--
-- These instructions only calculate the Z and N flags. Both are derived
-- directly from bf_ext_in & op1out with the help of the copy vector and
-- the offset/width fields. Thus Z and N are set from the previous contents
-- of the bitfield.
--
-- bfins
--------
-- bfins reuses most of the functionality of bfset, bfclr and bfchg. But it
-- has another 32 bit parameter that's being used for the source. This is passed
-- to the ALU via op2out. This is moved to the shift register and shifted
-- bf_shift bits to the right.
-- The input valus is also store in datareg and the lowest "width" bits
-- are masked. This is then forwarded to op1in which in turn uses the normal
-- mechanisms to generate the flags. A special bf_NFlag is also generated
-- from this. Z and N are set from these and not from the previous bitfield
-- contents as with bfset, bfclr or bfchg
--
-- bfextu/bfexts
----------------
-- bfexts and bfextu use the same shifter that is used by bfins to shift the
-- data to be inserted. It's using that same shifter to shift data in the
-- opposite direction. Flags are set from the extraced data
--
-- bfffo
--------
-- bfffo uses the same data path as bfext. But instead of directly returning
-- the extracted data it determines the highest bit setin the result
process (clk, bf_ins, bf_bchg, bf_bset, bf_exts, bf_extu, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
datareg, bf_NFlag, result, reg_QB, sign, bf_d32, copy, bf_loffset, bf_width)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_extu <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
case opcode(10 downto 8) IS
when "010" => bf_bchg <= '1'; --BFCHG
when "011" => bf_exts <= '1'; --BFEXTS
when "001" => bf_extu <= '1'; --BFEXTU
-- when "100" => insert <= (others =>'0'); --BFCLR
when "101" => bf_fffo <= '1'; --BFFFO
when "110" => bf_bset <= '1'; --BFSET
when "111" => bf_ins <= '1'; --BFinS
when others => NULL;
end case;
-- ea is a register
if opcode(4 downto 3) = "00" then
bf_d32 <= '1';
end if;
bf_ext_out <= result(39 downto 32);
end if;
end if;
------------- BF_SET2 --------------
if bf_ins = '1' then
bf_loff_dir <= 32 - bf_loffset;
else
bf_loff_dir <= bf_loffset;
end if;
if bf_d32 = '1' then
-- 32bit: rotate 0..31 bits left or right, don't care for upper 8 bits
bf_set2 <= "--------" & std_logic_vector(unsigned(OP2out) ror to_integer(unsigned(bf_loff_dir)));
else
if bf_ins = '1' then
-- 40 bit: shift 0..7 bits left
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) sll to_integer(unsigned(bf_loffset(2 downto 0))));
else
-- 40 bit: shift 0..7 bits right
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) srl to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
end if;
------------- COPY --------------
if bf_d32 = '1' then
-- 32bit: rotate 32 bits 0..31 bits left, don't care for upper 8 bits
copy <= "--------" & std_logic_vector(unsigned(sign) rol to_integer(unsigned(bf_loffset)));
else
-- 40 bit: shift 40 bits 0..7 bits left, fill with '1's (hence the two not's)
copy <= not std_logic_vector(unsigned(x"00" & (not sign)) sll to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
if bf_ins = '1' then
datareg <= reg_QB;
else
datareg <= bf_set2(31 downto 0);
end if;
-- do the bitfield operation itself
if bf_ins = '1' then
result <= bf_set2;
elsif bf_bchg = '1' then
result <= not (bf_ext_in & OP1out);
elsif bf_bset = '1' then
result <= (others => '1');
else
result <= (others => '0');
end if;
sign <= (others => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
for i in 0 TO 31 loop
if i > bf_width then
datareg(i) <= '0';
sign(i) <= '1';
end if;
end loop;
-- Set bits 32..39 to 0 if operating on register to make sure
-- zero flag calculation over all 40 bits works correctly
result_tmp(31 downto 0) <= OP1out;
if bf_d32 = '1' then
result_tmp(39 downto 32) <= "00000000";
else
result_tmp(39 downto 32) <= bf_ext_in;
end if;
bf_flag_z <= '1';
if bf_d32 = '0' then
-- The test for this overflow shouldn't be needed. But GHDL complains
-- otherwise.
if(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)) > 39) then
bf_flag_n <= result_tmp(39);
else
bf_flag_n <= result_tmp(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)));
end if;
else
--TH: TODO: check if this really does what it's supposed to
bf_flag_n <= result_tmp(to_integer(unsigned(bf_loffset)+unsigned(bf_width)));
end if;
for i in 0 TO 39 loop
if copy(i) = '1' then
result(i) <= result_tmp(i);
elsif result_tmp(i) = '1' then
bf_flag_z <= '0';
end if;
end loop;
if bf_exts = '1' and bf_NFlag = '1' then
bf_datareg <= datareg OR sign;
else
bf_datareg <= datareg;
end if;
--BFFFO
if datareg(31) = '1' then bf_firstbit <= "100000";
elsif datareg(30) = '1' then bf_firstbit <= "011111";
elsif datareg(29) = '1' then bf_firstbit <= "011110";
elsif datareg(28) = '1' then bf_firstbit <= "011101";
elsif datareg(27) = '1' then bf_firstbit <= "011100";
elsif datareg(26) = '1' then bf_firstbit <= "011011";
elsif datareg(25) = '1' then bf_firstbit <= "011010";
elsif datareg(24) = '1' then bf_firstbit <= "011001";
elsif datareg(23) = '1' then bf_firstbit <= "011000";
elsif datareg(22) = '1' then bf_firstbit <= "010111";
elsif datareg(21) = '1' then bf_firstbit <= "010110";
elsif datareg(20) = '1' then bf_firstbit <= "010101";
elsif datareg(19) = '1' then bf_firstbit <= "010100";
elsif datareg(18) = '1' then bf_firstbit <= "010011";
elsif datareg(17) = '1' then bf_firstbit <= "010010";
elsif datareg(16) = '1' then bf_firstbit <= "010001";
elsif datareg(15) = '1' then bf_firstbit <= "010000";
elsif datareg(14) = '1' then bf_firstbit <= "001111";
elsif datareg(13) = '1' then bf_firstbit <= "001110";
elsif datareg(12) = '1' then bf_firstbit <= "001101";
elsif datareg(11) = '1' then bf_firstbit <= "001100";
elsif datareg(10) = '1' then bf_firstbit <= "001011";
elsif datareg(9) = '1' then bf_firstbit <= "001010";
elsif datareg(8) = '1' then bf_firstbit <= "001001";
elsif datareg(7) = '1' then bf_firstbit <= "001000";
elsif datareg(6) = '1' then bf_firstbit <= "000111";
elsif datareg(5) = '1' then bf_firstbit <= "000110";
elsif datareg(4) = '1' then bf_firstbit <= "000101";
elsif datareg(3) = '1' then bf_firstbit <= "000100";
elsif datareg(2) = '1' then bf_firstbit <= "000011";
elsif datareg(1) = '1' then bf_firstbit <= "000010";
elsif datareg(0) = '1' then bf_firstbit <= "000001";
else bf_firstbit <= "000000";
end if;
end process;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
process (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
begin
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_rot <= OP1out(7);
when "01" | "11" => --Word
rot_rot <= OP1out(15);
when "10" => --Long
rot_rot <= OP1out(31);
when others => NULL;
end case;
case rot_bits IS
when "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
when "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
when "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
when "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
when others => NULL;
end case;
if exec(rot_nop) = '1' then
rot_out <= OP1out;
rot_X <= Flags(4);
if rot_bits = "10" then --ROXL, ROXR
rot_C <= Flags(4);
else
rot_C <= '0';
end if;
else
if exe_opcode(8) = '1' then --left
rot_out <= OP1out(30 downto 0) & rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
else --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb & OP1out(31 downto 1);
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_out(7) <= rot_msb;
when "01" | "11" => --Word
rot_out(15) <= rot_msb;
when others => NULL;
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
process (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1in, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
begin
if exec(andiSR) = '1' then
CCRin <= Flags and last_data_read(7 downto 0);
elsif exec(eoriSR) = '1' then
CCRin <= Flags xor last_data_read(7 downto 0);
elsif exec(oriSR) = '1' then
CCRin <= Flags OR last_data_read(7 downto 0);
else
CCRin <= OP2out(7 downto 0);
end if;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
if exec(use_XZFlag) = '1' and flags(2) = '0' then
flag_z <= "000";
elsif OP1in(7 downto 0) = "00000000" then
flag_z(0) <= '1';
if OP1in(15 downto 8) = "00000000" then
flag_z(1) <= '1';
if OP1in(31 downto 16) = "0000000000000000" then
flag_z(2) <= '1';
end if;
end if;
end if;
-- --Flags NZVC
if exe_datatype = "00" then --Byte
set_flags <= OP1in(7) & flag_z(0) & addsub_ofl(0) & c_out(0);
if exec(opcABCD) = '1' then
set_flags(0) <= bcd_a(8);
elsif exec(opcSBCD) = '1' then
set_flags(0) <= bcd_s(8);
end if;
elsif exe_datatype = "10" OR exec(opcCPMAW) = '1' then --Long
set_flags <= OP1in(31) & flag_z(2) & addsub_ofl(2) & c_out(2);
else --Word
set_flags <= OP1in(15) & flag_z(1) & addsub_ofl(1) & c_out(1);
end if;
if rising_edge(clk) then
if clkena_lw = '1' then
if exec(directSR) = '1' OR set_stop = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(directCCR) = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(opcROT) = '1' then
asl_VFlag <= ((set_flags(3) xor rot_rot) OR asl_VFlag);
else
asl_VFlag <= '0';
end if;
if exec(to_CCR) = '1' then
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
elsif Z_error = '1' then
if exe_opcode(8) = '0' then
Flags(3 downto 0) <= reg_QA(31) & "000";
else
Flags(3 downto 0) <= "0100";
end if;
elsif exec(no_Flags) = '0' then
if exec(opcADD) = '1' then
Flags(4) <= set_flags(0);
elsif exec(opcROT) = '1' and rot_bits /= "11" and exec(rot_nop) = '0' then
Flags(4) <= rot_X;
end if;
if (exec(opcADD) OR exec(opcCMP)) = '1' then
Flags(3 downto 0) <= set_flags;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if V_Flag = '1' then
Flags(3 downto 0) <= "1010";
else
Flags(3 downto 0) <= OP1in(15) & flag_z(1) & "00";
end if;
elsif exec(write_reminder) = '1' and MUL_Mode /= 3 then -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) and Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
elsif exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
elsif exec(opcOR) = '1' OR exec(opcand) = '1' OR exec(opcEOR) = '1' OR exec(opcMOVE) = '1' OR exec(opcMOVEQ) = '1' OR exec(opcSWAP) = '1' OR exec(opcBF) = '1' OR (exec(opcMULU) = '1' and MUL_Mode /= 3) then
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
if exec(opcBF) = '1' then
-- flags(2) has correctly been set from set_flags
Flags(3) <= bf_NFlag;
--TH TODO: check flag handling of fffo
-- "normal" flags are taken from op2in
if bf_fffo = '0' and bf_extu='0' and bf_exts='0' and bf_ins='0' then
Flags(2) <= bf_flag_z;
Flags(3) <= bf_flag_n;
end if;
end if;
elsif exec(opcROT) = '1' then
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
if rot_bits = "00" and ((set_flags(3) xor rot_rot) OR asl_VFlag) = '1' then --ASL/ASR
Flags(1) <= '1';
else
Flags(1) <= '0';
end if;
elsif exec(opcBITS) = '1' then
Flags(2) <= not one_bit_in;
elsif exec(opcCHK) = '1' then
if exe_datatype = "01" then --Word
Flags(3) <= OP1out(15);
else
Flags(3) <= OP1out(31);
end if;
if OP1out(15 downto 0) = X"0000" and (exe_datatype = "01" OR OP1out(31 downto 16) = X"0000") then
Flags(2) <= '1';
else
Flags(2) <= '0';
end if;
Flags(1 downto 0) <= "00";
end if;
end if;
end if;
Flags(7 downto 5) <= "000";
end if;
end process;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
process (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
begin
if (signedOP = '1' and faktorB(31) = '1') OR FAsign = '1' then
muls_msb <= mulu_reg(63);
else
muls_msb <= '0';
end if;
if signedOP = '1' and faktorB(31) = '1' then
mulu_sign <= '1';
else
mulu_sign <= '0';
end if;
if MUL_Mode = 0 then -- 16 Bit
result_mulu(63 downto 32) <= muls_msb & mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X' & mulu_reg(15 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) - (mulu_sign & faktorB(31 downto 16)));
else
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) + (mulu_sign & faktorB(31 downto 16)));
end if;
end if;
else -- 32 Bit
result_mulu <= muls_msb & mulu_reg(63 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) - (mulu_sign & faktorB));
else
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) + (mulu_sign & faktorB));
end if;
end if;
end if;
if exe_opcode(15) = '1' OR MUL_Mode = 0 then
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (others => '0');
else
faktorB <= OP2out;
end if;
if (result_mulu(63 downto 32) = X"00000000" and (signedOP = '0' OR result_mulu(31) = '0')) OR
(result_mulu(63 downto 32) = X"FFFFFFFF" and signedOP = '1' and result_mulu(31) = '1') then
set_mV_Flag <= '0';
else
set_mV_Flag <= '1';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
if micro_state = mul1 then
mulu_reg(63 downto 32) <= (others => '0');
if divs = '1' and ((exe_opcode(15) = '1' and reg_QA(15) = '1') OR (exe_opcode(15) = '0' and reg_QA(31) = '1')) then --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0 - reg_QA;
else
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
end if;
elsif exec(opcMULU) = '0' then
mulu_reg <= result_mulu;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
process (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
begin
divs <= (opcode(15) and opcode(8)) OR (not opcode(15) and sndOPC(11));
divisor(15 downto 0) <= (others => '0');
divisor(63 downto 32) <= (others => divs and reg_QA(31));
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
divisor(47 downto 16) <= reg_QA;
else
divisor(31 downto 0) <= reg_QA;
if exe_opcode(14) = '1' and sndOPC(10) = '1' then
divisor(63 downto 32) <= reg_QB;
end if;
end if;
if signedOP = '1' OR opcode(15) = '0' then
OP2outext <= OP2out(31 downto 16);
else
OP2outext <= (others => '0');
end if;
if signedOP = '1' and OP2out(31) = '1' then
div_sub <= (div_reg(63 downto 31)) + ('1' & OP2out(31 downto 0));
else
div_sub <= (div_reg(63 downto 31)) - ('0' & OP2outext(15 downto 0) & OP2out(15 downto 0));
end if;
if DIV_Mode = 0 then
div_bit <= div_sub(16);
else
div_bit <= div_sub(32);
end if;
if div_bit = '1' then
div_quot(63 downto 32) <= div_reg(62 downto 31);
else
div_quot(63 downto 32) <= div_sub(31 downto 0);
end if;
div_quot(31 downto 0) <= div_reg(30 downto 0) & not div_bit;
if ((nozero = '1' and signedOP = '1' and (OP2out(31) xor OP1_sign xor div_neg xor div_qsign) = '1' ) --Overflow DIVS
OR (signedOP = '0' and div_over(32) = '0')) and DIV_Mode /= 3 then --Overflow DIVU
set_V_Flag <= '1';
else
set_V_Flag <= '0';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
V_Flag <= set_V_Flag;
signedOP <= divs;
if micro_state = div1 then
nozero <= '0';
if divs = '1' and divisor(63) = '1' then -- Neg divisor
OP1_sign <= '1';
div_reg <= 0 - divisor;
else
OP1_sign <= '0';
div_reg <= divisor;
end if;
else
div_reg <= div_quot;
nozero <= not div_bit OR nozero;
end if;
if micro_state = div2 then
div_qsign <= not div_bit;
div_neg <= signedOP and (OP2out(31) xor OP1_sign);
if DIV_Mode = 0 then
div_over(32 downto 16) <= ('0' & div_reg(47 downto 32)) - ('0' & OP2out(15 downto 0));
else
div_over <= ('0' & div_reg(63 downto 32)) - ('0' & OP2out);
end if;
end if;
if exec(write_reminder) = '0' then
-- if exec_DIVU='0' then
if div_neg = '1' then
result_div(31 downto 0) <= 0 - div_quot(31 downto 0);
else
result_div(31 downto 0) <= div_quot(31 downto 0);
end if;
if OP1_sign = '1' then
result_div(63 downto 32) <= 0 - div_quot(63 downto 32);
else
result_div(63 downto 32) <= div_quot(63 downto 32);
end if;
end if;
end if;
end if;
end process;
set_V_Flag_out <= set_V_Flag;
Flags_out <= Flags;
c_out_out <= c_out;
addsub_q_out <= addsub_q;
end;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_OUT8_ENC8b10b.vhd | 2 | 6773 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT8_ENC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT8 module
entity EPROC_OUT8_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(7 downto 0) -- ready on every bitCLK
);
end EPROC_OUT8_ENC8b10b;
architecture Behavioral of EPROC_OUT8_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros8bit : std_logic_vector (7 downto 0) := (others=>'0');
signal enc10bit, enc10bit0, enc10bit1, enc10bit2, enc10bit3 : std_logic_vector (9 downto 0);
signal enc10bit_x4_r : std_logic_vector (39 downto 0) := (others=>'0');
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out, enc10bitRdy : std_logic;
signal word_cnt : std_logic_vector (1 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs, request is 2 clks wide, 2 bytes at a time
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then -- meaning request_cycle_cnt = "100"
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>4) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig; -- slow clock output trigger
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit,
encDataOutrdy => enc10bitRdy
);
-------------------------------------------------------------------------------------------
-- sending out 8 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
word_cnt <= word_cnt + 1;
else
word_cnt <= (others=>'0');
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
if word_cnt = "00" then
enc10bit0 <= enc10bit;
elsif word_cnt = "01" then
enc10bit1 <= enc10bit;
elsif word_cnt = "10" then
enc10bit2 <= enc10bit;
elsif word_cnt = "11" then
enc10bit3 <= enc10bit;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- slow clock logic
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_x4_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_x4_r <= enc10bit3 & enc10bit2 & enc10bit1 & enc10bit0;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>8)
port map (
data0 => enc10bit_x4_r(7 downto 0),
data1 => enc10bit_x4_r(15 downto 8),
data2 => enc10bit_x4_r(23 downto 16),
data3 => enc10bit_x4_r(31 downto 24),
data4 => enc10bit_x4_r(39 downto 32),
data5 => zeros8bit,
data6 => zeros8bit,
data7 => zeros8bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPATH_FIFO_WRAP.vhd | 3 | 2753 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
--! EPATH FIFO 16 bit wide, 1K deep
entity EPATH_FIFO_WRAP is
port (
rst : in std_logic;
fifoFlush : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
almost_full : out std_logic;
prog_full : out std_logic
);
end EPATH_FIFO_WRAP;
architecture Behavioral of EPATH_FIFO_WRAP is
----------------------------------
----------------------------------
component EPATH_FIFO -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic;
prog_empty : out std_logic;
prog_empty_thresh : in std_logic_vector(9 downto 0);
prog_full_thresh : in std_logic_vector(9 downto 0)
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, wr_en_s : std_logic;
signal prog_full_s, full_s, empty_s, prog_empty_s : std_logic;
signal rst_state : std_logic;
begin
--
rd_en_s <= rd_en and (not rst_state);
wr_en_s <= wr_en and (not rst_state);
--
EPATH_FIFO_INST: EPATH_FIFO
PORT MAP (
wr_clk => wr_clk,
wr_rst => fifoFlush,
rd_clk => rd_clk,
rd_rst => fifoFlush,
din => din,
wr_en => wr_en_s,
rd_en => rd_en_s,
dout => dout,
full => full_s,
empty => empty_s,
prog_full => prog_full_s,
prog_empty => prog_empty_s,
prog_full_thresh => std_logic_vector(to_unsigned(512, 10)),
prog_empty_thresh => std_logic_vector(to_unsigned(1010, 10))
);
--
rst_state <= rst or (full_s and empty_s);
--
process(rd_clk)
begin
if rising_edge(rd_clk) then
prog_full <= prog_full_s and (not rst_state);
end if;
end process;
--
process(wr_clk)
begin
if rising_edge(wr_clk) then
almost_full <= not prog_empty_s;
end if;
end process;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN8_DEC8b10b.vhd | 2 | 10753 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN8 module
entity EPROC_IN8_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (7 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8_DEC8b10b;
architecture Behavioral of EPROC_IN8_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (47 downto 0) := (others=>'0'); -- 48 bit (8 x 5 = 40, plus 8 more)
signal word10bx4_align_array, word10bx4_align_array_r : word10b_4array_8array_type;
signal word10b_array, word10b_array_s : word10b_4array_type;
signal isk_array : isk_4array_type;
signal comma_valid_bits_or, word10bx4_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1, realignment_ena : std_logic;
signal align_select : std_logic_vector (2 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (7 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 48 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(47 downto 8);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 7 generate -- 4 10bit-words per alignment, 8 possible alignments
--word10bx4_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx4_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(2) <= EDATAbitstreamSREG((I+29) downto (I+20)); -- 3rd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(3) <= EDATAbitstreamSREG((I+39) downto (I+30)); -- 4th 10 bit word, alligned to bit I
word10bx4_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx4_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
word10bx4_align_array(I)(2) <= EDATAbitstreamSREG(I+20)&EDATAbitstreamSREG(I+21)&EDATAbitstreamSREG(I+22)&EDATAbitstreamSREG(I+23)&EDATAbitstreamSREG(I+24)&
EDATAbitstreamSREG(I+25)&EDATAbitstreamSREG(I+26)&EDATAbitstreamSREG(I+27)&EDATAbitstreamSREG(I+28)&EDATAbitstreamSREG(I+29); -- 3rd 10 bit word, alligned to bit I
word10bx4_align_array(I)(3) <= EDATAbitstreamSREG(I+30)&EDATAbitstreamSREG(I+31)&EDATAbitstreamSREG(I+32)&EDATAbitstreamSREG(I+33)&EDATAbitstreamSREG(I+34)&
EDATAbitstreamSREG(I+35)&EDATAbitstreamSREG(I+36)&EDATAbitstreamSREG(I+37)&EDATAbitstreamSREG(I+38)&EDATAbitstreamSREG(I+39); -- 4th 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 7 generate -- 4 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx4_align_array(I)(0) = COMMAp or word10bx4_align_array(I)(0) = COMMAn) and
(word10bx4_align_array(I)(1) = COMMAp or word10bx4_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(7) or comma_valid_bits(6) or comma_valid_bits(5) or comma_valid_bits(4) or
comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx4_align_array_r <= word10bx4_align_array;
end if;
end process;
--
word10bx4_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3) or ( (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (
comma_valid_bits(5) or ( (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (
comma_valid_bits(7)
)))))));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
((comma_valid_bits(2) or comma_valid_bits(3)) or (
(not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (
comma_valid_bits(6) or comma_valid_bits(7))));
align_select(2) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3)) and
(comma_valid_bits(4) or comma_valid_bits(5) or comma_valid_bits(6) or comma_valid_bits(7));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx4_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "000" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx4_align_array_r(0);
when "001" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx4_align_array_r(1);
when "010" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx4_align_array_r(2);
when "011" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx4_align_array_r(3);
when "100" => -- bit4 word got comma => align to bit4
word10b_array <= word10bx4_align_array_r(4);
when "101" => -- bit5 word got comma => align to bit5
word10b_array <= word10bx4_align_array_r(5);
when "110" => -- bit6 word got comma => align to bit6
word10b_array <= word10bx4_align_array_r(6);
when "111" => -- bit7 word got comma => align to bit7
word10b_array <= word10bx4_align_array_r(7);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 3 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-- if more that 2 commas, will repeat itself next clock
realignment_ena <= '0' when (isk_array(0) = "11" and isk_array(1) = "11" and isk_array(2) = "11") else '1';
word10b_array_rdy_s1 <= word10b_array_rdy_s and realignment_ena;
-------------------------------------------------------------------------------------------
-- 4 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN8_ALIGN_BLOCK_inst: entity work.EPROC_IN8_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/upstreamEpathFifoWrap.vhd | 3 | 6159 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 23/06/2015
--! Module Name: upstreamEpathFifoWrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.all;
--! EPATH FIFO 18 bit wide, 1K deep
entity upstreamEpathFifoWrap is
port (
rst : in std_logic;
fifoFLUSH : in std_logic;
---
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(17 downto 0);
---
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(9 downto 0);
doutRdy : out std_logic;
---
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end upstreamEpathFifoWrap;
architecture Behavioral of upstreamEpathFifoWrap is
----------------------------------
----------------------------------
component fh_epath_fifo2K_18bit_wide -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(17 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(17 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, empty_efifo, prog_full_s : std_logic;
signal OE, rst_state, byte_cnt,byte_mux_sel,byte_rdy,rd_en1,rd_en2 : std_logic := '0';
signal dout18bit : std_logic_vector(17 downto 0);
signal byte0, byte1 : std_logic_vector(9 downto 0) := "1100000000";
constant comma_byte : std_logic_vector(9 downto 0) := "1100000000";
signal byte0_code,byte1_code,word16_code : std_logic_vector(1 downto 0);
signal empty_efifo1,empty_efifo2,empty_efifo3 : std_logic;
signal wr_en_r : std_logic := '0';
signal din_r : std_logic_vector(17 downto 0) := "110000000000000000";
begin
-------------------------------------------------------------------------------------------
-- write pipeline
-------------------------------------------------------------------------------------------
process(wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
wr_en_r <= wr_en;
din_r <= din;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- FIFO - ip
-------------------------------------------------------------------------------------------
epathFIFO: fh_epath_fifo2K_18bit_wide
port map(
wr_clk => wr_clk,
wr_rst => fifoFLUSH,
rd_clk => rd_clk,
rd_rst => fifoFLUSH,
din => din_r,
wr_en => wr_en_r,
rd_en => rd_en_s,
dout => dout18bit, --18 bit
full => full,
almost_full => open, --almost_full,
empty => empty_efifo,
prog_full => prog_full_s, -- 1008/960 from 1024
prog_full_thresh_assert => std_logic_vector(to_unsigned(990, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(980, 10))
);
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
process(rd_clk,rst)
begin
if rst = '1' then
byte_cnt <= '0';
elsif rd_clk'event and rd_clk = '1' then
if rd_en = '1' then -- 1 clk trigger
byte_cnt <= not byte_cnt;
end if;
end if;
end process;
--
rd_en_s <= rd_en and (not byte_cnt) and (not empty_efifo); -- only when byte_cnt = 0
--
word16_code <= dout18bit(17 downto 16);
--
process(word16_code,empty_efifo1,empty_efifo2)
begin
if empty_efifo1 = '1' then
byte0_code <= "11";
byte1_code <= "11";
else
if word16_code = "10" then -- start of message
byte0_code <= "11";
byte1_code <= "10";
elsif word16_code = "01" then -- end of message
byte0_code <= "01";
byte1_code <= "11";
else -- "00" data
byte0_code <= empty_efifo1 & empty_efifo1;
byte1_code <= empty_efifo2 & empty_efifo2;
end if;
end if;
end process;
--
byte0 <= byte0_code & dout18bit(15 downto 8);
byte1 <= byte1_code & dout18bit(7 downto 0);
--byte0 <= byte0_code & dout18bit(7 downto 0);
--byte1 <= byte1_code & dout18bit(15 downto 8);
--
process(byte_cnt,byte0,byte1)
begin
if byte_cnt = '1' then
dout <= byte0;
else
dout <= byte1;
end if;
end process;
--
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
byte_rdy <= byte_cnt;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
doutRdy <= rd_en;
empty_efifo1 <= empty_efifo;
empty_efifo2 <= empty_efifo1;
empty_efifo3 <= empty_efifo2;
end if;
end process;
--
empty <= empty_efifo;-- rd_clk domain
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
rst_state <= rst or fifoFLUSH;
OE <= not rst_state;
end if;
end process;
--
prog_full <= prog_full_s and OE;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/reg8to16bit.vhd | 4 | 3301 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/reg8to16bit.vhd | 4 | 3301 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/configuration/select_vmm.vhd | 1 | 4640 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity select_vmm is
Port (
clk_in : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
conf_di : in std_logic;
conf_di_vec : out std_logic_vector(8 downto 1);
conf_do : out std_logic;
conf_do_vec : in std_logic_vector(8 downto 1);
cktk_out : in std_logic;
cktk_out_vec : out std_logic_vector(8 downto 1);
conf_wen : in std_logic;
conf_wen_vec : out std_logic_vector(8 downto 1);
conf_ena : in std_logic;
conf_ena_vec : out std_logic_vector(8 downto 1)
);
end select_vmm;
architecture Behavioral of select_vmm is
begin
fill_fifo : process(clk_in, vmm_id)
begin
if rising_edge(clk_in) then
if vmm_id = x"0001" then
conf_wen_vec(1) <= conf_wen;
cktk_out_vec(1) <= cktk_out;
conf_ena_vec(1) <= conf_ena;
conf_do <= conf_do_vec(1);
conf_di_vec(1) <= conf_di;
elsif vmm_id = x"0002" then
conf_wen_vec(2) <= conf_wen;
cktk_out_vec(2) <= cktk_out;
conf_ena_vec(2) <= conf_ena;
conf_do <= conf_do_vec(2);
conf_di_vec(2) <= conf_di;
elsif vmm_id = x"0003" then
conf_wen_vec(3) <= conf_wen;
cktk_out_vec(3) <= cktk_out;
conf_ena_vec(3) <= conf_ena;
conf_do <= conf_do_vec(3);
conf_di_vec(3) <= conf_di;
elsif vmm_id = x"0004" then
conf_wen_vec(4) <= conf_wen;
cktk_out_vec(4) <= cktk_out;
conf_ena_vec(4) <= conf_ena;
conf_do <= conf_do_vec(4);
conf_di_vec(4) <= conf_di;
elsif vmm_id = x"0005" then
conf_wen_vec(5) <= conf_wen;
cktk_out_vec(5) <= cktk_out;
conf_ena_vec(5) <= conf_ena;
conf_do <= conf_do_vec(5);
conf_di_vec(5) <= conf_di;
elsif vmm_id = x"0006" then
conf_wen_vec(6) <= conf_wen;
cktk_out_vec(6) <= cktk_out;
conf_ena_vec(6) <= conf_ena;
conf_do <= conf_do_vec(6);
conf_di_vec(6) <= conf_di;
elsif vmm_id = x"0007" then
conf_wen_vec(7) <= conf_wen;
cktk_out_vec(7) <= cktk_out;
conf_ena_vec(7) <= conf_ena;
conf_do <= conf_do_vec(7);
conf_di_vec(7) <= conf_di;
elsif vmm_id = x"0008" then
conf_wen_vec(8) <= conf_wen;
cktk_out_vec(8) <= cktk_out;
conf_ena_vec(8) <= conf_ena;
conf_do <= conf_do_vec(8);
conf_di_vec(8) <= conf_di;
else
conf_wen_vec <= (others => '0');
cktk_out_vec <= (others => '0');
conf_ena_vec <= (others => '0');
conf_di_vec <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
tdotu/ra | registerBlock.vhd | 1 | 1674 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
ENTITY registerBlock IS
GENERIC
(
regSize : integer
);
PORT
(
regWrite : IN std_logic;
read0 : IN std_logic_vector(4 downto 0);
read1 : IN std_logic_vector(4 downto 0);
write0 : IN std_logic_vector(4 downto 0);
input0 : IN std_logic_vector(regSize-1 downto 0);
output0 : OUT std_logic_vector(regSize-1 downto 0);
output1 : OUT std_logic_vector(regSize-1 downto 0)
);
END registerBlock;
ARCHITECTURE behavior OF registerBlock IS
COMPONENT reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END COMPONENT;
SUBTYPE outSignal IS std_logic_vector(regSize-1 downto 0);
TYPE outSignalArray IS ARRAY(integer RANGE 0 TO 31) OF outSignal;
SIGNAL outSignals : outSignalArray;
SIGNAL writeBit : std_logic_vector(31 downto 0);
BEGIN
output0 <= "00000000000000000000000000000100" WHEN read0 = std_logic_vector(to_unsigned(0, 5)) ELSE (OTHERS => 'Z');
output1 <= "00000000000000000000000000000100" WHEN read1 = std_logic_vector(to_unsigned(0, 5)) ELSE (OTHERS => 'Z');
gen0 : FOR X IN 1 TO 31 GENERATE
regx : reg GENERIC MAP (regSize) PORT MAP (writeBit(X), input0, outSignals(X));
output0 <= outSignals(X) WHEN read0 = std_logic_vector(to_unsigned(X, 5)) ELSE (OTHERS => 'Z');
output1 <= outSignals(X) WHEN read1 = std_logic_vector(to_unsigned(X, 5)) ELSE (OTHERS => 'Z');
writeBit(X) <= regWrite WHEN write0 = std_logic_vector(to_unsigned(X, 5)) ELSE '0';
END GENERATE gen0;
END behavior;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_FIFO_DRIVER.vhd | 1 | 21242 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send_1st_clk : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal receiving_state_clk40, do_transmit_timeout_trailers,timout_ena,timeout_trailer_send : std_logic := '0';
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
process(clk40,rst)
begin
if rst = '1' then
receiving_state_clk40 <= '0';
elsif rising_edge (clk40) then
receiving_state_clk40 <= receiving_state;
end if;
end process;
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
elsif rising_edge (clk40) then
if receiving_state_clk40 = '1' then
timeCnt_lastClk <= timeCntIn;
end if;
end if;
end process;
--
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send_1st_clk);
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif ((DIN_RDY = '1' and DIN(9 downto 8) /= "11") or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timeout_trailer_send <= '0';
elsif rising_edge (clk160) then
if timeout_trailer_send_1st_clk = '1' then
timeout_trailer_send <= '1';
elsif data16bit_rdy = '1' then -- timeout_trailer was sent once, the rest of the block will be filled with null-trailers
timeout_trailer_send <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if receiving_state = '1' then
timout_ena <= '1';
elsif do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if do_transmit_timeout_trailers = '0' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_s <= "0100000000";
DIN_RDY_s <= '1';
end if;
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= DIN_RDY_s; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- DIN_r <= DIN_s(7 downto 0);
-- end if;
--end process;
--
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- if direct_data_mode = '1' then
-- if DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1' then
-- DIN_CODE_r <= "10"; -- soc
-- else
-- DIN_CODE_r <= "00"; -- data
-- end if;
-- else
-- DIN_CODE_r <= DIN_s(9 downto 8);
-- end if;
-- end if;
--end process;
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8))
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
DIN_CODE_r <= DIN_s(9 downto 8);
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK;
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
generic map (GBTid=>GBTid, egroupID=>egroupID, epathID=>epathID)
port map (
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/cktp_gen.vhd | 1 | 10146 | ----------------------------------------------------------------------------------------
-- Company: University of Washington
-- Engineer: Lev Kurilenko
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Lev Kurilenko
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.10.2016 15:47:35
-- Design Name:
-- Module Name: cktp_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: CKTP Generator
--
-- Dependencies:
--
-- Changelog:
-- 20.02.2017 Added dynamic CKBC input frequency and reset circuitry. Changed the input
-- clock frequency to 160 Mhz. (Christos Bakalis)
-- 27.02.2017 Added cktp_primary signal from flow_fsm. (Christos Bakalis)
-- 09.03.2017 Changed input bus widths and introduced integer range for logic and routing
-- optimization. (Christos Bakalis)
-- 14.03.2017 Added a cktp_start delay process. (Christos Bakalis)
--
----------------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cktp_gen is
port(
clk_160 : in std_logic;
cktp_start : in std_logic;
cktp_primary : in std_logic;
vmm_ckbc : in std_logic; -- CKBC clock currently dynamic
ckbc_mode : in std_logic;
ckbc_freq : in std_logic_vector(5 downto 0);
skew : in std_logic_vector(4 downto 0);
pulse_width : in std_logic_vector(11 downto 0);
period : in std_logic_vector(21 downto 0);
CKTP : out std_logic
);
end cktp_gen;
architecture Behavioral of cktp_gen is
--is_state <= "0101";
signal cktp_state : std_logic_vector(3 downto 0) := (others => '0');
signal cktp_cnt : integer range -2 to 2_100_000:= 0;
signal vmm_cktp : std_logic := '0';
signal cktp_start_i : std_logic := '0'; -- Internal connection to 2-Flip-Flop Synchronizer
signal cktp_start_sync : std_logic := '0'; -- Synchronized output from Synchronizer
signal cktp_start_final : std_logic := '0';
signal cktp_primary_i : std_logic := '0';
signal cktp_primary_sync : std_logic := '0';
signal cktp_start_aligned : std_logic := '0'; -- CKTP_start signal aligned to CKBC clock
signal align_cnt : unsigned(7 downto 0) := (others => '0'); -- Used for aligning with the CKBC
signal align_cnt_thresh : unsigned(7 downto 0) := (others => '0');
signal start_align_cnt : std_logic := '0'; --
signal cnt_delay : unsigned(3 downto 0) := (others => '0');
signal ckbc_mode_i : std_logic := '0';
signal ckbc_mode_sync : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of cktp_start_i : signal is "TRUE";
attribute ASYNC_REG of cktp_start_sync : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_i : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_sync : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_i : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_sync : signal is "TRUE";
begin
--period <= x"43200"; -- Hardcode 320,000 cycles at 320 MHz to give a period of 1ms
CKTP <= vmm_cktp;
--testPulse_proc: process(clk_10_phase45) -- 10MHz/#states.
-- begin
-- if rising_edge(clk_10_phase45) then
-- if state = DAQ and trig_mode_int = '0' then
-- case cktp_state is
-- when 0 to 9979 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '0';
-- when 9980 to 10000 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '1';
-- when others =>
-- cktp_state <= 0;
-- end case;
-- else
-- vmm_cktp <= '0';
-- end if;
-- end if;
--end process;
synchronizer_proc: process(vmm_ckbc, cktp_start_final)
begin
if(cktp_start_final = '0')then
start_align_cnt <= '0';
elsif rising_edge(vmm_ckbc) then
start_align_cnt <= '1';
--if (cktp_start_sync = '1') then
-- cktp_start_aligned <= '1';
-- --if (unsigned(skew) = "00000") then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
-- -- vmm_cktp <= '1';
-- --end if;
--else
-- cktp_start_aligned <= '0';
--end if;
end if;
end process;
sync160_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
cktp_start_i <= cktp_start;
cktp_start_sync <= cktp_start_i;
cktp_primary_i <= cktp_primary;
cktp_primary_sync <= cktp_primary_i;
ckbc_mode_i <= ckbc_mode;
ckbc_mode_sync <= ckbc_mode_i;
end if;
end process;
-- delay assertion of cktp start
cktpEnableDelayer: process(clk_160)
begin
if(rising_edge(clk_160))then
if(cktp_start_sync = '1')then
if(cnt_delay < "1110")then
cnt_delay <= cnt_delay + 1;
cktp_start_final <= '0';
else
cktp_start_final <= '1';
end if;
else
cnt_delay <= (others => '0');
cktp_start_final <= '0';
end if;
end if;
end process;
testPulse_proc: process(clk_160) -- 160 MHz
begin
if rising_edge(clk_160) then
if(cktp_start_final = '0' and cktp_primary_sync = '0')then
cktp_cnt <= 0;
vmm_cktp <= '0';
cktp_start_aligned <= '0';
align_cnt <= (others => '0');
cktp_state <= (others => '0');
elsif(cktp_primary_sync = '1')then -- from flow_fsm. keep cktp high for readout initialization
vmm_cktp <= '1';
else
if start_align_cnt = '1' or ckbc_mode_sync = '1' then -- Start alignment counter on rising edge of CKBC
if align_cnt < align_cnt_thresh then
align_cnt <= align_cnt + 1;
else
align_cnt <= (others => '0');
end if;
if ckbc_mode_sync = '1' then -- Just send periodic CKTPs if @ ckbc mode
cktp_start_aligned <= '1';
elsif cktp_start_final = '0' then -- Align CKTP generation to rising edge of CKBC if CKTPs are enabled @ top
cktp_start_aligned <= '0';
elsif (align_cnt = align_cnt_thresh) then
cktp_start_aligned <= '1';
if unsigned(skew) = "00000" then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
vmm_cktp <= '1';
end if;
end if;
end if;
if cktp_start_aligned = '1' then
if (cktp_cnt < (to_integer(unsigned(skew)) - 1 ) and (cktp_cnt /= to_integer(unsigned(skew)))) then
cktp_state <= "0000";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
elsif ( (cktp_cnt >= to_integer((unsigned(skew))) - 1) and (cktp_cnt <= (to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) ) then
cktp_state <= "0001";
vmm_cktp <= '1';
cktp_cnt <= cktp_cnt + 1;
-- Uncomment if period needs to be hardcoded
--elsif ( (cktp_cnt > ( unsigned(skew) + unsigned(pulse_width) - 2) ) and (cktp_cnt <= 320000 - 2) ) then
elsif ( (cktp_cnt > ( to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) and (cktp_cnt <= to_integer(unsigned(period)) - 2) ) then
cktp_state <= "0010";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
else
cktp_state <= "0011";
cktp_cnt <= 0;
end if;
else
cktp_state <= "1111";
cktp_cnt <= 0;
end if;
end if;
end if;
end process;
ckbc_freq_proc: process(ckbc_freq)
begin
case ckbc_freq is
when "001010" => -- 10 Mhz
align_cnt_thresh <= "00001111"; -- (16 - 1)
when "010100" => -- 20 Mhz
align_cnt_thresh <= "00000111"; -- (8 - 1)
when "101000" => -- 40 Mhz
align_cnt_thresh <= "00000011"; -- (4 - 1)
when others =>
align_cnt_thresh <= "11111111";
end case;
end process;
end Behavioral; | gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/l0_deserializer_decoder.vhd | 1 | 12667 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 20.04.2017 11:46:44
-- Design Name: Level-0 Deserializer/Decoder
-- Module Name: l0_deserializer_decoder - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Implementation of data0/data1 sampling and deserialization, comma
-- character recognition, and 8b/10b decoding.
--
-- Dependencies:
--
-- Changelog:
-- 30.04.2017: Changed the way wr_en is asserted to comply with the halved wr_clk
-- of the vmm level-0 data buffer. (Christos Bakalis)
-- 20.06.2017: Removed pipeline. (Christos Bakalis)
-- 29.06.2017: Swapped clk_des with IDDR to ease timing closure. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use work.StdRtlPkg.all;
use work.Code8b10bPkg.all;
use UNISIM.VComponents.all;
entity l0_deserializer_decoder is
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
level_0 : in std_logic; -- level-0 signal
------------------------------------
-------- Buffer Interface ----------
inhib_wr : in std_logic;
dout_dec : out std_logic_vector(7 downto 0);
commas_true : out std_logic;
wr_en : out std_logic;
------------------------------------
---------- VMM Interface -----------
vmm_data0 : in std_logic;
vmm_data1 : in std_logic
);
end l0_deserializer_decoder;
architecture RTL of l0_deserializer_decoder is
component Decoder8b10b
generic (
TPD_G : time := 1 ns;
NUM_BYTES_G : positive := 2;
RST_POLARITY_G : sl := '1';
RST_ASYNC_G : boolean := false);
port(
clk : in sl;
clkEn : in sl := '1';
rst : in sl;
dataIn : in slv(NUM_BYTES_G*10-1 downto 0);
dataOut : out slv(NUM_BYTES_G*8-1 downto 0);
dataKOut : out slv(NUM_BYTES_G-1 downto 0);
codeErr : out slv(NUM_BYTES_G-1 downto 0);
dispErr : out slv(NUM_BYTES_G-1 downto 0)
);
end component;
-- deserializing IDDR and Shift Register
signal ddr_sreg : std_logic_vector(11 downto 0) := (others => '0');
signal data0_pos : std_logic := '0';
signal data0_neg : std_logic := '0';
signal data1_pos : std_logic := '0';
signal data1_neg : std_logic := '0';
signal ddr_buff : std_logic_vector(3 downto 0) := (others => '0');
-- alignment logic
constant comma_p : std_logic_vector(9 downto 0) := "0101111100";
constant comma_n : std_logic_vector(9 downto 0) := "1010000011";
type word10b_2array_type is array (0 to 2) of std_logic_vector(9 downto 0); -- 2 words of 10bit
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal comma_valid_bits_p : std_logic_vector(2 downto 0) := (others => '0');
signal comma_valid_bits_n : std_logic_vector(2 downto 0) := (others => '0');
signal comma_valid_p : std_logic := '0';
signal comma_valid_n : std_logic := '0';
signal align_sreg_p : std_logic_vector(4 downto 0) := (others => '0');
signal align_sreg_n : std_logic_vector(4 downto 0) := (others => '0');
-- word selection logic and decoder
signal pos_p : std_logic_vector(2 downto 0) := (others => '0');
signal pos_n : std_logic_vector(2 downto 0) := (others => '0');
signal align_select : std_logic_vector(2 downto 0) := (others => '0');
signal word10b_rdy : std_logic := '0';
signal align_sel_p : std_logic := '0';
signal align_sel_n : std_logic := '0';
signal dec_en : std_logic := '0';
signal L0_8B_data : std_logic_vector(7 downto 0) := (others => '0');
signal L0_8B_data_i : std_logic_vector(7 downto 0) := (others => '0');
signal L0_8B_K : std_logic_vector(0 downto 0) := (others => '0');
signal din_dec : std_logic_vector(9 downto 0) := (others => '0');
-- comma counter
signal cnt_commas : unsigned(4 downto 0) := (others => '0');
constant cnt_thr : unsigned(4 downto 0) := "11111"; -- 6 consecutive commas
begin
------------------------------------------
-------- DDR and Shift Register ----------
------------------------------------------
IDDR_inst_data0: IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => data0_pos, -- 1-bit output for positive edge of clock
Q2 => data0_neg, -- 1-bit output for negative edge of clock
C => clk_ckdt, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => vmm_data0, -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
IDDR_inst_data1: IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => data1_pos, -- 1-bit output for positive edge of clock
Q2 => data1_neg, -- 1-bit output for negative edge of clock
C => clk_ckdt, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => vmm_data1, -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
sreg_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
ddr_buff(3) <= data0_pos;
ddr_buff(2) <= data1_pos;
ddr_buff(1) <= data0_neg;
ddr_buff(0) <= data1_neg;
ddr_sreg <= ddr_buff & ddr_sreg(11 downto 4);
end if;
end process;
------------------------------------------
------------------------------------------
-------- Alignment Logic -----------------
------------------------------------------
--- 10 bit array
input_map: for I in 0 to 2 generate -- 1 10bit-word per alignment, 2 possible alignments
word10b_align_array(I) <= ddr_sreg(I+9)&ddr_sreg(I+8)&ddr_sreg(I+7)&ddr_sreg(I+6)&ddr_sreg(I+5)&
ddr_sreg(I+4)&ddr_sreg(I+3)&ddr_sreg(I+2)&ddr_sreg(I+1)&ddr_sreg(I+0); -- 10 bit word, alligned to bit I
end generate input_map;
comma_test_p: for I in 0 to 2 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits_p(I) <= '1' when (word10b_align_array(I) = comma_p) else '0';
end generate comma_test_p;
comma_test_n: for I in 0 to 2 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits_n(I) <= '1' when (word10b_align_array(I) = comma_n) else '0';
end generate comma_test_n;
comma_valid_p <= comma_valid_bits_p(2) or comma_valid_bits_p(1) or comma_valid_bits_p(0);
comma_valid_n <= comma_valid_bits_n(2) or comma_valid_bits_n(1) or comma_valid_bits_n(0);
-- alignment shift register for Comma_P
align_sreg_p_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if comma_valid_p = '1' then
align_sreg_p <= "10000";
else
align_sreg_p <= align_sreg_p(0) & align_sreg_p(4 downto 1);
end if;
end if;
end process;
-- alignment shift register for Comma_N
align_sreg_n_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if comma_valid_n = '1' then
align_sreg_n <= "10000";
else
align_sreg_n <= align_sreg_n(0) & align_sreg_n(4 downto 1);
end if;
end if;
end process;
------------------------------------------
------------------------------------------
---- Word Selection Logic and Decoder ----
------------------------------------------
-- latch the 10-bit word array position while receiving commas
latch_pos: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(comma_valid_p = '1')then
pos_p <= comma_valid_bits_p;
else null;
end if;
if(comma_valid_n = '1')then
pos_n <= comma_valid_bits_n;
else null;
end if;
end if;
end process;
-- select the correct 10-bit word from the array
sel_fromArray: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(align_sel_p = '1')then
align_select <= pos_p;
elsif(align_sel_n = '1')then
align_select <= pos_n;
end if;
end if;
end process;
-- register the 10-bit word
input_reg1: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
-- final register stage before the decoder + word selection
reg_final: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
dec_en <= word10b_rdy;
case align_select is
when "001" => -- bit0 word got comma => align to bit0
din_dec <= word10b_align_array_r(0);
when "010" => -- bit1 word got comma => align to bit1
din_dec <= word10b_align_array_r(1);
when "100" => -- bit1 word got comma => align to bit1
din_dec <= word10b_align_array_r(2);
when others =>
end case;
end if;
end process;
Decoder8b10b_inst: Decoder8b10b
generic map (
TPD_G => 1 ns,
NUM_BYTES_G => 1,
RST_POLARITY_G => '1',
RST_ASYNC_G => false)
port map(
clk => clk_ckdt,
clkEn => dec_en,
rst => '0',
dataIn => din_dec,
dataOut => L0_8B_data,
dataKOut => L0_8B_K,
codeErr => open,
dispErr => open
);
------------------------------------------
------------------------------------------
----------- Misc Processes ---------------
------------------------------------------
-- process that counts commas
cnt_commas_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(L0_8B_data_i /= x"BC")then
cnt_commas <= (others => '0');
commas_true <= '0';
else
if(cnt_commas = cnt_thr)then
commas_true <= '1';
else
commas_true <= '0';
cnt_commas <= cnt_commas + 1;
end if;
end if;
end if;
end process;
-- process that scans for non-comma characters and asserts the FIFO wr_en
wr_ena_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(inhib_wr = '0' and dec_en = '1' and L0_8B_data /= x"BC")then
wr_en <= '1';
else
wr_en <= '0';
end if;
L0_8B_data_i <= L0_8B_data;
end if;
end process;
------------------------------------------
word10b_rdy <= align_sreg_p(4) or align_sreg_n(4);
align_sel_p <= align_sreg_p(0);
align_sel_n <= align_sreg_n(0);
dout_dec <= L0_8B_data_i;
end RTL;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/FIFO2Elink.vhd | 1 | 5127 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity FIFO2Elink is
generic (
OutputDataRate : integer := 80; -- 80 or 160 MHz
elinkEncoding : std_logic_vector (1 downto 0)
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
efifoDin : in std_logic_vector (17 downto 0); -- [data_code,2bit][data,16bit]
efifoWe : in std_logic;
efifoPfull : out std_logic;
efifoWclk : in std_logic;
------
DATA1bitOUT : out std_logic
------
);
end FIFO2Elink;
architecture Behavioral of FIFO2Elink is
----
signal efifoRE, doutRdy : std_logic;
signal efifoDout : std_logic_vector(9 downto 0);
signal dout2bit : std_logic_vector(1 downto 0);
signal bitCount1,dout2bit_r : std_logic := '0';
signal dout4bit, dout4bit_r : std_logic_vector(3 downto 0);
signal bitCount2 : std_logic_vector(1 downto 0) := "00";
----
begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
UEF: entity work.upstreamEpathFifoWrap
port map(
rst => rst,
fifoFLUSH => fifo_flush,
---
wr_clk => efifoWclk,
wr_en => efifoWe,
din => efifoDin,
---
rd_clk => clk160,
rd_en => efifoRE,
dout => efifoDout,
doutRdy => doutRdy,
---
full => open,
empty => open,
prog_full => efifoPfull
);
--
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
OutputDataRate80: if OutputDataRate = 80 generate
EPROC_OUT2bit: entity work.EPROC_OUT2
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_outbits => '0', -- when '1', the output bits will be swapped
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout2bit, -- @ 40MHz
TTCin => "00", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
-------------------------------------------
-- serialization of the 2-bit data output:
-------------------------------------------
process(clk80)
begin
if clk80'event and clk80 = '1' then
bitCount1 <= not bitCount1;
end if;
end process;
--
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
dout2bit_r <= dout2bit(1);
end if;
end if;
end process;
---
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
DATA1bitOUT <= dout2bit(0);
else
DATA1bitOUT <= dout2bit_r;
end if;
end if;
end process;
---
end generate OutputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
OutputDataRate160: if OutputDataRate = 160 generate
EPROC_OUT4bit: entity work.EPROC_OUT4
PORT MAP(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout4bit, -- @ 40MHz
TTCin => "00000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
-------------------------------------------
-- serialization of the 4-bit data output:
-------------------------------------------
process(clk160)
begin
if clk160'event and clk160 = '1' then
bitCount2 <= bitCount2 + 1;
end if;
end process;
--
process(clk160)
begin
if clk160'event and clk160 = '1' then
if bitCount2 = "00" then
dout4bit_r <= dout4bit;
end if;
end if;
end process;
---
process(clk80)
begin
if clk160'event and clk160 = '1' then
case bitCount2 is
when "00" => DATA1bitOUT <= dout4bit(0);
when "01" => DATA1bitOUT <= dout4bit_r(1);
when "10" => DATA1bitOUT <= dout4bit_r(2);
when "11" => DATA1bitOUT <= dout4bit_r(3);
when others =>
end case;
end if;
end process;
---
end generate OutputDataRate160;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN8_ALIGN_BLOCK.vhd | 2 | 4177 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 8bit bit-stream to two commas
entity EPROC_IN8_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_4array_type;
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN8_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN8_ALIGN_BLOCK is
signal bytes_r : word10b_4array_type := ((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(1 downto 0) := "00";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "11" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "00";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "00" => dataOUT_s <= bytes_r(0);
when "01" => dataOUT_s <= bytes_r(1);
when "10" => dataOUT_s <= bytes_r(2);
when "11" => dataOUT_s <= bytes_r(3);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_Complete_nomac.vhd | 2 | 10313 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
architecture structural of UDP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
begin
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX
PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
end structural;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/UDP_Complete_nomac.vhd | 2 | 10313 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
architecture structural of UDP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
begin
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX
PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
end structural;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN4_direct.vhd | 4 | 3202 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 |
adelapie/noekeon | tb_round_f.vhd | 2 | 4118 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
assert a_0_out = X"febb00d0"
report "ROUND ERROR (a_0)" severity FAILURE;
assert a_1_out = X"074ee42e"
report "ROUND ERROR (a_1)" severity FAILURE;
assert a_2_out = X"dde647ab"
report "ROUND ERROR (a_2)" severity FAILURE;
assert a_3_out = X"3207ef78"
report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/enc8b10_wrap.vhd | 4 | 4912 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: enc_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE, work;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
use work.all;
--! a wrap for 8b10b encoder
entity enc8b10_wrap is
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end enc8b10_wrap;
architecture Behavioral of enc8b10_wrap is
----------------------------------
----------------------------------
component MUX4_Nbit
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(1 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX4_Nbit;
----------------------------------
----------------------------------
component enc_8b10b
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaRise : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end component enc_8b10b;
----------------------------------
----------------------------------
signal isk : std_logic := '1';
signal encoder_rst, enc_ena_s : std_logic;
signal enc_ena, encoder_rst_delayed, encoder_rst_clk1 : std_logic := '1';
signal dataINrdy_s : std_logic;
signal rst_state : std_logic := '1';
signal dataIN_s, byte : std_logic_vector(7 downto 0);
signal dataCode_s : std_logic_vector(1 downto 0) := (others => '1');
begin
dataINrdy_s <= dataINrdy and (not encoder_rst);
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
process(clk)
begin
if clk'event and clk = '1' then
rst_state <= rst;
end if;
end process;
--
process(clk)
begin
if clk'event and clk = '1' then
if dataINrdy_s = '1' then
dataIN_s <= dataIN;
dataCode_s <= dataCode;
isk <= dataCode(1) or dataCode(0);
--rst_state <= '0';
-- else
-- dataIN_s <= Kchar_comma;
-- dataCode_s <= "11";
end if;
end if;
end process;
--
encoder_rst <= rst_state or rst;
--
-------------------------------------------------------------------------------------------
-- data code cases
-- 00"data, 01"eop, 10"sop, 11"comma
-------------------------------------------------------------------------------------------
inmux: MUX4_Nbit
generic map (N=>8)
port map (
data0 => dataIN_s,
data1 => Kchar_eop,
data2 => Kchar_sop,
data3 => Kchar_comma,
sel => dataCode_s,
data_out => byte
);
--
-------------------------------------------------------------------------------------------
-- 8b10b encoder
-------------------------------------------------------------------------------------------
process(clk)
begin
if clk'event and clk = '0' then
enc_ena <= dataINrdy_s or encoder_rst;
encoder_rst_clk1 <= encoder_rst;
encoder_rst_delayed <= encoder_rst_clk1;
end if;
end process;
--
enc_ena_s <= enc_ena or encoder_rst_delayed;
--
enc_8b10bx: enc_8b10b
port map(
RESET => encoder_rst, -- Global asynchronous reset (active high)
clk => clk,
ena => enc_ena_s,
--SBYTECLK => encClk_s, --clk, -- Master synchronous send byte clock
KI => isk, -- Control (K) input(active high)
AI=>byte(0), BI=>byte(1), CI=>byte(2), DI=>byte(3), EI=>byte(4), FI=>byte(5), GI=>byte(6), HI=>byte(7), -- Unencoded input data
JO=>encDataOut(9),HO=>encDataOut(8),GO=>encDataOut(7),FO=>encDataOut(6),IO=>encDataOut(5),EO=>encDataOut(4),DO=>encDataOut(3),CO=>encDataOut(2),BO=>encDataOut(1),AO=>encDataOut(0) -- Encoded out
);
--
--
process(clk)
begin
if clk'event and clk = '1' then
encDataOutrdy <= dataINrdy_s and (not encoder_rst);
end if;
end process;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/SCDataMANAGER.vhd | 4 | 5210 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: SCDataMANAGER - Sub-Chunk Data Manager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
--! sub-chunk data manager,
--! inserts sub-chunk trailer at the end of the chunk/block
entity SCDataMANAGER is
Port (
CLK : in std_logic;
rst : in std_logic;
xoff : in std_logic;
maxCLEN : in std_logic_vector (2 downto 0); -- (15 downto 0);
rstCLENcount : in std_logic;
truncateCdata : out std_logic; -- maximum allowed chunk length is reached of xoff received - truncation mark
-------------
trailerMOD : in std_logic_vector (1 downto 0); -- keeps its value till the next DIN_RDY_s
trailerTYPE : in std_logic_vector (2 downto 0); -- keeps its value till the next DIN_RDY_s
trailerRSRVbit : in std_logic; --
-------------
trailerSENDtrig : in std_logic;
dataCNTena : in std_logic; -- counts only data (or 'flush' padding), no header, no trailer
-------------
trailerOUT : out std_logic_vector (15 downto 0);
trailerOUTrdy : out std_logic
);
end SCDataMANAGER;
architecture Behavioral of SCDataMANAGER is
----
signal truncate_state, sc_counter_rst, first_byte_count_rst : std_logic := '0';
signal truncate_data_flag, rst_fall, rstCLENcount_s, trailerSENDtrig_next_clk : std_logic;
signal sc_data_count : std_logic_vector(9 downto 0) := (others => '0');
signal schunk_length : std_logic_vector(9 downto 0);
signal chunk_data_count : std_logic_vector(11 downto 0);
signal trailer_s : std_logic_vector(15 downto 0);
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
----
begin
rst_fall_pulse: entity work.pulse_fall_pw01 PORT MAP(CLK, rst, rst_fall);
-----------------------------------------------------------------
-- chunk data counter,
-- counts to MAX_COUNT then rises MAX_REACHED
-- used for chunk data truncation
-----------------------------------------------------------------
rstCLENcount_s <= rstCLENcount or rst_fall;
--
CD_COUNTER_inst: entity work.CD_COUNTER
PORT MAP(
CLK => CLK,
RESET => rstCLENcount_s,
xoff => xoff,
COUNT_ENA => dataCNTena,
MAX_COUNT => maxCLEN,
count_out => chunk_data_count, -- the whole chunk data counter, used for data truncation
truncate_data => truncate_data_flag
);
--
truncate_state_latch: process(rstCLENcount, CLK)
begin
if rstCLENcount = '1' then
truncate_state <= '0';
elsif CLK'event and CLK = '1' then
if truncate_data_flag = '1' and trailerSENDtrig = '1' then -- first trigger goes through
truncate_state <= '1';
end if;
end if;
end process;
--
truncateCdata <= truncate_data_flag;
--
-----------------------------------------------------------------
-- trailer: in case of zero data (last word of a block is left)
-----------------------------------------------------------------
zero_data_case: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>2) PORT MAP(CLK, trailerSENDtrig, trailerSENDtrig_next_clk);
--process(CLK)
--begin
-- if CLK'event and CLK = '1' then
-- trailerSENDtrig_next_clk <= trailerSENDtrig;
-- end if;
--end process;
--
-----------------------------------------------------------------
-- Sub-Chunk Trailer bits
-----------------------------------------------------------------
schunk_length <= sc_data_count; -- chunk_data_count(9 downto 0); --
trailer_s <= trailerTYPE & trailerMOD & trailerRSRVbit & schunk_length;
--
process(trailerSENDtrig_next_clk, trailer_s)
begin
if trailerSENDtrig_next_clk = '1' then
trailerOUT <= zero_data_trailer; -- in case the only a space for a single 16-bit word is left, null-chunk is sent (ignored by software)
else
trailerOUT <= trailer_s;
end if;
end process;
--
trailerOUTrdy <= trailerSENDtrig and (not truncate_state); -- same clock!
-----------------------------------------------------------------
-- sub-chunk data counter
-----------------------------------------------------------------
sc_counter_rst <= rst_fall or rstCLENcount;
--
sub_chunk_counter: process(CLK)
begin
if CLK'event and CLK = '1' then
if sc_counter_rst = '1' or (dataCNTena = '0' and trailerSENDtrig = '1') then
sc_data_count <= (others => '0');
else
if dataCNTena = '1' then --and first_byte_count_rst = '0' then
if trailerSENDtrig = '1' then
sc_data_count <= "0000000001";
else
sc_data_count <= sc_data_count + 1;
end if;
end if;
end if;
end if;
end process;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/CD_COUNTER.vhd | 4 | 1687 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: CD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--! chunk data counter
entity CD_COUNTER is
port (
CLK : in std_logic;
RESET : in std_logic;
xoff : in std_logic;
COUNT_ENA : in std_logic; -- high only when data is sent (not counting header and trailers)
MAX_COUNT : in std_logic_vector (2 downto 0); -- (15 downto 0);
-----
count_out : out std_logic_vector (11 downto 0);
truncate_data : out std_logic
);
end CD_COUNTER;
architecture Behavioral of CD_COUNTER is
signal count_sig : std_logic_vector (11 downto 0) := (others => '0');
signal max_mark, max_ena : std_logic;
begin
--
max_ena <= '0' when (MAX_COUNT = "000") else '1'; -- when max count is 0x0, no chunk length limit is set
max_mark <= '1' when ((count_sig(11 downto 9) = MAX_COUNT) and (max_ena = '1')) else '0'; -- stays high until reset
--
counter: process(RESET, CLK)
begin
if RESET = '1' then
count_sig <= (others => '0');
elsif CLK'event and CLK = '1' then
if (COUNT_ENA = '1' and max_mark = '0') then
count_sig <= count_sig + 1; -- keeps the final value until reset
end if;
end if;
end process;
--
truncate_data <= max_mark or xoff;
count_out <= count_sig;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_STORE_br.vhd | 2 | 10776 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_STORE_br - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ARP storage table using block ram with lookup based on IP address
-- implements upto 255 entries with sequential search
-- uses round robin overwrite when full (LRU would be better, but ...)
--
-- store may take a number of cycles and the request is latched
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
entity arp_STORE_br is
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end arp_STORE_br;
architecture Behavioral of arp_STORE_br is
type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
type count_mode_t is (RST, INCR, HOLD);
type mode_t is (MREAD, MWRITE);
-- state variables
signal ip_ram : ip_ram_t; -- will be implemented as block ram
signal mac_ram : mac_ram_t; -- will be implemented as block ram
signal st_state : st_state_t;
signal next_write_addr : addr_t; -- where to make the next write
signal num_entries : addr_t; -- number of entries in the store
signal next_read_addr : addr_t; -- next addr to read from
signal entry_found : arp_entry_t; -- entry found in search
signal mode : mode_t; -- are we writing or reading?
signal req_entry : arp_entry_t; -- entry latched from req
-- busses
signal next_st_state : st_state_t;
signal arp_entry_val : arp_entry_t;
signal mode_val : mode_t;
signal write_addr : addr_t; -- actual write address to use
signal read_result_int : arp_store_result_t;
-- control signals
signal set_st_state : std_logic;
signal set_next_write_addr : count_mode_t;
signal set_num_entries : count_mode_t;
signal set_next_read_addr : count_mode_t;
signal write_ram : std_logic;
signal set_entry_found : std_logic;
signal set_mode : std_logic;
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
variable ret : arp_store_rslt_t;
begin
case status is
when IDLE =>
ret := status;
when others =>
if mode = MWRITE then
ret := BUSY;
else
ret := status;
end if;
end case;
return ret;
end read_status;
begin
combinatorial : process (
-- input signals
read_req, write_req, clear_store, reset,
-- state variables
ip_ram, mac_ram, st_state, next_write_addr, num_entries,
next_read_addr, entry_found, mode, req_entry,
-- busses
next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
-- control signals
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
write_ram, set_mode
)
begin
-- set output followers
read_result_int.status <= IDLE;
read_result_int.entry <= entry_found;
entry_count <= to_unsigned(num_entries, 8);
-- set bus defaults
next_st_state <= IDLE;
mode_val <= MREAD;
write_addr <= next_write_addr;
-- set signal defaults
set_st_state <= '0';
set_next_write_addr <= HOLD;
set_num_entries <= HOLD;
set_next_read_addr <= HOLD;
write_ram <= '0';
set_entry_found <= '0';
set_mode <= '0';
-- STORE FSM
case st_state is
when IDLE =>
if write_req.req = '1' then
-- need to search to see if this IP already there
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MWRITE;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
elsif read_req.req = '1' then
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MREAD;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
end if;
when PAUSE =>
-- wait until read addr is latched and we get first data out of the ram
read_result_int.status <= read_status(BUSY, mode);
set_next_read_addr <= INCR;
next_st_state <= SEARCH;
set_st_state <= '1';
when SEARCH =>
read_result_int.status <= read_status(SEARCHING, mode);
-- check if have a match at this entry
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
-- found it
set_entry_found <= '1';
next_st_state <= FOUND;
set_st_state <= '1';
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
-- reached end of entry table
read_result_int.status <= read_status(NOT_FOUND, mode);
next_st_state <= NOT_FOUND;
set_st_state <= '1';
else
-- no match at this entry , go to next
set_next_read_addr <= INCR;
end if;
when FOUND =>
read_result_int.status <= read_status(FOUND, mode);
if mode = MWRITE then
write_addr <= next_read_addr - 1;
write_ram <= '1';
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
when NOT_FOUND =>
read_result_int.status <= read_status(NOT_FOUND, mode);
if mode = MWRITE then
-- need to write into the next free slot
write_addr <= next_write_addr;
write_ram <= '1';
set_next_write_addr <= INCR;
if num_entries < MAX_ARP_ENTRIES then
-- if not full, count another entry (if full, it just wraps)
set_num_entries <= INCR;
end if;
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
end case;
end process;
sequential : process (clk)
begin
if rising_edge(clk) then
-- ram processing
if write_ram = '1' then
ip_ram(write_addr) <= req_entry.ip;
mac_ram(write_addr) <= req_entry.mac;
end if;
if next_read_addr < MAX_ARP_ENTRIES then
arp_entry_val.ip <= ip_ram(next_read_addr);
arp_entry_val.mac <= mac_ram(next_read_addr);
else
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
end if;
read_result <= read_result_int;
if reset = '1' or clear_store = '1' then
-- reset state variables
st_state <= IDLE;
next_write_addr <= 0;
num_entries <= 0;
next_read_addr <= 0;
entry_found.ip <= (others => '0');
entry_found.mac <= (others => '0');
req_entry.ip <= (others => '0');
req_entry.mac <= (others => '0');
mode <= MREAD;
else
-- Next req_state processing
if set_st_state = '1' then
st_state <= next_st_state;
else
st_state <= st_state;
end if;
-- mode setting and write request latching
if set_mode = '1' then
mode <= mode_val;
if mode_val = MWRITE then
req_entry <= write_req.entry;
else
req_entry.ip <= read_req.ip;
req_entry.mac <= (others => '0');
end if;
else
mode <= mode;
req_entry <= req_entry;
end if;
-- latch entry found
if set_entry_found = '1' then
entry_found <= arp_entry_val;
else
entry_found <= entry_found;
end if;
-- next_write_addr counts and wraps
case set_next_write_addr is
when HOLD => next_write_addr <= next_write_addr;
when RST => next_write_addr <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
end case;
-- num_entries counts and holds at max
case set_num_entries is
when HOLD => num_entries <= num_entries;
when RST => num_entries <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
end case;
-- next_read_addr counts and wraps
case set_next_read_addr is
when HOLD => next_read_addr <= next_read_addr;
when RST => next_read_addr <= 0;
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/enc_8b10.vhd | 4 | 9805 | -------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; | gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/FIFO2Elink.vhd | 2 | 8819 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity FIFO2Elink is
generic (
OutputDataRate : integer := 80; -- 80 / 160 / 320 MHz
elinkEncoding : std_logic_vector (1 downto 0) -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
clk320 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
efifoDin : in std_logic_vector (17 downto 0); -- [data_code,2bit][data,16bit]
efifoWe : in std_logic;
efifoPfull : out std_logic;
efifoWclk : in std_logic;
------
DATA1bitOUT : out std_logic; -- serialized output
elink2bit : out std_logic_vector (1 downto 0); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit : out std_logic_vector (3 downto 0); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit : out std_logic_vector (7 downto 0) -- 8 bits @ clk40, can interface 8-bit of GBT frame
------
);
end FIFO2Elink;
architecture Behavioral of FIFO2Elink is
----
signal efifoRE, doutRdy : std_logic;
signal efifoDout : std_logic_vector(9 downto 0);
signal dout2bit : std_logic_vector(1 downto 0);
signal bitCount1,dout2bit_r : std_logic := '0';
signal dout4bit, dout4bit_r : std_logic_vector(3 downto 0);
signal dout8bit, dout8bit_r : std_logic_vector(7 downto 0);
signal bitCount2 : std_logic_vector(1 downto 0) := "00";
signal bitCount3 : std_logic_vector(2 downto 0) := "000";
----
begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
UEF: entity work.upstreamEpathFifoWrap
port map(
rst => rst,
fifoFLUSH => fifo_flush,
---
wr_clk => efifoWclk,
wr_en => efifoWe,
din => efifoDin,
---
rd_clk => clk160,
rd_en => efifoRE,
dout => efifoDout,
doutRdy => doutRdy,
---
full => open,
empty => open,
prog_full => efifoPfull
);
--
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
OutputDataRate80: if OutputDataRate = 80 generate
EPROC_OUT2bit: entity work.EPROC_OUT2
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_outbits => '0', -- when '1', the output bits will be swapped
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout2bit, -- @ 40MHz
TTCin => "00", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 2-bit data output:
-------------------------------------------
process(clk80)
begin
if rising_edge(clk80) then
bitCount1 <= not bitCount1;
end if;
end process;
--
process(clk80)
begin
if rising_edge(clk80) then
if bitCount1 = '0' then
dout2bit_r <= dout2bit(1);
end if;
end if;
end process;
---
process(clk80) -- serialized output
begin
if rising_edge(clk80) then
if bitCount1 = '0' then
DATA1bitOUT <= dout2bit(0);
else
DATA1bitOUT <= dout2bit_r;
end if;
end if;
end process;
---
elink2bit <= dout2bit; -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
OutputDataRate160: if OutputDataRate = 160 generate
EPROC_OUT4bit: entity work.EPROC_OUT4
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout4bit, -- @ 40MHz
TTCin => "00000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 4-bit data output:
-------------------------------------------
process(clk160)
begin
if rising_edge(clk160) then
bitCount2 <= bitCount2 + 1;
end if;
end process;
--
process(clk160)
begin
if rising_edge(clk160) then
if bitCount2 = "00" then
dout4bit_r <= dout4bit;
end if;
end if;
end process;
---
process(clk160) -- serialized output
begin
if rising_edge(clk160) then
case bitCount2 is
when "00" => DATA1bitOUT <= dout4bit(0);
when "01" => DATA1bitOUT <= dout4bit_r(1);
when "10" => DATA1bitOUT <= dout4bit_r(2);
when "11" => DATA1bitOUT <= dout4bit_r(3);
when others =>
end case;
end if;
end process;
---
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= dout4bit; -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate160;
------------------------------------------------------------
-- E-PATH case 320 MHz
------------------------------------------------------------
OutputDataRate320: if OutputDataRate = 320 generate
EPROC_OUT8bit: entity work.EPROC_OUT8
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout8bit, -- @ 40MHz
TTCin => "000000000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 8-bit data output:
-------------------------------------------
process(clk320)
begin
if rising_edge(clk320) then
bitCount3 <= bitCount3 + 1;
end if;
end process;
--
process(clk320)
begin
if rising_edge(clk320) then
if bitCount3 = "000" then
dout8bit_r <= dout8bit;
end if;
end if;
end process;
---
process(clk320) -- serialized output
begin
if rising_edge(clk320) then
case bitCount3 is
when "000" => DATA1bitOUT <= dout8bit(0);
when "001" => DATA1bitOUT <= dout8bit_r(1);
when "010" => DATA1bitOUT <= dout8bit_r(2);
when "011" => DATA1bitOUT <= dout8bit_r(3);
when "100" => DATA1bitOUT <= dout8bit_r(4);
when "101" => DATA1bitOUT <= dout8bit_r(5);
when "110" => DATA1bitOUT <= dout8bit_r(6);
when "111" => DATA1bitOUT <= dout8bit_r(7);
when others =>
end case;
end if;
end process;
---
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= dout8bit; -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate320;
------------------------------------------------------------
-- unsupported Data Rate
------------------------------------------------------------
unsupported_Data_Rate: if OutputDataRate /= 80 and OutputDataRate /= 160 and OutputDataRate /= 320 generate
---
DATA1bitOUT <= '0'; -- serialized output
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate unsupported_Data_Rate;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/common/temac_10_100_1000_reset_sync.vhd | 2 | 5019 | --------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity temac_10_100_1000_reset_sync is
generic (INITIALISE : bit_vector(1 downto 0) := "11");
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end temac_10_100_1000_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of temac_10_100_1000_reset_sync is
signal reset_sync_reg : std_logic;
signal reset_sync_reg2 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_sync_reg : signal is "TRUE";
attribute ASYNC_REG of reset_sync_reg2 : signal is "TRUE";
attribute RLOC : string;
attribute RLOC of reset_sync_reg : signal is "X0Y0";
attribute RLOC of reset_sync_reg2 : signal is "X0Y0";
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of reset_sync_reg : signal is "NO";
attribute SHREG_EXTRACT of reset_sync_reg2 : signal is "NO";
attribute INIT : string;
attribute INIT of reset_sync_reg : signal is "1";
attribute INIT of reset_sync_reg2 : signal is "1";
begin
reset_sync1 : FDPE
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg,
Q => reset_sync_reg2
);
reset_out <= reset_sync_reg2;
end rtl;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN2.vhd | 1 | 4824 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 2bit input
entity EPROC_IN2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_inputbits : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal edata_in_s : std_logic_vector (1 downto 0);
--
signal DATA_OUT_direct : std_logic_vector (9 downto 0);
signal DATA_RDY_direct : std_logic;
---
signal DATA_OUT_8b10b_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_8b10b_decoded : std_logic;
---
signal DATA_OUT_HDLC_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_HDLC_decoded : std_logic;
---
signal DATA_RDY_sig : std_logic;
signal DATA_OUT_s : std_logic_vector (9 downto 0);
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
--
in_sel: process(swap_inputbits,EDATA_IN)
begin
if swap_inputbits = '1' then
edata_in_s <= EDATA_IN(0) & EDATA_IN(1);
else
edata_in_s <= EDATA_IN;
end if;
end process;
--
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
--
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => edata_in_s,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => edata_in_s,
dataOUT => DATA_OUT_8b10b_decoded,
dataOUTrdy => DATA_RDY_8b10b_decoded,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => edata_in_s,
dataOUT => DATA_OUT_HDLC_decoded,
dataOUTrdy => DATA_RDY_HDLC_decoded
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_decoded,
data2 => DATA_OUT_HDLC_decoded,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_decoded,
data2 => DATA_RDY_HDLC_decoded,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_OUT2_ENC8b10b.vhd | 4 | 5403 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp.vhd | 2 | 26146 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in cache
-- request cache fill through ARP protocol if required
-- cache is simple 1 deep
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added req for mac tx and wait for grant
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added arp response timeout
-- Revision 0.05 - Added arp cache reset control
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
entity arp is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
end arp;
architecture Behavioral of arp is
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3);
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST,INCR,HOLD);
type arp_oper_type is (NOP,REQUEST,REPLY);
type set_clr_type is (SET, CLR, HOLD);
type tx_state_type is (IDLE,WAIT_MAC,SEND);
type arp_entry_type is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
is_valid : std_logic;
reply_required : std_logic;
end record;
-- state variables
signal req_state : req_state_type;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal mac_addr_found : STD_LOGIC_VECTOR (47 downto 0); -- mac address found
signal mac_addr_valid_reg: std_logic;
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
signal rx_state : rx_state_type;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_type;
signal arp_req_count : unsigned (7 downto 0);
signal arp_entry : arp_entry_type; -- arp entry store
signal new_arp_entry : arp_entry_type;
signal tx_state : tx_state_type;
signal tx_count : unsigned (7 downto 0);
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- requester control signals
signal next_req_state : req_state_type;
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal set_mac_addr : std_logic;
signal set_mac_addr_invalid : std_logic;
signal set_send_req : std_logic;
signal clear_send_req : std_logic;
signal set_timer : count_mode_type; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : count_mode_type;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_arp_entry_request : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_type;
signal clear_reply_req : std_logic;
signal set_chn_reqd : set_clr_type;
signal kill_data_out_valid : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
req_combinatorial : process (
-- input signals
arp_req_req,
-- state variables
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
freq_scaler, timer, timeout_reg,
-- control signals
next_req_state, set_req_state, set_req_ip, set_mac_addr, control,
set_mac_addr_invalid,set_send_req, clear_send_req, set_timer, timer_enable, set_timeout
)
begin
-- set output followers
if arp_req_req.lookup_req = '1' then
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry.mac;
elsif arp_req_req.lookup_req = '1' then
arp_req_rslt.got_mac <= '0'; -- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.mac <= arp_entry.mac;
else
arp_req_rslt.got_mac <= mac_addr_valid_reg;
arp_req_rslt.mac <= mac_addr_found;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
set_mac_addr <= '0';
set_mac_addr_invalid <= '0';
set_send_req <= '0';
clear_send_req <= '0';
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= RST;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
-- already have this IP
set_mac_addr <= '1';
else
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
set_mac_addr_invalid <= '1';
end if;
end if;
when LOOKUP =>
if arp_entry.ip = req_ip_addr and arp_entry.is_valid = '1' then
-- already have this IP
next_req_state <= IDLE;
set_req_state <= '1';
set_mac_addr <= '1';
else
-- need to request mac for this IP
set_send_req <= '1';
set_timer <= RST;
next_req_state <= REQUEST;
set_req_state <= '1';
end if;
when REQUEST =>
clear_send_req <= '1';
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when WAIT_REPLY =>
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (data_in_clk,reset)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
send_request_needed <= '0';
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= arp_req_req.ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- send request to TX&RX FSMs to send an ARP request
if set_send_req = '1' then
send_request_needed <= '1';
elsif clear_send_req = '1' then
send_request_needed <= '0';
else
send_request_needed <= send_request_needed;
end if;
-- Set the found mac address
if set_mac_addr = '1' then
mac_addr_found <= arp_entry.mac;
mac_addr_valid_reg <= '1';
elsif set_mac_addr_invalid = '1' then
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
else
mac_addr_found <= mac_addr_found;
mac_addr_valid_reg <= mac_addr_valid_reg;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when RST =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data,
set_arp_entry_request)
begin
-- set output followers
req_count <= STD_LOGIC_VECTOR(arp_req_count);
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_arp_entry_request <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 42 then
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
when REPLY =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (data_in_clk)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
-- reset arp entry store
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if control.clear_cache = '1' then
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
elsif set_arp_entry_request = '1' then
-- copy info from new entry to arp_entry and set reply required
arp_entry.mac <= new_arp_entry.mac;
arp_entry.ip <= new_arp_entry.ip;
arp_entry.is_valid <= '1';
if arp_operation = REQUEST then
arp_entry.reply_required <= '1';
else
arp_entry.reply_required <= '0';
end if;
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
elsif clear_reply_req = '1' then
-- note: clear_reply_req is set by tx logic, but handled in the clk domain of the rx
-- maintain arp entry state, but reset the reply required flag
arp_entry.mac <= arp_entry.mac;
arp_entry.ip <= arp_entry.ip;
arp_entry.is_valid <= arp_entry.is_valid;
arp_entry.reply_required <= '0';
arp_req_count <= arp_req_count;
elsif send_request_needed = '1' then
-- set up the arp entry to take the request to be transmitted out by the TX FSM
arp_entry.ip <= req_ip_addr;
arp_entry.mac <= (others => '0');
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
else
arp_entry <= arp_entry;
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
tx_combinatorial : process (
-- input signals
data_out_ready, send_request_needed, mac_tx_granted, our_mac_address, our_ip_address,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, arp_entry,
-- control signals
next_rx_state, set_rx_state, tx_count_mode, kill_data_out_valid,
set_chn_reqd, clear_reply_req)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set initial values for combinatorial outputs
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when OTHERS => data_out_valid <= '0';
end case;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
clear_reply_req <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if arp_entry.reply_required = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_request_needed = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" =>
data_out_first <= data_out_ready;
data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= x"ff";
when x"02" => data_out <= x"ff";
when x"03" => data_out <= x"ff";
when x"04" => data_out <= x"ff";
when x"05" => data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if arp_entry.is_valid = '1' then
data_out <= x"02"; -- 02 : REPLY if arp_entry valid
else
data_out <= x"01"; -- 01 : REQ if arp_entry invalid
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= arp_entry.mac (47 downto 40); -- target mac
when x"21" => data_out <= arp_entry.mac (39 downto 32);
when x"22" => data_out <= arp_entry.mac (31 downto 24);
when x"23" => data_out <= arp_entry.mac (23 downto 16);
when x"24" => data_out <= arp_entry.mac (15 downto 8);
when x"25" => data_out <= arp_entry.mac (7 downto 0);
when x"26" => data_out <= arp_entry.ip (31 downto 24); -- target ip
when x"27" => data_out <= arp_entry.ip (23 downto 16);
when x"28" => data_out <= arp_entry.ip (15 downto 8);
when x"29" =>
data_out <= arp_entry.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
clear_reply_req <= '1'; -- reset the reply request (done in the rx clk process domain)
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (data_out_clk,reset)
begin
if rising_edge(data_out_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_mac_chn_reqd <= '0';
else
-- Next rx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2_HDLC.vhd | 3 | 8523 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(8 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(8 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r,isflag : std_logic;
signal byte_out : std_logic_vector (8 downto 0);
signal dataByte : std_logic_vector (8 downto 0) := (others=>'1');
signal byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= '1' & HDLC_flag;
we <= '1';
else
dataByte <= '0' & edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= byte_out(8); --'1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out(7 downto 0);
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN8.vhd | 1 | 3937 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 8bit input
entity EPROC_IN8 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8;
architecture Behavioral of EPROC_IN8 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN8_direct_inst: entity work.EPROC_IN8_direct
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN8_DEC8b10b_inst: entity work.EPROC_IN8_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN2_direct.vhd | 1 | 3427 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN2_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_direct;
architecture Behavioral of EPROC_IN2_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic_vector (1 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 3
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= (others=>'0');
elsif bitCLK'event and bitCLK = '1' then
inpcount <= inpcount + 1;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when "00" => word8b(1 downto 0) <= edataIN;
when "01" => word8b(3 downto 2) <= edataIN;
when "10" => word8b(5 downto 4) <= edataIN;
when "11" => word8b(7 downto 6) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if inpcount = "11" then
word8bRdy <= '1';
else
word8bRdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 |
tdotu/ra | halfAdder.vhd | 1 | 312 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY halfAdder IS
PORT (
in1 : IN std_logic;
in2 : IN std_logic;
res : OUT std_logic;
carry : OUT std_logic
);
END halfAdder;
ARCHITECTURE behavior OF halfAdder IS
BEGIN
res <= in1 XOR in2;
carry <= in1 AND in2;
END behavior;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/level0_wrapper.vhd | 1 | 13403 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 28.04.2017 14:18:44
-- Design Name: Level-0 Wrapper
-- Module Name: level0_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Wrapper that contains all necessary modules for implementing
-- level0 readout of the VMMs
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;
entity level0_wrapper is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
clk : in std_logic; -- buffer read domain
rst_buff : in std_logic; -- reset buffer
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic;
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
linkHealth_bmsk : out std_logic_vector(8 downto 1);
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end level0_wrapper;
architecture RTL of level0_wrapper is
component l0_deserializer_decoder
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
level_0 : in std_logic; -- level-0 signal
------------------------------------
-------- Buffer Interface ----------
inhib_wr : in std_logic;
commas_true : out std_logic;
dout_dec : out std_logic_vector(7 downto 0);
wr_en : out std_logic;
------------------------------------
---------- VMM Interface -----------
vmm_data0 : in std_logic;
vmm_data1 : in std_logic
);
end component;
component l0_buffer_wrapper is
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic;
clk : in std_logic;
rst_buff : in std_logic;
wr_accept : in std_logic;
level_0 : in std_logic;
------------------------------------
--- Deserializer Interface ---------
inhib_wr : out std_logic;
commas_true : in std_logic;
dout_dec : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic
);
end component;
component l0_link_health
Generic(is_mmfe8 : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
vmm_conf : in std_logic;
daqOn_inhibit : out std_logic;
------------------------------------
--- Deserializer Interface ---------
commas_true : in std_logic_vector(8 downto 1);
------------------------------------
---- Packet Formation Interface ----
EventDone_dummy : out std_logic_vector(8 downto 1);
linkHealth_bitmask : out std_logic_vector(8 downto 1)
);
end component;
type dout_dec_array is array (8 downto 1) of std_logic_vector(7 downto 0);
type vmmWord_array is array (8 downto 1) of std_logic_vector(15 downto 0);
signal wr_en : std_logic_vector(8 downto 1) := (others => '0');
signal rd_ena_buff_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWordReady_i : std_logic_vector(8 downto 1) := (others => '0');
signal EventDone_health_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmmEventDone_i : std_logic_vector(8 downto 1) := (others => '0');
signal inhib_wr_i : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_i : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_s0 : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_s1 : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_i : vmmWord_array;
signal dout_dec : dout_dec_array;
attribute ASYNC_REG : string;
attribute ASYNC_REG of commas_true_s0 : signal is "TRUE";
attribute ASYNC_REG of commas_true_s1 : signal is "TRUE";
-- function to convert std_logic to integer for instance generation
function sl2int (x: std_logic) return integer is
begin
if(x='1')then
return 8;
else
return 1;
end if;
end;
begin
---------------------------------------------
------- Add VMM Readout Instances -----------
---------------------------------------------
readout_instances: for I in 1 to sl2int(is_mmfe8) generate
des_dec_inst: l0_deserializer_decoder
Port Map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt,
level_0 => level_0,
------------------------------------
-------- Buffer Interface ----------
inhib_wr => inhib_wr_i(I),
commas_true => commas_true_i(I),
dout_dec => dout_dec(I),
wr_en => wr_en(I),
------------------------------------
---------- VMM Interface -----------
vmm_data0 => vmm_data0_vec(I),
vmm_data1 => vmm_data1_vec(I)
);
l0_buf_wr_inst: l0_buffer_wrapper
Port Map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt,
clk => clk,
rst_buff => rst_buff,
wr_accept => wr_accept,
level_0 => level_0,
------------------------------------
--- Deserializer Interface ---------
inhib_wr => inhib_wr_i(I),
commas_true => commas_true_i(I),
dout_dec => dout_dec(I),
wr_en => wr_en(I),
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff => rd_ena_buff_i(I),
rst_intf_proc => rst_intf_proc,
vmmWordReady => vmmWordReady_i(I),
vmmWord => vmmWord_i(I),
vmmEventDone => vmmEventDone_i(I)
);
end generate readout_instances;
-- check comma alignment
l0_link_health_inst: l0_link_health
Generic Map(is_mmfe8 => is_mmfe8)
Port Map(
------------------------------------
------- General Interface ----------
clk => clk,
vmm_conf => vmm_conf,
daqOn_inhibit => daq_on_inhib,
------------------------------------
--- Deserializer Interface ---------
commas_true => commas_true_s1,
------------------------------------
---- Packet Formation Interface ----
EventDone_dummy => EventDone_health_i,
linkHealth_bitmask => linkHealth_bmsk
);
sync_linkHealth: process(clk)
begin
if(rising_edge(clk))then
commas_true_s0 <= commas_true_i;
commas_true_s1 <= commas_true_s0;
end if;
end process;
-- multiplexer that drives the packet formation signals corresponding to the vmmID
vmm_ID_MUX: process(vmmId, vmmWordReady_i, vmmWord_i, vmmEventDone_i, EventDone_health_i, rd_ena_buff)
begin
case vmmId is
when "000" =>
vmmWordReady <= vmmWordReady_i(1) and not EventDone_health_i(1);
vmmWord <= vmmWord_i(1);
vmmEventDone <= vmmEventDone_i(1) or EventDone_health_i(1);
rd_ena_buff_i(1) <= rd_ena_buff;
rd_ena_buff_i(8 downto 2) <= (others => '0');
when "001" =>
vmmWordReady <= vmmWordReady_i(2) and not EventDone_health_i(2);
vmmWord <= vmmWord_i(2);
vmmEventDone <= vmmEventDone_i(2) or EventDone_health_i(2);
rd_ena_buff_i(2) <= rd_ena_buff;
rd_ena_buff_i(8 downto 3) <= (others => '0');
rd_ena_buff_i(1 downto 1) <= (others => '0');
when "010" =>
vmmWordReady <= vmmWordReady_i(3) and not EventDone_health_i(3);
vmmWord <= vmmWord_i(3);
vmmEventDone <= vmmEventDone_i(3) or EventDone_health_i(3);
rd_ena_buff_i(3) <= rd_ena_buff;
rd_ena_buff_i(8 downto 4) <= (others => '0');
rd_ena_buff_i(2 downto 1) <= (others => '0');
when "011" =>
vmmWordReady <= vmmWordReady_i(4) and not EventDone_health_i(4);
vmmWord <= vmmWord_i(4);
vmmEventDone <= vmmEventDone_i(4) or EventDone_health_i(4);
rd_ena_buff_i(4) <= rd_ena_buff;
rd_ena_buff_i(8 downto 5) <= (others => '0');
rd_ena_buff_i(3 downto 1) <= (others => '0');
when "100" =>
vmmWordReady <= vmmWordReady_i(5) and not EventDone_health_i(5);
vmmWord <= vmmWord_i(5);
vmmEventDone <= vmmEventDone_i(5) or EventDone_health_i(5);
rd_ena_buff_i(5) <= rd_ena_buff;
rd_ena_buff_i(8 downto 6) <= (others => '0');
rd_ena_buff_i(4 downto 1) <= (others => '0');
when "101" =>
vmmWordReady <= vmmWordReady_i(6) and not EventDone_health_i(6);
vmmWord <= vmmWord_i(6);
vmmEventDone <= vmmEventDone_i(6) or EventDone_health_i(6);
rd_ena_buff_i(6) <= rd_ena_buff;
rd_ena_buff_i(8 downto 7) <= (others => '0');
rd_ena_buff_i(5 downto 1) <= (others => '0');
when "110" =>
vmmWordReady <= vmmWordReady_i(7) and not EventDone_health_i(7);
vmmWord <= vmmWord_i(7);
vmmEventDone <= vmmEventDone_i(7) or EventDone_health_i(7);
rd_ena_buff_i(7) <= rd_ena_buff;
rd_ena_buff_i(6 downto 1) <= (others => '0');
rd_ena_buff_i(8) <= '0';
when "111" =>
vmmWordReady <= vmmWordReady_i(8) and not EventDone_health_i(8);
vmmWord <= vmmWord_i(8);
vmmEventDone <= vmmEventDone_i(8) or EventDone_health_i(8);
rd_ena_buff_i(8) <= rd_ena_buff;
rd_ena_buff_i(7 downto 1) <= (others => '0');
when others =>
vmmWordReady <= '0';
vmmWord <= (others => '0');
rd_ena_buff_i <= (others => '0');
vmmEventDone <= '0';
end case;
end process;
vmm_cktk_vec(1) <= level_0;
vmm_cktk_vec(2) <= level_0;
vmm_cktk_vec(3) <= level_0;
vmm_cktk_vec(4) <= level_0;
vmm_cktk_vec(5) <= level_0;
vmm_cktk_vec(6) <= level_0;
vmm_cktk_vec(7) <= level_0;
vmm_cktk_vec(8) <= level_0;
end RTL; | gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/vmm_global_reset.vhd | 1 | 5193 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--
-- global reset
-- -----
-- ENA ------- --------
-- ---------
-- WEN ----- ------
--
-- IEEE VHDL standard library:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_global_reset is
port( clk : in std_logic; -- 100MHz
rst : in std_logic; -- reset
gbl_rst : in std_logic ; -- from control register. a pulse
vmm_ena : out std_logic ; -- these will be ored with same from other sm
vmm_wen : out std_logic -- these will be ored with same from other sm
);
end vmm_global_reset ;
architecture beh of vmm_global_reset is
signal state_switch_count : std_logic_vector(31 downto 0) := x"00010000"; --fast
signal cfg_rst_ctr : std_logic_vector(31 downto 0) := x"00000000";
signal state_nxt : std_logic_vector(2 downto 0) ;
signal vmm_wen_int, vmm_ena_int : std_logic ;
signal gbl_rst_int, done_int : std_logic ;
attribute keep: boolean;
attribute keep of vmm_ena_int: signal is true;
attribute keep of vmm_wen_int: signal is true;
attribute keep of cfg_rst_ctr: signal is true;
begin
process( clk, rst, done_int, gbl_rst, gbl_rst_int)
begin
if( rst = '1' or done_int = '1') then
gbl_rst_int <= '0' ;
else
if( rising_edge( clk)) then --100MHz
if (gbl_rst = '1') then
gbl_rst_int <= '1' ;
end if ;
end if ;
end if ;
end process ;
process( clk, state_nxt, rst, gbl_rst_int, vmm_ena_int, vmm_wen_int)
begin
if ( rising_edge( clk)) then --100MHz
if (rst = '1') then
state_nxt <= (others=>'0') ;
done_int <= '0' ;
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
cfg_rst_ctr <= (others=>'0') ;
else
case state_nxt is
when "000" =>
vmm_wen_int <= '0' ;
vmm_ena_int <= '0' ;
done_int <= '0' ;
if (gbl_rst_int = '1') then
state_nxt <= "001" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "000" ;
end if ;
when "001" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "010" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "001" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "010" =>
vmm_ena_int <= '1' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "011" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "010" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "011" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "100" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "011" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "100" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
state_nxt <= "000" ;
done_int <= '1' ;
when others => vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
done_int <= '1' ;
state_nxt <= (others=>'0') ;
end case ;
end if ;
end if;
end process ;
vmm_wen <= vmm_wen_int ;
vmm_ena <= vmm_ena_int ;
end beh ;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/8b10_dec.vhd | 4 | 8430 | -------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/temac_10_100_1000_config_vector_sm.vhd | 2 | 11959 | --------------------------------------------------------------------------------
-- File : temac_10_100_1000_config_vector_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up the MAC
-- to enable basic packet transfer in both directions.
-- Due to the lack of a management interface the PHy cannot be
-- accessed and therefore this solution will not work when
-- targeted to a demo platform unless some other method of enabing the PHY
-- is used.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0)
);
end temac_10_100_1000_config_vector_sm;
architecture rtl of temac_10_100_1000_config_vector_sm is
constant RUN_HALF_DUPLEX : std_logic := '0';
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
type state_typ is (STARTUP,
RESET_MAC,
CHECK_SPEED);
---------------------------------------------------
-- Signal declarations
signal control_status : state_typ;
signal update_speed_reg : std_logic;
signal update_speed_reg2 : std_logic;
signal update_speed_sync : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '0');
signal tx_reset : std_logic;
signal tx_enable : std_logic;
signal tx_vlan_enable : std_logic;
signal tx_fcs_enable : std_logic;
signal tx_jumbo_enable : std_logic;
signal tx_fc_enable : std_logic;
signal tx_hd_enable : std_logic;
signal tx_ifg_adjust : std_logic;
signal tx_speed : std_logic_vector(1 downto 0);
signal tx_max_frame_enable : std_logic;
signal tx_max_frame_length : std_logic_vector(14 downto 0);
signal tx_pause_addr : std_logic_vector(47 downto 0);
signal rx_reset : std_logic;
signal rx_enable : std_logic;
signal rx_vlan_enable : std_logic;
signal rx_fcs_enable : std_logic;
signal rx_jumbo_enable : std_logic;
signal rx_fc_enable : std_logic;
signal rx_hd_enable : std_logic;
signal rx_len_type_chk_disable : std_logic;
signal rx_control_len_chk_dis : std_logic;
signal rx_promiscuous : std_logic;
signal rx_speed : std_logic_vector(1 downto 0);
signal rx_max_frame_enable : std_logic;
signal rx_max_frame_length : std_logic_vector(14 downto 0);
signal rx_pause_addr : std_logic_vector(47 downto 0);
signal gtx_reset : std_logic;
begin
gtx_reset <= not gtx_resetn;
rx_configuration_vector <= rx_pause_addr &
'0' & rx_max_frame_length &
'0' & rx_max_frame_enable &
rx_speed &
rx_promiscuous &
'0' & rx_control_len_chk_dis &
rx_len_type_chk_disable &
'0' & rx_hd_enable &
rx_fc_enable &
rx_jumbo_enable &
rx_fcs_enable &
rx_vlan_enable &
rx_enable &
rx_reset;
tx_configuration_vector <= tx_pause_addr &
'0' & tx_max_frame_length &
'0' & tx_max_frame_enable &
tx_speed &
"000" & tx_ifg_adjust &
'0' & tx_hd_enable &
tx_fc_enable &
tx_jumbo_enable &
tx_fcs_enable &
tx_vlan_enable &
tx_enable &
tx_reset;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (zero)
gen_count : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
count_shift <= count_shift(19 downto 0) & (gtx_reset or tx_reset);
end if;
end process gen_count;
upspeed_sync : temac_10_100_1000_sync_block
port map (
clk => gtx_clk,
data_in => update_speed,
data_out => update_speed_sync
);
-- capture update_spped as only want to react to one edge
capture_update : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_reset = '1' then
update_speed_reg <= '0';
update_speed_reg2 <= '0';
else
update_speed_reg <= update_speed_sync;
update_speed_reg2 <= update_speed_reg;
end if;
end if;
end process capture_update;
------------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control
------------------------------------------------------------------------------
gen_state : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_reset = '1' then
tx_reset <= '0';
tx_enable <= '1';
tx_vlan_enable <= '0';
tx_fcs_enable <= '0';
tx_jumbo_enable <= '1';
tx_fc_enable <= '1';
tx_hd_enable <= RUN_HALF_DUPLEX;
tx_ifg_adjust <= '0';
tx_speed <= mac_speed;
tx_max_frame_enable <= '0';
tx_max_frame_length <= (others => '0');
tx_pause_addr <= X"0605040302DA";
rx_reset <= '0';
rx_enable <= '1';
rx_vlan_enable <= '0';
rx_fcs_enable <= '0';
rx_jumbo_enable <= '1';
rx_fc_enable <= '1';
rx_hd_enable <= RUN_HALF_DUPLEX;
rx_len_type_chk_disable <= '0';
rx_control_len_chk_dis <= '0';
rx_promiscuous <= '0';
rx_speed <= mac_speed;
rx_max_frame_enable <= '0';
rx_max_frame_length <= (others => '0');
rx_pause_addr <= X"0605040302DA";
control_status <= STARTUP;
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
else
case control_status is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if count_shift(20) = '0' then
control_status <= RESET_MAC;
end if;
when RESET_MAC =>
assert false
report "Reseting MAC" & cr
severity note;
tx_reset <= '1';
rx_reset <= '1';
rx_speed <= mac_speed;
tx_speed <= mac_speed;
control_status <= CHECK_SPEED;
when CHECK_SPEED =>
-- hold the local resets for 20 gtx cycles to ensure
-- the tx is captured by the mac
if count_shift(20) = '1' then
tx_reset <= '0';
rx_reset <= '0';
end if;
if update_speed_reg = '1' and update_speed_reg2 = '0' then
control_status <= RESET_MAC;
end if;
when others =>
control_status <= STARTUP;
end case;
end if;
end if;
end process gen_state;
end rtl;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_FIFO_DRIVER.vhd | 1 | 21682 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal BLOCK_HEADER : std_logic_vector (31 downto 0) := (others => '0');
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send_1st_clk : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal receiving_state_clk40, do_transmit_timeout_trailers,timout_ena,timeout_trailer_send : std_logic := '0';
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
process(clk40,rst)
begin
if rst = '1' then
receiving_state_clk40 <= '0';
elsif rising_edge (clk40) then
receiving_state_clk40 <= receiving_state;
end if;
end process;
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
elsif rising_edge (clk40) then
if receiving_state_clk40 = '1' then
timeCnt_lastClk <= timeCntIn;
end if;
end if;
end process;
--
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send_1st_clk);
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif ((DIN_RDY = '1' and DIN(9 downto 8) /= "11") or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timeout_trailer_send <= '0';
elsif rising_edge (clk160) then
if timeout_trailer_send_1st_clk = '1' then
timeout_trailer_send <= '1';
elsif data16bit_rdy = '1' then -- timeout_trailer was sent once, the rest of the block will be filled with null-trailers
timeout_trailer_send <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if receiving_state = '1' then
timout_ena <= '1';
elsif do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if do_transmit_timeout_trailers = '0' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_s <= "0100000000";
DIN_RDY_s <= '1';
end if;
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= DIN_RDY_s; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- DIN_r <= DIN_s(7 downto 0);
-- end if;
--end process;
--
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- if direct_data_mode = '1' then
-- if DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1' then
-- DIN_CODE_r <= "10"; -- soc
-- else
-- DIN_CODE_r <= "00"; -- data
-- end if;
-- else
-- DIN_CODE_r <= DIN_s(9 downto 8);
-- end if;
-- end if;
--end process;
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8))
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
DIN_CODE_r <= DIN_s(9 downto 8);
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK;
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
--BLOCK_HEADER <= "1010101111001101" & "00000" & "0000" & egroupID & '0' & epathID; -- 0xABCD_
--std_logic_vector(to_unsigned(GBTid, 5))
-- [0xABCD_16] [[00000_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & "00000" & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
PORT MAP(
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
BLOCK_HEADER => BLOCK_HEADER,
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2.vhd | 1 | 4930 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! 80 Mbps E-link processor, 2bit input @ clk40
entity EPROC_IN2 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_inputbits : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal edata_in_s : std_logic_vector (1 downto 0);
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
--
in_sel: process(swap_inputbits,EDATA_IN)
begin
if swap_inputbits = '1' then
edata_in_s <= EDATA_IN(0) & EDATA_IN(1);
else
edata_in_s <= EDATA_IN;
end if;
end process;
--
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
--
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => edata_in_s,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => edata_in_s,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => edata_in_s,
dataOUT => DATA_OUT_HDLC_case,
dataOUTrdy => DATA_RDY_HDLC_case
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/arp_RX.vhd | 2 | 13223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_rx is
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
architecture Behavioral of arp_rx is
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
type tx_state_type is (IDLE, WAIT_MAC, SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 41 then -- TB 2013-01-14 15:09:45 was 42
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
-- end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT4_ENC8b10b.vhd | 4 | 6466 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT4_ENC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT4 module
entity EPROC_OUT4_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(3 downto 0) -- ready on every bitCLK
);
end EPROC_OUT4_ENC8b10b;
architecture Behavioral of EPROC_OUT4_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros4bit : std_logic_vector (3 downto 0) := "0000";
signal enc10bit, enc10bit0, enc10bit1 : std_logic_vector (9 downto 0);
signal enc10bit_x2_r : std_logic_vector (19 downto 0) := (others=>'0');
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig, word_cnt : std_logic := '0';
signal inp_request_trig, inp_request_trig_out, enc10bitRdy : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs, request is 2 clks wide, 2 bytes at a time
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then -- meaning request_cycle_cnt = "100"
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>2) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig; -- slow clock output trigger
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit,
encDataOutrdy => enc10bitRdy
);
-------------------------------------------------------------------------------------------
-- sending out 4 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
word_cnt <= not word_cnt;
else
word_cnt <= '0';
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
if word_cnt = '0' then
enc10bit0 <= enc10bit;
else
enc10bit1 <= enc10bit;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- slow clock logic
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_x2_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_x2_r <= enc10bit1 & enc10bit0;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>4)
port map (
data0 => enc10bit_x2_r(3 downto 0),
data1 => enc10bit_x2_r(7 downto 4),
data2 => enc10bit_x2_r(11 downto 8),
data3 => enc10bit_x2_r(15 downto 12),
data4 => enc10bit_x2_r(19 downto 16),
data5 => zeros4bit,
data6 => zeros4bit,
data7 => zeros4bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/MUX2_Nbit.vhd | 4 | 1222 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 2x1, data 16 bit
entity MUX2_Nbit is
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX2_Nbit;
--architecture low_level_MUX2_Nbit of MUX2_Nbit is
--begin
--GENERATE_BIT_MUX2: for I in 0 to (N-1) generate
--MUXF7n : MUXF7 port map (data_out(I), data0(I), data1(I), sel);
--end generate GENERATE_BIT_MUX2;
--end low_level_MUX2_Nbit;
architecture behavioral of MUX2_Nbit is
begin
process(data0, data1, sel)
begin
if sel = '0' then
data_out <= data0;
else
data_out <= data1;
end if;
end process;
end behavioral; | gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN2_ALIGN_BLOCK.vhd | 1 | 1553 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--!
entity EPROC_IN2_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in std_logic_vector(9 downto 0);
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN2_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN2_ALIGN_BLOCK is
begin
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap --
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => bytes,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
rdy_pipe: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(bitCLKx4,bytes_rdy,dataOUTrdy);
--
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN4.vhd | 1 | 3940 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
---
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/arpv2.vhd | 2 | 13310 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arpv2 is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- though a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0) := (others => '0'); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0) := (others => '0'); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end arpv2;
architecture structural of arpv2 is
component arp_req
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_tx
port(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_rx
port(
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_sync
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end component;
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : std_logic_vector (31 downto 0);
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int : arp_store_result_t; -- lookup result
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int : arp_entry_t;
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
begin
req : arp_req
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
port map (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
clk => data_in_clk,
reset => reset
);
sync : arp_sync port map (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
tx : arp_tx port map (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
rx : arp_rx port map (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have => arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
end structural;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_TX.vhd | 2 | 11282 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added abort of tx when receive last from upstream
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
end UDP_TX;
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 8966 then
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING; -- 01
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
set_tx_state <= '1';
end if;
end if;
when PAUSE =>
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then -- 10
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT; --11
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif udp_txi.data.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_ERR; --10
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/centralRouter_package.vhd | 2 | 20363 | --!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
-- 1. 10-bit values
--- comma / idle character
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- -K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- +K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- -K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- +K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- -K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- +K.28.3
-- 2. 8-bit values
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
-------------------------------------------------------------------
-- TTC ToHost Data type
-------------------------------------------------------------------
type TTC_ToHost_data_type is record
FMT : std_logic_vector(7 downto 0); --byte0
LEN : std_logic_vector(7 downto 0); --byte1
reserved0 : std_logic_vector(3 downto 0); --byte2
BCID : std_logic_vector(11 downto 0); --byte2,3
XL1ID : std_logic_vector(7 downto 0); --byte4
L1ID : std_logic_vector(23 downto 0); --byte 5,6,7
orbit : std_logic_vector(31 downto 0); --byte 8,9,10,11
trigger_type : std_logic_vector(15 downto 0); --byte 12,13
reserved1 : std_logic_vector(15 downto 0); --byte 14,15
L0ID : std_logic_vector(31 downto 0); --byte 16,17,18,19
data_rdy : std_logic;
end record;
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"000000000000110",
"000000001111000",
"000000000000001",
"111111110000000",
"110011000101000",
"001100111010000",
"110011000101000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
constant zeros17bits : std_logic_vector(16 downto 0) := (others=>'0');
constant zeros21bits : std_logic_vector(20 downto 0) := (others =>'0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
| gpl-3.0 |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/event_timing_reset.vhd | 2 | 3646 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.numeric_std.all;
use IEEE.numeric_bit.all;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.vcomponents.all;
entity event_timing_reset is
port(
hp_clk : in std_logic; -- High precision clock 1 GHz
bc_clk : in std_logic; -- 40MHz
trigger : in std_logic;
readout_done : in std_logic;
reset : in std_logic; -- reset
bcid : out std_logic_vector(12 downto 0); -- 13 bits 12 for counting to 0xFFF and the MSB as a signal to auto reset.
prec_cnt : out std_logic_vector(4 downto 0); -- 5 bits are more than enough (32) while 1-25 used
vmm_ena : out std_logic; -- these will be ored with same from other sm. This should evolve to a vector.
vmm_wen : out std_logic -- these will be ored with same from other sm. This should evolve to a vector.
);
end event_timing_reset;
architecture Behavioral of event_timing_reset is
-- Signals
signal bcid_i : std_logic_vector(12 downto 0) := b"0000000000000";
signal prec_cnt_i : std_logic_vector(4 downto 0) := b"00000";
signal state_nxt : std_logic_vector(2 downto 0);
signal vmm_wen_int, vmm_ena_int : std_logic;
signal acq_rst_int, acq_rst_d : std_logic;
-- Components if any
begin
-- Processes
process (bc_clk)
begin
if (bc_clk'event and bc_clk = '1') then
end if;
end process;
process (bc_clk)
-- this process is an edge detect for acq_rst
begin
if rising_edge (bc_clk) then
end if;
end process;
-- process(clk, state_nxt, rst, acq_rst_int, vmm_ena_int, vmm_wen_int)
-- begin
-- if (rising_edge( clk)) then --100MHz
-- if (rst = '1') then
-- state_nxt <= (others=>'0');
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- else
-- case state_nxt is
-- when "000" =>
-- vmm_wen_int <= '0';
-- vmm_ena_int <= '0';
-- if (acq_rst_int = '1') then
-- state_nxt <= "001";
-- else
-- state_nxt <= "000" ;
-- end if ;
-- when "001" =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '1';
-- state_nxt <= "010";
-- state_nxt <= "001";
-- when "010" =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- state_nxt <= "000";
-- when others =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- state_nxt <= (others=>'0');
-- end case;
-- end if;
-- end if;
-- end process;
-- Signal assignment
vmm_wen <= vmm_wen_int;
vmm_ena <= vmm_ena_int;
prec_cnt <= prec_cnt_i;
bcid <= bcid_i;
-- Instantiations if any
end Behavioral; | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_blk_mem_gen_0_0/synth/OpenSSD2_blk_mem_gen_0_0.vhd | 4 | 14031 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY OpenSSD2_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END OpenSSD2_blk_mem_gen_0_0;
ARCHITECTURE OpenSSD2_blk_mem_gen_0_0_arch OF OpenSSD2_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_blk_mem_gen_0_0_arch : ARCHITECTURE IS "OpenSSD2_blk_mem_gen_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_blk_mem_gen_0_0_arch: ARCHITECTURE IS "OpenSSD2_blk_mem_gen_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=OpenSSD2_blk_mem_gen_0_0.mif,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.700549 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "OpenSSD2_blk_mem_gen_0_0.mif",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.700549 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END OpenSSD2_blk_mem_gen_0_0_arch;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/12.2/ml605/ml605_light/pcores/dcr_timebase_v1_00_b/hdl/vhdl/dcr_timebase.vhd | 9 | 6380 | --
-- \file dcr_timebase.vhd
--
-- Timebase pcore for measuring latencies between HW and SW
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
-- \author Enno Luebbers <[email protected]>
-- \date 06.05.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--library opb_ipif_v3_01_c;
--use opb_ipif_v3_01_c.all;
entity dcr_timebase is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32
);
port (
i_clk : in std_logic;
i_reset : in std_logic;
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
o_timeBase : out std_logic_vector(0 to C_DCR_DWIDTH-1);
o_irq : out std_logic
);
end dcr_timebase;
architecture implementation of dcr_timebase is
constant C_NUM_REGS : natural := 2;
signal dcrDBus : std_logic_vector( 0 to C_DCR_DWIDTH-1 );
signal dcrAck : std_logic;
signal dcrAddrHit : std_logic;
signal regAddr : std_logic_vector(0 to 0); -- FIXME: hardcoded
signal readCE : std_logic_vector(0 to C_NUM_REGS-1);
signal writeCE : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg0 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal timebase : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal set_timebase : std_logic := '0'; -- loads slv_reg0 into timebase when '1'
begin
-- generate outputs
o_dcrAck <= dcrAck;
o_dcrDBus <= dcrDBus;
-- 2 registers = 1 LSBs FIXME: hardcoded. Use log2 instead!
dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-2) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-2)
else '0';
regAddr <= i_dcrABus(C_DCR_AWIDTH-1 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite,
regAddr)
begin
-- clear all chip enables by default
for i in 0 to C_NUM_REGS-1 loop
readCE(i) <= '0';
writeCE(i) <= '0';
end loop;
-- decode register address and set
-- corresponding chip enable signal
if dcrAddrHit = '1' then
if i_dcrRead = '1' then
readCE(TO_INTEGER(unsigned(regAddr))) <= '1';
elsif i_dcrWrite = '1' then
writeCE(TO_INTEGER(unsigned(regAddr))) <= '1';
end if;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
dcrAck <= '0';
elsif rising_edge(i_clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and
dcrAddrHit;
end if;
end process;
--
-- update slave registers on write access
-- SYNCHRONOUS
--
reg_write_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
set_timebase <= '0';
elsif rising_edge(i_clk) then
set_timebase <= '0';
if dcrAck = '0' then -- register values only ONCE per write select
case writeCE is
when "01" =>
slv_reg0 <= i_dcrDBus;
set_timebase <= '1';
when "10" =>
slv_reg1 <= i_dcrDBus;
when others => null;
end case;
end if;
end if;
end process;
--
-- output slave registers on data bus on read access
-- ASYNCHRONOUS
--
reg_read_proc: process(readCE, timebase, slv_reg1,
i_dcrDBus)
begin
dcrDBus <= i_dcrDBus;
case readCE is
when "01" =>
dcrDBus <= timebase;
when "10" =>
dcrDBus <= slv_reg1;
when others =>
dcrDBus <= i_dcrDBus;
end case;
end process;
--
-- timebase register implementation
--
timebase_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
timebase <= (others => '0');
elsif rising_edge(i_clk) then
if set_timebase = '1' then
timebase <= slv_reg0;
else
timebase <= STD_LOGIC_VECTOR(UNSIGNED(timebase) + 1);
end if;
end if;
end process;
o_timeBase <= timebase;
o_irq <= '1' when timebase = X"FFFFFFFF" else '0';
end implementation;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/12.3/ml605/ml605_light_eth/pcores/dcr_timebase_v1_00_b/hdl/vhdl/dcr_timebase.vhd | 9 | 6380 | --
-- \file dcr_timebase.vhd
--
-- Timebase pcore for measuring latencies between HW and SW
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
-- \author Enno Luebbers <[email protected]>
-- \date 06.05.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--library opb_ipif_v3_01_c;
--use opb_ipif_v3_01_c.all;
entity dcr_timebase is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32
);
port (
i_clk : in std_logic;
i_reset : in std_logic;
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
o_timeBase : out std_logic_vector(0 to C_DCR_DWIDTH-1);
o_irq : out std_logic
);
end dcr_timebase;
architecture implementation of dcr_timebase is
constant C_NUM_REGS : natural := 2;
signal dcrDBus : std_logic_vector( 0 to C_DCR_DWIDTH-1 );
signal dcrAck : std_logic;
signal dcrAddrHit : std_logic;
signal regAddr : std_logic_vector(0 to 0); -- FIXME: hardcoded
signal readCE : std_logic_vector(0 to C_NUM_REGS-1);
signal writeCE : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg0 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal timebase : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal set_timebase : std_logic := '0'; -- loads slv_reg0 into timebase when '1'
begin
-- generate outputs
o_dcrAck <= dcrAck;
o_dcrDBus <= dcrDBus;
-- 2 registers = 1 LSBs FIXME: hardcoded. Use log2 instead!
dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-2) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-2)
else '0';
regAddr <= i_dcrABus(C_DCR_AWIDTH-1 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite,
regAddr)
begin
-- clear all chip enables by default
for i in 0 to C_NUM_REGS-1 loop
readCE(i) <= '0';
writeCE(i) <= '0';
end loop;
-- decode register address and set
-- corresponding chip enable signal
if dcrAddrHit = '1' then
if i_dcrRead = '1' then
readCE(TO_INTEGER(unsigned(regAddr))) <= '1';
elsif i_dcrWrite = '1' then
writeCE(TO_INTEGER(unsigned(regAddr))) <= '1';
end if;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
dcrAck <= '0';
elsif rising_edge(i_clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and
dcrAddrHit;
end if;
end process;
--
-- update slave registers on write access
-- SYNCHRONOUS
--
reg_write_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
set_timebase <= '0';
elsif rising_edge(i_clk) then
set_timebase <= '0';
if dcrAck = '0' then -- register values only ONCE per write select
case writeCE is
when "01" =>
slv_reg0 <= i_dcrDBus;
set_timebase <= '1';
when "10" =>
slv_reg1 <= i_dcrDBus;
when others => null;
end case;
end if;
end if;
end process;
--
-- output slave registers on data bus on read access
-- ASYNCHRONOUS
--
reg_read_proc: process(readCE, timebase, slv_reg1,
i_dcrDBus)
begin
dcrDBus <= i_dcrDBus;
case readCE is
when "01" =>
dcrDBus <= timebase;
when "10" =>
dcrDBus <= slv_reg1;
when others =>
dcrDBus <= i_dcrDBus;
end case;
end process;
--
-- timebase register implementation
--
timebase_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
timebase <= (others => '0');
elsif rising_edge(i_clk) then
if set_timebase = '1' then
timebase <= slv_reg0;
else
timebase <= STD_LOGIC_VECTOR(UNSIGNED(timebase) + 1);
end if;
end if;
end process;
o_timeBase <= timebase;
o_irq <= '1' when timebase = X"FFFFFFFF" else '0';
end implementation;
| gpl-3.0 |
iti-luebeck/RTeasy2 | RTeasy/src/vhdltmpl/mult.vhd | 3 | 27202 | -- VHDL model of UNNAMED
-- generated by RTeasy
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
-- generic components
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
-- CONTROL UNIT
-- combinatorial circuit for state transition function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_statetrans_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
CONSTANT endstate : std_logic_vector(1 DOWNTO 0) := "11";
END UNNAMED_cu_statetrans_net;
ARCHITECTURE behavioural OF UNNAMED_cu_statetrans_net IS
BEGIN
statetrans: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
NEXTSTATE <= "01";
WHEN "01" =>
NEXTSTATE <= "10";
WHEN "10" => -- LOOP:
IF I(0)='1' THEN -- if FAKTOR <> 0 then goto LOOP fi
NEXTSTATE <= "10";
ELSE
NEXTSTATE <= endstate;
END IF;
WHEN OTHERS =>
NEXTSTATE <= endstate;
END CASE;
END PROCESS;
END behavioural;
-- combinatorial circuit for output function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_output_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END UNNAMED_cu_output_net;
ARCHITECTURE behavioural OF UNNAMED_cu_output_net IS
BEGIN
output: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
C(0) <= '1';
C(1) <= '1';
C(2) <= '0';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "01" =>
C(0) <= '0';
C(1) <= '0';
C(2) <= '1';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "10" => -- LOOP:
C(0) <= '0';
C(1) <= '0';
C(2) <= '0';
-- if FAKTOR <> 0 then ERG <- ERG + A fi
C(3) <= I(0);
-- if FAKTOR <> 0 then FAKTOR <- FAKTOR - 1 fi
C(4) <= I(0);
-- if not FAKTOR <> 0 then OUTBUS <- ERG fi
C(5) <= NOT (I(0));
WHEN OTHERS =>
C <= (OTHERS => '0');
END CASE;
END PROCESS;
END behavioural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO 5);
I : IN std_logic_vector(0 TO 0)
);
END UNNAMED_cu;
ARCHITECTURE struct OF UNNAMED_cu IS
SIGNAL I_BUFFERED : std_logic_vector(0 TO 0);
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL STATE, NEXTSTATE : std_logic_vector(1 DOWNTO 0);
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
COMPONENT UNNAMED_cu_statetrans_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_statetrans_net USE ENTITY
WORK.UNNAMED_cu_statetrans_net(behavioural);
COMPONENT UNNAMED_cu_output_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_output_net USE ENTITY
WORK.UNNAMED_cu_output_net(behavioural);
BEGIN
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => 1, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => 2, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: UNNAMED_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: UNNAMED_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
END struct;
-- OPERATION UNIT
-- circuits realizing register-transfer operations
-- realization of RT operation A <- INBUS
-- triggered by control signal C(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C0_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C0_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C0_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- 0
-- triggered by control signal C(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C1_circuit IS
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C1_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C1_circuit IS
BEGIN
-- 0
OUTPUT <= "00000000";
END primitive;
-- realization of RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C2_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C2_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C2_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- ERG + A
-- triggered by control signal C(3)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C3_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C3_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C3_circuit IS
BEGIN
-- ERG + A
OUTPUT <= ("0" & reg_ERG_out_0_7(0 TO 7)) + ("0" & reg_A_out_0_7(0 TO 7));
END primitive;
-- realization of RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C4_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C4_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C4_circuit IS
BEGIN
-- FAKTOR - 1
OUTPUT <= ("0" & reg_FAKTOR_out_0_7(0 TO 7)) + ((not ("000000001")) + "000000001");
END primitive;
-- realization of RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C5_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C5_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C5_circuit IS
BEGIN
-- ERG
OUTPUT <= reg_ERG_out_0_7(0 TO 7);
END primitive;
-- circuits realizing conditions
-- realization of condition FAKTOR <> 0
-- driving condition signal I(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_cond_I0_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END UNNAMED_cond_I0_circuit;
ARCHITECTURE primitive OF UNNAMED_cond_I0_circuit IS
BEGIN
-- FAKTOR <> 0
OUTPUT <= signed_ne(("0" & reg_FAKTOR_out_0_7(0 TO 7)), ("000000000"), 8);
END primitive;
-- register logic circuits
-- register logic for A
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_A_logic_circuit IS
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_A_logic_circuit;
ARCHITECTURE primitive OF reg_A_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C0_out_7_0(7) WHEN C0 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C0_out_7_0(6) WHEN C0 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C0_out_7_0(5) WHEN C0 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C0_out_7_0(4) WHEN C0 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C0_out_7_0(3) WHEN C0 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C0_out_7_0(2) WHEN C0 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C0_out_7_0(1) WHEN C0 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C0_out_7_0(0) WHEN C0 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for ERG
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_ERG_logic_circuit IS
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_ERG_logic_circuit;
ARCHITECTURE primitive OF reg_ERG_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C1_out_7_0(7) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(7) WHEN C3 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C1_out_7_0(6) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(6) WHEN C3 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C1_out_7_0(5) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(5) WHEN C3 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C1_out_7_0(4) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(4) WHEN C3 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C1_out_7_0(3) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(3) WHEN C3 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C1_out_7_0(2) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(2) WHEN C3 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C1_out_7_0(1) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(1) WHEN C3 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C1_out_7_0(0) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(0) WHEN C3 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for FAKTOR
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_FAKTOR_logic_circuit IS
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_FAKTOR_logic_circuit;
ARCHITECTURE primitive OF reg_FAKTOR_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C2_out_7_0(7) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(7) WHEN C4 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C2_out_7_0(6) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(6) WHEN C4 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C2_out_7_0(5) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(5) WHEN C4 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C2_out_7_0(4) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(4) WHEN C4 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C2_out_7_0(3) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(3) WHEN C4 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C2_out_7_0(2) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(2) WHEN C4 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C2_out_7_0(1) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(1) WHEN C4 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C2_out_7_0(0) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(0) WHEN C4 = '1'
ELSE FROM_reg(7);
END primitive;
-- bus zero driver logic circuits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for OUTBUS
ENTITY bus_OUTBUS_zero_driver_logic_circuit IS
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_OUTBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_OUTBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(1) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(2) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(3) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(4) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(5) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(6) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(7) <= '0' WHEN NOT C5='1' ELSE 'Z';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for INBUS
ENTITY bus_INBUS_zero_driver_logic_circuit IS
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_INBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_INBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0';
TO_bus(1) <= '0';
TO_bus(2) <= '0';
TO_bus(3) <= '0';
TO_bus(4) <= '0';
TO_bus(5) <= '0';
TO_bus(6) <= '0';
TO_bus(7) <= '0';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_ou IS
PORT(
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 TO 5);
I : OUT std_logic_vector(0 TO 0)
);
END UNNAMED_ou;
ARCHITECTURE struct OF UNNAMED_ou IS
-- signal declarations
SIGNAL CLK_SIG, RESET_SIG : std_logic;
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL I0 : std_logic_vector(0 DOWNTO 0);
SIGNAL bus_OUTBUS : std_logic_vector (0 TO 7);
SIGNAL bus_INBUS : std_logic_vector (0 TO 7);
SIGNAL reg_A_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_A_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_ERG_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_ERG_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_FAKTOR_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_FAKTOR_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
-- D-flipflop register component declaration
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
-- register logic component declarations
COMPONENT reg_A_logic_circuit
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_A_logic_circuit USE ENTITY WORK.reg_A_logic_circuit(primitive);
COMPONENT reg_ERG_logic_circuit
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_ERG_logic_circuit USE ENTITY WORK.reg_ERG_logic_circuit(primitive);
COMPONENT reg_FAKTOR_logic_circuit
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_FAKTOR_logic_circuit USE ENTITY WORK.reg_FAKTOR_logic_circuit(primitive);
-- bus zero driver logic component declarations
COMPONENT bus_OUTBUS_zero_driver_logic_circuit
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_OUTBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_OUTBUS_zero_driver_logic_circuit(primitive);
COMPONENT bus_INBUS_zero_driver_logic_circuit
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_INBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_INBUS_zero_driver_logic_circuit(primitive);
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
-- function for input forcing (to 0 and 1)
FUNCTION forceSL (b : std_logic) RETURN std_logic IS
BEGIN
CASE b IS
WHEN '1'|'H' => RETURN '1';
WHEN OTHERS => RETURN '0';
END CASE;
END forceSL;
-- declarations for register-transfer circuits and signals
-- RT operation A <- INBUS
-- triggered by control signal C(0)
SIGNAL rtop_C0_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C0_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C0_circuit USE ENTITY WORK.UNNAMED_rtop_C0_circuit(primitive);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
SIGNAL rtop_C1_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C1_circuit
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C1_circuit USE ENTITY WORK.UNNAMED_rtop_C1_circuit(primitive);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
SIGNAL rtop_C2_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C2_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C2_circuit USE ENTITY WORK.UNNAMED_rtop_C2_circuit(primitive);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
SIGNAL rtop_C3_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C3_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C3_circuit USE ENTITY WORK.UNNAMED_rtop_C3_circuit(primitive);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
SIGNAL rtop_C4_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C4_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C4_circuit USE ENTITY WORK.UNNAMED_rtop_C4_circuit(primitive);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
SIGNAL rtop_C5_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C5_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C5_circuit USE ENTITY WORK.UNNAMED_rtop_C5_circuit(primitive);
-- COMPONENT declarations for condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
COMPONENT UNNAMED_cond_I0_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cond_I0_circuit USE ENTITY WORK.UNNAMED_cond_I0_circuit(primitive);
BEGIN
CLK_SIG <= CLK; RESET_SIG <= RESET; C_SIG <= C;
-- register logic instantiations
-- register A
-- component instantiation for register A
reg_A: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_A_in,
OUTPUT => reg_A_out);
reg_A_logic: reg_A_logic_circuit
PORT MAP(
C0 => C_SIG(0),
rtop_C0_out_7_0 => rtop_C0_out(7 DOWNTO 0),
FROM_reg => reg_A_out,
TO_reg => reg_A_in);
-- register ERG
-- component instantiation for register ERG
reg_ERG: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_ERG_in,
OUTPUT => reg_ERG_out);
reg_ERG_logic: reg_ERG_logic_circuit
PORT MAP(
C1 => C_SIG(1),
C3 => C_SIG(3),
rtop_C1_out_7_0 => rtop_C1_out(7 DOWNTO 0),
rtop_C3_out_7_0 => rtop_C3_out(7 DOWNTO 0),
FROM_reg => reg_ERG_out,
TO_reg => reg_ERG_in);
-- register FAKTOR
-- component instantiation for register FAKTOR
reg_FAKTOR: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_FAKTOR_in,
OUTPUT => reg_FAKTOR_out);
reg_FAKTOR_logic: reg_FAKTOR_logic_circuit
PORT MAP(
C2 => C_SIG(2),
C4 => C_SIG(4),
rtop_C2_out_7_0 => rtop_C2_out(7 DOWNTO 0),
rtop_C4_out_7_0 => rtop_C4_out(7 DOWNTO 0),
FROM_reg => reg_FAKTOR_out,
TO_reg => reg_FAKTOR_in);
-- bus zero driver logic logic instantiations
bus_OUTBUS_zero_driver_logic: bus_OUTBUS_zero_driver_logic_circuit
PORT MAP(
C5 => C_SIG(5),
TO_bus => bus_OUTBUS);
bus_INBUS_zero_driver_logic: bus_INBUS_zero_driver_logic_circuit
PORT MAP(
TO_bus => bus_INBUS);
-- instantiations for register-transfer circuits
-- RT operation A <- INBUS
-- triggered by control signal C(0)
rtop_C0: UNNAMED_rtop_C0_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C0_out);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
rtop_C1: UNNAMED_rtop_C1_circuit
PORT MAP(
OUTPUT => rtop_C1_out);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
rtop_C2: UNNAMED_rtop_C2_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C2_out);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
rtop_C3: UNNAMED_rtop_C3_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
reg_A_out_0_7 => reg_A_out(0 TO 7),
OUTPUT => rtop_C3_out);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
rtop_C4: UNNAMED_rtop_C4_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_out(0 TO 7),
OUTPUT => rtop_C4_out);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
rtop_C5: UNNAMED_rtop_C5_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
OUTPUT => rtop_C5_out);
tristate_OUTBUS_0_7_C5: tristate
GENERIC MAP(width => 8)
PORT MAP(
ENABLE => C(5),
INPUT => rtop_C5_out(7 DOWNTO 0),
OUTPUT => bus_OUTBUS(0 TO 7));
-- instantiations of condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
I(0) <= I0(0);
cond_I0: UNNAMED_cond_I0_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_in(0 TO 7),
OUTPUT => I0);
END struct;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED IS
PORT(
CLK, RESET : IN std_logic
);
END UNNAMED;
ARCHITECTURE struct OF UNNAMED IS
SIGNAL CLK_SIGNAL, RESET_SIGNAL : std_logic;
SIGNAL C : std_logic_vector(0 to 5);
SIGNAL I : std_logic_vector(0 to 0);
COMPONENT UNNAMED_cu
PORT (
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 to 5);
I : IN std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu USE ENTITY WORK.UNNAMED_cu(struct);
COMPONENT UNNAMED_ou
PORT (
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 to 5);
I : OUT std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_ou USE ENTITY WORK.UNNAMED_ou(struct);
BEGIN
CLK_SIGNAL <= CLK;
RESET_SIGNAL <= RESET;
Control_Unit: UNNAMED_cu
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
Operation_Unit: UNNAMED_ou
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
END struct;
| gpl-3.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@m@u@x8_1/_primary.vhd | 2 | 708 | library verilog;
use verilog.vl_types.all;
entity MUX8_1 is
port(
Sel : in vl_logic_vector(2 downto 0);
S0 : in vl_logic_vector(7 downto 0);
S1 : in vl_logic_vector(7 downto 0);
S2 : in vl_logic_vector(7 downto 0);
S3 : in vl_logic_vector(7 downto 0);
S4 : in vl_logic_vector(7 downto 0);
S5 : in vl_logic_vector(7 downto 0);
S6 : in vl_logic_vector(7 downto 0);
S7 : in vl_logic_vector(7 downto 0);
\out\ : out vl_logic_vector(7 downto 0)
);
end MUX8_1;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/12.1/ml605/ml605_light/pcores/dcr_v29_v9_00_a/hdl/vhdl/or_muxcy.vhd | 7 | 10361 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| gpl-3.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@mux4_1/_primary.vhd | 2 | 465 | library verilog;
use verilog.vl_types.all;
entity Mux4_1 is
port(
Data0 : in vl_logic_vector(31 downto 0);
Data1 : in vl_logic_vector(31 downto 0);
Data2 : in vl_logic_vector(31 downto 0);
Data3 : in vl_logic_vector(31 downto 0);
Sel : in vl_logic_vector(1 downto 0);
Data : out vl_logic_vector(31 downto 0)
);
end Mux4_1;
| gpl-3.0 |
makestuff/vhdl | test000/test.vhd | 1 | 923 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:31 04/08/2010
-- Design Name:
-- Module Name: test - test_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
x : out STD_LOGIC);
end test;
architecture test_arch of test is
begin
x <= not a and not b;
end test_arch;
| gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/User_Demo/src/hdl/Pwm.vhd | 1 | 1481 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 18:46:55 03/05/2013
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the 8-bit PWM component, used by the RgbLed module
-- to generate the sweeping colors
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity Pwm is
port(
clk_i : in std_logic; -- system clock = 100MHz
data_i : in std_logic_vector(7 downto 0); -- the number to be modulated
pwm_o : out std_logic
);
end Pwm;
architecture Behavioral of Pwm is
signal cnt : std_logic_vector(7 downto 0);
begin
COUNT: process(clk_i)
begin
if rising_edge(clk_i) then
cnt <= cnt + '1';
end if;
end process COUNT;
COMPARE: process(data_i, cnt)
begin
if unsigned(cnt) < unsigned(data_i) then
pwm_o <= '1';
else
pwm_o <= '0';
end if;
end process COMPARE;
end Behavioral;
| gpl-3.0 |
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