repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
luebbers/reconos | support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/hdl/vhdl/dcr_if.vhd | 2 | 2760 | ------------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
------------------------------------------------------------------------------
-- Module and Port Declaration
------------------------------------------------------------------------------
entity dcr_if is
generic (
C_ON_INIT : std_logic_vector(31 downto 0) := X"0000_0000";
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := B"10_0000_0000"
);
port (
clk : in std_logic;
rst : in std_logic;
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
-- Registers
ctrl_reg : out std_logic_vector(31 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of clk : signal is "Clk";
attribute SIGIS of rst : signal is "Rst";
end entity dcr_if;
architecture IMP of dcr_if is
------------------------------------------------------------------------------
-- Signal Declaration
------------------------------------------------------------------------------
signal dcr_addr_hit : std_logic;
signal dcr_base_addr : std_logic_vector(9 downto 0);
signal dcr_read_access : std_logic;
signal read_data : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal ctrl_reg_sig : std_logic_vector(31 downto 0);
begin
dcr_base_addr <= C_DCR_BASEADDR;
-- if the address specified by dcr_base_addr is the sane as the address received on DCR -> hit
dcr_addr_hit <= '1' when ( DCR_ABus(9 downto 1) = dcr_base_addr(9 downto 1) ) else '0';
DCR_1 : process(clk) is
begin
if clk'event and clk = '1' then
dcr_read_access <= DCR_Read and dcr_addr_hit;
Sl_dcrAck_sig <= (DCR_Read or DCR_Write) and dcr_addr_hit;
end if;
end process DCR_1;
DCR_2 : process(clk) is
begin
if clk'event and clk = '1' then
if (rst='1') then
ctrl_reg_sig <= C_ON_INIT;
elsif ( (DCR_Write = '1') and (Sl_dcrAck_sig = '0') and (dcr_addr_hit= '1') ) then
ctrl_reg_sig <= DCR_Sl_DBus;
end if;
end if;
end process DCR_2;
DCR_3 : process(clk) is
begin
if clk'event and clk = '1' then
if ( (DCR_Read = '1') and (Sl_dcrAck_sig = '0') and (dcr_addr_hit= '1') ) then
read_data <= ctrl_reg_sig;
end if;
end if;
end process DCR_3;
Sl_dcrDBus <= read_data when dcr_read_access = '1' else DCR_Sl_DBus;
Sl_dcrAck <= Sl_dcrAck_sig;
ctrl_reg <= ctrl_reg_sig;
end architecture IMP;
| gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/User_Demo/src/hdl/RgbLedDisplay.vhd | 1 | 9145 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy, Sam Bobrowicz
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 11:26:53 03/13/2014
-- Design Name:
-- Module Name: RgbLedDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RgbLedDisplay is
generic(
X_RGB_COL_WIDTH : natural := 50; -- = SZ_RGB_WIDTH - width of one RGB column
Y_RGB_COL_HEIGHT : natural := 150; -- = SZ_RGB_HEIGHT - height of one RGB column
X_RGB_R_LOC : natural := 1050; -- = FRM_RGB_R_H_LOC - X Location of the RGB LED RED Column
X_RGB_G_LOC : natural := 1125; -- = FRM_RGB_G_H_LOC - X Location of the RGB LED GREEN Column
X_RGB_B_LOC : natural := 1200; -- = FRM_RGB_B_H_LOC - X Location of the RGB LED BLUE Column
Y_RGB_1_LOC : natural := 675; -- = FRM_RGB_1_V_LOC - Y Location of the RGB LED LD16 Column
Y_RGB_2_LOC : natural := 840 -- = FRM_RGB_1_V_LOC + SZ_RGB_HEIGHT + 15 - Y Location of the RGB LED LD17 Column
);
Port (
pxl_clk : in STD_LOGIC;
RGB_LED_RED : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_GREEN : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_BLUE : in STD_LOGIC_VECTOR (4 downto 0);
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- RGB LED RED signal Data for the three columns
RGB_LED_R_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- RGB LED GREEN signal Data for the three columns
RGB_LED_G_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- RGB LED BLUE signal Data for the three columns
RGB_LED_B_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0)
);
end RgbLedDisplay;
architecture Behavioral of RgbLedDisplay is
-- RGB columns starting pixels
constant FRM_RGB_1_V_LOC : natural := Y_RGB_1_LOC;
constant FRM_RGB_2_V_LOC : natural := Y_RGB_2_LOC;
constant FRM_RGB_R_H_LOC : natural := X_RGB_R_LOC;
constant FRM_RGB_G_H_LOC : natural := X_RGB_G_LOC;
constant FRM_RGB_B_H_LOC : natural := X_RGB_B_LOC;
-- LD16 R, G, B Columns Top and Bottom locations
constant RGB1_COL_TOP : natural := FRM_RGB_1_V_LOC - 1;
constant RGB1_COL_BOTTOM : natural := FRM_RGB_1_V_LOC + Y_RGB_COL_HEIGHT + 1;
-- LD17 R, G, B Columns Top and Bottom locations
constant RGB2_COL_TOP : natural := FRM_RGB_2_V_LOC - 1;
constant RGB2_COL_BOTTOM : natural := FRM_RGB_2_V_LOC + Y_RGB_COL_HEIGHT + 1;
-- Scale factor for the height of the columns
constant SCALE_FACTOR : natural := natural (round(real(Y_RGB_COL_HEIGHT/30)));
-- Each column will have one moving color: the red column will be either red or white,
-- the green column either green or white, the blue column either blue or white
signal rgb_r_red_col : std_logic_vector(3 downto 0); -- Red signal for the Red column
signal rgb_g_red_col : std_logic_vector(3 downto 0); -- Green signal for the Red column
signal rgb_b_red_col : std_logic_vector(3 downto 0); -- Blue signal for the Red column
-- G and B color signals are the same for the red column
signal rgb_gb_red_col : std_logic_vector(3 downto 0);
signal rgb_r_green_col : std_logic_vector(3 downto 0); -- Red signal for the Green column
signal rgb_g_green_col : std_logic_vector(3 downto 0); -- Green signal for the Green column
signal rgb_b_green_col : std_logic_vector(3 downto 0); -- Blue signal for the Green column
-- R and B color signals are the same for the green column
signal rgb_rb_green_col : std_logic_vector(3 downto 0);
signal rgb_r_blue_col : std_logic_vector(3 downto 0); -- Red signal for the Blue column
signal rgb_g_blue_col : std_logic_vector(3 downto 0); -- Green signal for the Blue column
signal rgb_b_blue_col : std_logic_vector(3 downto 0); -- Blue signal for the Blue column
-- R and G color signals are the same for the blue column
signal rgb_rg_blue_col : std_logic_vector(3 downto 0);
-- Size of the columns according to the incoming RGB LED data
signal rgb_r_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
signal rgb_g_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
signal rgb_b_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
begin
-- Set the sizes of the columns
-- Red column
process (RGB_LED_RED)
begin
if (conv_integer(unsigned((RGB_LED_RED))) = 31) then
rgb_r_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_r_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_RED));
end if;
end process;
-- Green column
process (RGB_LED_GREEN)
begin
if (conv_integer(unsigned((RGB_LED_GREEN))) = 31) then
rgb_g_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_g_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_GREEN));
end if;
end process;
-- Blue column
process (RGB_LED_BLUE)
begin
if (conv_integer(unsigned((RGB_LED_BLUE))) = 31) then
rgb_b_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_b_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_BLUE));
end if;
end process;
-- RGB LED RED COLUMN
rgb_r_red_col <= x"F"; -- The column color will be either red or white
rgb_gb_red_col <= x"0" when (H_COUNT_I > FRM_RGB_R_H_LOC and H_COUNT_I < FRM_RGB_R_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_r_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_r_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_g_red_col <= rgb_gb_red_col;
rgb_b_red_col <= rgb_gb_red_col;
-- RGB LED GREEN COLUMN
rgb_rb_green_col <= x"0" when (H_COUNT_I > FRM_RGB_G_H_LOC and H_COUNT_I < FRM_RGB_G_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_g_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_g_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_g_green_col <= x"F"; -- The column color will be either green or white
rgb_r_green_col <= rgb_rb_green_col;
rgb_b_green_col <= rgb_rb_green_col;
-- RGB LED BLUE COLUMN
rgb_rg_blue_col <= x"0" when (H_COUNT_I > FRM_RGB_B_H_LOC and H_COUNT_I < FRM_RGB_B_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_b_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_b_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_b_blue_col <= x"F"; -- The column color will be either blue or white
rgb_r_blue_col <= rgb_rg_blue_col;
rgb_g_blue_col <= rgb_rg_blue_col;
-- Assign outputs
process (pxl_clk)
begin
if pxl_clk'EVENT and pxl_clk = '1' then
-- RGB LED RED signal data for the three columns
RGB_LED_R_RED_COL <= rgb_r_red_col;
RGB_LED_R_GREEN_COL <= rgb_r_green_col;
RGB_LED_R_BLUE_COL <= rgb_r_blue_col;
-- RGB LED GREEN signal data for the three columns
RGB_LED_G_RED_COL <= rgb_g_red_col;
RGB_LED_G_GREEN_COL <= rgb_g_green_col;
RGB_LED_G_BLUE_COL <= rgb_g_blue_col;
-- RGB LED BLUE signal data for the three columns
RGB_LED_B_RED_COL <= rgb_b_red_col;
RGB_LED_B_GREEN_COL <= rgb_b_green_col;
RGB_LED_B_BLUE_COL <= rgb_b_blue_col;
end if;
end process;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/synch_bus_wrapper.vhd | 1 | 975 | -------------------------------------------------------------------------------
-- synch_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bfm_synch_v1_00_a;
use bfm_synch_v1_00_a.All;
entity synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end synch_bus_wrapper;
architecture STRUCTURE of synch_bus_wrapper is
component bfm_synch is
generic (
C_NUM_SYNCH : integer
);
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to (C_NUM_SYNCH*32)-1);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
begin
synch_bus : bfm_synch
generic map (
C_NUM_SYNCH => 4
)
port map (
FROM_SYNCH_OUT => FROM_SYNCH_OUT,
TO_SYNCH_IN => TO_SYNCH_IN
);
end architecture STRUCTURE;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBSCFIFO64x64WC/synth/DPBSCFIFO64x64WC.vhd | 8 | 38586 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO64x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO64x64WC;
ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO64x64WC_arch;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBSCFIFO80x64WC/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 61 | 90319 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bNIbShH2EA0CHyFd3tcKzqAAHVrbIPwWhMG9NsC+dQUSMA6xt4c379IBpTIXbcWcRu47Z+xjBDyZ
pmPIKJwXiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aHvYZyL6jZFeED4yBNrYXGt5D78L6XKvfv3d1wuLye6gycFxQz5GvWsSx0S6xMB9xfjAd58Otvbz
klFCQAqOIJ1v9j3fyjGrdYiRUTQuApDhC+FsIz/c7IXqHLMU7bYHwJKasO9SrDTWvXQ7ih9U0p2k
1AKMnh+qiHrYpQorG5A=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RiEdSHs/Bt5umPP6K79selbyluJtARUHU0yj5nYfHoqZIAm8WpvDCQm54C/KO7nPLeyv8jHIHHlo
ALGpGGe0PjfMvHDpFSP2vV238cyunFX8V0T9k8bl6wjYh6At9VhihdwfU2o+IX5VBj8SP9UjNVm7
vVF4zMGwAkPIQLbID37yUDY79ZMmCkWbDezMLjj3KJUww291O1rtjgyC9U405d49Oz2JWy3P7QMn
8qdrMZbOorlxSjkf+hkEIpgWhS+pbRjZ8wYGv6o7pRDkDsG3+S5QG9lWf289rXA2RQvNu+gKmbHa
+29rBsgGnvv//KXcwxU1LPRwDeg4UvorpCIeXA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1kXEElfRhCg/jAKI1qgX87/xWqRpS0e1DlrBHXO8aH5H5hRB8yNxfJpWnAEYapsnx3bdBnU1AAyT
aS1HwJVWR+nZKer5YXEg9XX/LwYQGdvNDMOsfvUNry+U7z6Kbe/UEvv6lt1y8KsQyYySOWeC/GkY
gvuKcUlrP9I2nyTJMAM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mYglWFHrB9KUMFOAglZNRnS7Lnvi5gZL2XwL13GIjD89oHQqVk29jGx2KCeeLHh/cuuqyyaX8cnu
wVXmf6095a3qNER/BkizDns2ON7gXlfqDwAiwRQlnbHJVhuv339KnW9GIEeggUZhg16lG/xuic29
kcyTsJU92tL+0bqVkxdCDfWly3o+vB011FmTnOJvdxGOerq/smn5f+CNTSqTx6aWySd4focWp3FP
1IRx8Cjqp34czZQNDbnzZ90IVxyJuFmmDpW8roK21NFNjW7dbg4hrFdS8qcX75ES6c0+1Ad9MDUf
dJImpXUL0bDTxErqK6kqA1RFpvNA/Wd7osKy7g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65120)
`protect data_block
UZbNrxS4mSBhmAa3/X3oJLd1xGA21L5S7fYTS3C4Pl00SQLq0khiWZDE/rMLjNoEn/Q9gqXAkf5r
dS0XkN7psKi4vAgvXgDb6jUyeJQcZaaPu6bEMK2QiZKC2z7AfnWk7MweZnbr+H7GReUnwdm2DK51
MDcXAb9rAcRjGckM+m4YyD4npVSOWgiFba/ZCF/kZcw7zFb9ijQ+VQdl8daOjRzJKdrHK1D2eNf9
0PnNyiU1FyuhGX1RchUAy3ee7ah9wpq2y/z2eKsBDjl6E9tYZixrW46WC7vks9Zm75taH1XlwaMO
CKYBXLPHXoS25FIiforI3jJ4ChKnNpdDRHq7DJkvcgDCtf128Z+0cYoEj4i0Uiqk+PHV2jMY56CZ
jLzIOGBg2v1Cb0GlAZ5JpxHOs+tDnmbC1dfN9ZQxWmmt6lYd38K7ObLvOLlb+SZfrv/mvMLFMOZh
LCWQNCb3wXzbOHvo282/PfA3FRKlCCkMgrpTDuUOJC5r0wN78UqM0P7h8qdPaYt4Gft92w6HbWfl
8SWFMZUVrsEluKz7uqIwA5Y1MBFonm9lvHoe9slSuI19S3eThAFja8oX2KVPB0r5a1M1ERQDMyUO
YxKUgM4reBTzabbXjxvtUmnQSZjA+vsOj+knTLArWKOR6keaTAnQzjX6p+A5kfObnm9bFjPhmXDJ
iWX09FLa/hRH+lEPGs4TRAJvnoQoxgOmk7Cbi8o8sIQ5tRbeQPPW67NP10qeReefMGC1xARho2V8
JKgB5ykmD73sQobWmfG9ATGJLk724K2u6RKyzXvaJRSWh5GLMDLLWFm4yoUo23sQjxmOc1YWy42G
xN5jtvItXgIDYyQHCFHsmt8Cf7InFR4/ipGwwhI0yIewnOpTdUHhU63Su/X16kcX2kdjZa+0ipef
PQJh5HcnenyIgnD/QV0j3cTwiDlMLz0FMnmztT/kIgCpoAtAWGkskdopjV8bSN4XD5FVdayIcfNa
s9Z5730GrRHDCsA0SqbY0AtL6TwO91nARi8dxhEbBBIEUUALlWfUovxkAWJE5Yctz+WCJlP6jkqW
rFvUOzzXdgfJN3JdbNxXxUXXT9YlY8/N4CmgcX2gMkhHD4OpWQ6TBbN52XaOVlg7V9fvu4w55FHi
m/cVGzCN1EPT+61xCn31LxgxoE2JVJAJ544iwW2NvF4B7qV0StyyPNf9xmQcf1DSaaCWIpUOEkaZ
UwfZ+UHM97i/RqQcfgYIzcPonzsncl9Hdh8RvrLNatNqz7PRxkJ2t6i0vt5Jw4FxE1LIjqJp37lX
E63m97NCllBg+LCSOiYUBCGEBgl08bv/00dWT4zCB8rv4R04hAGUy4Ir7UHfQgXqfyoW8Cjwz0jL
jqrKh9LKITt02SWJUlRYpEfE0L1kjf8ZllJGoHVtiQRrbgFrl4myYmb76Sol+0Sn0jLWi0C3Wai4
LoKxAvicVXyC7SdwKOY7Hq7XdzuCeV9YfueO1D5IcvfRxQwYBmTXrdE/1TL7vY2Ria00EBfrJT6o
QabZw4upbGGuBE/ofODUWCT+iUy4nH7ohJgWtQ3nXbcMxGd/x0azGmLwNOs1Rd/aDxDJ6qgflrMv
m9xUJmNjQlJt5+gaoJZq+8zXK2l8AAMT9/5HBPNJiYIsAIWteyv91YzOtXO5Ni4sv4W8FSAo5V02
VUWp6ZGYEWnqDHLbygEZj24es+kY726v7PZwffJ5tHxDnrqYIjCFRipPQVvw3juT8Us8WzRsVXhx
aYa7iz+vGaDoVySo1M7nUbExvslkbSmJBH56nAxtjX+nv79/w/aB/o9xFBPGeYGXQnbbuZs/w82x
/HJYz1chqR1opC36GbHHxnDBGdXUeE0/eL5Qe0jLERRMuXleX18gIOhvIZdQPe255isxx0HydhAq
WPsH9IFZ5/GRmyUYYpLPaRrKvoItNs1j+5JHqKbhk912CuCFKAPo3V8vMsca1necdW4sJrejr5d8
sIyNo1v9Fy+ytjx2mlt7/I5u0nuV17+retHsEELPd8xps6xXcT4kGXIs3oqMu2QPtfb9FcHzSxba
+i0/Ii6oI0e3iJKrj5nGDdDw36xDPiudwP6tgaexhfzcsz/CoO+Zb6a9XEdFUFJFZPHx975wfOj6
/XULNYhnno8vXhao6J+HcywhnsvXbdO9qLur8ljzAjALm2zSqr1jokwJqGlYM9N6bMDFQepDXUFx
GUaE2G/Kxn84JlxJgLzMYSl/2gNomUVjvGOVdLLqIaYrS9Gc63Avw/cG0Hu1AAI2RyPhWheLaTAm
Vns+bdl8N3uhotXMGr3UpAwepwqlzuHh5syyEKYXL+JAs6TlkWer8oGJsKdRuSmrsUQYOZ0btvvt
hDQTSy85DsP+0BP32TseifmlDIiDv+CjMJt+k/vSmyU2FAkOH72wVG0qBzRKbUC6IPlYrnaYJLsS
Y9jLu4+OSZI1FQHnHStL994BMlgrvvUpQSU7YqWXVRmsuBc9dEP+3D/eMWqJ5vXxAHThoU/1AJ7e
SRBzpf7g7uT/VwwWIadimOrsdJvZ5A3yH8xbMDjo771psFV3xH/vs/6eeZIpaVOl+UoY6nCiJgRG
npoSYiVxXG6RkPdI0s8pvfNBFLvNQus/Aisf5w7Px3pV2RCEFjcUhqdjgyRwFOOwhkhf2/sd2osj
6s+gogUydB6QITrIe104Jo3cqzc/nI4/fowat9+lLRbrTjcoJtxqUTBYpDFuh3v4ipP41DneFEJt
DyqdPG5mx7GuuXk4bjGwn8n6cy+K/kfYun1U/eZ+HPU09iVCQv5EAk8yjOlvvTDcH6QmVRM6NsZI
PleWfMb5hg4AD8KqBd25vxamesKjqtZKR7H/we25CX1/+a838gzulGPzqb7U4rpL5DVTxac69aEm
gmvGHdWHieSsgoAKMmvtvNx/RHjpxlM2x1JOEAkdOdeZu4TDKAp/N/LMaqk5uXMU10fv3SFnvIUC
+MxlAF4s1uF4w/rkBP50WNAbhKsnJhosP4leXbSocFfjSVBUulaAaD0dIrsoUZ9IpjZYbxUxYpZk
p+m9P21xIdRTGLZ29Yifp65VcNOjA7uszdrrs6N+1QKJV+7frqHcdE/d/tyBrdy4EQyRdDQqnW5o
WhxtFb5DX4pS6YQJ1qO61KXA66W9h4jbhAKqGKgOEwjQKAD9G6LEAYPF/wWdp2mob/G/hfnem3Dr
boGSAzj3DACHF1cWhkgQXdbiFxuS6USN5amcsjZ0W/pEduCBDjoKumcNGfl86FqbRr4NVYvJWmyE
xydb48w5sBxM3CwlI4vgJMxBXwAp87YoHNkAtLdMOUcd3BCCVUqUDF3xGKovIlkbf8bwKCKNXvKM
6iy576fCjZTe32MCGigVBxJTTnVY0LmvtYicYG83a+8XmYkKAIsBniCTEsbKBnG1wsdEBLBgX+QL
U1IWID/4tqeshDpcdfA8dDz7BelrtuQTOrU1nQgoRabFRTlF+q+jof4TZd2TK1o2iOAYCjmy6Cp5
q0FmFNlJaiJmgxxn3+g/+sl1Pd9zEWlqulbTZFb+YQ+UcHkvpVDAgZSgEXhMriD9x4xF3+F9RHC2
ztaWGpSpLaJkFT9DAGLv89suWCU+7m3XZLT73HVbmVdRJ9+8GE495u6aralHA3UHw8xsRIAm0STC
46HUHc2zpSgWCw7VbfUJUdqyj277rEn5aatMXNTDiotCNEL7J7RU4lGUVE38xk3BroOUVdASwUts
Dub7eGlXF5BfXHgXn0Fml/d5uCpqstDBMhulEa1s4ak/btXL4YyYlD6zu/QVoNsYdzDuwHp2/Oet
PPP5wyb7BY+YFkbLoLKMv92SPY7QAlkbC2yxqyqRJuzyhF15VDq6lknh6blwHPx1AzTfHisXe2n9
BML847+c0MkZwBPnqDTQuEXUvYmJcA0kSEDtuUXTH+aFICXnsOMis+Jy85iFc/MXYn5aKl25B7P1
+PdBZYngWUQlG+M4CVlNEsy2/nJ/F6QZdU6vWv+qDKowCG+n2Hrf2BJXFQiky6uoKO2fzGYpP4/v
Y2Lw7jenBzZu8G+8s6lPgVnLMJimQSILbTAbOBTzGqYthkso+zXwakQUm7V6tiCeujAatEucxj5X
V1tXxSJyK4G/+tH/R5eU5bt05FaEJUut+8HuQFxi7Iz25YO9qKu5GwG3A2JV4lWB3tqEvbJABNK4
QRqTHOP6IY92Ry5KR5mJb7NpJfVURUM4R7yVG6aD5DM7IOiPY2805lelOkJQahAXz+g03ROvEj7y
vRHj+dHBQLVGvNvl1jfKNGCUWn3ahrxI7A2eGU0vUVAhs4nSfgG1QjC2YMqEVG/xn709uoaqiN5p
Lde2mKjMevATOn/t3UMXfOl2yCR86PWVSfaqrhiTKTt4sjAYRbx1siAApqDDoOjwNulB+S+2q7Tp
HJydgu3j9O6ib2GBO2eAMWef3H0ZWyIGZSqBaOWKbtklDAiL5S7rgafCsOzyZqtIbh6KGZYmx3oo
SmUuVmQetapF88SP/tfbL7hC4HkbWJbZ8Hp55H+EVmpiugvkaD69Lbzv2nC5bS/OgXZwQhmQ5hNU
IvENlcBCa7geKJFb425glhBfBSGMOK3om8tPyiXWgEQ+As125H7eFgEJ+hhQOGE4p9xtX2LZlbFI
2M5hht49GC7YwHbrnJMPznwVKOPlQ/KsfqBuSa3M7tlxeSGyko+jk/5YvDbhG+wQvCYjGoGiM2CB
fajXv4ZrfoPeu9/V6gX91v0Ewqsbhu3LvCoVZ509iYfn2g88CIE/zzDO7vSwqZ45nQebSn/fqTrj
BA7YW267ZwVJF8oor9sPAEVPx2H1R5PzDsK0CUeoTRDRZlUsjAI+zwLzpj3ZmO769fL+5bYUWWSy
tmvN/btFTV2LCxc13WSTJzE9sbzO7tKZbsaN5LwDtc7OBLK6rPL+jttKGzeQ4Qqd18xwh2Pwp31z
7zOVyPpTNAc3D7p+sc44vLKLfznV1/n8h9EEY8FSq2caFFdilsx97NjgiUg79nwtQoIO+cKI/YYv
/TFOfkySNpeBRj/wv7BES3Uetjr1tJhl3A3ZkE675+PNgGEVV7vfHbWK5Sx0NCAy5uiqUpfsWAp7
a7xeRYJ/ZKkgdL2ZG42He0y+HZ4g5gZEdyb5OKerKByCh2LbeS7hzrfAERY6nuKygHtOzAFJVFyg
aKtSApm+ZuSJ4ASdd7VxcEkP9cvWMb+lQH0PpdTiQsBSwRnPXngzZcapZ+IeDMkw113YF0wMFDzK
Vt+x3extWVm5p5cmyBcRgtbYpsFiY7apjZjSgPGEciyF1wMNC/S+BB7ScFyHqvZQj4Iw/lyEKJE6
nzlzBb4wyIAqmz5UoX8lKk9BSLenOUrRR24F4JeGTjBPRw9h8eaoCB+abt7m8TQJIL9PKGtTSGYu
fTuRH7Ii4jqxVIZCdYzbzTkwsbD5FEz4dlRAfVnP8Mjsa1nvzhS0A2Y9xeBhHTm/EVXGt5mSAZ1v
HJs+5xtysvLLL0F/vfcWixXPhbgkoCRGHhdjJi54Blz2Hu8yAVzj986/KeyS2+VHqsSQZbbW5gds
n0adW+gJ00yIlKA5qseWI4H6bSNSILoDx8lgcpyhQjfhphOVe7LFlqUa7BuB5CxFJVjVeOCDv0xf
OsYO1DXb9rGJ8vO1MFCMhvpWUxKXeB2Z+Ti9P7qIVFYY3Dvzb/aJFmF3l2pm2sKcJo9OA076HY96
0D/OUyYxuorREJWJDxeYecBqFdszCm444cHaCpz0ctDfgK96D3BSSBkLGPmTAVSR6TGezmUBF2Nu
wYZwiBTQkAZ8ocsmyg8IuKyML/hbmgvVO9pANxCKU0JUYcwDv5pniaoqolmg42cM2sgYyBOXsLZR
yv60V6ucThqDOPe7wwfq5IMfNiaJeR4fhHdcO8P9AW4P8tzZPk6n+ZXN63vQgiYLeUP/Q3hCJjDN
N/hfPLtf44uL+yse4IxB5qdcCLnmpVEvSyjAHR2nU6JY4NwMoKpHXi3EG4TLR5y+hY0vqXOEKaD8
+fWIHUoQZ9dSpMOkcWoTVBqnSH+XIXoGkkqLwZ5P0X+sC1TZRFS7EPIHj9gDw5JgfPf7VVjcnNg+
bJRjMXKp0IrPfrjxi/gNAHT1eChjLxvXFq94QOmQGqoJM4415PDw63Sg8e3JjK2q5VbKREQTwJJP
S0ArGMgkL7+1mtC2i6LRE61rfRsNbfsMefi04m0Ngl9q5qsbBEaIgDFJf+Usu5VaOCn9dHU07CFN
Bf/MpBf5RPJVth0aLIRTTrzlyhtMrDrpzCpzKVxd85+vyhVXEVJCbOyXd7DCojgbSRZbQ7lho8y+
4gfOdXjvtFOh9tPsbqu0FPa4BYi62hjZRH2lj+MsHPJ9MuopstdikVUaNz4tHmiADX2MTdlZzG1j
ygGByxv6g82ugU5Lncor4W2u0U8dM34qRbRgSNppCiYAt2nwo4w22mSR8rLxo1vKSKArvwRni/bf
hYcpDmMxfuDCQ9iUhku/pKQS7GQxgb5BmGBJxsLOqn3OVN2sucpIQijd2Hw8IbFtKL0pFIWushji
4uGy4xGJVbDZ1bVxnXiRtp8JLTDSAQVfraIfiwOupbFyUcfdtdgIv/STLHHyeppgsQvdzY5B+vAH
rdfoNn/1wP4HxjjfF9V2kOkLdmei337qXahXZIQITExpCj/yhfmGKeRfYSbAdF2dpImmMm4a9ucK
3KoEVG0gmFClz0mZe+nper0zn/RY8+HoH4BmFZkNtMyoOwUmc+eGWhnay2KQdbMYC7ZVIMRkwv1L
dyobYj3RsC9KE8gK49K/XwDtQ6HCAz1AXzV5u62iLDSWznRAiAZgFqbGmByUKTd39xemCVHXyFv+
x+AEjeD+7jHYEn8C1IIldJ5HxDapb3f8xo8FHjfugNnZIeWW5OCnNlpj0GjrgDc1RiVWnPn11iq/
sgZg9jPi29ZSzmm9oI0gnMrpTZRuoEsg6QNFkU6boHnEcK4Ic6RcxQ8gc6taVW959XUzpX3CLiFP
dHaZ92Zk1H9d9oVd84oDJq2kCykaiJhZdBve9qA0M8ViZ+qCzwchvI6rNL9DQtQwokIxtNoEDWyy
tdJLWBXFRma4EXv8W/dIelkwwS57d1faEqJ2gxqQ6B8ZrtUAgdw5V58SZKRN5tqeRvK0GjfexLxU
wodaVKtC5NcXdYpa09HJB3uLd53aojfo7pDMcrYUVQ2Qm8KXQB/M/mRbP1JTUTlbor6h262q5rWp
pezDMR5riFeaf7n8jgONnzbT7d97NKJhi3djXOAwtAooo/kpJxl4gNhZgy17OWJ9j+I2HFDR/dUk
qah2loubyR5OfnmtAu9yA4GFNtUQph4Qg/rwfN+pi3HH/Ehr9V9F4zq3f6srXc9s9sOph851EOqh
q2mFrP7x16fXpjbHPklmTiugnmq45r02GK3GIuKLFFa2nSkjHYCCO/80gexGiioZWWKxS4lKYn2A
8jr49pOo+m1IrDyU8fdNZTAMLVfzGXRokuj1m2kOH0gV/14HVcBG4uCl9oq3RZ9eNQOIfhEmHH80
ZbR0Jhyqi2jlQMUhPGjVA6QLZpD3sG3zYKGpWmVxGxAeJi0vdJJofxzYNOQ5p2EDluUG/sklzxuo
YRauV8B1EUkEPfQhQ6C17zr8523KMuDNs13Kk4NVHZz0mEivfRBDvwElesF6g/hxHlc4tH/zBXoF
9lEw8ScEnMOiM/XbCVbjn0fnBvwF55LRE2Sr9WQHi+YRJRcBBRQE8mXSgpUU0454G91TPhsQ7WZZ
dKyOfRS1B9JVDMAQRTfx9eAbIP7yIGnXzmFEGGk7F+YWWV9chsFBAA8MNvzrMG40N1shPJk5WUb9
Illkg1a9sbLrHHB8ql0WePNb/bHw1yXQggBmuHCtgOhU2FRWOms1W1omAkXe2Abq+7GSh9VZGq+u
m+y35O2AssAaQoiviQyRN/CkBs1phtTja37sAFKp64FOlKI9aHvNlLjW3vul3iktNWmESt9Wd1+c
Al7wNbiczlTD7yqqKjJb0h00sjS90vbQGJnhE+K+LBKg//d6+Yf1b9rdbuG2HNHD/kvprl+ymywX
QCYOPK3+u00SolQIVCndmBO++CvbNn7arLyP1Piyte6qq22A3tio4pyWl4s6CVoW1mnay0p1qLHe
Sk4qvDYQnplJNWZfTSQsH87GN1XtXFbot0XqHSuFyjbwi2dzA4rrzVdu7vq9hSODnMLWkn++2Bhc
LsXCq5pYQh+fd1ShtgAf1rY7Jp3ZyouxUN96s6fsQZ7VIjEYSvkAgRAHtLS34eYzBTrzu17rtikJ
hUGqS9kS8fL4Sgj5Gu+xvNUuqCeF0ox/FvrPNoaQc3GP8sqPcnxRftYVHBSvlE+ph8F08qNy9USp
m1+G2pqXyTH0GGw+sFR+wIaz/WXqwphROhLuYXsKNaJmu5CjAl1NIGItFZ7sAM4iWupJnnaruVK5
xAw7k7mglVBa4ZXRmtm6T51VBmeGzQ0M8F8z9B1uWP8z/o8r5MMUlKSUsbHbOzO/PFtmVMRxJy4r
1Ngudi2v+ub3ILDqUwoMWRLRjkqGb+BmE6YuypKe0BJc8391MJP63QBeFJEQyA+iuVxOK1LW9Uow
fVxHb6UA0gxmgEx7Mt4x/BoGKo16utTd7v/EbEVycAkOWZcHKKhO9x8dMKODuH5oZrk8WFIBj0c/
h154CjgTvPobOtu0ILQVNHdeV8CWmzWZWxcc18YvshnjLu1v9MrIce78BblkWJO3DTnKDihVFhgI
AM9IeW8hqL11rYVHz1lJM739vF0nFnwTRo2HHJFu/6lVbfy6sLAmqOID/bl+OcbBzDO3UrPRoyGv
d38sczo8R6uJr8frv46Pg//kgIrEpn8Hc9f3zFqbiO7DitL+EHIii4auBg/pC8BPSunD6yNNu00u
0+A8eJDCRysalxz1EwQukaFfRFR44nZ7WW0v1wrGWnFl6W2spgkHngnAOmcHW7NG238tvyB9HW3k
043/8v+XIkD6z4CZJYrrhF5niwVf/HXL/eS3X+y+HGvzE/dhxnDBpF7x34hHILmW9/xz3kWVVQLD
yHouwsoaZWq8ahtulUrzTzkaxJBlVB62Fqs9hJXO6fk7Kq3k70vVMnpzRjBkW0saCEUjqV36GpVW
2iuEW5ud/9WGyYHFzSg2FYjADHokQjs4dLypj4KMQHPwpwdVzAMsWwqE8vytsUV/TIuGpLY+MIdZ
8uaxXge4ZJ+JXFQqeICq2Fhv7/Ihs6Q3P6UTlhnGHbxQlP0QzJUEo5TXlXa8ujalLLOoB68Y+J8i
/8TRyHda0SVHyHWFyp7maDi144yAjbS89xpSHuD9lNgLXMbe74AZ55wAgD/oCCNDF0SPBPky5qma
KqE8WCV6h2CkN+HrC6AgHF69mZ+qjmMRO5h2P6bjb+os8snBp393jiFuewhEbo/xsBYIhBFN3Tvm
M72P2LEVnMyguso5WnkEpfP1S11oZpSul4YdJs1QPNhmcr4jnpAN9bEjSldwL1FqgC7PYp9bDrbe
TJoHTKQ36ctwAR6SRjpoPxcmWrUMnoI0rcieNLKLN7vZajvi6SGODkBHBON1kTJ0el7zOYWztfdU
fgjatO6dE2od8CSLvBqR7dVVpGIiCBGw+g3MwAgyCB1QNvyoc2nNM8AcqTi0GCljfK8QvunGfiDi
JqI3uO2zNx+QZcCxXN1IO6bSUYI1c1TimmRPs2a65vELggupdWgeAheBPO0OatgA6vev2gWm/q2w
WhCQeHuNZrMDVdir2LckagkMvipS5drgPUQpfI3SJOgupgrdKCfaZSsoWKfe/cbNp9GXk6Hb7L9q
xkbsIrfdIef9k6Zl3+JRzdXyP5kjno37rXAKC4WZYI7ePFxPrSz7hL1b9+S8ua0kRjkpxrmV0dUe
LK0fizjuTqPl+gKW21aBBUbipvFCqUrqdmXkn9QoHHUsEgf9pDaL1IlTiacBX+Di9eP75WzctYLI
5HdKG7DxIevBFr7xlkRr55jk1zDUN6ht7wgs6RtxZjuUv8PpjtrCmcOO8D5OxDa2z5uPB713+wwR
0A9KGC1OvrDf7/+YLO7KR+OkR1LPlkCZJk6HWREIsCWGPiHCYxyDxvwkyFi1qP5kW3SFfpDLBTg/
LhuczbVPmDQjR7xD9JpSk4n2BqXuZ6t4JsuFBdZ+TnIzZwXpppqSAsLEpM4WTgwXkI5pKW4VW2+a
5vOIkuT0Fz8jIPeGBivWQYWTsro1Hj1+6RSZhlpHFMFfO7E61O/p+somAucX0HId7q1wlIPS0Eqh
+Rwu7xXBjHlDTJ7Xv78r3EAQwM9O5lACgFTqbvulO253T0WzZZLxPk/J2/5aN0wY1wtsVFeE53yK
ktnD9VHsLhnU8ZaXRFwOEELEWgFrtq3Asz65AjWNGCj52XPAk7hrHw+RCARvVVZ7QZGu7IxCjiWo
ev7CtHwE59aOQaqWD3Zi5IbOVL2wTWwWG3nYj7rgJFcBNSi4m3ItYrBKZ5pPwZBWPPWuhffsxkRS
LI3BghBde/Clan0gANntYwWk1XWGvdObj7kHutb8rcLOthMKCU6xU+ddlBor0XPB3D5SxG+M4hKY
AZy+7OZuUUKvk8iP4s/kG9/Pojhfro+zkGgzoxS0prXUEAgY9oO+jhpwbYYkU24gefSTNTkMbfx/
zlEOwwY+Na/JHaISwLE85B29SeIAakE58oEKZnNFgEytDIIQ/KUhjppa3IVR+vwwCrW1AyyCdeOW
gEL7sJfHSLwKCZUzMbSAo0IjRNC1ecDVo+JVA/kIiLzjAcgWamBvKQUd0qxyIi03lsPi8tmN65Vc
taZL/cGfrrYy0NauwnWhmcxRj+cfWnBKyLVz9njMM32vwnK8MAeo8Kg7KZ+bd6DocmCGDK4Bcrm/
i2k3CphYWrZnOXeeA42kQ5Ah8eWYpRcSYJpnEXviu5wryqveyGTphRPz/YxrDD01IQ21SPR48Tfb
9p8tU7TybwioXm6aSft+Y2pSaPmGFzxemPofQPhrdqd8vSCm9HO4jukqt1feYJX3L4gtZiSnx2Bq
+kqLL9TXLdD7FfecWElHWneatF7jvDsvXd/5HBDwcJINuZsksFA4aj69sXRlkLma7ILyimXkqZo6
Pc6AQI6mIoy/+Ztzq4YJCWbUlYvCEjQBtLjPdGPLe5SMkrDYeYuCfeVXW74zO4huH46K6Cn/LVdq
mwsDBbI8ugnPI3vezMen5nYv1375K3S7UkRX21DkppG5trB9yLMosTqTCa/dZ6oS7KJ4S3cnTQAI
e9TzHpoRaIIVi8tARoSPzLS2HzJGwbzFyBmB/DQrMBkaoH/6hqNiiwPpipgEVt6Vp7Z2mIY5OSvy
/YJUr/uTDy9GS6uXQRRZoWd3yhJfATOvf6xOXsE60aGJzNI2Nzla6Z6COpwPPaKxTJZ8wuz5sQLB
b+GBROHxVV3wC/dTBZ5Dc2aUmpkGy3IjyMnCgGMemv1fH4I2wtnwocyu8rbMFSRsRhBQOzWlKYKi
doplWxzWUxfU9XGQNcyjMtHWYjrYHPqV3tSAsj/o6lQoV+RnQIWd8aQqXTEkhJIPqTYL5h/Y+y55
tEhaQ6KpbbxbH+WmismLgzy2vNeU5HTkZaLj752GqDbzZEAw61Z+1AehFFm6ocFUVDs1XHji41IO
A5XdyXXsp9TepCe5Hf3LzC3IAqtOTb4obx9gqOiqEYGqC9DfmNvmscd/8Q/17tdX30VAjT+gQsUr
ABj/EBDwgi3gi5+/AxMXtdrt/U71Wdc33QZinDE5qIEQTQ5wwGXosJRPKA/5tHUbC48BRYhgkINj
4HissckXbaIGb0QOI0v59JoMfx671D/Cj5wt8k9yvi5BXIgRvCuBZmXY0FLIN7xtgogQzQ6cXEPF
8lcguHNpQSO5S2A6zUe7giSaUJmvexC5W5sQ525klbNWVkkFMTDei7BmSUkGXTA8z6TOqTsUI0iy
YUW+b430k0CAzJlgyPoLlhLJZp39Ha74l1STT5xvm/jZnuwnq2LVF1booeNo5+pj7MpS7iibMwE0
fsTiH4W+mUIyJbwvHxSf4hGSHFTNji16oM9HGtuyrXcUjftuoN3f8S/LX7OX3yVBLKCOAUcqXlFi
7kxKDDMogenDjZbCqRtmxahQMYeXo3kBQUwhwTr38c7ka044BRR5Z31Ps777JblJ7W5n4vDKDCnF
NIh5GBE9e95yzht0JbPiQfNO44s8CmnU0zzw3yqBPLta6MV4wITOStc3ZT6KlQjq7cXOJhm7Sed7
4/9+gWEiGbTXVWIGkt3mfE7GJJ/Swyv1VWZFJY9TKo9FQHGxtSPDQeC9eqkCaR5uZ8cSOd/fHyEd
xxNp8qRcvYD5QEBS1qATVEuHOZ7ksXdhmXKe1dr9F6dbIqXZUIxeUzjMAG6jT6T71FIkFCjHl5+Q
M5q59QCLpzA0CfoNkpdPtDtbTswqxRUFkSdusVnxtPWiJUAltyA0R31h9Oi/Irulbygl6YkBtSQU
G7+PVHiqlYTV1TLfYCQHyK/h/JTiAltemFhKKO2Q0cv87Z5N9WWx0oQTgXpWQ7HMl7OCo+NAbpQO
3Ibdn6/0HbgMg2SCSggkJOwJzawR6LRVHySgbTtr0/2pDKdvq4RBaWv5apqTm7OeErD+BZMj4pqY
sbpzoUxsQQq5OP2d/FaSBrbHIIL7v4UXpvS9jbWD0mMHZDsoNF8AVcgbaiEfTnIdNT6VKJZnc+QM
nnKl18wiSadDzYSo6PgUGqHNklw5M6MBuQbcusRzvVblnmkmDVy14BtzPIBvm4BYTo55mJiokJZU
1eTqmggnPas0HaO0ybaCq+aodhWuv28u2uYGpbZnffNg9q1VtBJnwiZNoCHNKmHqO9DiqHI8ytBg
HqquMjbmz1tDwcJPBjmnPzMPd6aEnLF7Ax7UQgVJgB0IOyP8oqc0D0WxcTVX5f2EGqt60CF/HL+8
oh9lZHC0kOewqyxnthhNDw6WQDA9Y1U/a1Bxx/20ax4EiwUfrGORjRJKOIiYg48u7VEAL7P1CsmY
GUzvm9p3XR0dwps4Csv5ozki93T5QdfHXwa7/nugrGpZMtMwuU/kLw3IxXkNjAUT8Z8Jzj2Xi9+G
hBWV3TyE0jIhlGIrpfXHy7a4MtP9zGpL7WE70H0PMlmcwats/LfajQ+6pK5Ajg3XiFc3+RIZM7MZ
8Fi2N+JE3CKqnSC8aAfwCU4WnbridEwgOBbTyT2Nw8r3IyBHQ3jzCAYksJl10UGgmBhBQdELIzCG
kW4mmbxAAcGICdtW4+BNIyT9OTVCT6YWmaI0NQ6e1v6bj1hgLDfix4Rm2rqxuaCEDONdjuVU3dan
V6dVTuhMM4+HdnIQ0pLFWs3SsCPl5SG7ymUdakcg60M6zcQHG9ZmlzMq0s2SbTdfftMsYVQyfZrJ
GF1kVCw7j8o7o85qlugX2ThKTx2VO8/SultcF6CWhLzjNSxVRlZS25oxiTl3o1mk7CcRQG0tn8cf
7NV7IRZz87Fl4186CQOCNye/AO+wzgQZJzEJi8Arp1EBo0ueFe0IhrdldtEC/5ewiyFYMPe4Opbi
vYmfU7s9kV5c3itgGiF9jEr0C07TZmihszSJsm+uphcxXXDsgBc7SfnEhgOn7bfWdmMnbvZE2KTr
4MeAtoX3jxRbcyFDoNhdr0e/lHVmXtqvuH/JJTYjadx4APrwyvJUFoSQhPFqiEgcL6qtMqjN2/Ba
xKwSv203q4b9h3F5x6tNp39oD/LPXfVWtM5nybxglAXh6WHa2ZITrLincgCFFONqqakU611gMRfI
+noZVA87fQ89Be7+5JyCDiryYbhRaxY6R0Vl7EyjPnaVYDcisY0/iV65mhXFbFHhFl9uOLNnokKO
XqevUk1Ip/XQLvshi5xrqqwg1jjttGxUGq5VCJYhp4CrHX5gIY69Qw12vZqYkCH2GYdtNoa7FXjT
Jzj5UWZscux/QkSrYJ02jwFi9NGN/Je/pUqolxs822D5Yjvv2tVF7rcqe4kOOxu4K8RJ/mia2nrL
5J2F4QhH/F/XYBUVFAwIlKhkaC3zVFOqpU615/SF8gJQWOCLKfwVCSpVRoiahlxvY+v6Mpmeg++4
EcG0CqgytttfJzpHCi47B392sJ7tNxDVcKM/AqIDKF3UzmcSOIh34ZVhIZoAczyghIqdtYBGXtWk
d/oBTKdVxwNCMHRmQF56m78bfKOOCVv80QPttKC6AMcq1K+b18T3S9Upau6iGOiaUgbtUFwG7w82
VPvzV9I8XNAHfhSpzuqegXq9Yhq6l5+gU+0MxQ5IYZJwLD3PitkeAQ9i2Ax/p37FABe9oytEYQCS
HBaj6re9PwlIgZzb9s7RxbRd8MjrXOmS7VwmM9x6KVgYn4lZw6bkJ+/91qu+69rsaIaQQdDwc5VC
co1/sk7BHDvALpKW/HQRjFhn6nZrQJhTpI6Nqen5Qcocpicr7V0YEONCJlIjplr/n/X2zYWdXhj4
TdfWQaUghQxhRPTEfR0FiKpYnnP08C9+T78UtHKWeOPmzrF+M9OAF+atFLy2vv45ewr/gaFSJ+vf
eJAn4IIbEAU0COIQCo/cdnr58pFhEFvHHOXTjHIAveigqUnNsUCiulmnAP0z9Fl5vkzmL/gE6L9P
fYUTcPttu0aI0jv/Z/TWjKCrq+EFTDyWmw+nnKvRO8KIBb5Sk7mJfjNA/5HG6KKkY+DNvXS6tCHC
d06Tv70sJXt9N56Xd+ZxsZ15hOPpBPARrVyekSDCW5I/GrsJxw+JvMZGSGXSMt8gZLB96B7GtGJm
fUNPal4lKozB8SS9N6B/tG5HAi2uDzyX1LCzulMvZ8REbG30ewnxjekyPIS76DpP4HT0Klrg8lXp
kVKfcbl5IPNaQgVd+ZmcbtbYOnVvAY987MW8yZWi0H6xxT6eccxIpii4C930Xx9mK29wYJN0XkNt
X+7MxS/aJsVDauXlkL2ThzYjaMLEzTkvKu6LUvSeFoX5ruqjOE3x+tgbhc0taQQT8dhPsOgbxEIv
VMXm5PIPkGPdXpi4pnb+Lq8jSlRu4VFCfWWukbQAi0n/VdwywmiZgmcEpWI/pQqZZbGy407to3Zz
mhgIw3Na2jub5ZyW5XE+0jBuRCfZVFB9nXMXTuyBcVMhnWVKHetfF4i4bKeTXRcMCwz/zwg1+dpN
YjpR3DoYgsZstpclqJZnqA5XErt2hyFJooI3CEB880Aj8UTb9in6hj+AAwmZF7jEgcsQo809S9m+
etEFCRmjbF/kOhQEjzvTULbrVpEmKfsSoqboB3fGt8+/wtKUE5M5BaKfsAbhVwTmZX2fsxwQSI/m
pp7auDoOgzgcgPXrFItLHcdKUgxN8VrfVDg5AheJQH/LITf9Xz4u2vCoh3ax0KIJAgZ395MD/VaE
08Tl2i+jwNAY0f5Ji36f/MToPew8TqKu98EbmCkbm+SXjCeGAZOJHJe6FtxlrplXwwvPX77xUISO
0IejfaFSo3XEeXayUgWgZZKdST+7ggVw0U4Vo4slhdkP9KgkwuczlKHx3c00zDRYIm2O6mnUAAcG
hOXCIsYPZXFC0ftlpOU9vqivArBAfoRprAPzyDsCfMlFFC0jTNWt/8Ht9tMKwGqJ4uQL4tNizY9D
h6jUov13DVQQdOeI/mlojuGTlFjuZ5RNwtmNm4NaYbFQgQJgOv/EI5lTJE3ngGyrAudiiyK7SHnq
FMuI1THnPqJIRsSQH3+VdMD/6m5nAdzPlVeXauWlsue5K/5wrJklgehRYV/WDAwlnCYB3DuXwGci
gF3Ug5BVi/puLx//Eori7uSgwd7tP0nGBnFiHstjrwGBRnSEqK88ELf9RPf0kQWjIutD3QhSzDFI
9PuV1Xik+q1EebA8Y1MU3MBqxIoXPx1xP4mRHHvqt/335ooJPKPcoXEL7eDYwXHTpj7QdeHehZYu
Hksw2P7cmH3IlRvcQGYnTB8Q2fLsWeInuorqn5navSgqvXcy+ga+V1iSeK1VVZe2CkvZlRfReH8t
nx+YRSjTkB8U3QqzLe9xrS7tpMKXVgQdrTFn87WDveHLskcdr7L+A7zCqN57iA1SSuFUZPT0U9FH
EZvajRp7WbmzJQlWE4n69r48a1VT2zWwMlE4CzDthg5dfn9gsqV8OssM8eVFXMj+598dq48ZC6vI
aADCQm4m8xgKwo0FR6gGAecUltX+ICTxjpDCvALBuMEAATbji3dz8TRdW4MBu3nyEUjBXxq6rhml
7E1yOKBz3ArvGhEt1Uwge+EbvBbnNHSoB3pOxXavZtOegaBFeIE4cVO7/TWUADWgmaX6j8OcGw+u
c0iZQc1TQZQsP6ZtHt4SfrtRgH/JHQn63USj1ofIdjaY3jJB4W2OdY/xEQ0QNGvDeRimUi2YI7WF
sFmYKpgfsytwqwgtWDCsTjfKSuDMVn6unfZI88Dl37NQE8fpHTiLPSyktWXomOykCpCeyFY2kH/T
BZ/n//GcF5Ews/9MuXcqqy1e3fWM16x5Gnq2vaPeovKyikzjPTuN+MQ2EqdwFtnHOk8Zna1YdjL6
T7wDydDYarqz8IZ/S6uWW0QHTFuOn0wLyEo2TzpbbnCDxkxE7+xHWy/e7dEtc6x5ZjqpBO7XaDEJ
JRl3HJny5xCUveviFPjoStiUiLGYWVS9UOjOEV/7fQznpnfM6lUeJtFL49oK/DwJWlVnDjibhWw8
PGB3e2K1AsUg6RTpHa5wUUD1qLYHjO0+bsE/C+crcFulC4tTVxD8FTdUTexaNDQ8csfFQ95g2rmP
N0A06VCH91GJXqUHrMGcOA5eD4CKJeqV55xnXnJT0UvJJOsmv1j50YwRP5KN6xPIH+cU6gJENXY+
b6TkXfDsgYM9UbFHy/BG36T2o6Xbug4JB4WmgsnWmFeZp+V+tr9+xSMeG0BqKSq+1Xf08TN0c9Ri
nBl1td4EFR/5NvMOs8G823MEAajz/S3mEJh0WCLJZRH+zoRqC0e6FPdgS9JaFITM/TSCqM+jK7BX
tC43Szc4mxSPpB2ZvbKzrvZ9IToOTxsiHY5txq6XaoVAKdzstgefxJTZpCBe9gmCusj4/0EcpKHJ
iYGCphv8iXzcdcV5ZcddNq0QT7bL2erdzxrd+uhSS8SHsF4sCGt1Q9azTlx+PXp28xfHC9JoqwLE
ia83uM7VWLGPDlLNFXruHA2pefXoQYoljCwRkhZF74IIB7zM1VwgDVkIafkhr6LTyef9qw5OJuyj
QOyYu7SxSiyHMW/iaZg+B1JsTb0QAJoVgRd5g0x5ibiNYhQnyDdZpNBeSE2hzq6C7RbHoVEKL5m9
EkbytjcHzDG3jtB034SKLmWsoTvSEHoS2TdkGYJbZuRhcN2bPM4/njTEjh8orBRh8TxzbAcTBQqf
hvI37n6Tth8X8L/vUj6QLSwNuIdiciPR8wQCLpnCR2bFzI7YoovYKtu6SWSyMKPcLsVWwS3QbrIn
WPhTdkdzDixjOkv2qyOmJB8YEWN4lLJADbqpxUgrhtPn1c34YXsGPZiNUFbkG/kM24zP4UylZUV7
8SBsV9nL5SP013iv1Ov9sl9UVv36nZ8yGi1gZ4v2ITTsaGA7cDGg4sgyu0lMJYn1kyvfg/lFNG8r
I6YiGPaSMmAzz6pChdVFNTduO4LbFkadGmObmznEPohA0dv85ESJF5/ZcmsY2uIo1Bog97v2fVuN
2TckuVOg/RIqvedYpFP0QVqBCkXUKzJUFm2Z09uvVzn1oTCW1PeXoljE59xyWDkfn/5rkTludr2X
jDRsykTLpLKjNJDT0W2y7jKrA4g8i9TT5eYbGVF2bIaMIv985pRQzSOP9fFjKzGnnYICE2gLpla3
S+RSHwIkvvXx9kOocjLf1paTqTAJOcQKGSvcA+g9s93opGR/RRqZ8qpmXp1lHV0Mk+EjLVpNDk1m
pmaihwvB3DI5gG1vJYwlOdadeaZ1JJ9EvnMrf5NSwWKWnf2mRulWXDm72fMi1CeNY68ahhplCJGg
PTn8wvtwQNnz0+LXkCUQUpvCKYiz5YENuvoWFFbPU8DtCC0Mk7sstasbGnnz2NEyQ8lPUBu9HRDP
wQClK+yARLTWMdUcDkYCQpsFx1jVmqph+eKMkEbR2XY1yMqnj2ZSur1/zCPZfcgDulA4fbIAOaRO
czrTbDCVebrzOVCqfFLFjo8YdGP/iP04cff5pAO+JfQbQalk1kGzn425LRyeAEHWNTZ584iP7r2N
CzEsQsg9oJiiSP9e+XURTsqSFTCtVEWw79Qm7+uLmfKXwwJ2VUlmCLYz9T1DW17Tu53ZpPmA27xi
PNXvakQt3epBXOmO0LSvntLfL1dz5pQlgReBrBY0QRxD1AV/pEzAeb0veIMChrMZGr5LnFM9uZQb
QnREVEMtsUTMmqaFhDyWMXsAFeBg0mUQSBECs6rAeJD3NHmpOWPYcV66JQ9MlSTs0MzsP3CKyKcr
5WRheTJQy+1Usx9jXVZn4naN5wTeb5i36iEJ0ZPz1sgYsP9WojUVHqsQxgYFmgdAlbj6tDry0N3j
gm3zrysvEta5j71yNIhhAS1D4vX+vkDR5x//oSNMb4zAZuawQDchxAbtn5b4ffua4MjGf6DvfuW5
+Ji3/80Lbdf6dKII3RBTNawAN86xvHA0LV6qyLNLA1KR3uSyXh5LWoIWtwdTbVj9/XSQilnrIw6+
OaMHMz+o43oqdvFKQLriDEit+rSTNX1OVQzB4lNJwCeLzKmzM/wbu2AUYYHv+/+6AfLGZTg1yAV9
OI73+NXZ2UM1wkmKV1GJmZx9igNHnZf1E9MeGMa4kAiqhK4WPeYy2J2umhSpl8tkNcbAnV80fvd1
yslU90yacbWnw1CDlN9cJ49aVtnR+N7QUVpxf57lU6PA2scdQwnqnYF1bmOoeGHouBPgBJoMnyaz
twB4kjLKVs1ZjTgiOte4YA0y1WMY20rOjinIyMr6a4mFiz8FXo3BRjdWIrd+kWGX8UhdAI1x1Xy9
Sjwpm9DwSRTBTR4jiKEn5IL05Bee2d15V+LRl+102gT9AsKmB4VoPPxwWrsbgug9pI/20m02jKb2
mK1sQqYtDlw9sw6/MKqT/BKbN20ylEnyqObB4egS8BfgF93gKPta/kn01eTZvmAtpAJR4C8hF54p
GfYKegNntnmVCJgjNDndbZYvHQ2ad1jvSpm+pBXI2a322rIXqhM5nOv8fL5ogsDEk2Ki6XQhkKtR
NC1xDfVZmvGmZ0RqY/drQxim+fSzvv4KqBJx6vpnwotPqYvfHQmz0B0iJteBVFuSJDD2iuDVaZwl
cLH0bF6+vrJEAJGAepeP0wrZY6h4VXUGY4UvFOuCaoCU9wYbpYfPGNYUkm/PZ25X6cCcP0DPs+Oa
eZMjpeubWFz8pIXpSNkn96lOAdS5VcgwNo/UGP+KC776/kV7dR2tjvCGEuaoRW/yw10yIXZqbbR8
fhU3kCfkBeA5Bxb85/aPsaEmagmIVY4lUjSQZFnSzTcn/h0VhDW/bIaQ8cnP/2LKL0AAbNLNoEhj
UvL0U6X4J8RseyMglhcGmEHbcKmvsgWQLYHdiQZO6q8B1QLCSOIDxtydK5EceJcFXSGlxALBwiEw
Q6PwPc7jsrsVZnHWjhM+YQRrHWoYPTWRyNcdnJPBrBsFyDEvxJH5Vhroo/Y71AK2GvcmoZfAsjkn
PBUIawQGy5vKPFtFngnFG0zzrgn7s/iHP6VdKZ0r96RgUKnmp9EiPOgW6HAJ+iq2BCT1sWM7pIyz
1RX1j7OgsFriAMtKUhIStRcKtViYvJYaYoeFN9n7QnAk8DhuSdh90KNlLXIvrHcl0tCcw5glKw5n
Ok/7uPGBpo0pRympUMzyg57zkgIqhbXels5BOJVio9YMwScheaGD7PjigPvqYvfMPMFgwSHm2Hs+
y/0RfsNPYuGW5Qpz8fBkA88vJIcp6b5Dxns3MDSISRTpp22gbO7AfIlKwLp5z2//wr2N/y2+5sxv
5cU/igy1MRtBSzwk6pHV3QOg0j7c4P/wxPzLsBWjFZ8t6mA+wDtkP+9UHRhLwrwJplIqGHdrxlOQ
cCmctKGM+XFR6UmUaHjvG76cDDlPGGgX7wsKvC3w+rzooyYEydyUtEmlstSGps00n1efBONSh0C5
O8snSTVeQPltY7VQwgKyA85czzxIGQN3h55G5xFBhXmTEu48WtxugmBy27I/u1FSpNJy4az99tzd
Ych0PRPrSdK4hNDQaQKU8N5ZnYEJrKC056s5ruvPdecIms5BsagVUNSmCbHSkPvPcP5OpqTu0cGH
wHKegh6th34Iu6Q8q6ovrGOmhJJyihQxjGXsfF9PIaNLYw/fC3ZuuBBof99YrAuYe12JYpmI0rxX
9QMg4prlN6NQMtjaaBtbajWprez284YPWOlhE1/TGQZ/lAMgzQxyT3i4uFU7YJ88T7b7gmV4K4bO
RX5iUSICauTQ11L7LzFkmfheZhHKIQ5w5zum89+n+jSrtlAEGjGWmNHH956DjeLQGGg9FEZey/2d
4ctsMLr42NAdBddvClnGIu6HiZqpiUpxNsEgCEw6U6zIa/Wm1vDyRL419mFFuJwQajRHPe1QLIx4
6zImXh0x3/5gUj2o1ft8+EzSOLlvQ+ZdSi2Fc7kPlMT1JDGLPUmZHFTWXs8xocfJmUlOUoXwo/Ae
mYv2GsUepKQdv/e6Zsi/qExj9w/l1CZwJGm5Bo20mAR+HL4XqHdIeu2nf5es7p3nbaKmhtW+Twt1
UzkpiztNgo6cVask/KHgR9ugageKx/y2jZZ6WZ6MwSWqSARZIaGFQ7dOizV3R75+cGslfYndDJti
D3q8Htv/m8FHF11In5H0f0iGmXFxHmfpvdljJDh076x85YHfi88RWXDDB8u25VGnpt6prF6XGv4u
EfzojsQmlbMhM2UoIwgglK3lpmEBZLQ0sBUh+XOotrah/Fi8eMfXzV0MDM8MZUuzvRvqiqZB9XF1
K2lK+H+fu4PQ430u9DvRUm3oylt1o3VvlfmYx0gJoWdUcJVfXsnNML0G/hFku8PeShjhTU9flUNM
KPhtXotB4QeMpuXyDx/k3Hinh8v+FwbX3puIDEoqfOj3vuhwHf1lezRXCGRC2J319ufDOu3dl57L
C8mZgRU+Y3Hcq4Fvd5RRXR3HqXGCJTat9C3kIaEEWpMx1mNB0xnIx2+I2nM/YW3lneWT8dv47hki
CRbDtN1EJ09rOg4Imb4CfxJzwDmDFScllSATPLRQhQ7GamYZH+2+oVH8UV1I57t//eNethXXWzvJ
TFaIESUu8BCTsBe9TuqayOP5+6UKi3aYL6nsr0bJD+IXSq0WDxEgWaxW4KSgaG7tnttmQoRvkhT+
G8Px4VGxEoZSYFCgwh/cueaZud93KvIeMPV+7CMAqMtpwSnYlviZR9NCoVkelNNFBnJ/NsgnZaEI
P7Qr+VTeMcSyDT39PzcfLMWqlgB12FJg3dkaUIX75Z/DQxUaVZ+PYPRdpC6AStI9342h3knYGaLP
70O+WCoEZBAr0T3RL9X973fZfKtmE2qF5MwKWxrkeTORmE/3A8yzEhl/A27s9UHyZflUxsPVoBHc
tOmuhN6W2RnscaiuL3l8OPq0rdM25c2FCK8eF6args80DxdCpqygUw43TbliYqFvP9w//Cwc7nHN
LtyF9VrHroiqAiz77AaaH4hobRhiZMloGlxmrsYw5ArmlpEv2GLXnowwAexfWXWWH+AXtwrTrs0y
DVr+vjIEj1F1GOjRJaAq0C0sA5PJv4SpeSmuiEMqnBc3E6OROl0PJsUSAfRIk66/5GVrv9qYPQ61
K2AEsqm3oKScg1byB8LfBscnW8STatYIO8FkSuRka201HlXAWU2iY1VivMywyt4B01qNl0mLSATi
6IN+vp5/kRODj6noXBQQtJE8GQ9zRa6TVoMhMz2NUJpG513yHxpS7waov8RGQ2qMvftMeLn07ier
2fMilHE/y75+DXYr4POc3I+NciZh2alugJKLp+XbkgWgQUDJKX/KIp8o4twUWxmLFYtCxjHOiveE
L+KP7bzIQIR2L+b3cz/mKjMWEUSorCCnavS/1TOiISruQvy/Cubv8bMoHhGmmZQuBW7n4Z3PVWH9
VRmwsjD4h6CMR2VdlZ7Z0+pu6CH4d37l6pVLGSflsGcAqFreQdZ6yXP4uH+yBq/ovTWQcakpM2gm
f8iNiraGDbkjHuGDLHhh8KUnN/ZIWbhP/l1fs7pkUKnfpDbsWy7m0D192k8ZR+EAOJW53FU6dpzK
7zYRt/aKbJwH/RA9xDNSiKl0vdgLbHNvBNSvyvmwpTSsA24Pbv88nhflUh92dAY5HekmMD3Io6qn
u22qjQp67/BSUA5IQrZOVm1nmfXRcVpW0iFkLT6PB1x8U9OusaUx/WwRssnRRB5hQHXMjTaOzudK
FuRLc7y5wJsz3RDSEW7g4CKhAkJz4nbxQYHTqRuN56c0W+CTwllVVJ3C/UGa4ixDFR4rCIqN9NJv
gXSN9jwgdKz9yUk9KQx5wbEZKvTrCgVVyd3Gs1zho+FmTM6Fbnkib8FZZ4+hp+QAORGiKCfclp2U
PvyE2dui8HENm0kdY+LHa8B8JHEuJhLathEr+el50TVALigepUUtfLPws+zpds60843uau+8k1nW
ccaMNLuix3fHjv/m/ni7OSswJzwhzsOP9Vlcp9UgLfXRx4k5xJnrb+UX+XVEPdMcP+aQD+PUBPlT
oFjcGdMHezQqF9j5X67RGlzdttkCmXxIPO4n8PFFMl57DlrpXhn+eZRSZVsbHvGWJncQi05Df9xt
aFcUqgygN5YWTWrtCKL3DxgI3A3+n75DnATlwo/z551L9JgLYHG0Il29NLEfVAxFaglT2aQiK7A6
Sf7pEfbuvcpNqa42q1LWzi3Jl7r4mT0jbMT7oyuNKOpL77VpF2XyP5StJOLLT7Bc12ei+tAan9+L
Hi7p/vb9IPsLgF1BSNrgdx2t4XwGVJfFn83A2hHe/9eHIRpD9a2jMjCbGVFQftw3wO/0cBnffYJA
PuK53PmRrRYIe/GQ78tOvah3bHmSeoXpYo9VmCOWzTxlYKJVRKUc4pw4b+1s8GCmf4Ub+9USsnVe
FxixLmEzGtU8oX7P81uSGcUNXz6xVChCU/9J6ziHDk6BvGCk4y9evpcZmkzUTZsOtfL4COdK7DKF
HB7stRL3aHM0sojmQ6rBkLPHSvSzJ6/7h0xWxYYlOIDYgTOvrvmmHl5JOUR1nwEN5IqEwV9v4MpC
S+9c5yArufI0ls7vMotcsJ7Op2Z+2UkQJXOg/o7pM3opz/0afciamG8ywfySIMWdFcQSocjRrmSi
9Fo3ycpzFRpfxqhiBk0tAvfAB8MSWvkrNBPNEpzvsIQfPDSECkk36CYW4OUriAesWlPwoWpdLXhJ
LgKYBBuuForXm4+JQxeqAlU6vebHnSupAzA/Ln91n+cMNclcgDfX/9KyxBKLDoF1mBnhMZf0w27Y
dU3wIZv+64WepSwQiOuScH35wIk8WjVen/ZLkXMRzrp3/QDhPIdQvs3xGk32QNxguILoBllxNX0D
+Youx1gN8eOblOyvkf5VlwG8Zo9ZAeqaU48/J3iFzPlqwuSrcqNKEK3d/rUX4tJfVI4ROKgJUcO7
Vd4BD4kZcZNe88KcHOksDIWRQ+nr8yVKeai1PHbZPoUAeKoC/EFOdEJENKDbJFaNANGmYdVULsLb
/vdU3J6MB2+LnesSLumuZTg6Yy6l/24JOQWjNks+FYzJv/XXxUmXHvDka7xpUB+ghUG4/oUZAlNS
ZHUIXxP4or3QMbMmfS7kHvqQLTC1Z8dZLhjk5UDo+PrZVp6Zg8ZPt5sff/P72Hz6oSE84nXJxKjI
SIvwNtxuuR5ngJUzpkj4c/BLWxXIH4z/cHYch6BzcsaJ1lsJYmV8jaJ46yfjtzO/5fD3EuczhNq5
Ab0f7KyDrPYNPvSgaTgQ1VPQMj8p0EYwOSN/yVW1bi9uWxKQMkefGQYXd7xl9bkEdlanZSrBosJF
tnL4gyw+mUWXo6p6T4Z5U4jnbFasmwzR5KKGYeUd4x59kN6C0uFRT4RPlx/KDkr9NtVKnfdk8UCX
315/AjPG+LC47tXcwRLbU04wHEM/Y5bHBAKyaLuWESeQ1xwpl1bzcsWm+3GfHoLLlahuvC9R63Nh
ub8S7UZXnAaQfqrtbzWkRih1dBNRgT3j3mYjqsFD4VER5tgCvHgtB8+oX9KXYeD2OQa+NjBYJokF
8mZ+YJeozJG3IUguj74KsdJzAiHlhbbauV4UsM32PFLhvaoI8Q2XL8fuhsvyWg86XwFl7ew0Lo3Y
qq3yCLnlgL/FuphA38kyINFP2Kk9/Y3cvUHL7qXuXYECyEN8Yka/rr8qYyzbzvOWpCGcdNCYCg35
DsjZ7Q/CCjxT/1ea9vSXqDAdnLqunpCWIr6eIda/g78knkGZbzTxbaUGBnHGkg9slmOhDY+KZwBW
Z14BFnQjAqQnqRQ8Y0VsM7kqRbG2dKU50jQaKExucaWGd0Vw4D1dhKsce4mcIi5HYlqgzv+u2hC0
bWUzauNSd1M9STjOHWA4czZCvzA3ET3SLHqp08TMChLN8x0WdCuTrs4sz3hQTsyFhumijDVvgvwf
TgcRCt6rTIzrDeumFDC3TFn1jzBwdunpzGkkTtSneYLtK+9SDMeswfvWqzHkWiXJ+BWpb76j5zM8
DvxZSK8mmvqKa3fJXazGenP4U/BuquIYJLUVAmgxN1lgtgl6QnfVlI40VOnSRAdXKHsKBGQktfj1
pI05+yqS2LP97p7a6uJiBLhSWNWKT/kCV1eWICj2USldyZqKfHpve7T0gJlxlbEsdFejpobTknr1
qhOPWQxVP3os5B/4+8DVVuiTqGWGxwx/vo10bV0mWtpIiFjJQNjtiMMMrDI3ia7cn2zgSnAP5ion
cIoAnydQAo14CpYT0gua/bew9J3w1ku8zWhwbsPMyrQBTZnAVAILS/1POyvlx/Y1I9YSTweixAj2
K/I0symDFhD4K+tfa3zh7oq8s85A8w6fJnxt75Rs513R7xhscVdJDnc9lE/gQoR6136/ddS8ADoZ
z1heI38Mo0W1KoDcNs0HHwZ0jyiNIKiDVuDyHfNfaJogcxz9DCwQMo6AaLNC9gqCAWNNr7yjW6GK
g8eLXZMKLUIsBFTpMTlVeGdE1oHZRXBaQ3RUe8TVWLl7ntqRJ+HiKKQU5SEYfpXM7/FyCXEEM3Xg
raQzma6/QYCeybLpcyYxzMPXS6HZJvuYT9uP/KZvS8dRa0k/THdraQz2KWmmGW+3YWKaEh1HVF0M
p2Qqmd6Tr90ZgU62bXfkjwj1HjaGdLjtq8cOz0l7CVjsyhVAbJvtfqkiPg+/BdlLWZhGw4+69Wlz
dUEzpSYMZdCNW/FIIM0HjpQU3687eJ0IViN0dXHKR6Hb4Vd/AU808QT3XZ328pNZBMX7DgnETc+i
xC+Kiovyx95szAsxRAsjKYQ2lv9Pq8JCWqPUk0jLxbertDbPRwXsA4uPyoRCY54xbMItxRLfMTGW
ZeQI8X5dDFKLD19i/KmlDdr1mTvzpfSeHMjmLEtzWSO7guHBCMOgU6e5RMlQFYvcftzu3ADwH737
WoElUYfqvnHuYA/D/XbDTvViShTAaKApLTucrppzIdVanHVh+cvuU5nu6nmtbopaxYcfqj3j7LPO
bGzNioO+GlgiGwn91tVgrDcwrOv3UHfDpZ6ZXkjkGRj1jg+NDiOTSwF7lDlGM1AEWzotgiTr/6hr
ax0TVYKnXP7hZNe3Kv3TPqYIkBV2GBi0wlfoAK0r/BAoxd8yB0yuseqwVzENE/d6+rlwH96lLM2I
e/po5BEm8dUecPQ6sbYBFBd2nI+Cznab1IZP9X6kjiJRKs0a5IYi/obkuX0t8pT1CRhXe0hEx3nu
C3Ub0kx2uO8YFeQOMKg/TgWP5c+X53WmWPyQNAuV9F1IG/hQqjRozYerg8jhcpZR5aVTEqqLJhCg
DdTk677t9J7imV8BsoSjrRChUM4ZvMEEkpMkOmbMInnYOBjc4CPc2aGvHVDUC9WE+mXydA4LkSvt
3df7xeNR7zyIVRY8iEck4yMMiLIqxXMvEct95I58uCe5/r5jZWpibQAkxytwRLUIMXzLbLAlZPyp
+jmpRXP3Mwg0OqSdjYLxhlz/ATqNCU9U8gGTlsQ4/yGVW5IldFf9UE/Y65wxaLEq+IQh0UD+i64j
FCGrHhSunAQpjso9r8cH15K61PN3yMmztgPSPdzb1XB5QIqNQqJgNt84/U73o1BrUu77KMCu7eef
q4mOusTAydpHPiK7JJdQc2Nl2gppoDN4LIBV4JCmDd90xnkfbraKLRzTlZ6miznoFgR2d+LmOtIP
trgwIwQAYYhDt5alpuI90U6Io97OXtD7hJRqPHgc0KnZBA0Obvz1OIcCJNfCdVyc2c5Wk6v4t7qM
NM3mBQub/vE4XxFPQtVIRMkL5sbT2Y1gm9OrtrkHngALgJEmtunFKcO3d04h5D9wqVl7FoiaSH2p
y+EG5ays7tEnrmVUyXFWo/an5StV2PxjdtN2yXlluVImfHCAXIFVz7c0m/zvQnPlukZrBtFG465Y
mUZFbnwClzWUEhhxsmxT9Zj/V/Aseb8uY3eBn3tT4p1VtzKtR0twvCmfAzCW4m4WM2l2AR/prHow
5UZdlSPg6oCZt/HI+LtmTL2313FxwgTNfdlsnWGfCyrIsH+fo5gFY5YO4wp3kilTwo9BmeqTiaJ4
qXyQscGSKJeUrT++yGI4s2x3iL3tsaEVEeckiGd0kwMmbX0t06VUknwlCu1zgcsI8Nq67QHWQHc0
waWJ9Ef1ZocqUQdegMfpuFcS/hDEDcthrSLSndEDOxIgjiUpAiXlAGxNZHRHm1/YtAAyQ9GgseRC
K8kx0rlQR2v+Fu+o2WWIyIxUAXYbbm1RsOZQSolkzQ3VMtMzM+a7vc5swfkrCXUT3lgT5RV52mko
s6hpFcdVNTD/AkNYVwsMtUhv0K7GlI0aJ0JLdu6Gsu3AL5OMNp37FU3qy6N8MqsYhm/Nhz6QslJE
nMLOdEJp8FzrDLGwwynDUAhjL7NBormkTjxcD4jDp8XmSzDqkPi7LOaDTiz8r0ah7TrxpByn2MQT
RVgivUrPIgEIMSLXfyRo5/9jVunIyizt86fPTg6emLbora2z1ZIW267TXIp8uREX2htu+qq3Z6sa
jIs0ukCfFXQgomrQDAe6T1fenmRi9g/5kZOqmao0P3tJcU4C/C2BbQtwN8MKcOJkDtAa9dwX+OmK
SLAAqreMnRus0Vg0JciwS35zfTMn5FQRTSE4huIU701EM049+e8JFKRoRkHx+0KFA4QXEfMjerps
woFdZXcaAzzXFHEB2Y9BBgrpU+xropB7rp2FOtNYydhT0OmhnzQ61cE8sbr9IPbvHNuwdlBJkTqS
3eAjw+9aLSmAthTGiWkB93lQGtp03O8OuRSEToBu1pwnRZdaM3ovku14xFl4hrJcruK66JM09cZf
6s6WTb3iaqyZFP6uymAJ6rx4tNuF2yPLJ9OSMp63yKPi/b0t2HulonTrHV+nr0BleipoghzKYEUJ
OQhsWonk0fMmpgsJIQmiJT5lRmjeWjJGvPAN3HU/QEISNh1skL2GKzsa+2hSSvWEarLHFv3F3j/K
l903ArKB9wJn6XE5WsCGgt3SWY8rUkPqEjYxtY/NtIiDM2MFzwNag6XjkStdPemzgVXwLxbvPnN4
Oo3M82tCZoN9Gbm6xs+30aYjMWpUhlMXFkbal+43NASFPsEP9CblmmprOq0xFP736t4rThmT1O3/
i1XZIHtPvcfp9Gy7JQ22AywhiNevZTxoFOvBbrdmpyLEFP6NGWqNS5YuFLdxGsoGU8+TpeiEKZ/N
ZyWrkpb2yua71PUvYNSsGCnGoio6V5rgLkUPB77QsIsrWRjjuJq/nv9zuLZ6Lv8u7i+jIjnD/4kz
Q5A8AICvf6k9zsXrF5n/c2IWb78OwX4bk3Te1g2jjqcRk6AinpP2t2z2XC2tfZOrWXjav/K88FhA
RfPIQByt2N7yC+3sLNIX1uDjKFysXdUkBPheZ4HIm6jgtyJQEJWmLU1JeBcycPxWY129YKO0IZJx
7WVjcHq4uXhGTEaH1LUwBh7IZ/TYhoOZ9UaiIKavD7qnIMNIZGDcbuDPkYkyfvT1GngwWnhNSPyx
a2Fv6pGEp225on54pySh81fnTFGXqcW6FTmmDw/tWf3dYV4TVT1FbnCegb8AfKuxH1EGV7tmXclT
h1Qu334L/IgzS80VZjD9UIFLxt5L6SfQ8gTUvWy8voOfi6yaYh49Z5Eqy71Rv6fVbpOZyXzTQxRH
ZJG5b0R14kjDLC+ROf3lWqOMd+5fgGS4TLqtky2Bk9aYUtFNzvAPB6Q/xlPBi+B48e5x1mPXR3oR
ZO1XW9nZE0Uvijt8sdCPKzIaS0LkRMUMPn2VY0kbyFECdThv8dAjs8hMgJe79ON5DwCJgRaoKB0P
dNAqyP/n4eTDI1hsa/JYoiDJpTPH7CwRL8StTBBSGWzRKpc8CfsH/gvqWE0visSmYyQhXPXn6nJO
D3myws20JY8sUXiydWkp1kvITTR9OkNWRU0N8NP2DNeijZ7Z70fHAvLkMG8WKCNoVnDMQn5UBHDp
Qrz3hCOaPVXHoqK8yzORYCQvtNyzpYEl258C7vZc4WVhBegGkYhVd8a3gHvK63lXcNOe6IZ7KSQL
BfrA2NnH/7wbRDzCRdcLHLQKTK3AtHzBl/0f0e3fIv+3BP2Fea3E6C2AdpPMnoDO9fn3zQ44MW0I
9KgwF5oq7gJqnY3xkFssEucV+x5ZGGv2q3y7vi8GBeJAH8KwgudfOwy/GbJvIMYxlHMwLBBjUHR3
6ziKyJkuX42vnsfKZUbR+r/dbMqHToKYdvcZmBsDlSDEFZvKz54T9Sk+uk5RRJmPIEWLnh5rbO0C
9FZBxo5UnXVBOU9dbNEjAMhRNlQxH+n9LXn0m7f2HP0RXv/CXT62IkL7ia8SpuJLb60ZPZ3a2/Ad
wxRb1DdT8HuMTtyTSz/Srxf9ul3L8m1tHU+yWhM57Ea40CWmIpjTWYSIqOkiqkEIaApuB/IteyU0
2lFSXs+JOkqWmuKDrqL3K/sd1iddMRbYW+cvyrUXSZbggVBxEjOfshUJ8y2maaiFVCCS1KYV1zRw
q+O1CVGNm6dESdI42LDt9acfS/aI2Q6LTC/aMiw/7fSa8S3MvIXaVj/OnSC+z2jXdiBlXAhHzRtg
+BjsKvvOo5cFQ/Arwgu15I+7OziqySZx3sbNoWgrjRemM2G3FCvQvx2B++F3Iti8SK6uhwi4r9jm
NB4NU51HEcI6R8eL8POexwW4/XPOHBbD16uemW0xmpie3v3/B52YgCLf3GN/PE9yNoAQKGo2Dcj5
R2G4vm+WYI+bgSqOrHJPtV3KOiCKiYSxnMz1/jvbRc/2SCAZLm7D2NieMJY4eLbNIAUfXWLDpO3n
S1JNr1aKPggwIFqUtn8kYegUVe+bWlP2GKe1SQVNjwlvJNHG8VVl21spb7HIvPwUJRV1bcUYkESw
jBuKkyrHxmANiGsCTaFqkY7qfDhrg6QSXFgbN6QQZUk5PG7gDwIgeyyO7xoC6oeBkWqLhIayIXk4
aqLoPhNGHlIExF4LUIij2GP3u0Rc58xCTZ6tuqP0A3WOWlsleMG4zWbe/k2q0yoyckvQcVx6DOsQ
UErQ4Sz47oN8mqvkAcTx40l7ShSt2Ns3hJwfHHKC6O7ZxX/jpABhGuoTcb7i3Nxm2f5CSaXTCEtI
WWC4wDu8rnuDo/mc7rLcl+OK9QX5yVMPxLUf1XNKMzdrcZoCrJs2c9ofFhTSSsXbaxV0pDbBb3Hu
+1Ff54LEBQSGhuNtXj8MY6tw9tHz/kRmQTsrZQLe+cjeLdh8xi+Y9c/+/smi/UsfE5TdzYZm3umt
ftpgkn61UZ94FehkVPnDZJfHsdBxkh4BMiYuEDjIp1xuCF1WmjUkgDw7Do3ZdzI6qYRleHCGEjvl
RvOYyFjyWPRXMJ3WqLWztd08V3nLy48tpHxpJxu2FMC4krOsTJa6F79TfJudnZJ+6302IxtDhB0R
bh5mHZCRUB9D+Y3cfbgxouBQ+H4PLEnSmzLq+JZywgt1RlI1U+kgWqGR9ZkzEPhAZ2s34vMd9zOr
et68PqatOWOMUqnlRABaHIlIHM+pW9X/nHpNNtNHG0T/W8oil/+VuEfqGJFm9DA2GW8b/Fm5KEL1
roWyBlPFDPWXwl7JjhwYOf4r/Klb/t7DmplCBMZlq8M14bBuyLg6zKlH6uZ41iKmnp12Rh63eNPN
G9V+BG14BvYD8aN6M5rf2gvMmO5F/ClQIEeoNy5Ad8BRDXU0sphpALtiNr4Y1tvmRh0F/K1aE/9j
Sr8gfAhi8hTH1fSFWoPCFRFGtv5E5XOk00IlexO3myOris5L9jYF9CbYyKPIw1JqdW/uNpY0IubE
KsaE6w1pIhI/kr0IzZEu2lQQg1g04DdiS2BgiNxMoDd7+l2tc7LCLF9trXZ5D1Ntav1kbEkqIWOg
VrNPGbUeGwykfVSDFQX+V2pYvLNj2M9IAmqOdx20SkMmWSDik19bqQpqSDEFcDwKfei9kAlKBWJv
IQIS0v7pzA6zJYO6XQ+5mrbcCVKVwIzJhcOFOy1ET6ArumP6PK2HCMfo+y6j4CxEOBqT/jSO340s
y+GtZ1Mp4zj1fymnh6OL0OeQKBwqQXSyPK62ysi4t1kIwnn221ll5+w86wzi5EH+3VNHRVWwYl23
2o0WtDTKOcVMfgzga4gaX4IvJcvHqNd7fgHSbbtKYc5kiHYJs6e3fP376Hr6E73xbHHYMeCZmHSr
6I2qQsC+roxejSUn7bt+FxN8/uaJLkCguXy5GWTOie2llGhLL9UEzie+Zj+DSw9c0AXPv3JnG993
vaKUR5KOt9jNT0TizGPbqV382ukm71ZN8z97eao1iiUFnPOYguZQoU9CrU+1RnqxMwwV3h76mRm8
1QJ/W5NLeBxG7Z7LEdIWlwwhBelTXiC53/QtjH6tjGwLFtbZTW1XGaNae2F0O5j8/DON1W5ow+31
Clxf2ojonWrl21sTpFaOR8MxqdQDZfggustV3WYsxJzxrA+rTWK940cI6Jz9Z29FpbhnOiGndEd8
2x6jf9/7QoDbW3ZCXE2zokG6/HZCvPf/+SRX15R0TN4B6T7T/T8EL+LgnKT270jA5Fq0Lv7PlamB
yoc1lXllegWE69vzy/LVWbq/OV0jUcscq5Qp0VdABtedNWi0bML+T3mJUC03BnbkKOLs9YEsOj/t
4DxKPoMlfelQ68zeuE0clVl6a3KVgmibivB/21E1riMye6z6M7IAoKIjftOyz9ITuoiDqt3dr11t
dKAUR88VHpg0bluiUEeOxMnlrSZVnvQ+Lr5Yr64T6ezVHsyj5T5ru1IlE6glaT8CWzqLHXDZ8pwk
9ia+VoLT4bPgkkp8GghzIPIDrUkHbGbHR4sl0ccxpZm8iEcZUPCfE70dd/tenehcHL4fbywXP/xg
BGylIuLebZO9uf4MtQZiBcvPSDujW3phW2wslgSBPMZj/MEfSRpbyqBQyQoe5k9HWf3Br94nJK4u
iVbUcmFCju9PnDPwthf0wakqvWFfK+oNKAJAiZScfpdhcVHcGMaw3nouGz8gyi7CmGcEbaYUM5qa
dCtQu0LcsVXHaTcivW4I5tTm+/u9Gbri8mfeLIJFOgng1pEBoIzl/AdC1VkSppl3vlzFn9Mbp2yB
oMz1S4Ax49WLo2/IRuXsj0y0RsqIh/5kn1SdVwYZ7oPwcKHbzFupwunw9EhRURrJwmdvpD0mZBBA
VuvFuT4Va0R/SEvIu4cmabSWiIKXaa3Edq+qubD9fSysgRGo3qsi9uRo5gTjo68hsZxtijrAbKMn
vr/HJsTLpJxLnLBJUf++ba3XbGnFx4Emwl0393A7NKSCm2ayI/6a59GJ5RKE3Lst0TJsKxWEnR+o
+3det9xTaGUSzmdsoMH2ruOUo/6+fyJQcsmFlepsi6XSxeEnpF5qeUp768wk4rHwJ+1+pvbuNd5J
1cv9GuJOMPre3xLMMRJPbYknlakOGlGS7CjMuQrtdapUXfZQP5pjPb9Qd1Cxb6zEB/inE9aiw4Oi
Fvqcm2PENdJYvEs7i3mz0ycOaHM2WLn+XblUwhPXZRGwUIRLVna64K795xuQKCMz0R2c4NWvfZwh
cWuGHZMh5MV5sNU4TU+UVXcq/8r55FXSwMNpS/VIB1NkUDb7HyKTTo4j9A+sm2Dc9ltBF9HhmmtM
CVdiT8KwXWdwNuZU6Dzn3UtGt8GNjiiqpII9n2nP4kas63d37/CzFy8EnZ1Z45z9hWRc2Hvd/93l
LBCTTuEG/xcyLoDAnhhWZ20+5BoZbXZXASOxZfJthfZZq/zw212ZnmCjW682JGFGpHh1lW+H2WOH
70Q4f7hevEVFh16jpHh4NRdIN3HBWEse65shCWwkf1/HG2io44vjK9M7veTLgcX7YrQK8gOd/gJ2
BNfJVJQn/+Oodi7ri6v+HOk6LktDrzpb6dhX4BDGyemCOnVc+lWSwPbwIWYgPUuFFZIqEYnHifDv
PepHtDW1b7KQVb0IEiJhoN73E3EaiqJeVEiRn+CUIK9VZgsYHiH+SQ4qUT9BzZF0e4GvxTaHDPDw
ixfkZrEJ7UQvVYqvjV28pUtKEDtlH/S9423Xh8wxo0vhqbd67mPgP3tzqGzF64UID0h2WNJh3pBv
RhHmGcmCR2kdHS5aVRwJhmZIMSfNono3hT51HZ6x3lfnV/fO2Mfn43maSrjgtJGRPAbnPlBlkEl8
gVE2F4ImNKb5toCKYqWuk2pa/nOlm/AslPBN/MTSRucUVOaIkLpJ9DuRAJiFP0AfjhHbGkg29V9E
p+b/WF9Am+H7VX3BNFobgBPJ8/WCCnZ6V0Y6WNV2xxJtlBDSxUb6xmXYDP2swo+8beRp7ExVZHdT
4RUnYalKTIEGf8Lj6lZj1xO/1J13NuK4dSM2BHcByxF4TbtEoBE3la8Z7sfSxbg1FRYhpBPdcFRW
1e0e7dq+/4bcirbPBeLgiwELXOm4JllDMq1jusiy8RX4CmDhJ6/h8MjH9vQeh5qyw+s5Duf7RUyX
THXQKFUnWIn6udaqIQIbvjTMQQ7t492VkCoV9+KLay8/7lIO0rfjV9CkF2RYL73HW9cBNQlAvcxI
7nwGjSUDHM8rpVTHcSGY8ZxJgtb92JAAppwMHeiEXEaA9Hw4eGMNbiZLGHBITK4i51SuTYtshVKx
7Qxw1PiuqJlo4AsllEr7f2BrWBV2gjpt8JVdD6reavGITArhzlP25gkc5ENYXnebRAqFRI8TFshO
gzll55+6F1jSSY147uz5yHqQaij/nj0Qsq8BB/qnFBBCHg3NUj0ED8624kUkFqmKL1UA8aL3Ttp0
hEmPP+XtPdD5/2oBtHjoh11qotOZYcbm89k8F6q5hPt3Hv+0ByfxdMkSoGi8DP8o0isXThIRA5S9
Ae/xMszcOvJKxNuBhpK8spJXuqIyA9WZ+NaVmu23bSgsng51lttLAjwAfH+EOndu0Od8CnH86sNX
3Nmnw519xpKydRV1B2b9pWq/IxYoARJAgVAqrVrL9Q7RICycdhnmVIpuDF6dUnGSg5IvtqygBzqi
b/WO41xorGWucDZgWh9RKBcIwgW2lcbAo4vUsNm7Su80+IGK6mCN2BGjYMmVtyz85EAkioRa2asy
cg5pFLnWkbKS1B7YszSL2MRGhf3eLURhI1mS+8AiOhfR8Cw04TFhf1SGe3I3vex3sRVlXBGjbwDT
MlpN/Q3EQqnRkcQDE7vqpo8IJd489OAbreDeUDP+uwT3ZnBL20mkW0KjJbn1DUBrXA0ZSKsMODKO
EaehPkE/cIuOaRyhzBN5SSmIJU6u3B+/2NGRNPbB5/afoXA6UMV4KKp0WPVjJ8lmh2bg+8fxey9S
NdvJFwGrcZnegVgAVXiJd6+kwim5+JdtsLPQ5VxJuEK7N0fczearXNSXdMK6crxKkZM58ZViai9r
q7AMrOvSU1pxqftmal4a01cYLNjoraf07yWRxr1iW2Ij537OulBf+mE5kr0QOwmVPbO/6mzgcokv
ENgc/4fUHXNlZFctyPu8liHAzOs2xdmC7ccvS6wCtvrjPHRUznSQeZaHBsdWDTDS7eu8kJ4Lcmjw
UZeOgC69IsRVIK/4GVzw4q08/QvQlI7MqtFYFLHu0b0tLf0Hsc7i1Q6U7MOT9b273m0QmObSS+Y9
FdJiPWXiQwC24bMuW/GPDVlrze258kc7kwKZXBftzmyp8JQgeO6fVFfcDtgCPRW6FcF+q2T3xTxV
scc826oh2VweP2BNzopp/Hyf7CA90Ly0fuKm9+1M5eG6/YfzwGuTBOiPfl3JVd+QH5auP6/qAIJz
ifiVJNCg0trxsUkG5ij6wu0bXWDBEauV5wZKqLF48iS1osiPTbnTMRM4lvskCNY8vOxS+647Wo1p
gipCdjwzodQnd+NeaTwP5KXNT8e936drGQP3tHYlYzo3UBOppjyZGSAs4CsLVqe4i6o4iclCk/+Y
G1mGIkhorUrlAaDjXqZdhBzfe24R7jDWw//3aLFCwQMQ16ODsOuvO7e68qTVT4i7sKiq4eItvrAc
XKAoKugfZS7PKaofRUE9lq8vQsUusBWTdv6pd45MW579gYZqcqJW6zfHop1TZ40+RhKalwo9DI73
T9Tpxl91mcAaKXRlP6jIer8fGv12AR8Of48wbO2gLyuRlpkOnBLcpjP9GuPquBZqK93BU6d5eN7V
SyxTw9V7Uq9u0RQfclT96KrSgO6ASjXNyKPBL1klsGJ1qrvQZe2RpZDKpdArVINw4PpC/Fg/Wrfg
CIeOb/h2iHOWELaTw99k7lH3Noqc8rPJP4jtRIJGh94NwOewU7gmLHtcaQDvTo8GIxHtlGA7NC5g
BYRX12RkIZhIZcFnjtKinVlwmdLe9Hr+TgaLdkgFdBey8QLWxmiP1/NKfil2EcLgXpUYxSO3tylo
+OrWOupXexHj6Ct3O5fUF6txNcxf0ZmtEzAfY5Njq/Cfa38oMcmobhqOsAWgtAyH8JYlf2pbyOP2
fYfIeGiBWbXgjza1Bn05tKBTImTRzLmXfTFKiMUjUPdd/qksO5vymZ3zLHnfZN40BfBB1nahSQ20
d+Tn3OpHZA96G8egObirtX7LlL1vSWAo2sXOvu4/ALl2TuXqcQzuR6OTHw/ibtTCnEvPC18VB6Rc
0ZKZXhk+en2r2o+pC9tWvVLH+n7bylpwKZvHGbRTZbSSj/2E3TPkGPvGer9POrCJBq+1N2hUAQKQ
vwcXentC0IvBZ70rpQP9Sfpjj0T1t1bdt1yzN9+AUpfOE+BWTqmswyvQMi9+EHsSkMqnd/Acn1uN
wgSvdKowXRSZxxTg62/gd5pn+FSaYxQV8K3BE5jPYJgxREBoGlxtz/e9w6l8/rLrC6wJ+m5Qw5r/
kVmTGNMflbBMzzTpZHeiOwslvRhuMNbmgdJVAI1nFYpYpdgaR2T2+01UIw9+5JOaKFzJaJGhpbFz
ALKVfgTbZbtH5NouL8/QkU7NTNN08GM2LqXbyMkGePyn6E98tbKA32wgSYL/OFohKM7rdRkWHIQy
Z17F3GPvXXhDdJ5MUUxmGfSPGptdHowtmHz3ZTN8aDMYijQjdOkSsVluhfF3N7Fh8HCleF+11UEL
W9CYGmJyPBA/sFb4zINpr6hXo2oKUk2mpGLWtEooUqfV4BIiI44WDtYfv4vhF20WAZw/MES1u9uz
cMvCbovl+1xVIbKgcEwQsIZZ22OM8BfQTMXiK2FSUQFgCilnIHnAXsPXnuMmNsOC392QyA0eTTOn
ojH2kAwoTnTczvhajKhjdqQeswKXErOuf3TInE1wRnO0HbYhwqQPkOZP+lM2nDYFYN/gZO7DhxwH
obSREeVZn4pNzCnaylleFor5ZRf38lvCfjfip5NWwaj236gjH+9cn/SDiu6kBFGJM7w7nWggClZN
b0ZZBvPbPTCxjwIUUtBjv+Hw35aF/idEKKqBbTluGQArgZAtOJT8f32QVfxUN6Cyj4kLKQA+Cv/4
vAgah2lULjmfnATzn/tdSWFoe4PuzVPgps7B0YUPq1dH4VeX67SxeaPnaq6RXSpW1IoQ9gW41P/B
SgXBBWtBogL/rzEWU+mAcZ9YIvc08XYkBVpPqqFkCd83Vaf0jGctGiVI0zblVTBQqPTLyDpPX9oq
f0XEfbY5kAbl2xg4mQGBEWkKsiC+pF2AyaOFEOxcgGgw0bLkGrwVBPIh3HYoQfQiB5VUmOl7LyAv
AK9DWI6rYbM6k70HIVANyv/9PlV+bwe5raJ5P5j6mf+1zQ+LiGbKavSb2BNGgA9S9ewX9XStiJpm
gHRXofqIybV8fn2gYuCx3Oo00A7cJbu7oDgRBiuxPJlNjOJzq7RtaDT+Fe3qwRdOzAKMxGOUu+1/
tELz05dTnVFaCj5Ni2GrF4dCTMvcm3/SB2l4j+r0re42Th7UobS2vsY1BZQMh+hHyZsD3BOLxEwD
g6MHhyJd7V3mPjTyPrtLh8jXCE4aDjyBkR+5k1c3ltjH725wN+H+iTke9PHx2YE6QQESvPgv+6AS
81zNdFdo9KRiTBa3z6CRhXuXKKJWCO3I7uHCMI+Ysd+Y8NYkQv42AJVfqzi11JAkVqFtF05RzR57
sd5H3YfHrY/4q2TV3RV2Ql1NMSvzQafD54oku7jX4rpIGshpBHBaBtvQgTVQbl5bWW5PjA5FtSqU
3qjKjIu6EYVIwdYoihD30uuk3ETQi6y0xRoydLLI2ORVHuD3znf4cKGyOEdKSK1DCHav6v15ZoqX
2gI3DBgltO84xlGH7QIJSsL5yBeYDc8AbemJ5p5yPpf0ikc53Hde+Z8OKoeoieFo/njjRPWIG62L
GIv68Ks0wLucpnXxZdtHY7w49ObgoEhv6o1J2NRywTffemejoCWV1nNfZ13REDt0smL0IDKakDdb
ssOkQpNq+MPK7ix8np+4NwSuzqGG0UZGgGUzt4t6Rj4ZSZhwYk8zBr4lFKY3SuirQsQy7/F5MWRY
9fEGBZvM0ryfYVe5dzQYPl5O1zPUyKRC0/Xa/SxTvv7lZhi6ibJaFmgPBlIlnn7XOIZiOGBpj3ll
y80sU2a1CNHUCs+axY/cfg2B+UzQPQOGHvhPBmSGCDtjMTtSfrCLNBuqJmuFkbZzh1kDy4GINaBA
QG+k0ByKSSoTtliTGOL7Dwe666WbdwfLhXvoYVjDX7p+FwHYv/OyJ5eNPNN0aZsj9rV1KoKpyK5s
Q0lbY8h3TR9GvUN2ueG6tg+O4mBd452veXaA9Xo/saGnsyqmjq09ZJDcB95vlf+0rPM5SVtxgRJX
bkZ5AsVKilPF+zVzYHfUj/O25b7FQZPIaFxMnNYriZy/UJ2uStG+SpEN+wUFJKMQAOIJ2CgCxJpp
ZwoB+UrBJgzPzEjt6Z2y8YvPwG5IfcLiH2YXjdfWFiR0gOmJtYDern28S9T8C2NmfTZd+VTlx2XY
l2MTZk4rekI9ZvH6178hE52lPeJK9SM49+DFXazBKEiIIsOum76TWhbMGPOqEki3izZrLSjvD1ry
DE0xVa94QoqLtLXpaY3/CzJr3zTg+J5gNcsRDmTTeJxQ73lRJc8iGd+ejlNv4iZ+NKqerg73EKy3
zZqos/gaj921yChu8hDgq/FRqBaNuOamKQKPrKIoY4/o+40dE9RFcrktpTlU8t12RiC3p8fcGMUX
02ZK/mGpOhKF9jNQQ9CuSMzv+YW/gPvlznY/GOaEvty7/4Qj80muvku/PwNWOCgs0gprRfXFtyUF
HEaxEKSd6E0SohD94akHJKi7dUovCa5nwZAFTo0z2fSt9I5wHhfBiH7EQs3tZSu58c2LDSSlCXAW
3mhPDT5N2QBCSdFnvcC1w5T0PRXygGyNqPcTGSvO9OgusGQDjGmmK3CaEjofmkXkFIdnK4p7+Rl0
Z3xxyz+eL7BCE3qu5q3NFf8Lsq3+7c1qya9/iybfW8Zeyxb32R9M+Zt+Eoui+WwrHW210PUT5Wy6
0iTHWXmMaXCk8wDUGLw5QsX1L3KJfnBb7CPr1mB0x6XKAXHqAd0xCFhBAwxR56Bw0z4sOOWhSfUe
A49RKEdwf1JmPIPPyGfNw72YVPAN8cGbbXoGCnMTnCFy/B5mRpS5ts9blXB12nF+pSVbjmh1ysn8
FHoEbXvVYYYNl19btLV0i+XNwj8z6k3z2lUPT7zSoCfb7sgAcVfocr27Wmprk+itD7BqgbfUrdV4
nUsVclsV5tUMTW5MVFyBeHZG6TVDS9dFfecDGBTUaU93lkuD25aATEEccFPZgg719fojNah26wjn
93XVpRpo6hGHPtqwAIo78ZAfRQmY155viCO8vDM3YkkDzsmJeXHNqRjSGIoAmWbQ0pxKan+5ZpY5
1RMMWdbB+ynn7FoJ3J0WImfzi0BcU5/ph+WAF+W8Ei9k6bKJhnwqTebD9cxHbi0Zb1XMI3oZv9Ha
Epouwi/9ZTaja4QMQd3H9/bhDZpaBCd5HUZKBh46MReVudxbqSkvbxv3wJXFIfFTNrH78bQKvnjG
pQwXLo81L99U/yDlZKmWAJzUHY/atWYxcV3Hnbo/vGfKY0u0qicxZbz1gndWrTX0GCE5wKKuHIdZ
xZzGWeENiwHvQ1ZBIp+h9e2rkAEL5wJPnVh95jwiVk5STi1ltyCTwLh4jEnNeWzSI0iZY8VJHnMt
5vxVLh3z1ZZ8TtAB7pSHQQZ6PCFTh2JCJUdXyc3h/AkAPmvczyftVFM03VF8mn3XxsdIHpbqg2KR
PM3Dko9w4BtuvSpFCInh7djoJhcI7brDEo43M4RrkJNWbVGj9SPl49Tsx70uv4WfsBxSjLgebJZA
VTWoSbrjZA+yAvg63zpUjQysHxf7Ofqyva4eZFEX001U+U+svso3ghWogp/ewcdQaRYIGw3cbSQY
FOqXDkgdLa9vwBlifr1wG3hLfcL66FqjcRoQrp99G+CcSObKjN4hhTIMIkB2WyFo0slOAlu/2SVQ
lkotSJbsQaC9ZmN2/0Dm45nYHDKzdC/Bq4vT+3AkDpabVOCTaXjwINdO8dq6DZqlDJHU5/NeUa3T
+pUufnLcy7mw0G3W5nIyd9htxfj4czzgK2Rr1PS0kxb/Xyh9RkX04M6iQHtvwMGcEDOvzO4PKJd8
pIVT1Ff3rMBWA00ShAwxXh7BMA4VL0HmJ5nkVjcJRhKz+e0GFCxIwU/KlSo4bGS6tadh0ngEqocG
zNwRVTYn5QrUt46LL5O5hQIvq4QMWfN0l/Dfy2elhSXlQWEhYO1z/qYAsXH3k4stJnNqjL2SfLDE
VfJ3T8KwUSvEedwNWOKoWPORpPo0rJwhjj+Do1KSMBnP9kuZwTpS6i0aAnRCyZv3HV1oDRYH2JGW
15PAixHWjl2USd6i2On+4IVm/bTDgGse2KGzOXqQXAqHAgQB6Vrqae2pJmBrlyCUKWnEV5Mx7I6M
Q8Pk8pwgG3yZZ3uvHfMxrKdYZ6Dgpq+w6ej5Tx7jBVayhOZtGIfRY7Cq5c1hm/S+FnOagjlfhDy8
IbvuLrsckkgBjbWOSwOUfqskkMz19AodEHg+xxOngMXNZ4iwfGOPaPtP+0G6YjM3qmGG11LjINLG
FzU3qZ/VNIVX9UvpX/54m1Jan5oSlgCF3ZiAxA6e7gEfmw+Tn8ECkBJyHFRg7q8cAAuKhW1qDpGN
GEhxVDtikTIgaPy1hbwQG2SZigpXbvLsEqhFUlhqhs6XxqyJkLV4sVOemNDABDf6We5pPmVnUHrd
GgFKwkJtEazJFXVCCRzXIT2m99zBJfF+MJ7K1C7VZ5ybEtNMLP40YV2c5G1SQ4m3JMiTQflFCqO3
mxrsyAWgV7L6eK24YYr93enI2XS+CV6GCv3PQxlGfBAxxDKu4Wu1dsL7JAUfSH3Rocq1Fso52dwx
ZGz4Hv3kXn1Pwmw8ijneuDvHKTiTZetafRk8rhP2VGvcdQa51Vz8bPWqZvyFp8y2DWyh5gcoypyZ
pkeDjf1sW3Agq331rvpfrP+Xc1atoI7dc6ZydeywaPRFnAKScSFZXeDVp3W4p3NTYXoU8v098q3e
97wsgu2+xUL/ZGjbEFEN5xM0wkBlFKmAfBEN0dN2Ga2FV4Jhn7hUkMdEjsGR9IKIcYRBjOaYm2Y0
+8bygrky8wA0YXAmb/GKgpsceOi5PgiPuQQAkBsC2s5E1FeDXlcqQ9V32AGMBTWJyhXwnHvR3X9F
5xM/dYhMHnRvkP4VUNNv0KqmGl364zXdUXR8VhWGHHXUkzhpJp9ebeMgmKLS7eS0bxvU/swSZlVP
mSET0gZfagl7laRFJNGH8gmTf6J5uarq+AlXfviCZV1+j0uqCh9oFzMFK7OjtBrB07GuaYcvhjVe
NWlFd2m83t4SvHmWVDiHweKtHX+TrqCSgjn/3xQAau2LCrJtQ5+44wWnX9FMjlyh4UC72BJAYcdz
FEt+/94SjJEqL+rXspp+gjXrYz2McWseMYp9XTAHnkIg9/0IJR0cwj+xPZpe84geipYaifgxBukK
t2d1E6vlgZxGqQsDPaXTCmhNqj31MFGN8s8gRRh75/8nEoAZPAjy+2i/c849h0DdtR2MXhn0DMLr
GqZczXEF1pnK/sE7/8LfwJIrd/2V9q0H/3rYtctVZbPuaSXUHnZBhGl5BsBh0u+2I7VIihK+WWZR
trUEVaIJdzP3aKPanbW0xfvCxCbuOCp6TYcZhFnQZy/zjpQ4nRjUrtl3U4vEzRyf+wHb8ZKof9L/
QC4q8emIy/Qg70CTIxPGR3XxMo5YSdj6caU4xqZWwINp70kpb8C6kOlKw4fnoLbsX7c+zx+cTSD2
lLfPf+sfdLL0IfLEJIpCQFzxOVAfEamt9FCQZKAhmenrjnJjeGEaVgbTUJE3xkFcvNzyqDzu28f1
72fW7FDLpU+gs3Knc7G54m4Omj19tRk4jrU4TIxMWayQzBFvF701jOV9opVxjKwqOZErHqMFriQW
sw5Qa8H28+TkF9Pa6UzI78dl9u3grb4Ztxt769th08QLqKB+IL3CoCldpbPEl5K4fFnPocVnarRo
drSXwlDWgr2A02DYblaRBLyGDaaV3xcYfF5IEo3WkTD38bm6PfsYPpnPgyjYz0/pe6p6YrdBIpnC
+BfN1BlvbFCSzZ1l7HfqBNgAH9HQO3S7apdopNciDdkX02imCJ33upO2FyLoT16SvwDNhX3CUF7E
c4MmuMTSEOpK1wraLRkotQOAx0HxUAAfxS3oFp/5TJD8SgEtdusgpkvSEB5DSVTBGkOH+gsJWW3P
aYI1sHqXx9sL2hlaUqW3utQDApyxotdcAimcZQ+oaoNbwXpzdayT/LlNQwytjfrp64EWQJBvXPR8
wWLa50PjFQNyOLcXvL5P9Ov60S7gIvkHa0D1OTVYwNqIpITYDRSKzE9o+T9S780spr2L4lYiOJaa
ZfrcL26/5AOxYHDgYLu3Ri6KT6nnm1N1gANHvwgTVt/e7ZJf/RfVB1OvxxJg7O5R92oQvbllbW1u
VYYDi0531I/WUVqjIHGLlS7173YtAAK8br91SXW9rTVuqINsGhgPm/XqZxd3o69n7XXupqkMM7di
ch/mWRfAU0p3Zs/guong0y/EyUzi2ufEO0WzzgTqPzmR3so8H+dLgMYDlFbLfQwoVRZZWiWlIuWH
xPtLp8NAdl+1iAM0j129aTP4BxDb8qq5B+nL9yy6aAzHG49gvkZBRIVXl3hUVoSGyU5dxSVJ2Arx
Gvz/gw4Oe9cF2nwOmd9E3kPHeGFUWyp+uFQm1FlclG+aQPyjgRBW+4w5Fsw8frGJQ+6EjPdEq2Pq
lKMYAojvd95MSic9qk2ElTUdWQe/UBbR/827bzYu/Kv/6atiLMrVLYb2VKrTei60FxUJZl4hLk6+
ZpB+pDLZgZKT5fItmwVJXxeruCEL8gAfsxM/rDZZi0/ixeVCutdBekKXHRYYEzeF5YFPwcVRkvqW
vGqlYgpWcMuLq/wUM0n3Ol37DJDTKsVty4N1tXs0OnOhXckhakn+ZeCg4wRMUzGg/huAYU/aP2Xr
S4Dxm189ZG+lOMD+XX3AJdQTq9F1hWtrC1GgNmhmeRgCt7NuGx+i31JhtCe5wAGTjX4GyQZ3ig0N
csvF0N/b95vNuU30qRVYYpPLjzuXdFrQb205S0i+e8P3u71dMaMreyiDTOZ43hQzYsZ+8xMMgi6/
zN4B6NsEivIRHMtCn9rHk6WsQn6Mnekp0npkwwCJJQ1LMvn5FaR1YYxzVStATUX0MO0qJ3HEoDtS
I4AzlJNyZGcUWWlVrBe3t+Msg+TIb++zn4HJl6nP4tYe/tovG+GNvqA8k2KfGyv70ght0nIm4Dh7
dIFc+yq207ZbnjiiEUp+yY1S+X6D9RHOx6ZweDDUXT5WbNJMJapHlg78wJmRDGv6FAuO3G5aOhii
NrPSm0bnwXBOj15SfXqq2VmX4TZ50qfPsTSJL6d0Hdh3vEcGwV8HP16oB8zVmAzyk+L/of1hZ/OS
24VSZYSkmcgCNmwDA3vm1y2Qzpa4MfHbTaWYueRjNTLzD8DDEzphy8talhkw99vru7LqhlGI/e2U
syLUi442Qjq9phV0MExPbAW19mAplLD2aKzfy8DMQznBACjDa0Q343LYIFuOu9bMJYjS8oUQ0zTl
3cMSw8U9RsMRiFtkLxEVRy6jL7zy9Jc4Eh80Y1VNqyOVPv7eNj0Q3hmOSlhWNnRAJnL4EeXAaU0R
DK3BlmMIO4VEC6Ng69nuCeNnshYhUjXUZQrHfWruFTX1cloixNu0ZViomcAEl37iX6oihYQNzUv8
a6EYUsQ9ydD2q9EgXgCDa3C4ktE6Dy9TEiBgkETLkLNj4Z9SjmKqWiols7PsjFMZyV2+4hgyhT/z
Yv8QgNGyhv9yBwaO0FEv0y9blsMeR14Odp0d1OBIzRuPIkegXZ9dP92oo91xRUJpr8ZTPWU/9HJ4
+scSUlT46WctViJ1We3SxIvQYULyzpKvw+hWIJAv+QvFtIwMIhmVU8Cyf1l5qbRpLmBfZumd1pib
5vvjp9L/Ahse2iae1R/khnxN9iv5Y07MPYqd3PE6PtOAe/hKsvv/Tpo/vL5ION/UpwJT7dZCbYSU
MFttxysxwxZIAlZaYNiISdEQWTIdDlI41xI2sMuP/+BsORpStAE2pdUC32wssLskWO2Kux2lZLxc
vNn6HuTQPNqSE1uPf4vtk3YZfQ7f8Qz4ht8Y3uXxM7MS6aGdiDCsEMCfVMlOPvuuyzeTYII+giPg
VqScBPZpmI71ySmN0bUUgyMQ/9CZLukeIyP75UqZ09pcHAwMw/7/Tw+7ArC7sUMaRh8Bxb51loY6
HFN10l0rD0VmUXEU/a9C1j9YcAxsPjqRpm6G8etqTE8y3yObyxUAMFhhT/ZferlOEANc470eioGU
DZF8d0PdaTEpLjbG6hgxj40ZY47UW7swV3i8l1UmHqyaZFstDmePk/QrLE6IVEp2EM0TGeEboQ+A
wU1832ReYbXC1TEC7WQi3ArX/Uan+t7mXzYw4tsA4kB36QnhrOi/gNCBoKdiVBzeXKGaXEdSJJn+
PMGfandLYTlXOMRp4RePirfLDvJeejSmintls4hhw+/OSBuyPhpQd5eth41klYYJi5xMWWWQlaPM
avnZmXp02AdPYGZav3O1DlwZe5jTyqInDk5kHW0xrufW2IW0xK+A6jCuSV9pnLB4q+H+/+aK1Ouc
cXyl32UyklwEui6runIZPQLtzxvwT6v4JezBSLulroGzkb7K23hT9bBmXgUtY6McSzTokMXoZiCU
URvYSVujEh5SI/ZWMzLuUrQgiZEI8FIISXiEOD4iNmgDgazOO9UXCD+Ml/uVWvUOswWW8BCtfSL8
cYwjxTG1qR7Fy1wx2U3x4XM1T16+0x56FLDzfF4wOVc4sGkXZt9yYjO+Sal/F3nxSLdF5sfJ6q/V
ZX3R4JBIMlB/QrHJTvMnYHY2W+pl4jij+UNZAI86agRkc/WadfM1tgrr/8se7bl+KUJvc4S3nlDt
inDwcIHMLGw1lBGomR3BqYxNRiTWQkxggkPFqqSA4RQrWBwB6DghTbkzVXMiSnCNTQlDtTDCZhD0
7NpqAYFeU3WADHGnDQfvPSNi96RKseRs4cSqsVj4E0b+A3TdUh2eVkrG1Kvt9B/xbhlja5k+YJ7D
R062qWT/P9jOd+2Qgz93D6trUrfgd4tCywDJ3fL/DN1/rZFlVI7mCDWlm6qW42zpSM22EBf9ooko
WoBEVYG9SDeJ0WHcxY6xBUN03O78QDaEFIwTPPv2Hsj/tX4tOkHhE2Is9pOPdKNRrATc2ymrHxtf
2D/qjUq3ctztcXDGqXMz1TjTu60RMYERv9xL74S57GYjRWrEf+xmZ75iJjzIgMlIZxs9oZOo2F2d
ETKyUnNK1y63/ibuuYDITR0zv+9LFm8JC2v7WkTtIMAKMkOc8TDtJp56+DRZiulDS4Y2omcefjJd
9Y9E4z7ZMp2geLZZ+pv+RSYyhBcQxxRqUnwvie7m+Ipg21kOEIFwFOa9Ls8zP7MNYfuI9b7hha/U
0PjbDK3v1li7WAYNOYwSZd7i/rzqeHPo25uK5uf4QbEauBOvEN8XLtr+XOvPdVLRbgs7Okj3i45D
hjuVd2gvy+IZcrITwZqNh59ZM48b+Mx56YyH9jJxdpNPYDcuOpnwDVz+S58V0SAO92Wdvfe3e3j/
dueOaPyrp9iDqq3X3N3GvCwmvS8TR2XTS6dTCQygW97wjyp2UamPzbYFXP3SjXni2Ui5sI0ly9DY
BVCVFC6HdyN6NV6oVLxpQ8SmonfT5ZV24a4/t4VEXks/LUVMiS7RzTeCqgUofT/bgrU+wt2UUCE+
VPpjSdd0bXp33aC26si2SaFdrlUqLTIXAJUymUHC1yJ7Abn5/CdfpqFXj4wdi4q43EVXw7ZgcqEY
wIWEE6myrR3SkXZA6c5M16Jy0Fdk4fSE5KPB2Di/AYm6dTjkxQ4wDZUmQL/u8TPRPr0x1vtChJab
Yb7sZy6HUC0KRayNeXLJAM4NABvW6E2UXWdZq4bqQa0elgCkII80YpAC9rZvH2oPMH9u8HdPyt/M
NSr4+E7WqEDwxyEA0MqBtbvcLAGEJYz1U3/PziyvlfbXWAOye3lo2AZ/x6tJcHI2kgbyhgebeLAF
+qv//2fFtlTh9pC9JttYv84qY9Wpy/TzTeKGDXFqHj5Wxd/uYLtpo4xSIrWMBDufKPTeFUlkw/H9
ryLJHqapesx2wyjd6hNxc7iAnir2XaNwI1HiR9uKQExmb4pY/2wnYE4dcew4OWwTKyLHoR4a+4UQ
f8vYtr3FJgfaaxPBgq02Uo7t05eHo+44oIWFxloBooAizaryfF+1m1iK1QYp+Rwg1aC6nT/A41uD
Js3Rh5WtqPva3GgVUbsYK9H+C807T/xlsrFnlbpwgyDg0fVURvwI4YMvpE7U3MZjAFFOzY/aSib/
qbLRpr/sSyn7yLk+ZA4Y3k7IaIyrlkvd5xNoRzudBoRLlmnB0kLrqRf1uf/I9QsleCbO4t/0wMSV
zCffmB1OwXZ5/bJBYdrJqXxCLVXNHgfC+IoSzN/kTRhmUMwG5wUvyHyvRjOos6PGQeNq4mTJeozN
IZnZUJ0wv+xHJQ3FDctS3J+Z+eQzfw83CMTGZQcIHS+YbgTluwG3YPUtAo4R/zKKbWICeQcn3vMv
sNW7F7hBPdBO1/EZocKsPDH8KiLzZf82qXYc3YPDs7mFJPpLhwhVHYdYI2Ax/Apj5CfKpkeU0sh5
7o23A5P9NvPO/2h4AlFQPBPnTrUfIZ15RjmCTRzf0hGcug3YI4x1eMJOgTN+ihueLRPMre5aFih2
9wBddZZvJg67iCDvAKQ+fMm6JPm5C/ziDQsK7UcKhJ/g+JmfugCM9BpJXHP5LiNGxaKWN5xaL3pl
E68/JtyPBFh/TaVR4cH30fa5/59Z7jbOoDN4PDetgYDh+fdJ4SFf0gsY1IiMCYYNA8SRn0JdSdK7
fxIGRWUYkZvbTLPhhgZX9XhsHNkU0nVwtjUX9DrC1y3YAHY6RI+A99QODJbpHVACs4dg2JtcZVsD
c+7a/m49NLNbqmedQ2erUbW+CjqJ5w5w11T0Cw7GLw6AlsWgetchjJKafSLhbxC1cA8Dn4Fs8NQU
CKQzjmhEn4GcsJMzE2aMuQumVzOe0WERqYpme1fqh3bkP+IY0FL8nwCFd4af+r/E6t9ffxiZ9StK
SuWAwZuFzxvtYMmcBly8fa0YYiQDyd1gBD97rFx0s/In3xByWgf0ImfUHKXAmG7fb64xL9FHLHyV
e2ITPoKQXjZrIcJWmjabw7wLVg3I2y43Rq+4FRTInMirUE5IosdjHvskyBW+TEgF/FoJcHhD/VDr
vSr53r/zbPI4lEyoumwfnXbWh1OGVjnT/WGcX6tZypdtVpWOWdeOtiV6jHl05fQMqwladQAcqc5X
PLlyQ4t6VuFZ76+70TrN8x+zE3LioXyyq/2YY7TdIQP3CeR669i7KRFfqVl6/Q8Fi02LztMTIAMS
Tc9b7qxcTaNhzEBeYPKyUQpesEsrzFNy2fWP7/uctogngxckZO8piYFRsZT3gR3w1ChE/0BdPCRJ
7NDxs5D+9522jCdRY4mV800qaWrOwRoWdeew0fh6WmKNuTiQLgD8/nBfvyV+D24CFsoobhXgtGjf
UZh4nRQCuZfcjNjWPxBpHT3oNLSaCHE3QgWUVm0cBwigk9P4/E8g1ckLTjeHE8/CFfLgJG8LpjQl
aP6CFEFGVuvfeXuZvzqfyn946vFilRsj2UaHOrHQMnw75KAQi9eCuPDoUUxvV5vNcy9H85Ci4CcB
/W1jCaUoMM96HWj9a9pCo9P2riJcLWImhtiBM7LZ7VdmMxmsllN9v4Z1LHKAV4ouEvdCclEgF5E5
nimSvAysZDbysBOSxhxrJ4KAKwSHBhyrEwAqj8UbXRneqq0Jzrv2VdCv30NabLcVO7z9y6QtwcKX
6QXTgpX5K8Wn/+7alGKh9k069O3mPs3c9IVTzd19GpZ8iGcpvQeP8OrFDE6ndmp/51PteUyRahDc
HaZmIdvSokwahfgPclP4Mu7VjtnSJUZB+Av6VKCtLOOWx9p7rAa6ClNrjbVov+NTmIZuxdTeefnO
Xk7/hUnzwGjTW8DwwhrfVtJiFHmQzlQU/ZB3Ewn3vZ+3PpLbKrBzlorzVyVpx2oqK7WGBMk6G1W2
q1zCb1Tpydp2LelestY5dwuYoZsQPf3kJruqBEohVXmI/+jY4ffpnsUzbWTDpM4IuQMQ1lbJhPw1
hNNO74BgydHkqGD7SELo4kQUG+XtbRZrTg9LA+LSlQH8Pq8Te+giQLcLqFAEVnBSc8aA0MCQ+9XL
vhW04c5tBmW7yuoDFf4WVf9ll1rvVvL6qqf4DTIX/Yc0lXvexsU/tjPeEywm5nOuH2NVvnVVXDWO
cDy6uQSiyDbegOsgDRXY6rZyDIhwsbLJdzhdiG3YUd97ZyD188rXRDchlLXPs9xguOUS7Odx+dKq
26dAtWE5pNqekel3994ymbg57JOexyk1ntuk9aubJTWji/M9TFhKujv+eJrM7Sar6RU3ScnA1413
YC1fgNjqJ7OJlud8/gWbPoEH5D9OvJO8TTLnL62My75XlbQF3fp873jHMYDT+rdWL4BHQaUOSjiO
seFCxdpO8aevOsRQPESLy6ZHbVUB+HEDua5VkSlH5k+ZaK+9L/p0m+rZKMeymWGAu3nFjLJa9GBT
6BFzzhIxBVySdfA2cqMNX0yF8y0B3ZGJRIiMEhpwBnCH8gs76j5ipYcIHtBgYF5Ff9oJMMoHYeAm
1o0RfWIzUY6gbEc+OlOcnZZsWHFOpmoAKE1zdnBUxY8w75A0gFrbLbD/Nzjxhog+CLNGCi652+CR
k//7h8N5Pv0tLdXP0c7P7qnnAHKmBOXFYvLY1sxTI/WSZgfXlc86zwTvpDBnW/M9Di4G4TPTHKZ7
4dwJ7tChd+XifSGv+2di+tug0kCLrTB16MqAbTgomOPuQlvZiiJ+ie+wWjiMI0PidcLrVvaKHU0U
iZJ47msjh+7UrqjOD9Jf60T8+tgec+OleYMduSyoZzOxbvqwSNUBYMqHXV93oRl1zZ8ZCFEI92i6
aH3/V6mboMDzSHK17QTUTkFg1Q4eD55I6/LED8dWzCkMDmZPkSwLUP/wJchmYjzk/Pb76V3K65mK
sn2n2zvM9uTithjrJKj2Ym62Na2JglKvHy7B/MVYjQIcnZRgguNbN/TWX4iVYxmhYOna9oj8ja1p
PhRb6Bb1ax49tQmgDyxPCduNNBCwyKbEM4RHixnUyWNCnhJxztVSOK1wUnOv8DiiE00e52JLHBDL
TrPdxTskydYIvBrmGEQ77EFdTCQQuVGK6lH5BluE1cr91Vg6Aazf9GNc+q2rHB+hiUnp63AJS7zK
nl+yXOxX08EKFiv/Vef4jGV6DmSsDq6iHi0efWk5tEFB2njZgUQ+9OyS+AEEPw31OARLjyi7gqet
qQFii/QrmVIrNm8vZ7dKGoDssmrRuBPeYcxzFrAg6igkbdhbHTXg154EH+YkMfUVB06X9Zb3dVW0
UMdZcJ2Eu5np1aAD2Bd9h87m5FyQLe9NfRRayvk9TWlgqPeHLKYy2zZ5AJtAoSGX8IVNFyPl+SIt
xZNYHQkLN8+9rL3Qio0aZWa/zhgnvZxkDzRb/d04Tdt7G6WDZroZ0wdhBi3JmdPqP5vaSC5m0NZI
mmavN8u88urWACFjjQ26jKzN/5PjLuZSY3C7aoMFA6avTVB5YxMpppty1WZmND+6gDNQvoBOuuhT
i95wIsR2/YGKx5Lc3rmPP9W4oDllHA+NkBCG5W3DYbHcu1RVB5TzGOQGJeqw8mRvEtQSti8VN2Y5
UI0rim+vhE2KdgTlRXp3UMNfWvYsGl7/42Cm0eGCtzqTnEPPSo5PxgCQ8l9E84IYkUFZJC5wGRYl
VIsSrUAsv9U+8g2bdqlmzeRboHM1EwVCsDLq5uSqB3pBJRF/mNFFJ/8e49s03CVMRLWZ06l7bwCO
5X5Z7ePTqGj/MOIYpT6byxIAarELrRJ9ULm/9vejWs3xQk+nMXs6Cu3fYX3ubbVTRAIEiPZG2cbo
w+Z77R3hRzXtq8sVVVpeKXai3LWnfk4xnTIsxkzkhACLaJds+Tc4HZvGhANixLR6mKdmmZHhJiJa
EOwE415REA1eZ5qKOHXvndDmoN4J+diR3BM7h9vPJrSIfdm9ZDzOMvO9Ifx3V33BTC+/JY1ZGiv5
xv8odKoHi+n45CjIKa1/Yw1rKR3IwD+BrOuTCDlL6kdmahm3hQoKG40Ot8xfXTvEQpLqsSOKOFLL
GFaAC+LM/7tUaEFSQDDyvuTxBy+7NpY2hGPqIrbmEKk52Wc+cRr/Mb7ya0z9q3mkyXZDZZDEPGm4
ZLuzCNur0kOoBBUErOUrMgMnsFQ208AX2gpGFxYDFI+xAaOflUINvNPyxS8bJqDMge/tyijUDaj6
zGgmt7l0TlFwKFj3uE8tuzSw23X0HihAJcVWeTNfLxC7Pzr1158k+Zvp5gAPsvaZ6Nh8Q6RRJ7xH
DLf8LzRBtnbFZOUXe9/r1KHkOQH2KBRxb+FFAny8qjH5mTcMFDBJB8IUKSCiZerZgibU9jwDEMLm
ydP/94bPHsdwo7GoLD7auTdISSPY5BRBsdwm+2tsCoJ7eiCl8nP8ijZurRfz/bB2N6xBWW9tgyJH
XFwmxCVUfX/PDHfIq3/5DtdMLTeEUGGxEAu+zMl+QjpeY26tC4WLhyToX3dfWm2IgZdUP8Z9uCDb
zx5Z/eKnN/mRu1m2O36pTxnDnfFoWo1keASApr5koEzQfqqI7xtxlaVnnXbYfF2K8EWgAbHPZ1EP
fzupsOL8cWMae02q32uqGOd3K9ZoR/KAst5AbOIMSbuYOImkfjup12AvBucST8EO63gaIdoJKOK8
7tGK4llvz5hgljnrLXfCeF//kOc9BFjSRAsoRVkYamZo0A4Y18piemVfcC5wL/G/wWENAVUNJ2un
tSsaDURix+fbUYjAnc+pugLtp+fuPKus/aVqUyfR14wxzmCSAyod3MgZF3Ls55SjJPWneP+0ej3i
svLYgSkovgto3gtsjYqIiOSo1dkiU1xT6fxGQHP6pL4/+BqjuMecc2vRItZO9F3lVNCeZZyjbL9U
4e8Ctlu+qiOUdKqIxJnplUz2DWJHCY4HRTOA9sE7XgbwlvxRKuLaw0HfZfxO/dMvAa4yHLka+WRm
On59W903XSY6NtIYeRzGOXgXwUFJgkTLf8g5rEjGXwPVQBr+57oZZzAT4B7K1DYBtDLSMdMz5nkU
dZLwn+UKvol3dpUIxHEK9VTK0WU7xapdAPgGppOt2SHagu278jkHWD98OAga7LgEi+vsH2adjbVY
brYtxbfIHjO0/eur1a0F7xwHsovk1PI0x5k0KK4lfTX0rqcfREtcdeCdtu9xm6/UDFiJx6Insa7p
FNqdA9t5aHgyltunU9St9MvquQhE65I2HiRJyECIRGidM4Wk7GBVnUd4MN/1dricA6sgkk+RoWfO
lW+oltH0njgrT1SFim4UqDWn6kjaxvGdqNgqRXxvBQjrJMN06CS4ZAaqUBjd4uY8g/O1TQsI8H9e
20fQ7a2IP/4r6oZ4E+Y6QB2Cy5Z4u3Qa6tg4dzDazlcLxqMCAi0UjgOT0oS24/ATpe2K578MFQa4
+w1aK4OlnDZBoi4+GamxW1z0dm8ZQe0hM7pX49BghCnKqyPvG7f3izxT/pGBSwtfb913pp5LXPxd
CWAewt84c8u7z83GnO3tcovhSIiEg/UqQT5psRAu+Mc68znoTVN4A2sFHkF3YDZQMPHHHIwKqH2C
fFgndwl6isjKkqwelebSA7pTAkIj9tJo5r3Nsbf8VClw8dTGiKIzejclH2nOOVBnBXYBzo2MMk/d
kJp1tZFfR1zO5pX/adPV4GWkgVOg3H9lv2rL+pirMisw3kdR2OXDdX/5RfV7YrefCa4C9BaMJHJU
iWxZDq5GyX4zawvZLhrrYMR1AzSTX1OhahKDtjHh5EIRRdRX0jSigsqn76KEWvP97Po7mqLzUsD7
jp7o/cgicz725ew7mBYJvxDF3PjtiwkPrOwqEjVRItoJrrhCizCr3hqSv9gezGnKeeLNZifhWO35
kMjjDesU9e7Mn/rfqqPUbQyy1Wb4Xhqek2UNjVGt+rjuyPej4cIwGKTauGZmUScVzo2jFIApYhUR
kVdYaIiv0+7BFQL9xjJ8B+1Iqdi1itignn/xU/iLQ+Huttp1mCGYDBO77m/qC/AtspwnW+W0rIEc
Hu13WaXQGd87TD0ArIxxZaSNMurCf3qHs7n+eLXA4rMJZk6N5XGfG5ZnyXf9vYrEJtBmURcVX8Bv
pfBkt7MiPk0oJmluNIHiTveooLJtQF0gJS02l7fiTj2Jcvus+I4UpN133jhEl5N9JQrNn/OEqPXf
CdE7NrD2VT+xmAU1qHcIhnW5sDrJS12DzWdRySik+y3sqSLCpnjysWEG6Irck8e7qzaIZpikPRi4
xmOygALiazdFeBcHvNttRvb5SAFy8N+dTGFJzcYZhpj3XMpFgbdiDC0l+gerHHwVWbUQQoCOrGmv
C4hKkCtQJ7KW721eenirjYS0IGKU2pH2qZoXBesTJIPpr6JZ7hvv5IgP3DKf65XZCpKdlZB+Kuw4
QmwYGc7o4aYneKmMAzfLJHBL+FqieuKz7A2V0l1SY9JMqmcXEAkCHxLUdveUNvzyXHMtrqilaFRe
qi+A1BA5Dr08AwSRkxCvbVxygpJPWw+LbCOmdSxuYcbHOqN/tR4V3DLlZrNNSy5zbFgIKGCFkoQ5
gDyK4l6GJEszuAuf7T0vBnfADtIgBv4U5A3ckZ9Dcft1uT4G0i8KfIlGLA3+h78ddDG7NJ9crj7h
42/bxZqztAa20Du4BkgQWiOMm9Z4ypcCy8mUv8y3eW43w5XjM66a6nT7k03fHepRkiUAT2qcqBNC
ijb85AnApWNttNsX0HOBlTe7toYrf+4dfxjJe5S5lrtTh8+RgVpWVhs9FO23B+LPaYMAKBpTows4
K3IYi7/G2QbMl5/wMMzH09yNrdJ9ZzeSGEjNT+fGF8XaYmkMtqQfFHKegnJcbVFD6tHVRPXkXP0V
63FBGZRHrzxa59sKGHhiO+kpf2VXTlD3KAQRhej9UN5rFMpf0h9ERyhInng6S/+aOKOejlt+xnF+
20ofYQFCJ7lrcoZ/5jjFUsxMNeEL+AkfmuO+2apC5IoRiNbgNE/+YuIMYJcCTCRGdgzaEObb6J1u
Sgi2Sz4I2W4rQA/VSERDmZK92A1N4EybYncSg5LXVNhUUhoJlII0haHJfkBHkLK06BHJIgw9lNgm
jiWKwQ32bfkDjw7gT5oGKdNTGuqIdFf+hRsSf4hJsej52KQpVhvAielWySFxvC7OG7D8Lku0koIy
9g7WSCJSLtDKR06oyTDVRlBb0N6YJcmFhclW2ixmAQLUujcsj5bXGFQrqxK6w8Zlnz/og4GHwzvT
tVo+i1Osv0HKXGRGPHkCfU4gb4xOUl5DnXoEP2EgN6tbfbTa3JkbFpZROXumaaTAu6sxSuZUq+fC
N805FC9Lzzu80WwePO4lHRezIOSFyFBRfgLH+TDZtqG5DQmL4USWFDFKj2Bk4d3jlsG8Q49SogWx
YPGf8Jl1lAZBkDFa3q9ItZj5t/eXJiAeOrbG3hhZJolYFmLInxBbE+3P5N87ylbgdx6gNIzZUotd
zlm6AnkSnclmGxE9xr+JLNoNKUhkp3CgmKVTfkwDYUqhz6g6krQNVFt6A3TY4oMsR/V3biz4ZFTL
HPp++A8jMIxi95shOJ66jWAHVQdCTRjwc2JRPZ3kZZ+78G/7e2kJrp0qIcwwdYxpUT+PI31y3Pye
6hCylzVf/RtH+JynBN22+Gs5XxfV0pnOht1uBDpgRVkaerKfnEh3mfbWCcXAc1PMyU28rh8rgMQv
PFoYEJRYTZH6NAhufOuOUorJMywwlxBJb/GEPZiCuE38oDwx9yF8tkdG1XV2Td7excDxkFwR7u4R
4Y0XT8bNGu5blDqqjsHreYlji2APRf1SBrbGmrVhGvR3Oy2ggaLJbwPdDFnK+8sEhv5+WKb5B+GU
wbPtnC0sGUmrlJ6zOcS1inW8+Gv9tTQlOzh5fuc0ybfqzCb6lDljlPMKkSWM9I9lEUXUphaLzOqi
ujMivFjDkb0vSvq3SbNqFKjDjFxHvNQrXy4LgVIMziArvgJdBjric9dhZ/LXH5KMI8u+toFUAOjP
K3h1ne9fpmczr548opGP4zJmmj7G3sIGbKaxvTVYd1WGI4D6BTckeouHwpTtsvfuhQVMXyaB55Q9
FM8F0xU1IEP2inUhjSILF+8SJlVSdxMKbmn7HldcblYjv6rakJduDD3ALaA3Z1w23aAdBqlIAYZS
SvX481WtIsk2ExVFel3IAK+VO8IerW4cwWO++6559QmGmp6wpWfLkVOchZWukglx081mZw8l4IpC
YOmaUCO1I5Ml4fo1gvFQ9TVdso7N8GR97K8M1ZLvHwQkRMyyFyWKOF21g/oA2yxJ1gEFLp9rS+vf
Gh8FCfJQ3luA08FAp9KQ7wYkjBPpD9VqTIwuywNdzdQ+MUAemtxDmxrwMoSr5UJI7xKxr6WmE4Yz
YEWyaLZP5sG0DcnmtceQUDSz/dVStxUQY52Tfh0XpE6xOLe/QNt5BJ0P2X4eG6F+46An1aHHdC7Z
JFM9lx5AmFj94/sR3+xwzSIMlckcXm2izyf1PWjirAuOmhIbkGM9evYw40YeDSKR1bDcYXYUYDBR
nbZ4K7058lRrqXXsbV4xdZxWZJBVjdbIeR0fzs/4hNA6d8LwYIzui1pKw7yfn1YZIRRU96kyvlSM
qpkUY7fE+H9GYeIBhaPrT2dR1jfblF4lz1nfqC3yJI88zh2CeOFF8qVAoTeT+rriXAQPrJ/NIY6w
JqCpN/jBeNyiaofKnjmD06xwVvlr6rV+FXGt1pgOZ3bliKjUSVPj1iQ9OBllnqkuLP7CWs4YGqqK
UCLnMApa3O6jvSfvj63HwVw9ZMTC/e7RWjDE84Da3WXjO7T8TQj056PJnSBEON6GRKJ66Gyim7BD
zmarvhV3LwOl+kDJ4TgWZpFMI4SnBiLlrRUcOhKy13Z5HdbI9wbcyS9/rAx1IX21P37vgi2rqCNw
VSZYq4ulCh8q7nDXfwt2U8PYdZhsFUApPkEVH4XNZsF6biAcVeJMEwiLqOY+UeElvXJIXQfVL7MG
+5hqzN36G99CG4YJxuDDtnpQyGvE76/U/IFKy0TWi9h0EgaTPRyau9ZqPwKNVkd5CSMH2KQy4EE1
xs97IiY/y5Uq5AFj1kwrWyp0/jGP001GX6cwg4b9chsFHBRS5vvnhq/+vbfMtFEEiJsoORtH9k+7
Rp32YOIXGKoMWj3cntkVaDC+0sb6ISzbjLoAeSOXdLPFT6ABrWZCngAtU3TbmUSiAiKwqZCggya5
MaSMUNdReGhgQaUKKsuRaTb1yjwoB4IDak/AyDAzpTZcfOPZ2k1jlUCG8ApfYd7Gq8W2vVaOYrHG
CV39/ENZTvSGjIEuBDmbYBIs6OadPHFBWKOMKS1KX/mc3jiE8nocyTdA+a6L9G3E94kqmnpIw5v9
jg7VeVFVtrh6RAMh1xACZW0dvOByk9Yde7hYA53SckjOaOUYyT26RgIRT2ToZt8yG9Xku2VRdPKp
ly2qARZm5rr3/TQnUWrGGPjYKBRvblP78xBF/tSsAKb0wGbJReVT0aTL+WFOS31d/QIGCpOGxZmX
i6zui3/wlEExjRaqSHSNLckKjiq5+Erdhx84kPT/8tIXlvqr2RW+7BS/7F5w9Vn5on8sKR94DmGW
GURFAxNcF3pJ7f0Bd8k1vhr0VNg4c6sFo+Gk9v7QSctf9rEkFF/lsxWBPn2RLxhX7M9GW7oeiGL3
nv6zKRlfMNM+3iAh5byhm0gOYdY17tmTGb1CVBXomFmNcH9avM3yWAtGw/0bmAjp1trSlZ6IW7f+
xSQZ8pVH/ee6BznPYx1fqjEC7GIw+JzQxctAt1BVedgqiBS8Hm+78+xpC7FNUVo3iSybuxu3S3cF
XD0cEeo/HHSJVdVdzfXTJJNo34KTwBAwcoLcbUysmnDk5640owrMxyi1oM4W4NnBhp4VmhIAdyI2
Pak0UxL0g+XieUtboIgQ1Vs2GF1al/6HsH7h270HE2ZHJaa9ZXC8CFoNROw3dlrnmcKK2/OIEKCU
cttZP7Hrmfd3qqeLKhtnrOvfJ4olXwND1fWWZxUuUyfvsJAGKvgAlDuh+kDoo5QCCYuxOHd4TEgL
4N2U2JtTJWIWm/w07QEbIsdtQ8ygc20IQs6HB9Qe/my/af5FGw0+uKFMT2E6zkWB0OL/Q37axTx1
vYe7EBMhZiQtjBfVMYxDQ7koSy36RIjEMBQRWoqhMF1MHH8BdlZ507F0+E9KxYkSD8asr5hjsaze
TJv6eOhPuCuiAhsDfYX1xAxjUGK92KO+2qmogAoHBGyuFibQpX6kLKaoECSQNYtPHhprstLdTXWg
A9LU2LzElhsCPuMKjPyw41mxOPySzMM7R+M3bOVVLkL73hyVvgv9vLh9FjfOvoUYJyoQTY+cSkMf
eHOGXAe53RWbn1YMf52mIg7DcydS7ey+jfrHISnhkgPSMB3Iru//nI5NCPD+E3jvrCpRj3Do3tMP
yXNmB0EQLVtP++vR4+qN+JlSGoICthUQBoPmOKSASHtjK3G5dpuzRb8B+h/AZhPcDT+gCSE8AlVP
6Qu0oN1AGHXboFgfzLR1GkE/sSBDa9xLBS7pBDtocvxJixCpxa50dSntKPLD05JPi1ArRB9Oe8xD
j2AR+UhVzlhtqzeo1WYCHedO9/sIMIH9PVQWOXA/wdFUw4hS5/gsC0TGGw7dFRI+dY6pbEaTqx9V
zbwQ8uFBuRywIw7CvQ53R1iugWzsyhBnoLoIWHGOaxqyw5NciebnsOqZMZva3/XKHF2ir5kdFD64
WfLjybUeZ9XdH6+D4Fl/lITDT4wnYNEMQRLdFWSDxmH3qA/oDxW8HV2hN0BibQRf/OeCS2xER02W
JtyAmzqgSJXVLEXlnui0wW59jr6m8sQkYdVPPETaPtB3Qat5cwJKjlUdFlMGBxNo+UBYU536cFET
x9MUW95DaGBYvufKsBYB6iCwaG4ijVx0ulcfbgLLM0IuaZrUKF63a2VuNpcoCqEflGHveyrOHcYl
sRd3nFh0GiWKsCqV3Zd7dI6caIGqWOrIl8OVde37NtL07nurg3UW0ZXMoRFNqTTAijfau4zdwax7
p/9M/qkI8pGFnonqXr2B1VbbBjzXgCSCYk8frpQjPAqqLSCtJ6qgdYFu/8PyLM6Diig7cyiKl2PI
uop0yVY5ET8Bv5wffdyJs8S4CMkoX9d7a3v5BVF8rTd/LAgzZENse5CmX2Xy67+kh1vAwvfilFu+
2H4jMI+D12Cpm8O8ueHyi/mwRjmXIzTalq+j+wxmhPA7xctr2BZdme8bwbG3tkM1jEtOOCf+Yr8Q
G6j1Qnc0rZc7JnnJq+b/7sKOjj4BEDIEchw7nmPFTeP8ZxdOVBLu0yAyWq077jUAx7ElkbxWheP7
tYAZacZP1sPgCO3DioMfwczvx0IstHCgBZeWpUAz1P10vPh0ynSRC6iZDme/BKtEe4Vh35mRE4uo
5F/yeQia55MRF9/56tkYi5ILK+d3YcmM6oUW5jK5FIy3hAKbcrnoe/mbxpQucWsTj4wQcEzZuZUb
Xh2Rjuhv2vQqGE6OzNS92DzcIiETHXMVWULGnYaHleRABdqNVI3Vfl5zXQkbC0iPhNHX6kLEvl/L
wN0MLkGTqlstu6aIf7sHosHhRRhwebWHdWDu7UeaUIVah7VerAq3elxRQa9WfBcq2Tm1/CCpNZWL
t0TM43vDFkpVk/+5FB5J82VFA2Kkr8WawkQ8Bfc9vehEhuntS74GdDNSvI2H4AHah0jp1UFlB1S1
hamvHHA7fKd4fF3c7iLtQIkAr3+i3Ao6AbkZI/xC4btZDVaXYinLC+GsSgbwXdJ7uMLY7lF4KR3w
7e9B/1J1Tgd068u2AbQQAxoazFifl6YdZwf2d3jUq/F56rRZjjPLyQn4tUqHwYFIFoSw/6/H2XC3
J8OSZ7jazHlWxXG+k3OsU0TMktVSrN0+CQvGUI9MW/I4Qm37SwPwNJFUL1s15s+wCNFh0OwNzYNL
SozNSipGFeVPPUBE1dJ01IRHneUU7jk0FYMsShcEIdfiXcCpRn5e10uZ330hT+2ZbEQq+k7za3vy
BNv4dyLfNhwJlgPSCOXYKNgI9QCYasrUcXsS7RW9rHLqMN6cqzkC2a/bVJsLyH7l9f0zd5T3dHHP
TUjlS5Jv0/7SLExRJDhkqP8Wq7TZUdcpqPFXD+YQSv3JrqPm3VlE+w3lXyDs0r9bMJgH6KLzDByx
6cU6zcvp6GvcvLalWgSH4ptvc4e7OkG+a0iuDYblG4cTlIXK6rUgCL+sgTnaKnC2ANBWSYIQ7pTM
SnfrJNs2odYyLc56ZKrOCeUgfR2nYR6aaKdcRKlKL2ZflPmAiFtiFepWBNsaCNJ5Y9kqZMPz0wG3
9igNSTbJu0x1lF4e5EjAYsgdBO0yDnjluuJJJN6oW5A5gWcYeMEWqjsPyfKWiCD1+SSnEZC4g1hr
JFK1EtaumQy2q3Sy/DdckZsVWaC7GYTLLATz7VrOZ7HxYsyC9pvkE9pk9XGdFnN2S8PlhZCe/BCb
xbKmoL939zc5p+muwRkNaNNKqS0vYnBMB5WeogsBiUqSvp9DWexKWQo/GBiuXF7Pd5xsFDazpOlp
uz2yTf2Qstg0RDgme/Y0IlQXe1YIGeo5UzLHCIRk+xiTiqwEb+DIJn+IFC7y+4bgnk2DE9deJUc4
eds2rarFQK/lppitGX9b/AhEoZVa7Hp5kstvtzFUdjdVuRyhG/AUnort3PiEchfInNZ+pN/L3fB7
tpZdZfUcMhwR1VGRgXCRHNj7Pc9Mb1WjJ3tdw37LOMjKUjdYvotrmedesFZaiW4YKr9s9dtjuXej
Gq/xpTbSeQ5snKtsqbn62jQDUis16a12wf9M3Y9L+6GvtjVdTfIy/1rab8S0Cnd1mXSXZNiQjBGy
e+4YeRPSfn4CD2gpODMB8jf2Jsk7g/OA16lR73jqmEBXLIbBpodO9Ut+QR12MXEFucsCfxAzUlF2
c5VuHOfbkgXz55BtIWKEEhPYd6qWE1SIbHszyPPh/EBVO/0V8ovo1UxkwCxWvdD/r0m/vhjpb8/7
/OMqkrfOsIsCfGoThmo+hPeM4KLXLUGs9PVDUFl+3ENm+CZTgnLLArJxiAtL03Mx8OIan40b/IiJ
sfnj2Xzn+fJ4DTiCADTxGUilGRrKYwUV7CrEn30OOr2oEVtpPScerM7NgoNINkWbBgLciD/QyxlO
R/yyar3oPXoZuPXSzKmh4iKE0tdgsoyT99uBiVio1DP2FHj3kUxw0V+DsC5hA1TLvClUjuHfRMCr
9xn9UbsFebFa2IxlerW/kKQ1EE+sWg2l3udxsbcyC5mCJhosaUktVE9tsbXeogGkXuXdFoaR4b4O
IvvdRHrjeGzgNP1mUsY57PDW+RFdff+FZtfKvuxbaHdnTJvizCXGf8BvqYPqq6/qsS4Uu54vzAiV
4toMHMTolazDVM392JRZq1hRrv/866kO1Bcf4nUg2mJ+vikZI+F2Oe+DzWiRtlel/+fX8W9qsPA3
/npiqakKX6c1uvF6pSQvKC7I44fcv/09Hw1xTNVfmXnvusva8ieh99SXVLzUZx+S/M/LPu15VEkN
0KBcFOwFHyx497F9pHUEcICex9HIeFAaKE9y4zShTydLWX43R7BXhWT6AdCvrPWstrkqA7q1r9iS
K3tB7svuo/vukwwydE0RGB/4z+fg1lrG3ksQGZsJUt4gG+XiRfZPlbWhSLwx86PV8o7SXHhK3p3k
3POe5/A+bFHP+tG9Rb0uElagooUO59/YURusZehBBAryDDSZQE5iqD1PJNvkzquz6ftUFMZwx5Cf
Us1x1tpptSezmp4dlqlNtW420MJpB9BezAstWtApXfb6NUx9Sbc3+a/oQu/uCor/eIwTDuixYaUW
IRpcKZPbJrh3ZGXoKKv73uivX0H7p+umCXUmTr3dgoNdR9PdPXHs2S5CO9JHSAB0jr845ZwEDlC8
2zFDk9lNtg3uFsU3cRQxu1qmXR28CuzT9wbng6raeFuBIWtQnaGKXwsduYxN3oGjz80D5GrflhvT
bKq3GidMQ7xzzFzPipYPzYB8Mcx5qHuqUtfl2lsCbS8LX+tztIP8mr8Uw1IE23Drf5GkF6G4MRRM
pGj1G+aEgRX2dtvW7m4lsuBfweBS9TBvgOj5cobwX7wvxV9q2Bxm+w1TOJwuk1D+jNzvzP1MFpsG
V2bqboa33eH1WiA4T3bQfowOAdZK0vHe6E3Qs4jH6IAojPAH9V5zfUtKzv8FmLNkqGUQQZp8LDSU
suKkkNBnqdYhTD5b9Q3AWJLqIiJWjLIX+6Jwg2G3ApI54omeY2TYE+qkGl26/TWqNy+lnjEZ39Aq
J2ZRXWKaEP2SUSSRd91ExmAxrfU9zkusZS8+kQuMrTQdMjycLCXS6VAwGIP7e4N/LDUNf8gTNtzn
3SbrLVN88REQUybpzp+DOSkV1SmpX/OS5btvLTlOi/UzWYUC3GkSidRAVbesks0I6of5gkNFySod
tc6fIxXD25kyQ9n0EzewQr7iWCnWlbiqbH3wM/wJo/aQJfKo16nwdyl3tzh5t9K6yFPv1KeVKVvj
/N+T+rifVoeaMfT18BmMsk8PRNy/XAOX785IdOFwcgFmutFrV2LSeSI3RR3Zci0c0RauXtRIcyKL
cIH9ohbjfslJiqQC1mdBz1g/Zl5JI+LQGo5nPjuJnsQQZjA1+BR/jsFzzyDwXPa4PftmR+rXBphL
WKIs+xt12zE2j8P4o8F4vqNleojcxrQSdQQEizmcM3kuO1/WnevpEeXHR4SmFpDyhhhVkeblrNV4
Am7Jpc1yaOnMwZKjLYaEnkadk6MZzRwNC+vLmGtVUXBdgBXjaeKmXZYh/ONVMmDVxsbWgsjysWtb
a2t/G3YHEWc3Qh6jebgrmUbiG/XJkJG2tnPjgJkF5DXOiuMhOeUcTQVgyqxEHRLkjT9tDsAidPUr
FqD2iWsphQA01AcUsDxQ/flUiQNYFaq3kjLgQwKymWxOmB10hQsWpn+QkFDKYWadFgI7vCR8Lh3K
n4NejpY8CZwXuegHSVMYjdkQ9NohJU5m8Evdzm/PpekQhigau9b75JmR/NuStCN2Kw9mvfQh5phK
+vsuRrNssX1U4EgUUfgZYyQrwNRsoUb5T+MQe7vqmzjHcwj7vhG1nPZmhgmb0d1X0jibzmsHFaLv
rlTgu+6quIO5bbGX0eRp6RRf8IITrWQbG3mPELK6Mqge0Q2GOHwe8wvDlWmloQy1AN0Y6e5iL16o
dRdooyhLMR4Age0SyZEWnj92yQgmi/5rtQFcOGe9TMOx1KCKNnyvcbR7qIX9X3+cDpiEJP62A340
k3l3F8q839jETxFTuCuYLVdOAEGege6Za2xkyFK0sE25McTBAEGuBEsdLh+du8SYWNDFx/cTKI3b
Xj81OWxWKKZldBd/uirKSjWZTdPlBmGFT91RB6eK9zMaU3gTMKolUuLN4bRm/coOeW00wX7bgugB
tm3Wp1lhjZOGkWsHRCZzEI523QZTmxVLwYGPK7TsUCxH3+2s/t97eXfuldnaSXktU7t3JQSgF/ki
2EcOa9wqepmkPYjNm1qy7qvUiYcOuLDrsgQoQyzsRXpYp95Napt1+lLwNlpW0Nk2DHFS4Xg6u51i
1A8KgWbC3K22931G0on2GeeutILApoCDGa2Xaz+/ZhPlUVSCEQyOj3dnllr8YpxNb0J0RuC7Z/uz
QOhQajaS+/XVOu39d/GNZ6G+mmFaIX6aMPw7ftimu2YXKVZTL4kOSIZXondOByR/L7eUbLyzhvFV
vRiyt0Xx8KLHQCxq4PDg+tR5kB+a9DiI2I13xNYZDZkotsm3cnYR8ZrDpU3uTTHIByajRcIIiyWc
yM49fLlrys6K5pR3GrmeA6pWsAI08HR+LoGsfYt+hcatl1OanJs1+lUxKu/v25EYRytd3bptVxKH
1EWLcsn1hgBnyC7gG88svJWJ/hdQjuYPI33hYbul77VpVwwHeKGzoXlFzigSkjfFuNQBxSLezIxR
YTeMs8JhSqhazqxIyAIGMeVTH81DUqs0F11HyUPL7lK0LbwYwuEJe3AVyTYEI9wmWNbL7ugNTJoX
VQR1qSs7WzBBAQrzww7EQTEq5TkhP4lFSJT2utwHz+OzMU23HDng8GSPPc1GNRPmzF14gIztmvoF
/pxwCPfZps2rzGd3IwmbSZcPR/qjUsPrBWoMavNJqGDXQjIad0q35y4/G77ET9cMtJ/4NEPXmHYE
pJ+cDgKV3B3tLIvXryMLRl2+ZhJK/ak1FH46/9KlmUOvM70LS0DMJzbwlm0UEUJBQzWn1aMVC98W
ysvPYbAfN4/7KO6U+Fgqlb9beVRDm3b5c9DkMh9yzKCZvtYwo4ao06mL4y6Sk/mDfebCckkqgJD5
v32YLivaj3OyHX/kpM2FZUI/Y9Ii7L5HpwyUoeAH5Dslzj97r0s+dRS53UN9TclH1CX8G9HnvHmN
E0ZVV8qIIacYIX3JNzDPwgwTbXQn6ej6/AHAgwuJavsDTGrsdmMozzDDE6B9mf3DOtOgZegk2Bwf
JFv/2iLCO1K9fblWMB4ChSgNl4wFdmr7sOIZ6SQNPeMv4nsy+BIFh/yck2V9TVWTv7HVPpaMYbJR
8bL0n0sJalHfklrQacjUrC2dcmXIc6Yx1X0oQK3Ug2oIBCJDWjm5SgpX/CM3ACWdZ3LvGsxXZbq4
F7ayLoNQgY7r2SAqRYBWtoOeDdll9ToScrNj3OvvBXGbxXBrlAFapkvL7EdxeyKkGG09H/GAtDc/
A6/GRFXTjFrXTon7gx90D/iaIyhmAqt0hP8TE2Vu2oxQ9jAlYk/NN4dNt8LdQWnDVW7pdX6H/czA
cbFEEi8uCJht2z8T0NivFD1aTCSApgtC4my4IhXQG47sgMdGUpiGp2dNBe5Eo1CeSVWQLDIWcOiE
o1n8r9PwooDs817XcXNv1sG1StD/ZV3m91YRLa69uYBL31G4opUzS6iUFB7Sb90mDy8lBndEzVa+
CD4R7z1NiOT1oD6bL2ObuxZz6RcWftWfQgux2ie+/MgWfoSmSRmk1VtNYeDoPojJreh+CJBPtZuk
6T/OobhlmN8Z0xHTdVZ4iD6879Imsfmpx1WJuvjHw2VfEEcQf3EBZNGEmdql0StzH4oIw+Zmvfwv
i17H+kwbBw91rhYkK1D80ywMAmXZFUudeCC5PB8AwUa/AuFjCcVW9dZlD1X3xXA4B/vw0p6VklA5
sr8/DhOJxklTmiE93LoAbgaJ0Txlg1ub5nIC8CIbH2y3m1u4pBXuersw75plb255Gb8ZW0C152m4
CfD0Fdbw4E49YU9sUst2zjQ+GwvAavWezDlNlvpjH3X68qlPrB8kob/qX5/GJV01Tzye1ahmTiv0
VeFEbeP9+NJwwZKnCDqWBHdNHPMVe7WKFQjEY5JJ4K3Vx5oQ10+n/MevzUZLflx5xojq7PVmq2Rb
hhwIxCGIjHZIlxsn93tQHyk9NVaXIrKOwKGzAKySzxE0HFtRYRpJ0GvfMOTjuspe0oDjkaEUKsC7
ViFbDf1Q62DhxSXmm2mM0hraS2HtX9cNETQQ3ndY/EUCasqbwoVGESLREze4TCfIz1pnN7tTMblI
1QbeMup7n3qfo+Ngc2VqH7IYYx/t/OLT3zbE+HGF3uoLsfwMX9VNTT1aN3VaeWxLw/EdGkZt1UHL
m15ZaZ9rStBZkH/7yCJkac+oKhmTHmSXPfleVeMaK0qzUqaYC4sc6QFgJWSfVixA08V7nYCoDXjx
Vx8h+okNBharzesNORRhk+9IUO26eVS5TNYEPK1DSD47CBGtUsULJXUIU4eqzvwtfyI9G1L14HHP
jB6lyOJOiuZRuo1uIPfnp1N7AItIvR0bKpW0USJWNsz54811JV6/T4hiKQczWJK7XFW4VE/Vnh8Q
/dK3JUp3EM02L5BMCp1BCQ0gdF+xCOQ8yMMKR8EKmDFSWzKOqz+UP26dsaR1jPT0E+KRbtpYmW42
H9VfY2UHdlAUReaODjfr/rBR61LC1zn/UlEyRb65g6LBgdUfRxi2x877SVjyzaba49PjgDSxrKDf
w7KhmBEyQKbIQ5byP7osvywEJvpuK4J5F3yImpyqOPufyzYgfvlkpORtjJaQAjfVFWqIjtndwtn0
yp7TGaiMsRqGcT+yD2AIh0YAu8dmDvMSioVGTrRoYmreCkJwzn0M7jUGnHa+i6frsNOZ+Q0D56Am
BDBQMnkuj2g1TV2Qbw5kckvutIOURC0fNoNQY0V6HL9tSYCzABrZ26mmKDwHYmYToMYBMbIZPWtO
ay5kPyKy5R/lL8rmji9DvAgfnMoyDaW+C598sL7xaobuHNdLUwqSNaI5mcF7+0CcwEaQuPdrvnbB
OxCdnK5NPqCYWJUCHrrVw/ps3aRQx5Faq1dRTSoDM0jp06jlSNoTId6GO3oiluQjTnuB4pPqGc1w
z7USQx91M/8XAYoxOsVS3DKRfUprgnqEZ8dcmpzJGignaeboWITEH1wZHDc4KL63DvvC1Nuhx1vz
4TBJ0riiFaTUboskSsDiBDe+kYGTTGbSv3xUXJ/NCqnFVduQ80ygyd19OE2PTHbiHJ3YjREs2zRR
HLgb53eJKe3c9rC35vQpJaH6xxnFOHiyB/cyb7P+rC6S/uJOfbecpmTPAPzr41Lj7ehd2OyX8k8s
SNGKeJnNfxsBV88b2eqrEXS6hlbSS+SPEFmSF+j0ysb/JkWDs57yftCuc7wlNjQw/6VRWKlOhQBE
aAglzHY2YoHmLO45k9iyQzRwIG/kUWS+erlOZeA+Jjla7ioV7Ogr/Jccf1Ni2Q3vXIyHD0FPnLZT
cbDx4qMYzFj42fL0EeqzdYNj7Zv2wH9rA12y4mTlsqMIQWlWG8HUm9j38kXyO3repP4J6Cxbhm6q
6SHCo1bNGhBafPaAiVjFyEF/rwK3ffzOOsMyTikGTtSHTTtemlFJ66gKNaNHVosiGLu1NX2XPRDR
oyr2wIPrjG3g/dWTNtYc+vvR/CA8eA0Tbq3OyUInGZlFn/xApysOXv/k2D8QtPYiBKb7Vxzi6ZJe
pKPwMf9zZKcYpbcXEIzlURyZC7ps990b+kdSpq8gGIwYo/nPAh9Pw8GuuHVVRh2EE3fJiX8Wmxgl
lbTTdcTfHBEh2azm4Af1FqDJzelLvRsHfAQJbIEAMKbQtJkM9AMr4zf0LIkDhce0xXm8s7wcZ+3n
OWfN3cVzDkEB/OSTs3PAySis1krmXJETLpJag1Dbe3XXvG7dZglQzzGEIhx7RtYnK52+Dl4Hgf61
JOMqo5mUWt/nTywB+LI4WpJQ5e1JYnpZ26l+26aTOwFJWe3sNFr4POr07Fga1dWuOMjp9MhvItol
QREc159yhofqqW2wa95Y1ZsCFTuVG/3DV744Mg2YDdCREBLV3DqCGeAlWOT3FLhWCbny3jtdR7Ha
zKwm0SyjM3GncALn0mmKlQq3l+e/7oiLj2eDg3t13d565HbMQY14t6doIRGwG/EE9gg0luNzE0xe
XpxHnavTsERSv496Y5XbQJu7Qc9bfDBzFDN21GzsOiQ2WZ1/5PL8hFed/DC/VZBGrriLnoxf7r9o
gpVjjfq0lAiHYXhI1AXpjJYwISV/tKJdODeJCRMSswuGKjosCGKG1bl8Bb32a9ZqryheUE69AKV/
NC8H82+2HgetYKndEGx3nPuQ7eTRiCd9vWqhghCTGSif+ze+XUCPQXMHqMTcplZX+VaY+FTW8Wym
LdbErO3WuNzNQywIa09QU73v5uE4OoLo9JXTHBPj3x6uzPyIX/lTsGc+6yOXgspEvDTMbhErlN1c
+1vt+/qLMdtGZaN2XoGJW+tG/zN1smL0NZN6q91C00K+RGu6h2I6nIhUIu0xFMtVNdvI/cbM98F5
uN4XLkqkrXi71t738lBhaCkh11DAlcXgHb/doPF8W4a9efnD6rAKvaqvEr8jeecRyQ8eAJhrOV/t
bjL8zOWemCE7ecY0Y1H7PZJ/deB6xjArXKkuCGPra/87tym1PcquoVpHSEZmk4M/iMMRKhUEQma4
fOL+gMDOlrNFujC7A41sxWMNiz03KoXM+wiT6gLCd7Gru0Am2PhpUI4HfgMLV1g+Lm5n9HBPfum1
IabD5y0xwUvKP4Hw3v6MeI4cGg4uRi2KTYR1buWBYQYcAD2Tcrd0dKmUaJFMhjGYxfTTjvlyb0n6
rgihRUuMz/hK0dQkkxaygxmzBEcyUnMJKgi1E1dl8U+8eqvBuPnRLdWEsu0dgHYf6aSrf3re4Sj5
Qh0mrR4Ozr3R9txTjGAXbhBR02G0YRX/rW3aB5SFWwGuwFvKGM3nG5xjp1OhItak/UjIXthkpQJ9
ALJob3Ybu982SE3Og9hFjKwyQEvjsxlfPTyTpLm4E+cCatij9gjOf0I412mZUxnClZvS9CdqwXWn
MsnNFBVrHFiG4VwDW/Uz3EeYC7AANkCUtXDK7OF76DCdlpnalTf6VmKJf2AzcBdG3pXTZB9IEPij
dtzrE3A48QUK+RpRmn4WVWk4KiBPxayM3UKL2LLxRdkvjdFbq6jv9M4z0epyt8GuygYYcsTlaZiG
303+CPZDdRGJ6tQ7Sg8luP8ekMcr6GdpQkLIJOIwcZzKBd7M7r/xAmZGARLS+yWwlLbwufRcr5dP
aIuo9G7rays5hzsjcdDyCqGgQ0fJ0n0YVP2eWzwCxpj78kLgujcCj6aJ+0swWprOksd/B8/8hU9F
0g9qDNq6b4+/C9UXdzGoI0ji7jtX+Ptt9l4iqJIWijZBmZ2BOGYPX2XEHRl0ZumBBtiame/E3099
uCtcxm/U6abSvmZwW7raoFuJBmKcD0CUB63iFA1U7ehfnmxXx5/aCV7kDWkl386BYYXLZyc5aUrC
e135soWyPFXKR3Ur+dFqn2KwQwCZUCC4b/MC8EgGu6nJ5ilu0luRYc+V4LUL7KO/g/S588b65yu3
1r9GJ/mPoDXAgRtHFnvtbk7eN1rXmwJ34tno40qIa8j5MnQ/cSq5Yk30mqy/lK8G6sVGI6VSmKnt
MmJRnJFKnRZY2g7zXVRyGYJ5ltkz7Z69xODlNxF6TMaHxuD/51UB9AbniofuSXx6zU1hVWv+f3Ck
3yyOSMQHf82DjF1KuUBKYNlNwMD0eIxz2iPqpylgoJSVa+773oM4BTQlj7Tq7yBiO5gzJcI9xU1N
q79nbcrED94bkROSa/wNIaXP8lxc3RaYnzLg8FIplB3LQ/7AXTu+8SQGZ/Sc+SlGAmVhRK6j9pch
QNU0yUZWPFmAhqZPmBek7061hj64EL1ACMnQfFYE8OdrvPO9d6LQbcHZ07sZR4UWGOSm8JZwPWne
8Zrzcr38ZA6By/HckHP/SBytFWFMVzALDQU3s4pVIU+O6Dw846w3H9GqLQHChXhVJehYhL3DptDj
t5Y0uehc2irLfBIqW7eN20Y78z3KpiMaFY0fcRYtbqZyrupRpPu4aeXF/yx99VI0Alw9Wlyoz520
pjLycf574pXrUSH/xNeS/pRgtczpKiHGaKydNep5F+imrVcY5gUkwJY7j/9sjLcYJMCJKro87Fdl
bS7Wd36B9D3j/iy2YRsi28J84rbduno34S/RZAZYbxI2AjJU4wgi09loTGitKQhS0LdekrgkWEyu
ytBw7HQBE7RFGC7oqghBqAwj4p2TvA2GJS5deEYVSZt/BEAOvw25Do7/DZwnZAy9zXU/yJixe/Sk
dox2bZqZXLQzrFcjrYUO5qLmCRnI0zZK07dx7c9dVsgWL4AeHOX/NBYYVPyWnqc7sEmhbcBiFVzo
y4dWwT0qgNkc7de0BtndDr/xhu1XVbUlTMSdwBp+aULO5FuNE14r26mrLxKU4GdcAbq9pAnZZAWl
Mb4TQk/9n8vDJCO2IT4YTtciBa84jpqC7brZfOLIYXN/JskfBdeBFdbpQjo/YrhGcG/qVfx9OvYw
gEjNr/2Iu0pgk3BCpbY1EkvtYCgkXzT0RRaotEj9QF7bC6vGYu/V4dm8l86MFFiibvBRbSqniC+c
sxu5cQgUmKBRYRtefa+PgW5DDvrMQa+XtzFfM6x0PpjMO05lvS8zc3FZUpt44RCyBuJRPF3f/1Ix
6DAKc5fCSUtxFRqx2xDFZiOpt2JzYHS2MfzQmaPiU2gHO2A1U99eg5yZsIk52s/0yb3eedbRKedz
jeLvEP13am6H/4HVXQKJwQXiKYjsGfcaxZX3SrFjDmsPZlEW4qFGjShLQ4LBalVY+xIPZ/3LbI49
KlSavdnai1pe+hWRgpML3jiA/42/mcdKSRN/JDev8hnGAP0AsTfOrF3qQiShnd4tWszStu3bRQID
5Lmkn11vwEpTegCJ0qEDzt/vhGfVqvz6O7uG12E94f/i3vD+7c2x4XiFGbVs9QejNEP//EL9HQ8Y
zFS0xJeTvVJ7EJ+m/Y7M6iOBXtHtRpr+m/ATVWro3Pl4+DsoPR4bFLnQRgeIwYWsDQs7HZQ9NNRo
5sUQuGX34buWPfRaEGw3PpJEVCGRIKAuqhZXJJLi+ygDij+jLwFMvpIn3H9eoqoM8qpTmoUUwwPs
D8c1kW7GtfGLQXSzPwPNQJICzR+7lPeShNFT+7mAmM2RPPc5p3F4OhSypJZ9jKqFsI3rB7pEV/N9
uizKCEQsvafQvPvi5/NkRGEpo3QQTse7Gd+cjnNKnvqQokw3eEUO1o18+zc1zbM37ppx4Xsdt64W
t0esSm4wv9KnO/8uGnMK57vucS/u9oBJmEiaOTmmcGyETo5G+jUY9gDKCM/c2TPHjSujmGlHtSCf
2L9USGbRbJsSae4GaP9sH+1eiWLKJOBYmkGtIXs0ky7xQI+DJQujXxJNdb2ryuHWb/lGBRAJIcz0
zbzJ2r9kV4ZVVgd13h9I+28VCaTKc2jofW+pqLEJEI459UMzxtmobFf0+SZK8NVz0a5s1yqy0HxF
7esZ+Rqk4yXZQbMqqsaKbXKqiLjl9si0SK0CC2OccbTiYsnpg695xVDMx26X2/TSlhtm1+H9twmy
YJbSFKFyWPwgXfhhXcg5m90yoPFOip2B9ahz6Kx7bzlxHCZRr1eun4w1IbxxGTWq8HqgavJV8qKa
69CjVTujMHeJJ00eVeeicRHZeqRcFn+Jm/TFJWrMott70JGm6AjeEdr5Y+h+sZ2FmQt26wCHl9iM
f+u62ZeSq34weIzTa34yxqcjyYJGvWG2VKDj3j8qEsxEbkpTKT3aHfhvPT+JOpD0WQ9MXFyb9GHD
DuSLePT8ZDhT8MMzKQQS9PyTpuGXY1OqzgHeiHAk7q3T0LTGJNv4060Oq/LdDV4/ymWDKI6+AJ9s
O0RJ28gQ13zXqEnaQLAQYuRt8u5RCrQhjdS8N1ZH54oKfxboDj+oSaqAqN3O8um598V8S3A084cM
hc8shpaJok7x+T7S4zGzdfWflYqvyg7xH/RMoaVVWevgh1Yxp4e5IyW/UOeu2vuxZViHXmmpLOuf
NOJQ3M4nP2u7e15MIG1B5pQvu6k7j1sqICcwGrIjKkbjyW+Cp3uwVJNuGyVNkn9w0kIftMZmiToG
1KVR0I36a+VwM8lmK17sJdgZ+6FvBReHROhQfZjRghEdWDLXcyw2VohqYCz6gOhRZBwitLrOvwW+
uAzkcTyEK1CoVEWHWU8rwUDz44xogOfDPGZdE9b2SpgXvwPAakmWC2+zq7GqAhUTvIK01to4W/FK
nq+L8aOWhmnSoXiLibcxZ8bkV5CVKiHttmF4YCIORjEWS8ZKyp5WvHt5vpDoez543PfmFxyemJF3
6mUp68MPbkVvcSvmqQH5H7wHLuJXJk9gUvJS0xDdXgdAIn/WZMIvgXYi5TLI4kBDK5Kcz/tjEBAc
XCHbEcvAgcHk4VsIuxsaxZw1j8G2KZ7hUvzhZpdU/06+6gh9s9H+kaNUIXzK8DVG3eYkpsN9Z1vM
Up36acoQCTGsCGh9xqxd+ar4+RjxIqOObTS6qccpHPnWF4OzrZMbDvTNVrzHOyI2gN1HxOU5kBdx
6BMbE0SKQjP1HVgdZBgvb/OLJ5uZfJb+zMCUc8aGvsy3PiX3CnynBK5YGVXPlt/zMqcQX/NSdYEV
2f7I+Dye1SfYD+HN91ZOeUUtmesX+FxJx6FFsvIKWo53wS199HAJIG7PHDBy/u+5yf4yTW8aea9x
2EkoxeLF2zsz4ISCOARlhtFLpufUc55QAdvxc+0o9WVTc3RL+rS+gT/mNHUP9xAAsCIxTnU6DlaQ
kt3XzkcJKELMJ9QXP8h7Uqm54Tlz8fEytbc24hAzsSflH7B8lvsMq2IO5YGz9lZuzOu6J7+pXb9W
VIFXkKCkpVgG5OmwouyK7PWy3I7INhs8brb4PJj29cNWehHc2ZNJ366N/zAPjxd02pEV2aIYc/J3
zKYT3pwzI6066LjpZvlbQwDi/qXYcyt/5Go8i0BhWf94aH7XFIWBK7iFaDailkg9eAvbK/NWkzz4
KaivpIyI1K7yE8fZPxwWn0P+0ilyu2uHe/GbD0QCFWN1XaYdZPFXK2pciCrxkNhqeUQKnQNkde7x
meurXm4cjLYCGvMLSmKKAcbSAOP5YuD8anySZtTgzPfEc1Xe4vNi//nd75fgjz+uF25oX/k+esZb
e7z3/g0viF7mHak5oKtrdb0T8cE9vlDOqQllWO/jKk+77VE2izuf+VycUNnGzZ8w41mzAUnJUPfO
znHFE1/JMUbNcgtYn0D6seYzLogHNiK7Y/0RLfjCJZN9pZD8W3h7vfMBBmVgty7rKdHgD0HmVAcF
4+lnkCozDjnhckvrLASho7fQf3HabBvOzlo0n/aLPNcKoJmZf3jC6jek58a8Pmvl0eXIAlJXYQc5
cYqnWkfROo0ZO4FaWvJFioHg5E+PBjqAIwhDOrVqknX/0rlzf89t/DUCjyrT9MX95JVBzF+3e3LW
rybot7OcUJjVgatfEPQj34rGs5LrcNWTx232VlEN1MlA3sPsUHTOikY85d5nOXfnDA4I8T4rTY1R
nFEDXnklnPORasULyi7wtntl40JEVP4X4WiMpMYWsFm2uomhPyTS7YolAS3DwrAl60/esckuGZ6q
NGcWiza1tPtS6mtB7o9yxjT1DFX2dl0kOu22W1PDM2hIp+tAYnFx0yhSXMSgmbDQ1/HjX+e1Ij+H
f04iH6+ksLM31T6MzikZ8dX8P35tkrPXj4iS0/qK/UvPjKXJIn03WOB2rXJGi95Fc625VYIyERpg
GT8/R29Op+3iUFFmmmpE4F3Jh581KT6wbrLfO5NKcpquLhbCyMlXlv9K7djF0t+phcfsT76Q/dHA
gn4mS9jqlsUkYRtAH2NREngFPOiR8ozOzwQV09QJzeOp8/gbgeiCRe2/INFizFIZ/GBL7dAEC1pv
mrmCG8+PnKslJvS7luoo9DitSqBq6KXuwATSBWo/F33F4OdQKzIZQwWjBfE7JUIo1m/6ZX1gYcfU
e8tNfsglYWfIkGoWtwlPnIbn8O1NdFKoKuK/YUbEp6tbsmwlNcRsoAuLSfxfyFiUsLIsi9oFnmDr
9BDQLEWGmrVWdlwugXz/3N1ytG6/7ojpykm7OF/KvJ+7m4LUbaGJq3mN46FPc2wibjlGjq+Fd3Ka
4qLn+KV5AnEWowed8eTpe/nbbBg7jljSd/3L8NBWew9gj/6CCdCTBRgF2YJwrduVz5IPHwmCqyfT
GcFa7cJGCB0US955zewEtfO5F1SNM/6AIreZcptnmu/fl7WCFa60sjl4lA5EnV1kUJTcAXfGtnIb
gN3ZGi+jnJvakUzJHX0Mng/Cfsl5YoPeBWvDjWrCaVYDYVWZw0oiQtL/wxmkVY5eV8gmM9X5P7Cg
l6qpXYzJr/6GW/K4qCNCNgtzCJa9jTAf8DQ62pak1eYvIwwj4sll2ca3LhomNfyzmf06U0910lXG
cFrhXOe6D/NPFgZMW6ZugvPsBqe4NS7F8vYRlv9zmEiNFl616H8sql2a/+N3+3ArDVsZHCO1Q2gF
5JE+HKoZxfx6wBT8QOpq/xhrIj2UOPvHzG4/i+1Y+jh7sXuEMVzzDT3Q/gdyAoryb4cUD/ntFMiF
tVSTEZBAFhQ7KbEEpCwhI9p2uUUbxQac2+QJz8Ufk7Pl6LiD3uOCIudpuUwzybTEq0VGTKGksTL9
xRKh2oh47glC+i6Lr4uPnZFW8XJqtwB6UoYWkObNXbsPtudm6WCRPna/yG1eK7CxVjP1m/eo8Lva
2QaYftvDtr/1QY4C2Ibp4CJVybweAY1GKdpDWXCTasyRrovObiTGWahmfwbfUowXZmxLjYftFSr5
jwcZdl9odLrhzqVy3lFJPrrKjtJd0D91Q0bmsG0TDTkelvE5Z8noUVpd2y3Y7XP6syYTjjKSn79N
QHJNekeiwh2VjXkl1+RmKbBTWITeGS6TxUpqMzrGjpehQlt4T8n9HMtQPTWMAW3Sfoai+ILIp51y
05iqGsO+OQmMZK2Hh+Wkp0PHNiLNeFUem36OMiTbJV7WCgweCfRG1WaUq4b6HB1b7qKs2D5+p68x
PmMs63h5JKuOO5DeNnbfB49bXN+v9PkHK/sXjFZ9u4a5Ku5p9tc85Aarq4T80h9DCRyohzJGAMFD
fu8FJCDx/4UgoztMggLeJAe6u7R42D1iAp4YGYP6x8Ol4xZdfw6iJyR4VZkV7mgvP4ZjBNrg+Nkh
Zl5RIU+ppfz7wDeOYleMU1qSdva2xrh1wQ3XwO97NmQ2XrptWoh4JRYSKH2BoRVESYlKiaQ439jZ
D1gxXvG9QFVOWwWN0sd81OgjDTIkF8bLuXqHvoJSY3ldTNDT20uLFXL/m5Fz84AfP3kERD9Ta8kA
fDWi8HWqjitt4tB+lkC869/YLH3DZakyu5zXXWmFdFw2BQImNW6CLODzmjxkso6ktfT0lp4EgIwZ
bRhdeE1WY8PjEJ3e+pTY5IYgNs8KXcX1BClG4RWFo2xaMmt+ZinS1jW8zr0Ds8bl9MRKbw9ejIZ0
Qi+VCeEhbowugrBhGpfth/iTP3oliwYmCW9fif1nMq2zA1Cle4YKWFkQXBYsDHcWavNC8ewnPxKt
Sog4AdC3DxfwOub7wG5IOqwiZDan9upmffnQS80ll/ZiPINLQWexum+J1LplSqSg/H4hJhu7BRUh
JumlCxt/CEPhTbvgL3CiafM42NgGluV2oGovqAIqM4dXN9s89H8hB2lbUdSJmujPymeZzo8016rd
eNxugUsAACyBvcjA9HInpUZztjz6A7L6WQ4I1FqZVZbbHqOyyzeFFM1g/bEGL+KGQazfRysygaaO
dFv+MacInq95pqMa5VcfRjnof5iUAuRYdF2L51+lVc+8KPsSbHOQo4lwDxBwBMmNgFW4v/s9jVOa
WeqSPRaCt0okzLUz0MGwVbCU++WC9QlOmbLZHvreQv/sf1hMP8gYVZRs8T3UYrzihMgaklXT0513
QOB0P3qefvNX9hqUG2RWLAAERb3C1V0cmjkAKJEYnZPyyr0sPWSZtxL795vYZVgZUzIBmvQz6Zu4
MZZB8BmjbHFwFwl2d6rfQtGOS6/I4n5btFpKYSNXANzUp2AU7zWCWN5SSLvkUELgQXSM7KuFx6eH
ZX3CbK3txgVZ2YemB7OoXC7diqNB92wmpdY/0GRVWMz9+qgJjC8Ovh+chQk6yyjZEh7gQolBMy6c
pBMjONYgmHbjm0iVS2aDXWskMLSO5n8O3OKKQ38q/JWjVXM7bf/uQgWMSfXkpHyX9ikmIDlIGroh
ovGG0FM3XxaiToy8IsvCyy21S/R5SMywfAr69hFwhVJLju80ulVDFzvQ3tG2AWzlK69MSumS+WNQ
9/k8ODe2lTx6/yvhmLVwV26mlQAlDXbq6h2j4+UfM1OvrCwC6xq2br/c2SPnFmd6T0IFMfsCuMLs
j7E+ASBXKFZGWDkY3aoVl3z2cYKxQ0xp23Yac5Ek3kOmS+P5D/tcegArNQkAiZel1pF6PRP2kwMs
BYBB60bxjnjU4sgEbBa+sq180W7kdibNNH2LxKfiI4eYLym66DbDBrOEdDD2lRfoMi5pPlpWapk1
HRmzBMLNlNSthDAPDcKj5GHcmshcRLaVTOz6X0McBuxCsco3mybfc/IhDb/Klerz48tOiGMNLVUs
mkxGx2DXWwfs1Z514Fnwg1VNXw+NDH0ZBrxmm6k1R+W1TpKXN8zEAP+UOnPid6QXcRLbVkGFgAmc
j/1XlK5jC3tsPwNgstq2jMjzUgkTu35uEWjflGv+2y9ozvueXxbkCgXMnVz3211ZkoL3Jf9KZj+j
Ahej/OuiILPCYR6VKLK5tga2DZOKokKYOf/NVjHtylpeZegDFyAbnrRAf0fVXzWY+Lo4td3V4isr
pomUflpFdx/eN4iyyzSJ6c76W3J76xWlZSdOgZSkZ/8nRJ7wOyh7TBLdQ2yrr/2pU545IERouQJ1
/3b3b3QSy5dgwthST0r/zavuYuqFNsGBBclIW1l8ifEOi7ev83p5spXDceh6i2ogKRGdTH1rMGb2
9JxGgjo2mwK/YqY+clx0M2WPWI1oe6eKIQu3GmzgPHa0VgMiwj9kvqSjVBHXV9mWVIHQ6ySNgD/N
f2N7EArPdpE4p+0Rg/+A7GBzJi9+5sJJNMkSW1R6sbIBtdqrkCO8QyZcyh0wXpnkxHUjF/otSrZz
Kf+U76CPEFS/OcfFDGbDdYsoYgrEhHpt+LyNOK0v9qcSuy+lT6nl//pkHOEzzbg286EzbPqctNB3
AW4pU4qoPbuNsYefDgXbEpkIta9BFwK2Xr4oolr/IEb/Blae7i/K2QBLe1LKYnERakzE9I/jhzMl
7ti1X+mf5hFk+nx48OvbqPjPo/5Gj//M+ff9S9EJy5qMUI4JLQUmBl2GsDGfcWJdSPWOJuSDc12b
dfk1STZ81o756Fm4h8nhBa1wZEYvV9fgjZkhQ2LBdGLw23W8a7xtHu6X0XVlwsyB+KmacAL3XGyE
dXpyBe/nGe79v40mz+jXiAspx/+oy54WL0uPb8DPP2a7p89HscTiaGT8+fpFxRhnB0RxDQ7jNp+8
F+P7WUkqFet0/mW5KEZASSf0OgLXYGT39f6oE+odyRNNnRpH2rpSaFoXIduWBvREAI06V3dcb2Lq
ueBge4DbTGFLqSQXmKYCDOwxdIYDlEC3QRY0r3nZffk8WGfuIfzC78n+f1e2M7omQW/QshWnzHEW
J2kKl0NTaXvrlzG/YiLxqyTF8yv8JMhj3sYMgH64QDx42WCuUN8qRhWDwcZ7Z4AxdxepPVprXZDi
lGacToo68wvggllKYx106o3gUAsFyMLJd4/av/MsjaOpKoILvTKRPO42Pq9WHtAEQ9PRK+C5wf7I
RqWbESILi8qlV2BXim57BD9QhyUKMN40FlmpFWVqMVhqUNKFBMMx6if3uy/wg5+0SEZAsxGZ1OuN
C0atQoJgaLXghEBLFF0AowQ5ql96odjpIk0Bj0RMsbktZZwlrkQxlu/jWm3rgBSWQudSXk04HGd0
JDJtADfI2EDNHJN3vYclOhjnIFRuiZZAh/HHPjADK3bUavTRZ8WAbAsE7bdke1X8MaRBa0lA8Myc
2heFPpD88LzLNBrBl2/a6e3d6ypVb6U8tthUiOeggO6qvLQutwrjpmcLBnFMYZj4E0gnvYOcZNnk
wSZ/7H8hKvuPOuHYeAedqt5EeeW2Rn3tmksbN/OeMqGK97IPHLVkcr6o1XsUwSAxqoncUACjzxVV
0PZn/uHznQX9lgBTpNa8lkhpU3VSjLda0U5QN8z1PZxAWxPfxYyYLMjg8Z/Cv8h60i55sRNQQ2jt
pvISim59JQsmcWQkKf3RFwWTsJfE7Jh2I2qLH6PxfGpBShL6Elc61ExwcFlF+a6yWlbB+gZu+8DV
4bsezitTZYUEDCpVSTkBCTVq/lmq/AszbfI3M34UtellDBdOf7rd43ZkMceQdXJvKwjekMvjczuE
OxRzmOD7kDgGF36of+pYjfQCSVwIZxnES5G5NVJrVDNq5tMWrrCLSNolcQKFC8X4xHTp5okW/mVS
4gyuQqbqGIab5KO5uzjLgLP6hAgG6EwKRY9Ql2dUF30+vs59oY/kusaySWYG4Roh0Q27FgCBd7gI
7EizNk0yh8SDtHGd7MF9iO4BFg5wl63QxJeBdd55MEs32yHfsc8iUxn7Z1r1sCkf/E4Vsb/aybJa
+n4oADrqng0ZCRPLHvHsie5pqEFnlu2QZtDtE+HYtm83BPuQpDZVeklt78mPAV60xruVk+gzvHjM
NbT7xdopX6ULe7Z7SqKdatU9AsarH2rc+JD7B5ZOZRNi3Qj9xI1QgvMsDGYJHRjOooAfBBPEjYC/
ipI3qXtjum+9N/22buyiVxw38Ya2fDtQNVNGMl0boAzJ9ol6FlCS9eEIZXz7o7c9KtYBsxQxMx17
JMl8KtL03AkKhb6oViB/RVhbyASUW3u4KumWTDdhu4oZ/lba4W0SpJ8yivv40H7yAP1mQtRZyh/M
wTWvv+38r8B0+UnpcjHPfBV49K7XHIcpnNKgyU1PNKLiXhzLIdDFhSEnzqsQsoDjeE53QP2p0+2o
AoAuWdyzXrnjWReuiFp4/lpN7C4GOcA2ZMvo9usyacSi1iEIs8fSFo6FxMpQ12sET0TmnNsi+lR/
rJApyNSm8m1AaENek3/Yie3lHY3dzJwCYd+FBCmhyVxA8zzduChyTOPUTUreAMmFq1TeqpW34NwV
ao2GcuaDM4X217qovIA3vZhmmgfWIgKALLm+PunsQHRtsvSRBC25Yy6dreL2nPYPAUayx8dhpepW
7EjIh3bOmwAl5kP8unea9l50cucGLCGfM9wxVddQYIcFGJvXawRAevKMcIDM1F8cdafvKJqoSNH+
W4KZvJaHMuaD8QAeXQIOi8Kb3HYOrAcjCCxWS+TeiXgQZ4sXMa26yoD3NEC6ZjHQ9EHpheXR6vJq
KGhp5HyPJkSLn8ApfPHM+nAcC8H72laN9uLlscP7IcXZyuRNo564MOKbWeDgmeH/pnW5qGy+cPwa
vgFHzmgL4KWHLwfXjqZ92rlh46/nM9j+2O9wRI2YmdQ5OsrUguN68cQTZYrWOeGJB1AiWXZdo0GZ
ZcMr3qB+sEQg3JKwcKBesizNoG6Ms24k7wRM315p0t5PrLfS9wM2vir5LUWHYqeC8QDkndqzaGXq
09Tywu1RTUwK0bGZx/DIQjIbbkQ4wbW11qEwEkWPrbXZAHm+7LRs0FTezt+aq43OcJL/QVH+18tO
/SF+r1osTdojTeRFG++63zJVMTMu0aLnXxbmXU9dLN9ZsXF4lx/QfB/oN3RMIeJro24+ii7i3Bz7
oa70sff1Y9GIbldeSFWHUbnwYMfzRjw2noJ2FN+54DzeinrgTn+UBM4rjpnhKFwYr26Q0FAJZthk
MDeVxIo4z5Y/1g/u99XWLYOHFVkU1adZm6fJqx7h8svgI09zTD8pw/YwVKzlr5qLFSwOETAOx/QT
pyJc49KllndTlbKSLAr+lNUpPtQwR3SZHNS/W3uob2s8Hz4TToT9BPUANI7qBwdXT/NvrnmJwcn0
jIjXjaJTWN8zVer2iU7TLYYcgL8iRzPtjiivqghR0CNWC75cUvAgXMyroI1w4jmjT35WIhXgFNGG
E9wGz8GDPSsUaKDXxujZfcXqSrYoNX0eLvYE3jm7GmdJ91uxDcmCiRPUa+ZSfEdRbHcuBWwaUl+F
Mg/x62sXFthnrbBZ9CKX3uINPupsjWkE7RbOG/YuxqSvDx2IgPBYj4hwZ7AmjvlO0gvhXVSSabmG
/5YwzDKBl3cAIma828thlbCYOlaWktH/A5aMiBt/l8wli43EaWcqHdTYCXXquFtDvJs1nUNAigvG
y3I5oXrFvYS363AsYAKUcyBLsqAcVJOKdBKHusRPEev8hEZ2YjtuAkozteC6c9S5LO1+XajWdDa3
DnfJft49VlxyyJrS6nnhl+jNPumTGwZ34BhR8EHh/KIOC7xMPukXBomxJPhJllCA+tuMGt0eapjH
xLLGhamshbVx3O0NM8223ZbQW/gdukhjB1xxqjLOLMBi7Fl8jFZvP7SRR3zjq5DmaQU5ObEwcbaR
5V8/lck3tNaDrgYCrltfuZ8+pujOa3x/kYIvZmbMpZTNvoEpwQ+eUHP9mwx3gLNyIlV0HInxBul4
khKA0968fQJvdS3d9BJ73BGzdjyutzMhzeSiXwDiJNXvk0EKbV2Tu4J6igT07SZ9+/P3sC6BD0PC
ExQOYb7Uzd/K9xZ+f8rEkx5yVia4USzy5ycWBbh2/+ADlt7Ot15xLp6V4cyi94YFM3vU1iSKKnZM
ZQSfYouM6trmwc8Hrn61RlfwqeUmuDtPVae8NS9NBaVB83e9ehXEkyF1S9IJ+wjoaR1SLJ6PFYOK
hID7ipUn1lvO+mPC6liJWBNEWJ8SrnSCkfZ1bID4CSo4PeMI5oT9xdPMrr3u3e8K7JN3My3ufy62
xGE1wyqAnHeNK2tkfsccoGIRplaOHqyBu8GOsglMB1UIZhMnfPMkcZ7lN9X/wZjuri+Zi5eBUolU
Zx26bntnyDvSBFCIV6tfSXQ38DPUclGufQl1cEQKlPvu10kY6ksbKTTI3yxg6F6QKUeiZi9uTFHB
Erarscwt2CWTuWfBzn9BN1kMY4pA1/D9lGjhVUr+eXIUMRQ70AABfFDlkBOtPC3RZVhxpRC0TOs1
LyNdMBZWAdU1xGomAipQb9ei9Rf3a3YBtH9ibLrIv2F+iPaedc2nX1Mi6q/u2zx6EByog9Z68lOT
4xtVMGgPHkbzNiIZA+7TCCoS2LbO7I4CkSNQZSqmyb6GpHzHHsfMPOqGfshUns4wJL6FflMdVmAK
yiJUIjcSLpXE6e1k9sQyNZ7P7X0AzIqvJcJR0jdJbZjpmmGjiXTRSY9I7Znmh3N324bahvbiQKc1
OpagysgfcLehEnjf/BURQcwcrY6W5RnPFUs+f7FJ21VPv87DdMomKritoVXMFDCzu3m+p9Ekje1x
nSho4wpx6IomUY9Mg8/6Y2BmGMF37fSbEFsEaJEhGgMYk5QAYk2vLWStEn21UsfzecXRtZLHfbDs
KsNE2hjN+ykxkMKMsYrRR6yMYKoJ8ZflR+zsDIw06A+XFprdoMKkxUg77oUvH2xNFYXTxAby+JG/
N2/Nwztc/5ciEU88PGVOSda9yXFfSShbjLDZY4AKWd64keEDuZx4J2tfJqeSkCPm4CExNPrSMpWt
loPXDMLzQOKQl1zO1BoFJQI0XfA4rkKYHi5YAHrBspnkSs37oJHZxxUc6bh2z15arxNcjf/dd6q5
D7I667l89E4kXll/lMNtwOFnE2074EPJ3gGXSWP8FN2rTJuf5CjjeU3gGPyYYPH60y8ci855lc3g
1+GGvj/17wSrLEPeRT5U487J2e6C878cCaLHMnEu0uN8JNwy7g8zmikjCcvNlhv5KBj0VndiUEX2
ZkJ7XkwKiXZ4oORCp6UoEvACiZwGk7XcXL6kbx8QTlCRBsM1FigoK/8V85traSxCOE0NvmtMxVQx
1fbwiem3a/FcRKRKp8FIV4GTk5jKao02tSfJRvB8SJQHlLMbBUWO73FEfd6CR/hubwzW1NPwvLPF
YmkMfl/F2nOQXvdxNEeT2T3UB6vqVmnjgg6djD3x69bwlmyuVy3w1a3W7RKE9mHHg8DPwk+EqHeV
i+D2umB4k3Q8yf91PdfBoKu76STXtIQyXDg+P6T/HYFg5V2XEl/i5rPYYaPpwj5L1uH11PYVwfWy
9xoy3Di+xCTWAkiQfDZYqsYoLu7CdGcWTKDjDHFV2X0IY73GttsN4wOToKsIVcYFlQ7RL5Ck82mn
Dm1kMOD3Ph3+Hx7hOLn3QWH+XUOklY840idopEI48n8gpiOf3NUUsGKG1ktjBquydlcNyP4EP+Gf
mytxnxPtGIlxivZF2xIX5gkPBYGvW51Q/bNv+HKzrJM/zDtNjNDo0g8jaoFyv8CGxiCtJxVuN8bC
xYHHwcXTOEVfmtpRA2OqM5UOw8Iy8nW5Mq/zEXQSV3xMwksrD6kBg3/pnEfJYbTd4/oviQenxSns
9cxjzGpXlS8dsnG+vN/4ArJtzYLXntF6kaDjvR0rVx+No3BnOFnt6u5jiR5NZSi5wjaFcMdA9MXs
EXavaaYT8l/jj9AqjC7eB8HpkGQZu+6e4c7wl773YVi5r73Pipr1KTdGBJyAWMvQ4PHvXxApdOdN
Py8SIeOVIM+NMfwfzicEMp+QERoxe4Jb6elqoXLq4JvxAswwti7q6uJu3nSuNZ+OancdOa7nyXKA
HDpdOwT0KlXrFf/n7YK/M6ZNefs8fNghlfUnsG3Wp5wQE/rDClbYw4urisVsFTaP+6uwNj9BCHlR
gmjjBIxdFo/UB9BXApx7VGr82ogVRwM7W3TBYz5g7rsUChsWq9KIn4KwabtKJDMK0I5im6UtEIDc
yAEDlcw4TC8OaPQZb6kbKrk6kD4KvXWVFKX6cIX9PzHOS2MzwxIhMWQVBaE0YWDS5JftlUONCsKG
6Em/cxZI0aD7OcRzPt9WKvHefjkpgaMdwQloqxawMExY5znBhVuNeAWei+aAnLcO2NFgctSkVFut
WUyCoPoKeQrtGK9DGDZ3GFbzdFuAbSA5Sk3YnO+oUNMDa1agZj/SuSv8j2nFdKRZ2MDcf04OHwif
yJx9JUSIj99V941g5yr/GRaMndb/IcdwwTm5ZklBmp6jV1I1+2NGuo+GmxD3DCNQ8eWqnqyIuxM7
+BtF1xXFhutx8+Efa24+PXkthuuq5miN44ydgFZr8hIknTckw5O3x/NQFlt+CNglkOh3C1PCA+T6
t5to79IjG5681zwArw5y0xHEbB0FvXyAnG12B4Tk6YXCA6Uw8I71M+LXXX5zriXi92AcFebP7Q18
YqqtJhhIudlQiApJTJZKkhLrgazNKaGMJS07u/QnF59N0wQAD+wOPG/dFa1zDYKAgU+p/bf+U1y8
xw1GKn+JXOdmBH15ORzeB3cYmGYZakLrCoiTfRut7LeaopJKjXks0mLkpo6fzySDBByxOIoQD9G3
EE4sPWKJArkUeTO2F6SrZdIGkYBQFdA0TOIkK4+fm9RRcouENqmF0c0Fgj8lGb0rubeM+rpT7uGX
PrL9sEAsViz+iLN5O4SvpjpqsJdCF3R2V/G4iH+rqATwf4ZxKKixo0n9C2+quVkmCnjyDGTA+PRo
y7V04wlh+8ZCv0xLQxTuUvPDtFzE+MZUw+PcGHb9CovYPZeQu3IXcnZRDMdfy16xp5XsZIFrc9Ku
+wHNXp7UGdJq0w3WRkYl6QSKBD20Irys2We7nUi7Q1nXPvvnSR45NVSTNx8CeWrS0l+3IaqOcIQb
I+NLMdWus72JOjoUVfw38g/cceEVzh+t8Jixd8V0u8CB1Ezmthv8y4BAM32DsCtnLJAD5GwgLOnZ
L5rGgzwbhf1IokgzQ967TvyKZIuZWvB01xpW6j3Sl4hdwCEGAR1eoHBoTmrmayxUsq6jUQvhPuZe
Kt/Ys0xe0nEHWkyMmkdbPJhfVha33bz2W1KC95F3yS1hgBl9T0UNurSA3I4pBtYmF0zK4i1HTmws
XC63Ag7AbcKruUGZet+4gmVryv0xL48fTwb40y+qRAX4VUb2q2HUupg3a3DtHeb/TMtyffqn2rV3
/BJig3eeGyUu3MKH8ds56edhYya8Ph2QZVgXq0E6I+AR1GxJYfu3IcgPh5fDFDVkskSvB07pNBNK
YNZBp4FW4lFg6IL6mPax1YCYa7l300RrMPrly0xeWOCkd1zPfwd31eR3NSD6V6ZLe1kxoiolr/5z
hBfKX3PS7qXmfH0trK+m2JGXSYT1Mzq+e3GA25FWT2GZfMisuMMMUXHIG5MHq7Ziz459bXW5kSqK
jFhPjVbRs3zy6XMYxLx0bnfopYAj468x2Vi7QOtVdLGIUoJ73jiD1ABiHato2Z1to7b8+tsBER79
H0P4J7VFj5AvjnkZ6SMioUhQO6wvddEPjiKd/h6/u5WS1JZZ8lpjmABhQWldP/ngquOG1yeUmAN9
h4zNEydc5MHCL8RmnIbZrnIq5nshieU2wM71mGpo7Vpi3CSlWEQouDQ/r5o/dhCTasI5drV41mNd
NrlRslP/YXmU9c20fIKXEIq52Kws9MV8+SFZyswWXJSZoQ2z+wCdjU7H6ZoU783yvE0BaNwvEQ1z
BhSynxQ68bCzLPe/fZa9/+Df/8kaeJsyoQYRzY/jdmiJWas1EmHQctpImgM6Ra5cAGLwepAYl/+H
1nNWGOPlyRnI7qkA4gCG+5s8BItRZIGeDD1ObuZAMFBS4LHbCvvW8NngiaJ1o5+7zKRq9kXDblEu
22lzFu/4TuItOdxlLh4kQ+dd+xki49B8XcFMVpzaLhzRrE2DIrBMhlA6bySuPCXsot9uaag9l8ih
B6i6kCOi6vAUJC21+ta630PeGA4V4PgbxvgOf+aC7T2BIcCRX4E9LURXGv27i4dve0GuliR4dIRH
Znwaq5OG1SSrGP7WGWgKLJgUgOyEpDnTMZIFT6baXwmInQv05xTYz9yg6F/NIrsZEzLtt05WFdd9
m9MC9huIBSQ9PVcC0lxsVC+3TiTql9CCC5pRaKXSV1kCiEgLJIad6SEPXPFeYO2/K13ZVbTf4Wb5
GGTWIdF8nnAuvRfBzLBg5d+ZxV+aaPhcFZe3IDjUsoYXVeqrzxhTb/8EXDsVk2UFTmrk+WAla7rG
0AtYJ0CcVl2Bg2h/UBaPJu4+G0cLcpLJ7nYZ4H7doy4En0NRshSrj8WAM5ZRiMyjXi4aYZCuEDc+
i3s3l3LkuAnIzmSK5Gaw65xYoW/imFBLdQs35swQ3Cfjior4IFBujL+9LIjq8YprLispFu1cgcC+
H0mjNcnkB3chVT9fpI/8LaZfSUk8xSnmor7SPfiY1i123idJuqrJkthyndUvCGMCRX+BN8Pdx7d6
lmXdCBmHDYXwvC3JLosVfQ9i4Ih/jc01Dau+hraAuAUiL/UHgKjBZkGqikLJJN9N7deYFyB2a4T2
gnXE0cvRByfQmavh5tF1HJtLVFTUGx6UqF8Rbn4oq3P8CqoigCskUdg1wNX0iRXdNx2X/6BTUN1r
meFWiuBmM5fnJwVr7JJOI3wqSl2bJDm83QLehVgC264Yrf+8d7Xfn5dEX6fRlbA2YIe5lVxUGvxn
VAKajliuW0ca3apdHxAVLFjHtlq43inBomTcs8FtuQb6f6wCdyTm4fPvW+w4GzgkJfNqmVo7BqDr
nBxCOfsrbfkhyGaQuRoQ6HvF7fkVmdBSY6S4/CRSmGsbdvTxOoDmG/hOYKGYujViKrIrLT2iwWpJ
Dlx9/8AtbUUnKZdHR90Tt5cWND1+8rAcEq51Qn4WS4IWt89ogZqDeBS8NjxVfe3+d4RSKqH0m8G9
avh0qURudWBAPSGGVVpJ5jgKg6cqE7SXmFCnvrOR6NhV3MmJdKlHQi0R6ie6AtNenrDY1zQv4lcJ
1vi5FeRMztbsd+GhhlNk9lwNKcQLX9fl1MDc6b5pqRcgt1GXcGc9DgOqozC3KoUMkig/fLbuOcj0
xxJMkhklQ0c1LZ2oIHL7SLqA0aKRlgdVynMlWDeLryiIrTr+tejJ/OjFuCovzz//rHdZAQgPo7cX
scja/7x+BOFvmPyF0FaBfZh9eFFxMv1mL4UI1GwWpEzmBAXKe7jAivNb2XcVSPARwffB+w58oCrK
Bg/1xUujcaMvgzQBd1ur/FeVPF3wL7fMKEAzG8nF71c/BMIK/pLYbNIwRAPUssAxuUNV+8BaN6rm
CZGNZV26GDAlmGHZ3AGEJbfPsPHBl/Z+8DFbuCm9fmZat5gHOdZybQOvUWxY0r9CsLyh+LRyJ82d
MGmsXNWgR3yPeOy8b+S5pmTA5Y9P+NkBv08jrBz/GudYfBolxS5DRNoPNZf4Hs1es9SAQNNfgEks
Xp6vYp4AUR9cDHlIdVZgxxJ2ZHJ7rrMhh2WoS5fmFF4r9klavWTIxUiH2cUc7mCfSCIc+Ilr6O+P
hLcf8ghZoIOyduX+XpxSuK1oYFP9jh0m10wmd3mopQ7SxC4dvP+9hf604xo0BufMtkNX7VWCXTe3
WSositmUM8fuoGNDOjasxyHKzKV5QXFJ6qQEqZXAS9oMtGW/XYrZE/GHFbxMR+bhIgXzSnLTUQ/y
voBWSbDoEmBogNM3rTwEnvXeNITVGFI/RHeVTmonLoMOIuuRLrG8KdDPciFKErTivPHqqOArCOim
Knbq5qlksOVqV9GYlWzEk+NhsmOs/Csv4kG5z7X5nA1fmlxawu0RhgZYrDJx1IX/OWeN4LEup34i
rPhEXpt5c/ILtFHk8NlpYKHlNRvb7ehcmnoXMXMRROBYqNvda4Wbjnd03ks1/+ahqE+BE7PicyBM
i07HN+5Rs0Yd1xsQEEUgl5YLS1oq0OCcOsrbisuDP7Cx9Z3UOPXe9m1zmkCrf8RYTwMyiTkkrm+k
Up/z/4zhWIzuYbNTEIXbenGEAtk0IxABialN+wWj3GVp37zc9jkvfyayKyI1k/3dqpYmEcTfujXw
mfY0EjNq/+qK5YFUcQ4PE+9ioxspIoo/NCPjlh91Nd5w7Al9xNr6bhLS+RqgIhzI0sbLINYkXdcQ
WYYB66oa32KAk8DW1DBzO5ii47rbELPLRC1czyXmhMRGV7c4m/I3HKBZFScWmPM0Ln65xBckq+P3
vP2Keyscvv0eEY4J2iIMxKA2HOZQu/xRYrMOBTAZE6TtPwG2g3bCJ+DEnQRYihCEFOJeVpbOm16J
slQT4pM7F9e9mNxn4zxqScgylaqr2HL671XwXxLMAM2zK8YXoEX7kclqKTe0JNp3ZKNi04p1VcM+
VzAE0qxFY1cm7ILxLsiydbgPbWk+sERqCdX1/Oem/G/YHpaGUQO0n1YRIxv7y/mM3s/zwvyFBdUm
9UKIZDewrifJipJ7wbbBDUG1RPNSQpAyrVBb6oXpyzkBse4wQ4/LkZcJ7y+YHm/lXi4FDaPlNuvg
tDmoYky/kDswI0ua5hHxo+ROvWxl6wDi25SBrSfdUk1mZSAO9EJz6jOCfPYQCMkjy45P8PSyifB9
l87grQZApEm7qMdFPMq08/trVIgpHmqdG0pr8rjRR+orxmUL6CxOWGDHVp7cKJnq/MuUktnerpYa
zsLj3AL9N97pfRWU0xZ9LiX8tTZ621fU7jrlPCbiORFoxx3BgC6KYdVznrpUel7Vyi+k+co3gBII
j3aJLvzRThcnH7QhcttjOSGf7TwGXkt8HRaKWENHs4AdF5azgMa/OLi5I45uAfpdkLqrwvP7FeI6
ZXHgOLvQjOsvVn+NPyFagzf6hMcel9JBH/D/sBKtVmMTcxeiQ6K0Y7yCPwcODVfgzdwGZfAI7xcp
NITE1EG8T/3Xg89Y3RBuxh23A41aQySOeJyDEAHAvnqiPkTJM+dyaj7UMHjRggNP6Vwcvu0yUrSD
D6ll3c9gq/yZ+RnDNKTgwB5YRFIbggBz/4b8MbmbsF4vQRwRNLTAaKEoyLEJeGhFAUaym/ddRnKB
yfLy69UaiUlV4NdcWPg0nYWNxUPQ4+ctvHFpe2dNfHcoo4kKVkrNWGt7FY7AnzWSujP0tvWhXhaM
oh1QCTEMf+FbxgQUBpbhWJMeFjp6Pr2wynH5S7zz2hj9ohv8lJ3YnDlDnPavDkakijXP67aayWxn
JYL181lvKvniCLiyoVQB5+0Griad3HDBkFYdcS4wjXReRPMzTNcHeFLnlzFuUHHMeytEBlIcdTgr
udFoF1oLcdSqg6aoT3HpqHFSfftzw45IqniPqvsRxcKO9VTWh2FgKyd5C0Sa66yENGjwoyezoABh
AhHSJkPMJyI/3EQbqa6EIzKFlTNU71DEIcyVm8qLGsMK8NPmu5P9dOPMNhPHV/L6f3WOpMB7VpuE
fZW3bYw1yOwm56lEi2FovfQOe6shLvdkvVV0LDiBrSLsBFz01x38EfUdUALXUu3H4VRmLnn7MgRP
JC9sjNWdC5LYO7D452h8DGMT9FRSGlH85P978h9GHwjMYO8XiMpVhG5wTzVEDe27Y3panEl9KSCz
/PAm5UjtGi3ywc2cH1BtjsL5G/s2C8+e/hwJrMqYTtDT7XShZWTXIf2Kqu5zULPqeEU6E593VIMG
EQtdrUJr32kM5oAvReVI3wImvMBI/rtIbXd/PIuW/kqHENs0SbAP4M9H/VjcxBcabLPVyUO6PxLU
6JA/PvVYrnCz+RDo6J9YWDc2e8X8K8+Qae4TVvAMH+DHy5qiTnman6fj/RQV/oLgcqcAmSQQxDVK
w066mPxn8Dco4oKRcMJWs1j6XK7EpJdGaWALq4rBNiq+NG7AxpzUxErzsSNc4I4m4ZChEg+iVIrG
La56KLJZ6/8lfd5gY6+G6qkdPNsUMWO4vav1i9ag1pdI7xCX/rBpEx7Z38JnCnnCRuuFniWh+0yu
YlNnOksvVIcTFQx90jSwEhP+YJSgZjIIrU3R6XdraM+l0Qr2KBSQLCGEvs0wSZp8OEUvbOxbyo+P
nZ7k/re43J5N/qn/GCEZq1JR2ENAE1n5H2qdtHDup3wm6eb7tITwWFQbPrAmwSGRF8va6OKPCVtR
VyOD4CqlencORWeD9QGrWiQEOePbC2yZDuSN/szsF1UxKEiAD7L7ifGFO/lvlNnXqHSTmR8Z+1+R
ZxUE506sFmMnnvTGN8NDESkTaI+h8oboZ9bO5i3hbrZT6+i9enO1Vbgv0BdZ3TrpUVlVaYbbHuuM
K5XXEZzyo7AYrxtBiKhRVBACj8Qlpo8QAFqF9cXWhlDpZgMlB2QNGIZR3AE+DvBYF3Ddb9QifnBk
NodbHQv+y0Wfbdiz+UQkdYr7glQAf3+R7GfUlnuHFfmrYiusjPjHV29pFycByyGRHfDx0ncuyGYL
W6wrlUSjNPeAJuMFRkqD5JU6udeqgDXjp4QJTEf/azTcoswhlhwilezhCltyfImyEqu66uT7HNjl
Fh+D6yWISEcRZatnBfGQ4Oa9+Is9rUvMJlXmCgE5WGWN+QBgzWHmsml1QTHuyHFZPtcVvOyUjp4f
aZtP2W5jI+RBE2IJNNTqDK1I1s6EWCzxwY9zqOozHrqK6GFasIHd7BZ12nkNBFJHtNJKCIziSlnX
94wdiXinJTx22VOMT24vg9wa5RTDE1KEergxOlBVeexBHUBOuwhZiJ5mJNZNv5+CDQbtVMHT2eU2
yEb1I02GVBeGWcCVe70WVVag0OriQjdMQ1PU1JksEmhlpr/IPU9R9pgxZwnHhSxyGjUhzi8OhbaR
NkbXEf7dL7aWBbwCPEqp9tY182P9NktS73S8iWb3TjOwJbTBGio/qYCF9hx+0dFlAIZ7WdeRkJ0h
RddKyuC17GnR+nsmQ0u4WLIOxpNNtEHwC9LuHmFdIkx61TU1+dJBDEhSTJL8q6rO57QIyBNR+mR8
3OGzzhA0fHEhyRESof6kKJ1Yv4Wx1uUcE6kUW/RW1igEbEOD8KZO3+cT3jURspoi4M/KPFkW8gOH
S/3h7ZRulqTCQLljS6kXQNlFiOj3aFVC4HVWiK1uVdt1SapBpzYxclHy0BkV0IzfdM8SleBNDM/F
2nzxOhdC9mwr9QyKDGRfaS/Z/umejoprjfY=
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBSCFIFO80x64WC/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 61 | 90319 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bNIbShH2EA0CHyFd3tcKzqAAHVrbIPwWhMG9NsC+dQUSMA6xt4c379IBpTIXbcWcRu47Z+xjBDyZ
pmPIKJwXiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aHvYZyL6jZFeED4yBNrYXGt5D78L6XKvfv3d1wuLye6gycFxQz5GvWsSx0S6xMB9xfjAd58Otvbz
klFCQAqOIJ1v9j3fyjGrdYiRUTQuApDhC+FsIz/c7IXqHLMU7bYHwJKasO9SrDTWvXQ7ih9U0p2k
1AKMnh+qiHrYpQorG5A=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RiEdSHs/Bt5umPP6K79selbyluJtARUHU0yj5nYfHoqZIAm8WpvDCQm54C/KO7nPLeyv8jHIHHlo
ALGpGGe0PjfMvHDpFSP2vV238cyunFX8V0T9k8bl6wjYh6At9VhihdwfU2o+IX5VBj8SP9UjNVm7
vVF4zMGwAkPIQLbID37yUDY79ZMmCkWbDezMLjj3KJUww291O1rtjgyC9U405d49Oz2JWy3P7QMn
8qdrMZbOorlxSjkf+hkEIpgWhS+pbRjZ8wYGv6o7pRDkDsG3+S5QG9lWf289rXA2RQvNu+gKmbHa
+29rBsgGnvv//KXcwxU1LPRwDeg4UvorpCIeXA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1kXEElfRhCg/jAKI1qgX87/xWqRpS0e1DlrBHXO8aH5H5hRB8yNxfJpWnAEYapsnx3bdBnU1AAyT
aS1HwJVWR+nZKer5YXEg9XX/LwYQGdvNDMOsfvUNry+U7z6Kbe/UEvv6lt1y8KsQyYySOWeC/GkY
gvuKcUlrP9I2nyTJMAM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mYglWFHrB9KUMFOAglZNRnS7Lnvi5gZL2XwL13GIjD89oHQqVk29jGx2KCeeLHh/cuuqyyaX8cnu
wVXmf6095a3qNER/BkizDns2ON7gXlfqDwAiwRQlnbHJVhuv339KnW9GIEeggUZhg16lG/xuic29
kcyTsJU92tL+0bqVkxdCDfWly3o+vB011FmTnOJvdxGOerq/smn5f+CNTSqTx6aWySd4focWp3FP
1IRx8Cjqp34czZQNDbnzZ90IVxyJuFmmDpW8roK21NFNjW7dbg4hrFdS8qcX75ES6c0+1Ad9MDUf
dJImpXUL0bDTxErqK6kqA1RFpvNA/Wd7osKy7g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65120)
`protect data_block
UZbNrxS4mSBhmAa3/X3oJLd1xGA21L5S7fYTS3C4Pl00SQLq0khiWZDE/rMLjNoEn/Q9gqXAkf5r
dS0XkN7psKi4vAgvXgDb6jUyeJQcZaaPu6bEMK2QiZKC2z7AfnWk7MweZnbr+H7GReUnwdm2DK51
MDcXAb9rAcRjGckM+m4YyD4npVSOWgiFba/ZCF/kZcw7zFb9ijQ+VQdl8daOjRzJKdrHK1D2eNf9
0PnNyiU1FyuhGX1RchUAy3ee7ah9wpq2y/z2eKsBDjl6E9tYZixrW46WC7vks9Zm75taH1XlwaMO
CKYBXLPHXoS25FIiforI3jJ4ChKnNpdDRHq7DJkvcgDCtf128Z+0cYoEj4i0Uiqk+PHV2jMY56CZ
jLzIOGBg2v1Cb0GlAZ5JpxHOs+tDnmbC1dfN9ZQxWmmt6lYd38K7ObLvOLlb+SZfrv/mvMLFMOZh
LCWQNCb3wXzbOHvo282/PfA3FRKlCCkMgrpTDuUOJC5r0wN78UqM0P7h8qdPaYt4Gft92w6HbWfl
8SWFMZUVrsEluKz7uqIwA5Y1MBFonm9lvHoe9slSuI19S3eThAFja8oX2KVPB0r5a1M1ERQDMyUO
YxKUgM4reBTzabbXjxvtUmnQSZjA+vsOj+knTLArWKOR6keaTAnQzjX6p+A5kfObnm9bFjPhmXDJ
iWX09FLa/hRH+lEPGs4TRAJvnoQoxgOmk7Cbi8o8sIQ5tRbeQPPW67NP10qeReefMGC1xARho2V8
JKgB5ykmD73sQobWmfG9ATGJLk724K2u6RKyzXvaJRSWh5GLMDLLWFm4yoUo23sQjxmOc1YWy42G
xN5jtvItXgIDYyQHCFHsmt8Cf7InFR4/ipGwwhI0yIewnOpTdUHhU63Su/X16kcX2kdjZa+0ipef
PQJh5HcnenyIgnD/QV0j3cTwiDlMLz0FMnmztT/kIgCpoAtAWGkskdopjV8bSN4XD5FVdayIcfNa
s9Z5730GrRHDCsA0SqbY0AtL6TwO91nARi8dxhEbBBIEUUALlWfUovxkAWJE5Yctz+WCJlP6jkqW
rFvUOzzXdgfJN3JdbNxXxUXXT9YlY8/N4CmgcX2gMkhHD4OpWQ6TBbN52XaOVlg7V9fvu4w55FHi
m/cVGzCN1EPT+61xCn31LxgxoE2JVJAJ544iwW2NvF4B7qV0StyyPNf9xmQcf1DSaaCWIpUOEkaZ
UwfZ+UHM97i/RqQcfgYIzcPonzsncl9Hdh8RvrLNatNqz7PRxkJ2t6i0vt5Jw4FxE1LIjqJp37lX
E63m97NCllBg+LCSOiYUBCGEBgl08bv/00dWT4zCB8rv4R04hAGUy4Ir7UHfQgXqfyoW8Cjwz0jL
jqrKh9LKITt02SWJUlRYpEfE0L1kjf8ZllJGoHVtiQRrbgFrl4myYmb76Sol+0Sn0jLWi0C3Wai4
LoKxAvicVXyC7SdwKOY7Hq7XdzuCeV9YfueO1D5IcvfRxQwYBmTXrdE/1TL7vY2Ria00EBfrJT6o
QabZw4upbGGuBE/ofODUWCT+iUy4nH7ohJgWtQ3nXbcMxGd/x0azGmLwNOs1Rd/aDxDJ6qgflrMv
m9xUJmNjQlJt5+gaoJZq+8zXK2l8AAMT9/5HBPNJiYIsAIWteyv91YzOtXO5Ni4sv4W8FSAo5V02
VUWp6ZGYEWnqDHLbygEZj24es+kY726v7PZwffJ5tHxDnrqYIjCFRipPQVvw3juT8Us8WzRsVXhx
aYa7iz+vGaDoVySo1M7nUbExvslkbSmJBH56nAxtjX+nv79/w/aB/o9xFBPGeYGXQnbbuZs/w82x
/HJYz1chqR1opC36GbHHxnDBGdXUeE0/eL5Qe0jLERRMuXleX18gIOhvIZdQPe255isxx0HydhAq
WPsH9IFZ5/GRmyUYYpLPaRrKvoItNs1j+5JHqKbhk912CuCFKAPo3V8vMsca1necdW4sJrejr5d8
sIyNo1v9Fy+ytjx2mlt7/I5u0nuV17+retHsEELPd8xps6xXcT4kGXIs3oqMu2QPtfb9FcHzSxba
+i0/Ii6oI0e3iJKrj5nGDdDw36xDPiudwP6tgaexhfzcsz/CoO+Zb6a9XEdFUFJFZPHx975wfOj6
/XULNYhnno8vXhao6J+HcywhnsvXbdO9qLur8ljzAjALm2zSqr1jokwJqGlYM9N6bMDFQepDXUFx
GUaE2G/Kxn84JlxJgLzMYSl/2gNomUVjvGOVdLLqIaYrS9Gc63Avw/cG0Hu1AAI2RyPhWheLaTAm
Vns+bdl8N3uhotXMGr3UpAwepwqlzuHh5syyEKYXL+JAs6TlkWer8oGJsKdRuSmrsUQYOZ0btvvt
hDQTSy85DsP+0BP32TseifmlDIiDv+CjMJt+k/vSmyU2FAkOH72wVG0qBzRKbUC6IPlYrnaYJLsS
Y9jLu4+OSZI1FQHnHStL994BMlgrvvUpQSU7YqWXVRmsuBc9dEP+3D/eMWqJ5vXxAHThoU/1AJ7e
SRBzpf7g7uT/VwwWIadimOrsdJvZ5A3yH8xbMDjo771psFV3xH/vs/6eeZIpaVOl+UoY6nCiJgRG
npoSYiVxXG6RkPdI0s8pvfNBFLvNQus/Aisf5w7Px3pV2RCEFjcUhqdjgyRwFOOwhkhf2/sd2osj
6s+gogUydB6QITrIe104Jo3cqzc/nI4/fowat9+lLRbrTjcoJtxqUTBYpDFuh3v4ipP41DneFEJt
DyqdPG5mx7GuuXk4bjGwn8n6cy+K/kfYun1U/eZ+HPU09iVCQv5EAk8yjOlvvTDcH6QmVRM6NsZI
PleWfMb5hg4AD8KqBd25vxamesKjqtZKR7H/we25CX1/+a838gzulGPzqb7U4rpL5DVTxac69aEm
gmvGHdWHieSsgoAKMmvtvNx/RHjpxlM2x1JOEAkdOdeZu4TDKAp/N/LMaqk5uXMU10fv3SFnvIUC
+MxlAF4s1uF4w/rkBP50WNAbhKsnJhosP4leXbSocFfjSVBUulaAaD0dIrsoUZ9IpjZYbxUxYpZk
p+m9P21xIdRTGLZ29Yifp65VcNOjA7uszdrrs6N+1QKJV+7frqHcdE/d/tyBrdy4EQyRdDQqnW5o
WhxtFb5DX4pS6YQJ1qO61KXA66W9h4jbhAKqGKgOEwjQKAD9G6LEAYPF/wWdp2mob/G/hfnem3Dr
boGSAzj3DACHF1cWhkgQXdbiFxuS6USN5amcsjZ0W/pEduCBDjoKumcNGfl86FqbRr4NVYvJWmyE
xydb48w5sBxM3CwlI4vgJMxBXwAp87YoHNkAtLdMOUcd3BCCVUqUDF3xGKovIlkbf8bwKCKNXvKM
6iy576fCjZTe32MCGigVBxJTTnVY0LmvtYicYG83a+8XmYkKAIsBniCTEsbKBnG1wsdEBLBgX+QL
U1IWID/4tqeshDpcdfA8dDz7BelrtuQTOrU1nQgoRabFRTlF+q+jof4TZd2TK1o2iOAYCjmy6Cp5
q0FmFNlJaiJmgxxn3+g/+sl1Pd9zEWlqulbTZFb+YQ+UcHkvpVDAgZSgEXhMriD9x4xF3+F9RHC2
ztaWGpSpLaJkFT9DAGLv89suWCU+7m3XZLT73HVbmVdRJ9+8GE495u6aralHA3UHw8xsRIAm0STC
46HUHc2zpSgWCw7VbfUJUdqyj277rEn5aatMXNTDiotCNEL7J7RU4lGUVE38xk3BroOUVdASwUts
Dub7eGlXF5BfXHgXn0Fml/d5uCpqstDBMhulEa1s4ak/btXL4YyYlD6zu/QVoNsYdzDuwHp2/Oet
PPP5wyb7BY+YFkbLoLKMv92SPY7QAlkbC2yxqyqRJuzyhF15VDq6lknh6blwHPx1AzTfHisXe2n9
BML847+c0MkZwBPnqDTQuEXUvYmJcA0kSEDtuUXTH+aFICXnsOMis+Jy85iFc/MXYn5aKl25B7P1
+PdBZYngWUQlG+M4CVlNEsy2/nJ/F6QZdU6vWv+qDKowCG+n2Hrf2BJXFQiky6uoKO2fzGYpP4/v
Y2Lw7jenBzZu8G+8s6lPgVnLMJimQSILbTAbOBTzGqYthkso+zXwakQUm7V6tiCeujAatEucxj5X
V1tXxSJyK4G/+tH/R5eU5bt05FaEJUut+8HuQFxi7Iz25YO9qKu5GwG3A2JV4lWB3tqEvbJABNK4
QRqTHOP6IY92Ry5KR5mJb7NpJfVURUM4R7yVG6aD5DM7IOiPY2805lelOkJQahAXz+g03ROvEj7y
vRHj+dHBQLVGvNvl1jfKNGCUWn3ahrxI7A2eGU0vUVAhs4nSfgG1QjC2YMqEVG/xn709uoaqiN5p
Lde2mKjMevATOn/t3UMXfOl2yCR86PWVSfaqrhiTKTt4sjAYRbx1siAApqDDoOjwNulB+S+2q7Tp
HJydgu3j9O6ib2GBO2eAMWef3H0ZWyIGZSqBaOWKbtklDAiL5S7rgafCsOzyZqtIbh6KGZYmx3oo
SmUuVmQetapF88SP/tfbL7hC4HkbWJbZ8Hp55H+EVmpiugvkaD69Lbzv2nC5bS/OgXZwQhmQ5hNU
IvENlcBCa7geKJFb425glhBfBSGMOK3om8tPyiXWgEQ+As125H7eFgEJ+hhQOGE4p9xtX2LZlbFI
2M5hht49GC7YwHbrnJMPznwVKOPlQ/KsfqBuSa3M7tlxeSGyko+jk/5YvDbhG+wQvCYjGoGiM2CB
fajXv4ZrfoPeu9/V6gX91v0Ewqsbhu3LvCoVZ509iYfn2g88CIE/zzDO7vSwqZ45nQebSn/fqTrj
BA7YW267ZwVJF8oor9sPAEVPx2H1R5PzDsK0CUeoTRDRZlUsjAI+zwLzpj3ZmO769fL+5bYUWWSy
tmvN/btFTV2LCxc13WSTJzE9sbzO7tKZbsaN5LwDtc7OBLK6rPL+jttKGzeQ4Qqd18xwh2Pwp31z
7zOVyPpTNAc3D7p+sc44vLKLfznV1/n8h9EEY8FSq2caFFdilsx97NjgiUg79nwtQoIO+cKI/YYv
/TFOfkySNpeBRj/wv7BES3Uetjr1tJhl3A3ZkE675+PNgGEVV7vfHbWK5Sx0NCAy5uiqUpfsWAp7
a7xeRYJ/ZKkgdL2ZG42He0y+HZ4g5gZEdyb5OKerKByCh2LbeS7hzrfAERY6nuKygHtOzAFJVFyg
aKtSApm+ZuSJ4ASdd7VxcEkP9cvWMb+lQH0PpdTiQsBSwRnPXngzZcapZ+IeDMkw113YF0wMFDzK
Vt+x3extWVm5p5cmyBcRgtbYpsFiY7apjZjSgPGEciyF1wMNC/S+BB7ScFyHqvZQj4Iw/lyEKJE6
nzlzBb4wyIAqmz5UoX8lKk9BSLenOUrRR24F4JeGTjBPRw9h8eaoCB+abt7m8TQJIL9PKGtTSGYu
fTuRH7Ii4jqxVIZCdYzbzTkwsbD5FEz4dlRAfVnP8Mjsa1nvzhS0A2Y9xeBhHTm/EVXGt5mSAZ1v
HJs+5xtysvLLL0F/vfcWixXPhbgkoCRGHhdjJi54Blz2Hu8yAVzj986/KeyS2+VHqsSQZbbW5gds
n0adW+gJ00yIlKA5qseWI4H6bSNSILoDx8lgcpyhQjfhphOVe7LFlqUa7BuB5CxFJVjVeOCDv0xf
OsYO1DXb9rGJ8vO1MFCMhvpWUxKXeB2Z+Ti9P7qIVFYY3Dvzb/aJFmF3l2pm2sKcJo9OA076HY96
0D/OUyYxuorREJWJDxeYecBqFdszCm444cHaCpz0ctDfgK96D3BSSBkLGPmTAVSR6TGezmUBF2Nu
wYZwiBTQkAZ8ocsmyg8IuKyML/hbmgvVO9pANxCKU0JUYcwDv5pniaoqolmg42cM2sgYyBOXsLZR
yv60V6ucThqDOPe7wwfq5IMfNiaJeR4fhHdcO8P9AW4P8tzZPk6n+ZXN63vQgiYLeUP/Q3hCJjDN
N/hfPLtf44uL+yse4IxB5qdcCLnmpVEvSyjAHR2nU6JY4NwMoKpHXi3EG4TLR5y+hY0vqXOEKaD8
+fWIHUoQZ9dSpMOkcWoTVBqnSH+XIXoGkkqLwZ5P0X+sC1TZRFS7EPIHj9gDw5JgfPf7VVjcnNg+
bJRjMXKp0IrPfrjxi/gNAHT1eChjLxvXFq94QOmQGqoJM4415PDw63Sg8e3JjK2q5VbKREQTwJJP
S0ArGMgkL7+1mtC2i6LRE61rfRsNbfsMefi04m0Ngl9q5qsbBEaIgDFJf+Usu5VaOCn9dHU07CFN
Bf/MpBf5RPJVth0aLIRTTrzlyhtMrDrpzCpzKVxd85+vyhVXEVJCbOyXd7DCojgbSRZbQ7lho8y+
4gfOdXjvtFOh9tPsbqu0FPa4BYi62hjZRH2lj+MsHPJ9MuopstdikVUaNz4tHmiADX2MTdlZzG1j
ygGByxv6g82ugU5Lncor4W2u0U8dM34qRbRgSNppCiYAt2nwo4w22mSR8rLxo1vKSKArvwRni/bf
hYcpDmMxfuDCQ9iUhku/pKQS7GQxgb5BmGBJxsLOqn3OVN2sucpIQijd2Hw8IbFtKL0pFIWushji
4uGy4xGJVbDZ1bVxnXiRtp8JLTDSAQVfraIfiwOupbFyUcfdtdgIv/STLHHyeppgsQvdzY5B+vAH
rdfoNn/1wP4HxjjfF9V2kOkLdmei337qXahXZIQITExpCj/yhfmGKeRfYSbAdF2dpImmMm4a9ucK
3KoEVG0gmFClz0mZe+nper0zn/RY8+HoH4BmFZkNtMyoOwUmc+eGWhnay2KQdbMYC7ZVIMRkwv1L
dyobYj3RsC9KE8gK49K/XwDtQ6HCAz1AXzV5u62iLDSWznRAiAZgFqbGmByUKTd39xemCVHXyFv+
x+AEjeD+7jHYEn8C1IIldJ5HxDapb3f8xo8FHjfugNnZIeWW5OCnNlpj0GjrgDc1RiVWnPn11iq/
sgZg9jPi29ZSzmm9oI0gnMrpTZRuoEsg6QNFkU6boHnEcK4Ic6RcxQ8gc6taVW959XUzpX3CLiFP
dHaZ92Zk1H9d9oVd84oDJq2kCykaiJhZdBve9qA0M8ViZ+qCzwchvI6rNL9DQtQwokIxtNoEDWyy
tdJLWBXFRma4EXv8W/dIelkwwS57d1faEqJ2gxqQ6B8ZrtUAgdw5V58SZKRN5tqeRvK0GjfexLxU
wodaVKtC5NcXdYpa09HJB3uLd53aojfo7pDMcrYUVQ2Qm8KXQB/M/mRbP1JTUTlbor6h262q5rWp
pezDMR5riFeaf7n8jgONnzbT7d97NKJhi3djXOAwtAooo/kpJxl4gNhZgy17OWJ9j+I2HFDR/dUk
qah2loubyR5OfnmtAu9yA4GFNtUQph4Qg/rwfN+pi3HH/Ehr9V9F4zq3f6srXc9s9sOph851EOqh
q2mFrP7x16fXpjbHPklmTiugnmq45r02GK3GIuKLFFa2nSkjHYCCO/80gexGiioZWWKxS4lKYn2A
8jr49pOo+m1IrDyU8fdNZTAMLVfzGXRokuj1m2kOH0gV/14HVcBG4uCl9oq3RZ9eNQOIfhEmHH80
ZbR0Jhyqi2jlQMUhPGjVA6QLZpD3sG3zYKGpWmVxGxAeJi0vdJJofxzYNOQ5p2EDluUG/sklzxuo
YRauV8B1EUkEPfQhQ6C17zr8523KMuDNs13Kk4NVHZz0mEivfRBDvwElesF6g/hxHlc4tH/zBXoF
9lEw8ScEnMOiM/XbCVbjn0fnBvwF55LRE2Sr9WQHi+YRJRcBBRQE8mXSgpUU0454G91TPhsQ7WZZ
dKyOfRS1B9JVDMAQRTfx9eAbIP7yIGnXzmFEGGk7F+YWWV9chsFBAA8MNvzrMG40N1shPJk5WUb9
Illkg1a9sbLrHHB8ql0WePNb/bHw1yXQggBmuHCtgOhU2FRWOms1W1omAkXe2Abq+7GSh9VZGq+u
m+y35O2AssAaQoiviQyRN/CkBs1phtTja37sAFKp64FOlKI9aHvNlLjW3vul3iktNWmESt9Wd1+c
Al7wNbiczlTD7yqqKjJb0h00sjS90vbQGJnhE+K+LBKg//d6+Yf1b9rdbuG2HNHD/kvprl+ymywX
QCYOPK3+u00SolQIVCndmBO++CvbNn7arLyP1Piyte6qq22A3tio4pyWl4s6CVoW1mnay0p1qLHe
Sk4qvDYQnplJNWZfTSQsH87GN1XtXFbot0XqHSuFyjbwi2dzA4rrzVdu7vq9hSODnMLWkn++2Bhc
LsXCq5pYQh+fd1ShtgAf1rY7Jp3ZyouxUN96s6fsQZ7VIjEYSvkAgRAHtLS34eYzBTrzu17rtikJ
hUGqS9kS8fL4Sgj5Gu+xvNUuqCeF0ox/FvrPNoaQc3GP8sqPcnxRftYVHBSvlE+ph8F08qNy9USp
m1+G2pqXyTH0GGw+sFR+wIaz/WXqwphROhLuYXsKNaJmu5CjAl1NIGItFZ7sAM4iWupJnnaruVK5
xAw7k7mglVBa4ZXRmtm6T51VBmeGzQ0M8F8z9B1uWP8z/o8r5MMUlKSUsbHbOzO/PFtmVMRxJy4r
1Ngudi2v+ub3ILDqUwoMWRLRjkqGb+BmE6YuypKe0BJc8391MJP63QBeFJEQyA+iuVxOK1LW9Uow
fVxHb6UA0gxmgEx7Mt4x/BoGKo16utTd7v/EbEVycAkOWZcHKKhO9x8dMKODuH5oZrk8WFIBj0c/
h154CjgTvPobOtu0ILQVNHdeV8CWmzWZWxcc18YvshnjLu1v9MrIce78BblkWJO3DTnKDihVFhgI
AM9IeW8hqL11rYVHz1lJM739vF0nFnwTRo2HHJFu/6lVbfy6sLAmqOID/bl+OcbBzDO3UrPRoyGv
d38sczo8R6uJr8frv46Pg//kgIrEpn8Hc9f3zFqbiO7DitL+EHIii4auBg/pC8BPSunD6yNNu00u
0+A8eJDCRysalxz1EwQukaFfRFR44nZ7WW0v1wrGWnFl6W2spgkHngnAOmcHW7NG238tvyB9HW3k
043/8v+XIkD6z4CZJYrrhF5niwVf/HXL/eS3X+y+HGvzE/dhxnDBpF7x34hHILmW9/xz3kWVVQLD
yHouwsoaZWq8ahtulUrzTzkaxJBlVB62Fqs9hJXO6fk7Kq3k70vVMnpzRjBkW0saCEUjqV36GpVW
2iuEW5ud/9WGyYHFzSg2FYjADHokQjs4dLypj4KMQHPwpwdVzAMsWwqE8vytsUV/TIuGpLY+MIdZ
8uaxXge4ZJ+JXFQqeICq2Fhv7/Ihs6Q3P6UTlhnGHbxQlP0QzJUEo5TXlXa8ujalLLOoB68Y+J8i
/8TRyHda0SVHyHWFyp7maDi144yAjbS89xpSHuD9lNgLXMbe74AZ55wAgD/oCCNDF0SPBPky5qma
KqE8WCV6h2CkN+HrC6AgHF69mZ+qjmMRO5h2P6bjb+os8snBp393jiFuewhEbo/xsBYIhBFN3Tvm
M72P2LEVnMyguso5WnkEpfP1S11oZpSul4YdJs1QPNhmcr4jnpAN9bEjSldwL1FqgC7PYp9bDrbe
TJoHTKQ36ctwAR6SRjpoPxcmWrUMnoI0rcieNLKLN7vZajvi6SGODkBHBON1kTJ0el7zOYWztfdU
fgjatO6dE2od8CSLvBqR7dVVpGIiCBGw+g3MwAgyCB1QNvyoc2nNM8AcqTi0GCljfK8QvunGfiDi
JqI3uO2zNx+QZcCxXN1IO6bSUYI1c1TimmRPs2a65vELggupdWgeAheBPO0OatgA6vev2gWm/q2w
WhCQeHuNZrMDVdir2LckagkMvipS5drgPUQpfI3SJOgupgrdKCfaZSsoWKfe/cbNp9GXk6Hb7L9q
xkbsIrfdIef9k6Zl3+JRzdXyP5kjno37rXAKC4WZYI7ePFxPrSz7hL1b9+S8ua0kRjkpxrmV0dUe
LK0fizjuTqPl+gKW21aBBUbipvFCqUrqdmXkn9QoHHUsEgf9pDaL1IlTiacBX+Di9eP75WzctYLI
5HdKG7DxIevBFr7xlkRr55jk1zDUN6ht7wgs6RtxZjuUv8PpjtrCmcOO8D5OxDa2z5uPB713+wwR
0A9KGC1OvrDf7/+YLO7KR+OkR1LPlkCZJk6HWREIsCWGPiHCYxyDxvwkyFi1qP5kW3SFfpDLBTg/
LhuczbVPmDQjR7xD9JpSk4n2BqXuZ6t4JsuFBdZ+TnIzZwXpppqSAsLEpM4WTgwXkI5pKW4VW2+a
5vOIkuT0Fz8jIPeGBivWQYWTsro1Hj1+6RSZhlpHFMFfO7E61O/p+somAucX0HId7q1wlIPS0Eqh
+Rwu7xXBjHlDTJ7Xv78r3EAQwM9O5lACgFTqbvulO253T0WzZZLxPk/J2/5aN0wY1wtsVFeE53yK
ktnD9VHsLhnU8ZaXRFwOEELEWgFrtq3Asz65AjWNGCj52XPAk7hrHw+RCARvVVZ7QZGu7IxCjiWo
ev7CtHwE59aOQaqWD3Zi5IbOVL2wTWwWG3nYj7rgJFcBNSi4m3ItYrBKZ5pPwZBWPPWuhffsxkRS
LI3BghBde/Clan0gANntYwWk1XWGvdObj7kHutb8rcLOthMKCU6xU+ddlBor0XPB3D5SxG+M4hKY
AZy+7OZuUUKvk8iP4s/kG9/Pojhfro+zkGgzoxS0prXUEAgY9oO+jhpwbYYkU24gefSTNTkMbfx/
zlEOwwY+Na/JHaISwLE85B29SeIAakE58oEKZnNFgEytDIIQ/KUhjppa3IVR+vwwCrW1AyyCdeOW
gEL7sJfHSLwKCZUzMbSAo0IjRNC1ecDVo+JVA/kIiLzjAcgWamBvKQUd0qxyIi03lsPi8tmN65Vc
taZL/cGfrrYy0NauwnWhmcxRj+cfWnBKyLVz9njMM32vwnK8MAeo8Kg7KZ+bd6DocmCGDK4Bcrm/
i2k3CphYWrZnOXeeA42kQ5Ah8eWYpRcSYJpnEXviu5wryqveyGTphRPz/YxrDD01IQ21SPR48Tfb
9p8tU7TybwioXm6aSft+Y2pSaPmGFzxemPofQPhrdqd8vSCm9HO4jukqt1feYJX3L4gtZiSnx2Bq
+kqLL9TXLdD7FfecWElHWneatF7jvDsvXd/5HBDwcJINuZsksFA4aj69sXRlkLma7ILyimXkqZo6
Pc6AQI6mIoy/+Ztzq4YJCWbUlYvCEjQBtLjPdGPLe5SMkrDYeYuCfeVXW74zO4huH46K6Cn/LVdq
mwsDBbI8ugnPI3vezMen5nYv1375K3S7UkRX21DkppG5trB9yLMosTqTCa/dZ6oS7KJ4S3cnTQAI
e9TzHpoRaIIVi8tARoSPzLS2HzJGwbzFyBmB/DQrMBkaoH/6hqNiiwPpipgEVt6Vp7Z2mIY5OSvy
/YJUr/uTDy9GS6uXQRRZoWd3yhJfATOvf6xOXsE60aGJzNI2Nzla6Z6COpwPPaKxTJZ8wuz5sQLB
b+GBROHxVV3wC/dTBZ5Dc2aUmpkGy3IjyMnCgGMemv1fH4I2wtnwocyu8rbMFSRsRhBQOzWlKYKi
doplWxzWUxfU9XGQNcyjMtHWYjrYHPqV3tSAsj/o6lQoV+RnQIWd8aQqXTEkhJIPqTYL5h/Y+y55
tEhaQ6KpbbxbH+WmismLgzy2vNeU5HTkZaLj752GqDbzZEAw61Z+1AehFFm6ocFUVDs1XHji41IO
A5XdyXXsp9TepCe5Hf3LzC3IAqtOTb4obx9gqOiqEYGqC9DfmNvmscd/8Q/17tdX30VAjT+gQsUr
ABj/EBDwgi3gi5+/AxMXtdrt/U71Wdc33QZinDE5qIEQTQ5wwGXosJRPKA/5tHUbC48BRYhgkINj
4HissckXbaIGb0QOI0v59JoMfx671D/Cj5wt8k9yvi5BXIgRvCuBZmXY0FLIN7xtgogQzQ6cXEPF
8lcguHNpQSO5S2A6zUe7giSaUJmvexC5W5sQ525klbNWVkkFMTDei7BmSUkGXTA8z6TOqTsUI0iy
YUW+b430k0CAzJlgyPoLlhLJZp39Ha74l1STT5xvm/jZnuwnq2LVF1booeNo5+pj7MpS7iibMwE0
fsTiH4W+mUIyJbwvHxSf4hGSHFTNji16oM9HGtuyrXcUjftuoN3f8S/LX7OX3yVBLKCOAUcqXlFi
7kxKDDMogenDjZbCqRtmxahQMYeXo3kBQUwhwTr38c7ka044BRR5Z31Ps777JblJ7W5n4vDKDCnF
NIh5GBE9e95yzht0JbPiQfNO44s8CmnU0zzw3yqBPLta6MV4wITOStc3ZT6KlQjq7cXOJhm7Sed7
4/9+gWEiGbTXVWIGkt3mfE7GJJ/Swyv1VWZFJY9TKo9FQHGxtSPDQeC9eqkCaR5uZ8cSOd/fHyEd
xxNp8qRcvYD5QEBS1qATVEuHOZ7ksXdhmXKe1dr9F6dbIqXZUIxeUzjMAG6jT6T71FIkFCjHl5+Q
M5q59QCLpzA0CfoNkpdPtDtbTswqxRUFkSdusVnxtPWiJUAltyA0R31h9Oi/Irulbygl6YkBtSQU
G7+PVHiqlYTV1TLfYCQHyK/h/JTiAltemFhKKO2Q0cv87Z5N9WWx0oQTgXpWQ7HMl7OCo+NAbpQO
3Ibdn6/0HbgMg2SCSggkJOwJzawR6LRVHySgbTtr0/2pDKdvq4RBaWv5apqTm7OeErD+BZMj4pqY
sbpzoUxsQQq5OP2d/FaSBrbHIIL7v4UXpvS9jbWD0mMHZDsoNF8AVcgbaiEfTnIdNT6VKJZnc+QM
nnKl18wiSadDzYSo6PgUGqHNklw5M6MBuQbcusRzvVblnmkmDVy14BtzPIBvm4BYTo55mJiokJZU
1eTqmggnPas0HaO0ybaCq+aodhWuv28u2uYGpbZnffNg9q1VtBJnwiZNoCHNKmHqO9DiqHI8ytBg
HqquMjbmz1tDwcJPBjmnPzMPd6aEnLF7Ax7UQgVJgB0IOyP8oqc0D0WxcTVX5f2EGqt60CF/HL+8
oh9lZHC0kOewqyxnthhNDw6WQDA9Y1U/a1Bxx/20ax4EiwUfrGORjRJKOIiYg48u7VEAL7P1CsmY
GUzvm9p3XR0dwps4Csv5ozki93T5QdfHXwa7/nugrGpZMtMwuU/kLw3IxXkNjAUT8Z8Jzj2Xi9+G
hBWV3TyE0jIhlGIrpfXHy7a4MtP9zGpL7WE70H0PMlmcwats/LfajQ+6pK5Ajg3XiFc3+RIZM7MZ
8Fi2N+JE3CKqnSC8aAfwCU4WnbridEwgOBbTyT2Nw8r3IyBHQ3jzCAYksJl10UGgmBhBQdELIzCG
kW4mmbxAAcGICdtW4+BNIyT9OTVCT6YWmaI0NQ6e1v6bj1hgLDfix4Rm2rqxuaCEDONdjuVU3dan
V6dVTuhMM4+HdnIQ0pLFWs3SsCPl5SG7ymUdakcg60M6zcQHG9ZmlzMq0s2SbTdfftMsYVQyfZrJ
GF1kVCw7j8o7o85qlugX2ThKTx2VO8/SultcF6CWhLzjNSxVRlZS25oxiTl3o1mk7CcRQG0tn8cf
7NV7IRZz87Fl4186CQOCNye/AO+wzgQZJzEJi8Arp1EBo0ueFe0IhrdldtEC/5ewiyFYMPe4Opbi
vYmfU7s9kV5c3itgGiF9jEr0C07TZmihszSJsm+uphcxXXDsgBc7SfnEhgOn7bfWdmMnbvZE2KTr
4MeAtoX3jxRbcyFDoNhdr0e/lHVmXtqvuH/JJTYjadx4APrwyvJUFoSQhPFqiEgcL6qtMqjN2/Ba
xKwSv203q4b9h3F5x6tNp39oD/LPXfVWtM5nybxglAXh6WHa2ZITrLincgCFFONqqakU611gMRfI
+noZVA87fQ89Be7+5JyCDiryYbhRaxY6R0Vl7EyjPnaVYDcisY0/iV65mhXFbFHhFl9uOLNnokKO
XqevUk1Ip/XQLvshi5xrqqwg1jjttGxUGq5VCJYhp4CrHX5gIY69Qw12vZqYkCH2GYdtNoa7FXjT
Jzj5UWZscux/QkSrYJ02jwFi9NGN/Je/pUqolxs822D5Yjvv2tVF7rcqe4kOOxu4K8RJ/mia2nrL
5J2F4QhH/F/XYBUVFAwIlKhkaC3zVFOqpU615/SF8gJQWOCLKfwVCSpVRoiahlxvY+v6Mpmeg++4
EcG0CqgytttfJzpHCi47B392sJ7tNxDVcKM/AqIDKF3UzmcSOIh34ZVhIZoAczyghIqdtYBGXtWk
d/oBTKdVxwNCMHRmQF56m78bfKOOCVv80QPttKC6AMcq1K+b18T3S9Upau6iGOiaUgbtUFwG7w82
VPvzV9I8XNAHfhSpzuqegXq9Yhq6l5+gU+0MxQ5IYZJwLD3PitkeAQ9i2Ax/p37FABe9oytEYQCS
HBaj6re9PwlIgZzb9s7RxbRd8MjrXOmS7VwmM9x6KVgYn4lZw6bkJ+/91qu+69rsaIaQQdDwc5VC
co1/sk7BHDvALpKW/HQRjFhn6nZrQJhTpI6Nqen5Qcocpicr7V0YEONCJlIjplr/n/X2zYWdXhj4
TdfWQaUghQxhRPTEfR0FiKpYnnP08C9+T78UtHKWeOPmzrF+M9OAF+atFLy2vv45ewr/gaFSJ+vf
eJAn4IIbEAU0COIQCo/cdnr58pFhEFvHHOXTjHIAveigqUnNsUCiulmnAP0z9Fl5vkzmL/gE6L9P
fYUTcPttu0aI0jv/Z/TWjKCrq+EFTDyWmw+nnKvRO8KIBb5Sk7mJfjNA/5HG6KKkY+DNvXS6tCHC
d06Tv70sJXt9N56Xd+ZxsZ15hOPpBPARrVyekSDCW5I/GrsJxw+JvMZGSGXSMt8gZLB96B7GtGJm
fUNPal4lKozB8SS9N6B/tG5HAi2uDzyX1LCzulMvZ8REbG30ewnxjekyPIS76DpP4HT0Klrg8lXp
kVKfcbl5IPNaQgVd+ZmcbtbYOnVvAY987MW8yZWi0H6xxT6eccxIpii4C930Xx9mK29wYJN0XkNt
X+7MxS/aJsVDauXlkL2ThzYjaMLEzTkvKu6LUvSeFoX5ruqjOE3x+tgbhc0taQQT8dhPsOgbxEIv
VMXm5PIPkGPdXpi4pnb+Lq8jSlRu4VFCfWWukbQAi0n/VdwywmiZgmcEpWI/pQqZZbGy407to3Zz
mhgIw3Na2jub5ZyW5XE+0jBuRCfZVFB9nXMXTuyBcVMhnWVKHetfF4i4bKeTXRcMCwz/zwg1+dpN
YjpR3DoYgsZstpclqJZnqA5XErt2hyFJooI3CEB880Aj8UTb9in6hj+AAwmZF7jEgcsQo809S9m+
etEFCRmjbF/kOhQEjzvTULbrVpEmKfsSoqboB3fGt8+/wtKUE5M5BaKfsAbhVwTmZX2fsxwQSI/m
pp7auDoOgzgcgPXrFItLHcdKUgxN8VrfVDg5AheJQH/LITf9Xz4u2vCoh3ax0KIJAgZ395MD/VaE
08Tl2i+jwNAY0f5Ji36f/MToPew8TqKu98EbmCkbm+SXjCeGAZOJHJe6FtxlrplXwwvPX77xUISO
0IejfaFSo3XEeXayUgWgZZKdST+7ggVw0U4Vo4slhdkP9KgkwuczlKHx3c00zDRYIm2O6mnUAAcG
hOXCIsYPZXFC0ftlpOU9vqivArBAfoRprAPzyDsCfMlFFC0jTNWt/8Ht9tMKwGqJ4uQL4tNizY9D
h6jUov13DVQQdOeI/mlojuGTlFjuZ5RNwtmNm4NaYbFQgQJgOv/EI5lTJE3ngGyrAudiiyK7SHnq
FMuI1THnPqJIRsSQH3+VdMD/6m5nAdzPlVeXauWlsue5K/5wrJklgehRYV/WDAwlnCYB3DuXwGci
gF3Ug5BVi/puLx//Eori7uSgwd7tP0nGBnFiHstjrwGBRnSEqK88ELf9RPf0kQWjIutD3QhSzDFI
9PuV1Xik+q1EebA8Y1MU3MBqxIoXPx1xP4mRHHvqt/335ooJPKPcoXEL7eDYwXHTpj7QdeHehZYu
Hksw2P7cmH3IlRvcQGYnTB8Q2fLsWeInuorqn5navSgqvXcy+ga+V1iSeK1VVZe2CkvZlRfReH8t
nx+YRSjTkB8U3QqzLe9xrS7tpMKXVgQdrTFn87WDveHLskcdr7L+A7zCqN57iA1SSuFUZPT0U9FH
EZvajRp7WbmzJQlWE4n69r48a1VT2zWwMlE4CzDthg5dfn9gsqV8OssM8eVFXMj+598dq48ZC6vI
aADCQm4m8xgKwo0FR6gGAecUltX+ICTxjpDCvALBuMEAATbji3dz8TRdW4MBu3nyEUjBXxq6rhml
7E1yOKBz3ArvGhEt1Uwge+EbvBbnNHSoB3pOxXavZtOegaBFeIE4cVO7/TWUADWgmaX6j8OcGw+u
c0iZQc1TQZQsP6ZtHt4SfrtRgH/JHQn63USj1ofIdjaY3jJB4W2OdY/xEQ0QNGvDeRimUi2YI7WF
sFmYKpgfsytwqwgtWDCsTjfKSuDMVn6unfZI88Dl37NQE8fpHTiLPSyktWXomOykCpCeyFY2kH/T
BZ/n//GcF5Ews/9MuXcqqy1e3fWM16x5Gnq2vaPeovKyikzjPTuN+MQ2EqdwFtnHOk8Zna1YdjL6
T7wDydDYarqz8IZ/S6uWW0QHTFuOn0wLyEo2TzpbbnCDxkxE7+xHWy/e7dEtc6x5ZjqpBO7XaDEJ
JRl3HJny5xCUveviFPjoStiUiLGYWVS9UOjOEV/7fQznpnfM6lUeJtFL49oK/DwJWlVnDjibhWw8
PGB3e2K1AsUg6RTpHa5wUUD1qLYHjO0+bsE/C+crcFulC4tTVxD8FTdUTexaNDQ8csfFQ95g2rmP
N0A06VCH91GJXqUHrMGcOA5eD4CKJeqV55xnXnJT0UvJJOsmv1j50YwRP5KN6xPIH+cU6gJENXY+
b6TkXfDsgYM9UbFHy/BG36T2o6Xbug4JB4WmgsnWmFeZp+V+tr9+xSMeG0BqKSq+1Xf08TN0c9Ri
nBl1td4EFR/5NvMOs8G823MEAajz/S3mEJh0WCLJZRH+zoRqC0e6FPdgS9JaFITM/TSCqM+jK7BX
tC43Szc4mxSPpB2ZvbKzrvZ9IToOTxsiHY5txq6XaoVAKdzstgefxJTZpCBe9gmCusj4/0EcpKHJ
iYGCphv8iXzcdcV5ZcddNq0QT7bL2erdzxrd+uhSS8SHsF4sCGt1Q9azTlx+PXp28xfHC9JoqwLE
ia83uM7VWLGPDlLNFXruHA2pefXoQYoljCwRkhZF74IIB7zM1VwgDVkIafkhr6LTyef9qw5OJuyj
QOyYu7SxSiyHMW/iaZg+B1JsTb0QAJoVgRd5g0x5ibiNYhQnyDdZpNBeSE2hzq6C7RbHoVEKL5m9
EkbytjcHzDG3jtB034SKLmWsoTvSEHoS2TdkGYJbZuRhcN2bPM4/njTEjh8orBRh8TxzbAcTBQqf
hvI37n6Tth8X8L/vUj6QLSwNuIdiciPR8wQCLpnCR2bFzI7YoovYKtu6SWSyMKPcLsVWwS3QbrIn
WPhTdkdzDixjOkv2qyOmJB8YEWN4lLJADbqpxUgrhtPn1c34YXsGPZiNUFbkG/kM24zP4UylZUV7
8SBsV9nL5SP013iv1Ov9sl9UVv36nZ8yGi1gZ4v2ITTsaGA7cDGg4sgyu0lMJYn1kyvfg/lFNG8r
I6YiGPaSMmAzz6pChdVFNTduO4LbFkadGmObmznEPohA0dv85ESJF5/ZcmsY2uIo1Bog97v2fVuN
2TckuVOg/RIqvedYpFP0QVqBCkXUKzJUFm2Z09uvVzn1oTCW1PeXoljE59xyWDkfn/5rkTludr2X
jDRsykTLpLKjNJDT0W2y7jKrA4g8i9TT5eYbGVF2bIaMIv985pRQzSOP9fFjKzGnnYICE2gLpla3
S+RSHwIkvvXx9kOocjLf1paTqTAJOcQKGSvcA+g9s93opGR/RRqZ8qpmXp1lHV0Mk+EjLVpNDk1m
pmaihwvB3DI5gG1vJYwlOdadeaZ1JJ9EvnMrf5NSwWKWnf2mRulWXDm72fMi1CeNY68ahhplCJGg
PTn8wvtwQNnz0+LXkCUQUpvCKYiz5YENuvoWFFbPU8DtCC0Mk7sstasbGnnz2NEyQ8lPUBu9HRDP
wQClK+yARLTWMdUcDkYCQpsFx1jVmqph+eKMkEbR2XY1yMqnj2ZSur1/zCPZfcgDulA4fbIAOaRO
czrTbDCVebrzOVCqfFLFjo8YdGP/iP04cff5pAO+JfQbQalk1kGzn425LRyeAEHWNTZ584iP7r2N
CzEsQsg9oJiiSP9e+XURTsqSFTCtVEWw79Qm7+uLmfKXwwJ2VUlmCLYz9T1DW17Tu53ZpPmA27xi
PNXvakQt3epBXOmO0LSvntLfL1dz5pQlgReBrBY0QRxD1AV/pEzAeb0veIMChrMZGr5LnFM9uZQb
QnREVEMtsUTMmqaFhDyWMXsAFeBg0mUQSBECs6rAeJD3NHmpOWPYcV66JQ9MlSTs0MzsP3CKyKcr
5WRheTJQy+1Usx9jXVZn4naN5wTeb5i36iEJ0ZPz1sgYsP9WojUVHqsQxgYFmgdAlbj6tDry0N3j
gm3zrysvEta5j71yNIhhAS1D4vX+vkDR5x//oSNMb4zAZuawQDchxAbtn5b4ffua4MjGf6DvfuW5
+Ji3/80Lbdf6dKII3RBTNawAN86xvHA0LV6qyLNLA1KR3uSyXh5LWoIWtwdTbVj9/XSQilnrIw6+
OaMHMz+o43oqdvFKQLriDEit+rSTNX1OVQzB4lNJwCeLzKmzM/wbu2AUYYHv+/+6AfLGZTg1yAV9
OI73+NXZ2UM1wkmKV1GJmZx9igNHnZf1E9MeGMa4kAiqhK4WPeYy2J2umhSpl8tkNcbAnV80fvd1
yslU90yacbWnw1CDlN9cJ49aVtnR+N7QUVpxf57lU6PA2scdQwnqnYF1bmOoeGHouBPgBJoMnyaz
twB4kjLKVs1ZjTgiOte4YA0y1WMY20rOjinIyMr6a4mFiz8FXo3BRjdWIrd+kWGX8UhdAI1x1Xy9
Sjwpm9DwSRTBTR4jiKEn5IL05Bee2d15V+LRl+102gT9AsKmB4VoPPxwWrsbgug9pI/20m02jKb2
mK1sQqYtDlw9sw6/MKqT/BKbN20ylEnyqObB4egS8BfgF93gKPta/kn01eTZvmAtpAJR4C8hF54p
GfYKegNntnmVCJgjNDndbZYvHQ2ad1jvSpm+pBXI2a322rIXqhM5nOv8fL5ogsDEk2Ki6XQhkKtR
NC1xDfVZmvGmZ0RqY/drQxim+fSzvv4KqBJx6vpnwotPqYvfHQmz0B0iJteBVFuSJDD2iuDVaZwl
cLH0bF6+vrJEAJGAepeP0wrZY6h4VXUGY4UvFOuCaoCU9wYbpYfPGNYUkm/PZ25X6cCcP0DPs+Oa
eZMjpeubWFz8pIXpSNkn96lOAdS5VcgwNo/UGP+KC776/kV7dR2tjvCGEuaoRW/yw10yIXZqbbR8
fhU3kCfkBeA5Bxb85/aPsaEmagmIVY4lUjSQZFnSzTcn/h0VhDW/bIaQ8cnP/2LKL0AAbNLNoEhj
UvL0U6X4J8RseyMglhcGmEHbcKmvsgWQLYHdiQZO6q8B1QLCSOIDxtydK5EceJcFXSGlxALBwiEw
Q6PwPc7jsrsVZnHWjhM+YQRrHWoYPTWRyNcdnJPBrBsFyDEvxJH5Vhroo/Y71AK2GvcmoZfAsjkn
PBUIawQGy5vKPFtFngnFG0zzrgn7s/iHP6VdKZ0r96RgUKnmp9EiPOgW6HAJ+iq2BCT1sWM7pIyz
1RX1j7OgsFriAMtKUhIStRcKtViYvJYaYoeFN9n7QnAk8DhuSdh90KNlLXIvrHcl0tCcw5glKw5n
Ok/7uPGBpo0pRympUMzyg57zkgIqhbXels5BOJVio9YMwScheaGD7PjigPvqYvfMPMFgwSHm2Hs+
y/0RfsNPYuGW5Qpz8fBkA88vJIcp6b5Dxns3MDSISRTpp22gbO7AfIlKwLp5z2//wr2N/y2+5sxv
5cU/igy1MRtBSzwk6pHV3QOg0j7c4P/wxPzLsBWjFZ8t6mA+wDtkP+9UHRhLwrwJplIqGHdrxlOQ
cCmctKGM+XFR6UmUaHjvG76cDDlPGGgX7wsKvC3w+rzooyYEydyUtEmlstSGps00n1efBONSh0C5
O8snSTVeQPltY7VQwgKyA85czzxIGQN3h55G5xFBhXmTEu48WtxugmBy27I/u1FSpNJy4az99tzd
Ych0PRPrSdK4hNDQaQKU8N5ZnYEJrKC056s5ruvPdecIms5BsagVUNSmCbHSkPvPcP5OpqTu0cGH
wHKegh6th34Iu6Q8q6ovrGOmhJJyihQxjGXsfF9PIaNLYw/fC3ZuuBBof99YrAuYe12JYpmI0rxX
9QMg4prlN6NQMtjaaBtbajWprez284YPWOlhE1/TGQZ/lAMgzQxyT3i4uFU7YJ88T7b7gmV4K4bO
RX5iUSICauTQ11L7LzFkmfheZhHKIQ5w5zum89+n+jSrtlAEGjGWmNHH956DjeLQGGg9FEZey/2d
4ctsMLr42NAdBddvClnGIu6HiZqpiUpxNsEgCEw6U6zIa/Wm1vDyRL419mFFuJwQajRHPe1QLIx4
6zImXh0x3/5gUj2o1ft8+EzSOLlvQ+ZdSi2Fc7kPlMT1JDGLPUmZHFTWXs8xocfJmUlOUoXwo/Ae
mYv2GsUepKQdv/e6Zsi/qExj9w/l1CZwJGm5Bo20mAR+HL4XqHdIeu2nf5es7p3nbaKmhtW+Twt1
UzkpiztNgo6cVask/KHgR9ugageKx/y2jZZ6WZ6MwSWqSARZIaGFQ7dOizV3R75+cGslfYndDJti
D3q8Htv/m8FHF11In5H0f0iGmXFxHmfpvdljJDh076x85YHfi88RWXDDB8u25VGnpt6prF6XGv4u
EfzojsQmlbMhM2UoIwgglK3lpmEBZLQ0sBUh+XOotrah/Fi8eMfXzV0MDM8MZUuzvRvqiqZB9XF1
K2lK+H+fu4PQ430u9DvRUm3oylt1o3VvlfmYx0gJoWdUcJVfXsnNML0G/hFku8PeShjhTU9flUNM
KPhtXotB4QeMpuXyDx/k3Hinh8v+FwbX3puIDEoqfOj3vuhwHf1lezRXCGRC2J319ufDOu3dl57L
C8mZgRU+Y3Hcq4Fvd5RRXR3HqXGCJTat9C3kIaEEWpMx1mNB0xnIx2+I2nM/YW3lneWT8dv47hki
CRbDtN1EJ09rOg4Imb4CfxJzwDmDFScllSATPLRQhQ7GamYZH+2+oVH8UV1I57t//eNethXXWzvJ
TFaIESUu8BCTsBe9TuqayOP5+6UKi3aYL6nsr0bJD+IXSq0WDxEgWaxW4KSgaG7tnttmQoRvkhT+
G8Px4VGxEoZSYFCgwh/cueaZud93KvIeMPV+7CMAqMtpwSnYlviZR9NCoVkelNNFBnJ/NsgnZaEI
P7Qr+VTeMcSyDT39PzcfLMWqlgB12FJg3dkaUIX75Z/DQxUaVZ+PYPRdpC6AStI9342h3knYGaLP
70O+WCoEZBAr0T3RL9X973fZfKtmE2qF5MwKWxrkeTORmE/3A8yzEhl/A27s9UHyZflUxsPVoBHc
tOmuhN6W2RnscaiuL3l8OPq0rdM25c2FCK8eF6args80DxdCpqygUw43TbliYqFvP9w//Cwc7nHN
LtyF9VrHroiqAiz77AaaH4hobRhiZMloGlxmrsYw5ArmlpEv2GLXnowwAexfWXWWH+AXtwrTrs0y
DVr+vjIEj1F1GOjRJaAq0C0sA5PJv4SpeSmuiEMqnBc3E6OROl0PJsUSAfRIk66/5GVrv9qYPQ61
K2AEsqm3oKScg1byB8LfBscnW8STatYIO8FkSuRka201HlXAWU2iY1VivMywyt4B01qNl0mLSATi
6IN+vp5/kRODj6noXBQQtJE8GQ9zRa6TVoMhMz2NUJpG513yHxpS7waov8RGQ2qMvftMeLn07ier
2fMilHE/y75+DXYr4POc3I+NciZh2alugJKLp+XbkgWgQUDJKX/KIp8o4twUWxmLFYtCxjHOiveE
L+KP7bzIQIR2L+b3cz/mKjMWEUSorCCnavS/1TOiISruQvy/Cubv8bMoHhGmmZQuBW7n4Z3PVWH9
VRmwsjD4h6CMR2VdlZ7Z0+pu6CH4d37l6pVLGSflsGcAqFreQdZ6yXP4uH+yBq/ovTWQcakpM2gm
f8iNiraGDbkjHuGDLHhh8KUnN/ZIWbhP/l1fs7pkUKnfpDbsWy7m0D192k8ZR+EAOJW53FU6dpzK
7zYRt/aKbJwH/RA9xDNSiKl0vdgLbHNvBNSvyvmwpTSsA24Pbv88nhflUh92dAY5HekmMD3Io6qn
u22qjQp67/BSUA5IQrZOVm1nmfXRcVpW0iFkLT6PB1x8U9OusaUx/WwRssnRRB5hQHXMjTaOzudK
FuRLc7y5wJsz3RDSEW7g4CKhAkJz4nbxQYHTqRuN56c0W+CTwllVVJ3C/UGa4ixDFR4rCIqN9NJv
gXSN9jwgdKz9yUk9KQx5wbEZKvTrCgVVyd3Gs1zho+FmTM6Fbnkib8FZZ4+hp+QAORGiKCfclp2U
PvyE2dui8HENm0kdY+LHa8B8JHEuJhLathEr+el50TVALigepUUtfLPws+zpds60843uau+8k1nW
ccaMNLuix3fHjv/m/ni7OSswJzwhzsOP9Vlcp9UgLfXRx4k5xJnrb+UX+XVEPdMcP+aQD+PUBPlT
oFjcGdMHezQqF9j5X67RGlzdttkCmXxIPO4n8PFFMl57DlrpXhn+eZRSZVsbHvGWJncQi05Df9xt
aFcUqgygN5YWTWrtCKL3DxgI3A3+n75DnATlwo/z551L9JgLYHG0Il29NLEfVAxFaglT2aQiK7A6
Sf7pEfbuvcpNqa42q1LWzi3Jl7r4mT0jbMT7oyuNKOpL77VpF2XyP5StJOLLT7Bc12ei+tAan9+L
Hi7p/vb9IPsLgF1BSNrgdx2t4XwGVJfFn83A2hHe/9eHIRpD9a2jMjCbGVFQftw3wO/0cBnffYJA
PuK53PmRrRYIe/GQ78tOvah3bHmSeoXpYo9VmCOWzTxlYKJVRKUc4pw4b+1s8GCmf4Ub+9USsnVe
FxixLmEzGtU8oX7P81uSGcUNXz6xVChCU/9J6ziHDk6BvGCk4y9evpcZmkzUTZsOtfL4COdK7DKF
HB7stRL3aHM0sojmQ6rBkLPHSvSzJ6/7h0xWxYYlOIDYgTOvrvmmHl5JOUR1nwEN5IqEwV9v4MpC
S+9c5yArufI0ls7vMotcsJ7Op2Z+2UkQJXOg/o7pM3opz/0afciamG8ywfySIMWdFcQSocjRrmSi
9Fo3ycpzFRpfxqhiBk0tAvfAB8MSWvkrNBPNEpzvsIQfPDSECkk36CYW4OUriAesWlPwoWpdLXhJ
LgKYBBuuForXm4+JQxeqAlU6vebHnSupAzA/Ln91n+cMNclcgDfX/9KyxBKLDoF1mBnhMZf0w27Y
dU3wIZv+64WepSwQiOuScH35wIk8WjVen/ZLkXMRzrp3/QDhPIdQvs3xGk32QNxguILoBllxNX0D
+Youx1gN8eOblOyvkf5VlwG8Zo9ZAeqaU48/J3iFzPlqwuSrcqNKEK3d/rUX4tJfVI4ROKgJUcO7
Vd4BD4kZcZNe88KcHOksDIWRQ+nr8yVKeai1PHbZPoUAeKoC/EFOdEJENKDbJFaNANGmYdVULsLb
/vdU3J6MB2+LnesSLumuZTg6Yy6l/24JOQWjNks+FYzJv/XXxUmXHvDka7xpUB+ghUG4/oUZAlNS
ZHUIXxP4or3QMbMmfS7kHvqQLTC1Z8dZLhjk5UDo+PrZVp6Zg8ZPt5sff/P72Hz6oSE84nXJxKjI
SIvwNtxuuR5ngJUzpkj4c/BLWxXIH4z/cHYch6BzcsaJ1lsJYmV8jaJ46yfjtzO/5fD3EuczhNq5
Ab0f7KyDrPYNPvSgaTgQ1VPQMj8p0EYwOSN/yVW1bi9uWxKQMkefGQYXd7xl9bkEdlanZSrBosJF
tnL4gyw+mUWXo6p6T4Z5U4jnbFasmwzR5KKGYeUd4x59kN6C0uFRT4RPlx/KDkr9NtVKnfdk8UCX
315/AjPG+LC47tXcwRLbU04wHEM/Y5bHBAKyaLuWESeQ1xwpl1bzcsWm+3GfHoLLlahuvC9R63Nh
ub8S7UZXnAaQfqrtbzWkRih1dBNRgT3j3mYjqsFD4VER5tgCvHgtB8+oX9KXYeD2OQa+NjBYJokF
8mZ+YJeozJG3IUguj74KsdJzAiHlhbbauV4UsM32PFLhvaoI8Q2XL8fuhsvyWg86XwFl7ew0Lo3Y
qq3yCLnlgL/FuphA38kyINFP2Kk9/Y3cvUHL7qXuXYECyEN8Yka/rr8qYyzbzvOWpCGcdNCYCg35
DsjZ7Q/CCjxT/1ea9vSXqDAdnLqunpCWIr6eIda/g78knkGZbzTxbaUGBnHGkg9slmOhDY+KZwBW
Z14BFnQjAqQnqRQ8Y0VsM7kqRbG2dKU50jQaKExucaWGd0Vw4D1dhKsce4mcIi5HYlqgzv+u2hC0
bWUzauNSd1M9STjOHWA4czZCvzA3ET3SLHqp08TMChLN8x0WdCuTrs4sz3hQTsyFhumijDVvgvwf
TgcRCt6rTIzrDeumFDC3TFn1jzBwdunpzGkkTtSneYLtK+9SDMeswfvWqzHkWiXJ+BWpb76j5zM8
DvxZSK8mmvqKa3fJXazGenP4U/BuquIYJLUVAmgxN1lgtgl6QnfVlI40VOnSRAdXKHsKBGQktfj1
pI05+yqS2LP97p7a6uJiBLhSWNWKT/kCV1eWICj2USldyZqKfHpve7T0gJlxlbEsdFejpobTknr1
qhOPWQxVP3os5B/4+8DVVuiTqGWGxwx/vo10bV0mWtpIiFjJQNjtiMMMrDI3ia7cn2zgSnAP5ion
cIoAnydQAo14CpYT0gua/bew9J3w1ku8zWhwbsPMyrQBTZnAVAILS/1POyvlx/Y1I9YSTweixAj2
K/I0symDFhD4K+tfa3zh7oq8s85A8w6fJnxt75Rs513R7xhscVdJDnc9lE/gQoR6136/ddS8ADoZ
z1heI38Mo0W1KoDcNs0HHwZ0jyiNIKiDVuDyHfNfaJogcxz9DCwQMo6AaLNC9gqCAWNNr7yjW6GK
g8eLXZMKLUIsBFTpMTlVeGdE1oHZRXBaQ3RUe8TVWLl7ntqRJ+HiKKQU5SEYfpXM7/FyCXEEM3Xg
raQzma6/QYCeybLpcyYxzMPXS6HZJvuYT9uP/KZvS8dRa0k/THdraQz2KWmmGW+3YWKaEh1HVF0M
p2Qqmd6Tr90ZgU62bXfkjwj1HjaGdLjtq8cOz0l7CVjsyhVAbJvtfqkiPg+/BdlLWZhGw4+69Wlz
dUEzpSYMZdCNW/FIIM0HjpQU3687eJ0IViN0dXHKR6Hb4Vd/AU808QT3XZ328pNZBMX7DgnETc+i
xC+Kiovyx95szAsxRAsjKYQ2lv9Pq8JCWqPUk0jLxbertDbPRwXsA4uPyoRCY54xbMItxRLfMTGW
ZeQI8X5dDFKLD19i/KmlDdr1mTvzpfSeHMjmLEtzWSO7guHBCMOgU6e5RMlQFYvcftzu3ADwH737
WoElUYfqvnHuYA/D/XbDTvViShTAaKApLTucrppzIdVanHVh+cvuU5nu6nmtbopaxYcfqj3j7LPO
bGzNioO+GlgiGwn91tVgrDcwrOv3UHfDpZ6ZXkjkGRj1jg+NDiOTSwF7lDlGM1AEWzotgiTr/6hr
ax0TVYKnXP7hZNe3Kv3TPqYIkBV2GBi0wlfoAK0r/BAoxd8yB0yuseqwVzENE/d6+rlwH96lLM2I
e/po5BEm8dUecPQ6sbYBFBd2nI+Cznab1IZP9X6kjiJRKs0a5IYi/obkuX0t8pT1CRhXe0hEx3nu
C3Ub0kx2uO8YFeQOMKg/TgWP5c+X53WmWPyQNAuV9F1IG/hQqjRozYerg8jhcpZR5aVTEqqLJhCg
DdTk677t9J7imV8BsoSjrRChUM4ZvMEEkpMkOmbMInnYOBjc4CPc2aGvHVDUC9WE+mXydA4LkSvt
3df7xeNR7zyIVRY8iEck4yMMiLIqxXMvEct95I58uCe5/r5jZWpibQAkxytwRLUIMXzLbLAlZPyp
+jmpRXP3Mwg0OqSdjYLxhlz/ATqNCU9U8gGTlsQ4/yGVW5IldFf9UE/Y65wxaLEq+IQh0UD+i64j
FCGrHhSunAQpjso9r8cH15K61PN3yMmztgPSPdzb1XB5QIqNQqJgNt84/U73o1BrUu77KMCu7eef
q4mOusTAydpHPiK7JJdQc2Nl2gppoDN4LIBV4JCmDd90xnkfbraKLRzTlZ6miznoFgR2d+LmOtIP
trgwIwQAYYhDt5alpuI90U6Io97OXtD7hJRqPHgc0KnZBA0Obvz1OIcCJNfCdVyc2c5Wk6v4t7qM
NM3mBQub/vE4XxFPQtVIRMkL5sbT2Y1gm9OrtrkHngALgJEmtunFKcO3d04h5D9wqVl7FoiaSH2p
y+EG5ays7tEnrmVUyXFWo/an5StV2PxjdtN2yXlluVImfHCAXIFVz7c0m/zvQnPlukZrBtFG465Y
mUZFbnwClzWUEhhxsmxT9Zj/V/Aseb8uY3eBn3tT4p1VtzKtR0twvCmfAzCW4m4WM2l2AR/prHow
5UZdlSPg6oCZt/HI+LtmTL2313FxwgTNfdlsnWGfCyrIsH+fo5gFY5YO4wp3kilTwo9BmeqTiaJ4
qXyQscGSKJeUrT++yGI4s2x3iL3tsaEVEeckiGd0kwMmbX0t06VUknwlCu1zgcsI8Nq67QHWQHc0
waWJ9Ef1ZocqUQdegMfpuFcS/hDEDcthrSLSndEDOxIgjiUpAiXlAGxNZHRHm1/YtAAyQ9GgseRC
K8kx0rlQR2v+Fu+o2WWIyIxUAXYbbm1RsOZQSolkzQ3VMtMzM+a7vc5swfkrCXUT3lgT5RV52mko
s6hpFcdVNTD/AkNYVwsMtUhv0K7GlI0aJ0JLdu6Gsu3AL5OMNp37FU3qy6N8MqsYhm/Nhz6QslJE
nMLOdEJp8FzrDLGwwynDUAhjL7NBormkTjxcD4jDp8XmSzDqkPi7LOaDTiz8r0ah7TrxpByn2MQT
RVgivUrPIgEIMSLXfyRo5/9jVunIyizt86fPTg6emLbora2z1ZIW267TXIp8uREX2htu+qq3Z6sa
jIs0ukCfFXQgomrQDAe6T1fenmRi9g/5kZOqmao0P3tJcU4C/C2BbQtwN8MKcOJkDtAa9dwX+OmK
SLAAqreMnRus0Vg0JciwS35zfTMn5FQRTSE4huIU701EM049+e8JFKRoRkHx+0KFA4QXEfMjerps
woFdZXcaAzzXFHEB2Y9BBgrpU+xropB7rp2FOtNYydhT0OmhnzQ61cE8sbr9IPbvHNuwdlBJkTqS
3eAjw+9aLSmAthTGiWkB93lQGtp03O8OuRSEToBu1pwnRZdaM3ovku14xFl4hrJcruK66JM09cZf
6s6WTb3iaqyZFP6uymAJ6rx4tNuF2yPLJ9OSMp63yKPi/b0t2HulonTrHV+nr0BleipoghzKYEUJ
OQhsWonk0fMmpgsJIQmiJT5lRmjeWjJGvPAN3HU/QEISNh1skL2GKzsa+2hSSvWEarLHFv3F3j/K
l903ArKB9wJn6XE5WsCGgt3SWY8rUkPqEjYxtY/NtIiDM2MFzwNag6XjkStdPemzgVXwLxbvPnN4
Oo3M82tCZoN9Gbm6xs+30aYjMWpUhlMXFkbal+43NASFPsEP9CblmmprOq0xFP736t4rThmT1O3/
i1XZIHtPvcfp9Gy7JQ22AywhiNevZTxoFOvBbrdmpyLEFP6NGWqNS5YuFLdxGsoGU8+TpeiEKZ/N
ZyWrkpb2yua71PUvYNSsGCnGoio6V5rgLkUPB77QsIsrWRjjuJq/nv9zuLZ6Lv8u7i+jIjnD/4kz
Q5A8AICvf6k9zsXrF5n/c2IWb78OwX4bk3Te1g2jjqcRk6AinpP2t2z2XC2tfZOrWXjav/K88FhA
RfPIQByt2N7yC+3sLNIX1uDjKFysXdUkBPheZ4HIm6jgtyJQEJWmLU1JeBcycPxWY129YKO0IZJx
7WVjcHq4uXhGTEaH1LUwBh7IZ/TYhoOZ9UaiIKavD7qnIMNIZGDcbuDPkYkyfvT1GngwWnhNSPyx
a2Fv6pGEp225on54pySh81fnTFGXqcW6FTmmDw/tWf3dYV4TVT1FbnCegb8AfKuxH1EGV7tmXclT
h1Qu334L/IgzS80VZjD9UIFLxt5L6SfQ8gTUvWy8voOfi6yaYh49Z5Eqy71Rv6fVbpOZyXzTQxRH
ZJG5b0R14kjDLC+ROf3lWqOMd+5fgGS4TLqtky2Bk9aYUtFNzvAPB6Q/xlPBi+B48e5x1mPXR3oR
ZO1XW9nZE0Uvijt8sdCPKzIaS0LkRMUMPn2VY0kbyFECdThv8dAjs8hMgJe79ON5DwCJgRaoKB0P
dNAqyP/n4eTDI1hsa/JYoiDJpTPH7CwRL8StTBBSGWzRKpc8CfsH/gvqWE0visSmYyQhXPXn6nJO
D3myws20JY8sUXiydWkp1kvITTR9OkNWRU0N8NP2DNeijZ7Z70fHAvLkMG8WKCNoVnDMQn5UBHDp
Qrz3hCOaPVXHoqK8yzORYCQvtNyzpYEl258C7vZc4WVhBegGkYhVd8a3gHvK63lXcNOe6IZ7KSQL
BfrA2NnH/7wbRDzCRdcLHLQKTK3AtHzBl/0f0e3fIv+3BP2Fea3E6C2AdpPMnoDO9fn3zQ44MW0I
9KgwF5oq7gJqnY3xkFssEucV+x5ZGGv2q3y7vi8GBeJAH8KwgudfOwy/GbJvIMYxlHMwLBBjUHR3
6ziKyJkuX42vnsfKZUbR+r/dbMqHToKYdvcZmBsDlSDEFZvKz54T9Sk+uk5RRJmPIEWLnh5rbO0C
9FZBxo5UnXVBOU9dbNEjAMhRNlQxH+n9LXn0m7f2HP0RXv/CXT62IkL7ia8SpuJLb60ZPZ3a2/Ad
wxRb1DdT8HuMTtyTSz/Srxf9ul3L8m1tHU+yWhM57Ea40CWmIpjTWYSIqOkiqkEIaApuB/IteyU0
2lFSXs+JOkqWmuKDrqL3K/sd1iddMRbYW+cvyrUXSZbggVBxEjOfshUJ8y2maaiFVCCS1KYV1zRw
q+O1CVGNm6dESdI42LDt9acfS/aI2Q6LTC/aMiw/7fSa8S3MvIXaVj/OnSC+z2jXdiBlXAhHzRtg
+BjsKvvOo5cFQ/Arwgu15I+7OziqySZx3sbNoWgrjRemM2G3FCvQvx2B++F3Iti8SK6uhwi4r9jm
NB4NU51HEcI6R8eL8POexwW4/XPOHBbD16uemW0xmpie3v3/B52YgCLf3GN/PE9yNoAQKGo2Dcj5
R2G4vm+WYI+bgSqOrHJPtV3KOiCKiYSxnMz1/jvbRc/2SCAZLm7D2NieMJY4eLbNIAUfXWLDpO3n
S1JNr1aKPggwIFqUtn8kYegUVe+bWlP2GKe1SQVNjwlvJNHG8VVl21spb7HIvPwUJRV1bcUYkESw
jBuKkyrHxmANiGsCTaFqkY7qfDhrg6QSXFgbN6QQZUk5PG7gDwIgeyyO7xoC6oeBkWqLhIayIXk4
aqLoPhNGHlIExF4LUIij2GP3u0Rc58xCTZ6tuqP0A3WOWlsleMG4zWbe/k2q0yoyckvQcVx6DOsQ
UErQ4Sz47oN8mqvkAcTx40l7ShSt2Ns3hJwfHHKC6O7ZxX/jpABhGuoTcb7i3Nxm2f5CSaXTCEtI
WWC4wDu8rnuDo/mc7rLcl+OK9QX5yVMPxLUf1XNKMzdrcZoCrJs2c9ofFhTSSsXbaxV0pDbBb3Hu
+1Ff54LEBQSGhuNtXj8MY6tw9tHz/kRmQTsrZQLe+cjeLdh8xi+Y9c/+/smi/UsfE5TdzYZm3umt
ftpgkn61UZ94FehkVPnDZJfHsdBxkh4BMiYuEDjIp1xuCF1WmjUkgDw7Do3ZdzI6qYRleHCGEjvl
RvOYyFjyWPRXMJ3WqLWztd08V3nLy48tpHxpJxu2FMC4krOsTJa6F79TfJudnZJ+6302IxtDhB0R
bh5mHZCRUB9D+Y3cfbgxouBQ+H4PLEnSmzLq+JZywgt1RlI1U+kgWqGR9ZkzEPhAZ2s34vMd9zOr
et68PqatOWOMUqnlRABaHIlIHM+pW9X/nHpNNtNHG0T/W8oil/+VuEfqGJFm9DA2GW8b/Fm5KEL1
roWyBlPFDPWXwl7JjhwYOf4r/Klb/t7DmplCBMZlq8M14bBuyLg6zKlH6uZ41iKmnp12Rh63eNPN
G9V+BG14BvYD8aN6M5rf2gvMmO5F/ClQIEeoNy5Ad8BRDXU0sphpALtiNr4Y1tvmRh0F/K1aE/9j
Sr8gfAhi8hTH1fSFWoPCFRFGtv5E5XOk00IlexO3myOris5L9jYF9CbYyKPIw1JqdW/uNpY0IubE
KsaE6w1pIhI/kr0IzZEu2lQQg1g04DdiS2BgiNxMoDd7+l2tc7LCLF9trXZ5D1Ntav1kbEkqIWOg
VrNPGbUeGwykfVSDFQX+V2pYvLNj2M9IAmqOdx20SkMmWSDik19bqQpqSDEFcDwKfei9kAlKBWJv
IQIS0v7pzA6zJYO6XQ+5mrbcCVKVwIzJhcOFOy1ET6ArumP6PK2HCMfo+y6j4CxEOBqT/jSO340s
y+GtZ1Mp4zj1fymnh6OL0OeQKBwqQXSyPK62ysi4t1kIwnn221ll5+w86wzi5EH+3VNHRVWwYl23
2o0WtDTKOcVMfgzga4gaX4IvJcvHqNd7fgHSbbtKYc5kiHYJs6e3fP376Hr6E73xbHHYMeCZmHSr
6I2qQsC+roxejSUn7bt+FxN8/uaJLkCguXy5GWTOie2llGhLL9UEzie+Zj+DSw9c0AXPv3JnG993
vaKUR5KOt9jNT0TizGPbqV382ukm71ZN8z97eao1iiUFnPOYguZQoU9CrU+1RnqxMwwV3h76mRm8
1QJ/W5NLeBxG7Z7LEdIWlwwhBelTXiC53/QtjH6tjGwLFtbZTW1XGaNae2F0O5j8/DON1W5ow+31
Clxf2ojonWrl21sTpFaOR8MxqdQDZfggustV3WYsxJzxrA+rTWK940cI6Jz9Z29FpbhnOiGndEd8
2x6jf9/7QoDbW3ZCXE2zokG6/HZCvPf/+SRX15R0TN4B6T7T/T8EL+LgnKT270jA5Fq0Lv7PlamB
yoc1lXllegWE69vzy/LVWbq/OV0jUcscq5Qp0VdABtedNWi0bML+T3mJUC03BnbkKOLs9YEsOj/t
4DxKPoMlfelQ68zeuE0clVl6a3KVgmibivB/21E1riMye6z6M7IAoKIjftOyz9ITuoiDqt3dr11t
dKAUR88VHpg0bluiUEeOxMnlrSZVnvQ+Lr5Yr64T6ezVHsyj5T5ru1IlE6glaT8CWzqLHXDZ8pwk
9ia+VoLT4bPgkkp8GghzIPIDrUkHbGbHR4sl0ccxpZm8iEcZUPCfE70dd/tenehcHL4fbywXP/xg
BGylIuLebZO9uf4MtQZiBcvPSDujW3phW2wslgSBPMZj/MEfSRpbyqBQyQoe5k9HWf3Br94nJK4u
iVbUcmFCju9PnDPwthf0wakqvWFfK+oNKAJAiZScfpdhcVHcGMaw3nouGz8gyi7CmGcEbaYUM5qa
dCtQu0LcsVXHaTcivW4I5tTm+/u9Gbri8mfeLIJFOgng1pEBoIzl/AdC1VkSppl3vlzFn9Mbp2yB
oMz1S4Ax49WLo2/IRuXsj0y0RsqIh/5kn1SdVwYZ7oPwcKHbzFupwunw9EhRURrJwmdvpD0mZBBA
VuvFuT4Va0R/SEvIu4cmabSWiIKXaa3Edq+qubD9fSysgRGo3qsi9uRo5gTjo68hsZxtijrAbKMn
vr/HJsTLpJxLnLBJUf++ba3XbGnFx4Emwl0393A7NKSCm2ayI/6a59GJ5RKE3Lst0TJsKxWEnR+o
+3det9xTaGUSzmdsoMH2ruOUo/6+fyJQcsmFlepsi6XSxeEnpF5qeUp768wk4rHwJ+1+pvbuNd5J
1cv9GuJOMPre3xLMMRJPbYknlakOGlGS7CjMuQrtdapUXfZQP5pjPb9Qd1Cxb6zEB/inE9aiw4Oi
Fvqcm2PENdJYvEs7i3mz0ycOaHM2WLn+XblUwhPXZRGwUIRLVna64K795xuQKCMz0R2c4NWvfZwh
cWuGHZMh5MV5sNU4TU+UVXcq/8r55FXSwMNpS/VIB1NkUDb7HyKTTo4j9A+sm2Dc9ltBF9HhmmtM
CVdiT8KwXWdwNuZU6Dzn3UtGt8GNjiiqpII9n2nP4kas63d37/CzFy8EnZ1Z45z9hWRc2Hvd/93l
LBCTTuEG/xcyLoDAnhhWZ20+5BoZbXZXASOxZfJthfZZq/zw212ZnmCjW682JGFGpHh1lW+H2WOH
70Q4f7hevEVFh16jpHh4NRdIN3HBWEse65shCWwkf1/HG2io44vjK9M7veTLgcX7YrQK8gOd/gJ2
BNfJVJQn/+Oodi7ri6v+HOk6LktDrzpb6dhX4BDGyemCOnVc+lWSwPbwIWYgPUuFFZIqEYnHifDv
PepHtDW1b7KQVb0IEiJhoN73E3EaiqJeVEiRn+CUIK9VZgsYHiH+SQ4qUT9BzZF0e4GvxTaHDPDw
ixfkZrEJ7UQvVYqvjV28pUtKEDtlH/S9423Xh8wxo0vhqbd67mPgP3tzqGzF64UID0h2WNJh3pBv
RhHmGcmCR2kdHS5aVRwJhmZIMSfNono3hT51HZ6x3lfnV/fO2Mfn43maSrjgtJGRPAbnPlBlkEl8
gVE2F4ImNKb5toCKYqWuk2pa/nOlm/AslPBN/MTSRucUVOaIkLpJ9DuRAJiFP0AfjhHbGkg29V9E
p+b/WF9Am+H7VX3BNFobgBPJ8/WCCnZ6V0Y6WNV2xxJtlBDSxUb6xmXYDP2swo+8beRp7ExVZHdT
4RUnYalKTIEGf8Lj6lZj1xO/1J13NuK4dSM2BHcByxF4TbtEoBE3la8Z7sfSxbg1FRYhpBPdcFRW
1e0e7dq+/4bcirbPBeLgiwELXOm4JllDMq1jusiy8RX4CmDhJ6/h8MjH9vQeh5qyw+s5Duf7RUyX
THXQKFUnWIn6udaqIQIbvjTMQQ7t492VkCoV9+KLay8/7lIO0rfjV9CkF2RYL73HW9cBNQlAvcxI
7nwGjSUDHM8rpVTHcSGY8ZxJgtb92JAAppwMHeiEXEaA9Hw4eGMNbiZLGHBITK4i51SuTYtshVKx
7Qxw1PiuqJlo4AsllEr7f2BrWBV2gjpt8JVdD6reavGITArhzlP25gkc5ENYXnebRAqFRI8TFshO
gzll55+6F1jSSY147uz5yHqQaij/nj0Qsq8BB/qnFBBCHg3NUj0ED8624kUkFqmKL1UA8aL3Ttp0
hEmPP+XtPdD5/2oBtHjoh11qotOZYcbm89k8F6q5hPt3Hv+0ByfxdMkSoGi8DP8o0isXThIRA5S9
Ae/xMszcOvJKxNuBhpK8spJXuqIyA9WZ+NaVmu23bSgsng51lttLAjwAfH+EOndu0Od8CnH86sNX
3Nmnw519xpKydRV1B2b9pWq/IxYoARJAgVAqrVrL9Q7RICycdhnmVIpuDF6dUnGSg5IvtqygBzqi
b/WO41xorGWucDZgWh9RKBcIwgW2lcbAo4vUsNm7Su80+IGK6mCN2BGjYMmVtyz85EAkioRa2asy
cg5pFLnWkbKS1B7YszSL2MRGhf3eLURhI1mS+8AiOhfR8Cw04TFhf1SGe3I3vex3sRVlXBGjbwDT
MlpN/Q3EQqnRkcQDE7vqpo8IJd489OAbreDeUDP+uwT3ZnBL20mkW0KjJbn1DUBrXA0ZSKsMODKO
EaehPkE/cIuOaRyhzBN5SSmIJU6u3B+/2NGRNPbB5/afoXA6UMV4KKp0WPVjJ8lmh2bg+8fxey9S
NdvJFwGrcZnegVgAVXiJd6+kwim5+JdtsLPQ5VxJuEK7N0fczearXNSXdMK6crxKkZM58ZViai9r
q7AMrOvSU1pxqftmal4a01cYLNjoraf07yWRxr1iW2Ij537OulBf+mE5kr0QOwmVPbO/6mzgcokv
ENgc/4fUHXNlZFctyPu8liHAzOs2xdmC7ccvS6wCtvrjPHRUznSQeZaHBsdWDTDS7eu8kJ4Lcmjw
UZeOgC69IsRVIK/4GVzw4q08/QvQlI7MqtFYFLHu0b0tLf0Hsc7i1Q6U7MOT9b273m0QmObSS+Y9
FdJiPWXiQwC24bMuW/GPDVlrze258kc7kwKZXBftzmyp8JQgeO6fVFfcDtgCPRW6FcF+q2T3xTxV
scc826oh2VweP2BNzopp/Hyf7CA90Ly0fuKm9+1M5eG6/YfzwGuTBOiPfl3JVd+QH5auP6/qAIJz
ifiVJNCg0trxsUkG5ij6wu0bXWDBEauV5wZKqLF48iS1osiPTbnTMRM4lvskCNY8vOxS+647Wo1p
gipCdjwzodQnd+NeaTwP5KXNT8e936drGQP3tHYlYzo3UBOppjyZGSAs4CsLVqe4i6o4iclCk/+Y
G1mGIkhorUrlAaDjXqZdhBzfe24R7jDWw//3aLFCwQMQ16ODsOuvO7e68qTVT4i7sKiq4eItvrAc
XKAoKugfZS7PKaofRUE9lq8vQsUusBWTdv6pd45MW579gYZqcqJW6zfHop1TZ40+RhKalwo9DI73
T9Tpxl91mcAaKXRlP6jIer8fGv12AR8Of48wbO2gLyuRlpkOnBLcpjP9GuPquBZqK93BU6d5eN7V
SyxTw9V7Uq9u0RQfclT96KrSgO6ASjXNyKPBL1klsGJ1qrvQZe2RpZDKpdArVINw4PpC/Fg/Wrfg
CIeOb/h2iHOWELaTw99k7lH3Noqc8rPJP4jtRIJGh94NwOewU7gmLHtcaQDvTo8GIxHtlGA7NC5g
BYRX12RkIZhIZcFnjtKinVlwmdLe9Hr+TgaLdkgFdBey8QLWxmiP1/NKfil2EcLgXpUYxSO3tylo
+OrWOupXexHj6Ct3O5fUF6txNcxf0ZmtEzAfY5Njq/Cfa38oMcmobhqOsAWgtAyH8JYlf2pbyOP2
fYfIeGiBWbXgjza1Bn05tKBTImTRzLmXfTFKiMUjUPdd/qksO5vymZ3zLHnfZN40BfBB1nahSQ20
d+Tn3OpHZA96G8egObirtX7LlL1vSWAo2sXOvu4/ALl2TuXqcQzuR6OTHw/ibtTCnEvPC18VB6Rc
0ZKZXhk+en2r2o+pC9tWvVLH+n7bylpwKZvHGbRTZbSSj/2E3TPkGPvGer9POrCJBq+1N2hUAQKQ
vwcXentC0IvBZ70rpQP9Sfpjj0T1t1bdt1yzN9+AUpfOE+BWTqmswyvQMi9+EHsSkMqnd/Acn1uN
wgSvdKowXRSZxxTg62/gd5pn+FSaYxQV8K3BE5jPYJgxREBoGlxtz/e9w6l8/rLrC6wJ+m5Qw5r/
kVmTGNMflbBMzzTpZHeiOwslvRhuMNbmgdJVAI1nFYpYpdgaR2T2+01UIw9+5JOaKFzJaJGhpbFz
ALKVfgTbZbtH5NouL8/QkU7NTNN08GM2LqXbyMkGePyn6E98tbKA32wgSYL/OFohKM7rdRkWHIQy
Z17F3GPvXXhDdJ5MUUxmGfSPGptdHowtmHz3ZTN8aDMYijQjdOkSsVluhfF3N7Fh8HCleF+11UEL
W9CYGmJyPBA/sFb4zINpr6hXo2oKUk2mpGLWtEooUqfV4BIiI44WDtYfv4vhF20WAZw/MES1u9uz
cMvCbovl+1xVIbKgcEwQsIZZ22OM8BfQTMXiK2FSUQFgCilnIHnAXsPXnuMmNsOC392QyA0eTTOn
ojH2kAwoTnTczvhajKhjdqQeswKXErOuf3TInE1wRnO0HbYhwqQPkOZP+lM2nDYFYN/gZO7DhxwH
obSREeVZn4pNzCnaylleFor5ZRf38lvCfjfip5NWwaj236gjH+9cn/SDiu6kBFGJM7w7nWggClZN
b0ZZBvPbPTCxjwIUUtBjv+Hw35aF/idEKKqBbTluGQArgZAtOJT8f32QVfxUN6Cyj4kLKQA+Cv/4
vAgah2lULjmfnATzn/tdSWFoe4PuzVPgps7B0YUPq1dH4VeX67SxeaPnaq6RXSpW1IoQ9gW41P/B
SgXBBWtBogL/rzEWU+mAcZ9YIvc08XYkBVpPqqFkCd83Vaf0jGctGiVI0zblVTBQqPTLyDpPX9oq
f0XEfbY5kAbl2xg4mQGBEWkKsiC+pF2AyaOFEOxcgGgw0bLkGrwVBPIh3HYoQfQiB5VUmOl7LyAv
AK9DWI6rYbM6k70HIVANyv/9PlV+bwe5raJ5P5j6mf+1zQ+LiGbKavSb2BNGgA9S9ewX9XStiJpm
gHRXofqIybV8fn2gYuCx3Oo00A7cJbu7oDgRBiuxPJlNjOJzq7RtaDT+Fe3qwRdOzAKMxGOUu+1/
tELz05dTnVFaCj5Ni2GrF4dCTMvcm3/SB2l4j+r0re42Th7UobS2vsY1BZQMh+hHyZsD3BOLxEwD
g6MHhyJd7V3mPjTyPrtLh8jXCE4aDjyBkR+5k1c3ltjH725wN+H+iTke9PHx2YE6QQESvPgv+6AS
81zNdFdo9KRiTBa3z6CRhXuXKKJWCO3I7uHCMI+Ysd+Y8NYkQv42AJVfqzi11JAkVqFtF05RzR57
sd5H3YfHrY/4q2TV3RV2Ql1NMSvzQafD54oku7jX4rpIGshpBHBaBtvQgTVQbl5bWW5PjA5FtSqU
3qjKjIu6EYVIwdYoihD30uuk3ETQi6y0xRoydLLI2ORVHuD3znf4cKGyOEdKSK1DCHav6v15ZoqX
2gI3DBgltO84xlGH7QIJSsL5yBeYDc8AbemJ5p5yPpf0ikc53Hde+Z8OKoeoieFo/njjRPWIG62L
GIv68Ks0wLucpnXxZdtHY7w49ObgoEhv6o1J2NRywTffemejoCWV1nNfZ13REDt0smL0IDKakDdb
ssOkQpNq+MPK7ix8np+4NwSuzqGG0UZGgGUzt4t6Rj4ZSZhwYk8zBr4lFKY3SuirQsQy7/F5MWRY
9fEGBZvM0ryfYVe5dzQYPl5O1zPUyKRC0/Xa/SxTvv7lZhi6ibJaFmgPBlIlnn7XOIZiOGBpj3ll
y80sU2a1CNHUCs+axY/cfg2B+UzQPQOGHvhPBmSGCDtjMTtSfrCLNBuqJmuFkbZzh1kDy4GINaBA
QG+k0ByKSSoTtliTGOL7Dwe666WbdwfLhXvoYVjDX7p+FwHYv/OyJ5eNPNN0aZsj9rV1KoKpyK5s
Q0lbY8h3TR9GvUN2ueG6tg+O4mBd452veXaA9Xo/saGnsyqmjq09ZJDcB95vlf+0rPM5SVtxgRJX
bkZ5AsVKilPF+zVzYHfUj/O25b7FQZPIaFxMnNYriZy/UJ2uStG+SpEN+wUFJKMQAOIJ2CgCxJpp
ZwoB+UrBJgzPzEjt6Z2y8YvPwG5IfcLiH2YXjdfWFiR0gOmJtYDern28S9T8C2NmfTZd+VTlx2XY
l2MTZk4rekI9ZvH6178hE52lPeJK9SM49+DFXazBKEiIIsOum76TWhbMGPOqEki3izZrLSjvD1ry
DE0xVa94QoqLtLXpaY3/CzJr3zTg+J5gNcsRDmTTeJxQ73lRJc8iGd+ejlNv4iZ+NKqerg73EKy3
zZqos/gaj921yChu8hDgq/FRqBaNuOamKQKPrKIoY4/o+40dE9RFcrktpTlU8t12RiC3p8fcGMUX
02ZK/mGpOhKF9jNQQ9CuSMzv+YW/gPvlznY/GOaEvty7/4Qj80muvku/PwNWOCgs0gprRfXFtyUF
HEaxEKSd6E0SohD94akHJKi7dUovCa5nwZAFTo0z2fSt9I5wHhfBiH7EQs3tZSu58c2LDSSlCXAW
3mhPDT5N2QBCSdFnvcC1w5T0PRXygGyNqPcTGSvO9OgusGQDjGmmK3CaEjofmkXkFIdnK4p7+Rl0
Z3xxyz+eL7BCE3qu5q3NFf8Lsq3+7c1qya9/iybfW8Zeyxb32R9M+Zt+Eoui+WwrHW210PUT5Wy6
0iTHWXmMaXCk8wDUGLw5QsX1L3KJfnBb7CPr1mB0x6XKAXHqAd0xCFhBAwxR56Bw0z4sOOWhSfUe
A49RKEdwf1JmPIPPyGfNw72YVPAN8cGbbXoGCnMTnCFy/B5mRpS5ts9blXB12nF+pSVbjmh1ysn8
FHoEbXvVYYYNl19btLV0i+XNwj8z6k3z2lUPT7zSoCfb7sgAcVfocr27Wmprk+itD7BqgbfUrdV4
nUsVclsV5tUMTW5MVFyBeHZG6TVDS9dFfecDGBTUaU93lkuD25aATEEccFPZgg719fojNah26wjn
93XVpRpo6hGHPtqwAIo78ZAfRQmY155viCO8vDM3YkkDzsmJeXHNqRjSGIoAmWbQ0pxKan+5ZpY5
1RMMWdbB+ynn7FoJ3J0WImfzi0BcU5/ph+WAF+W8Ei9k6bKJhnwqTebD9cxHbi0Zb1XMI3oZv9Ha
Epouwi/9ZTaja4QMQd3H9/bhDZpaBCd5HUZKBh46MReVudxbqSkvbxv3wJXFIfFTNrH78bQKvnjG
pQwXLo81L99U/yDlZKmWAJzUHY/atWYxcV3Hnbo/vGfKY0u0qicxZbz1gndWrTX0GCE5wKKuHIdZ
xZzGWeENiwHvQ1ZBIp+h9e2rkAEL5wJPnVh95jwiVk5STi1ltyCTwLh4jEnNeWzSI0iZY8VJHnMt
5vxVLh3z1ZZ8TtAB7pSHQQZ6PCFTh2JCJUdXyc3h/AkAPmvczyftVFM03VF8mn3XxsdIHpbqg2KR
PM3Dko9w4BtuvSpFCInh7djoJhcI7brDEo43M4RrkJNWbVGj9SPl49Tsx70uv4WfsBxSjLgebJZA
VTWoSbrjZA+yAvg63zpUjQysHxf7Ofqyva4eZFEX001U+U+svso3ghWogp/ewcdQaRYIGw3cbSQY
FOqXDkgdLa9vwBlifr1wG3hLfcL66FqjcRoQrp99G+CcSObKjN4hhTIMIkB2WyFo0slOAlu/2SVQ
lkotSJbsQaC9ZmN2/0Dm45nYHDKzdC/Bq4vT+3AkDpabVOCTaXjwINdO8dq6DZqlDJHU5/NeUa3T
+pUufnLcy7mw0G3W5nIyd9htxfj4czzgK2Rr1PS0kxb/Xyh9RkX04M6iQHtvwMGcEDOvzO4PKJd8
pIVT1Ff3rMBWA00ShAwxXh7BMA4VL0HmJ5nkVjcJRhKz+e0GFCxIwU/KlSo4bGS6tadh0ngEqocG
zNwRVTYn5QrUt46LL5O5hQIvq4QMWfN0l/Dfy2elhSXlQWEhYO1z/qYAsXH3k4stJnNqjL2SfLDE
VfJ3T8KwUSvEedwNWOKoWPORpPo0rJwhjj+Do1KSMBnP9kuZwTpS6i0aAnRCyZv3HV1oDRYH2JGW
15PAixHWjl2USd6i2On+4IVm/bTDgGse2KGzOXqQXAqHAgQB6Vrqae2pJmBrlyCUKWnEV5Mx7I6M
Q8Pk8pwgG3yZZ3uvHfMxrKdYZ6Dgpq+w6ej5Tx7jBVayhOZtGIfRY7Cq5c1hm/S+FnOagjlfhDy8
IbvuLrsckkgBjbWOSwOUfqskkMz19AodEHg+xxOngMXNZ4iwfGOPaPtP+0G6YjM3qmGG11LjINLG
FzU3qZ/VNIVX9UvpX/54m1Jan5oSlgCF3ZiAxA6e7gEfmw+Tn8ECkBJyHFRg7q8cAAuKhW1qDpGN
GEhxVDtikTIgaPy1hbwQG2SZigpXbvLsEqhFUlhqhs6XxqyJkLV4sVOemNDABDf6We5pPmVnUHrd
GgFKwkJtEazJFXVCCRzXIT2m99zBJfF+MJ7K1C7VZ5ybEtNMLP40YV2c5G1SQ4m3JMiTQflFCqO3
mxrsyAWgV7L6eK24YYr93enI2XS+CV6GCv3PQxlGfBAxxDKu4Wu1dsL7JAUfSH3Rocq1Fso52dwx
ZGz4Hv3kXn1Pwmw8ijneuDvHKTiTZetafRk8rhP2VGvcdQa51Vz8bPWqZvyFp8y2DWyh5gcoypyZ
pkeDjf1sW3Agq331rvpfrP+Xc1atoI7dc6ZydeywaPRFnAKScSFZXeDVp3W4p3NTYXoU8v098q3e
97wsgu2+xUL/ZGjbEFEN5xM0wkBlFKmAfBEN0dN2Ga2FV4Jhn7hUkMdEjsGR9IKIcYRBjOaYm2Y0
+8bygrky8wA0YXAmb/GKgpsceOi5PgiPuQQAkBsC2s5E1FeDXlcqQ9V32AGMBTWJyhXwnHvR3X9F
5xM/dYhMHnRvkP4VUNNv0KqmGl364zXdUXR8VhWGHHXUkzhpJp9ebeMgmKLS7eS0bxvU/swSZlVP
mSET0gZfagl7laRFJNGH8gmTf6J5uarq+AlXfviCZV1+j0uqCh9oFzMFK7OjtBrB07GuaYcvhjVe
NWlFd2m83t4SvHmWVDiHweKtHX+TrqCSgjn/3xQAau2LCrJtQ5+44wWnX9FMjlyh4UC72BJAYcdz
FEt+/94SjJEqL+rXspp+gjXrYz2McWseMYp9XTAHnkIg9/0IJR0cwj+xPZpe84geipYaifgxBukK
t2d1E6vlgZxGqQsDPaXTCmhNqj31MFGN8s8gRRh75/8nEoAZPAjy+2i/c849h0DdtR2MXhn0DMLr
GqZczXEF1pnK/sE7/8LfwJIrd/2V9q0H/3rYtctVZbPuaSXUHnZBhGl5BsBh0u+2I7VIihK+WWZR
trUEVaIJdzP3aKPanbW0xfvCxCbuOCp6TYcZhFnQZy/zjpQ4nRjUrtl3U4vEzRyf+wHb8ZKof9L/
QC4q8emIy/Qg70CTIxPGR3XxMo5YSdj6caU4xqZWwINp70kpb8C6kOlKw4fnoLbsX7c+zx+cTSD2
lLfPf+sfdLL0IfLEJIpCQFzxOVAfEamt9FCQZKAhmenrjnJjeGEaVgbTUJE3xkFcvNzyqDzu28f1
72fW7FDLpU+gs3Knc7G54m4Omj19tRk4jrU4TIxMWayQzBFvF701jOV9opVxjKwqOZErHqMFriQW
sw5Qa8H28+TkF9Pa6UzI78dl9u3grb4Ztxt769th08QLqKB+IL3CoCldpbPEl5K4fFnPocVnarRo
drSXwlDWgr2A02DYblaRBLyGDaaV3xcYfF5IEo3WkTD38bm6PfsYPpnPgyjYz0/pe6p6YrdBIpnC
+BfN1BlvbFCSzZ1l7HfqBNgAH9HQO3S7apdopNciDdkX02imCJ33upO2FyLoT16SvwDNhX3CUF7E
c4MmuMTSEOpK1wraLRkotQOAx0HxUAAfxS3oFp/5TJD8SgEtdusgpkvSEB5DSVTBGkOH+gsJWW3P
aYI1sHqXx9sL2hlaUqW3utQDApyxotdcAimcZQ+oaoNbwXpzdayT/LlNQwytjfrp64EWQJBvXPR8
wWLa50PjFQNyOLcXvL5P9Ov60S7gIvkHa0D1OTVYwNqIpITYDRSKzE9o+T9S780spr2L4lYiOJaa
ZfrcL26/5AOxYHDgYLu3Ri6KT6nnm1N1gANHvwgTVt/e7ZJf/RfVB1OvxxJg7O5R92oQvbllbW1u
VYYDi0531I/WUVqjIHGLlS7173YtAAK8br91SXW9rTVuqINsGhgPm/XqZxd3o69n7XXupqkMM7di
ch/mWRfAU0p3Zs/guong0y/EyUzi2ufEO0WzzgTqPzmR3so8H+dLgMYDlFbLfQwoVRZZWiWlIuWH
xPtLp8NAdl+1iAM0j129aTP4BxDb8qq5B+nL9yy6aAzHG49gvkZBRIVXl3hUVoSGyU5dxSVJ2Arx
Gvz/gw4Oe9cF2nwOmd9E3kPHeGFUWyp+uFQm1FlclG+aQPyjgRBW+4w5Fsw8frGJQ+6EjPdEq2Pq
lKMYAojvd95MSic9qk2ElTUdWQe/UBbR/827bzYu/Kv/6atiLMrVLYb2VKrTei60FxUJZl4hLk6+
ZpB+pDLZgZKT5fItmwVJXxeruCEL8gAfsxM/rDZZi0/ixeVCutdBekKXHRYYEzeF5YFPwcVRkvqW
vGqlYgpWcMuLq/wUM0n3Ol37DJDTKsVty4N1tXs0OnOhXckhakn+ZeCg4wRMUzGg/huAYU/aP2Xr
S4Dxm189ZG+lOMD+XX3AJdQTq9F1hWtrC1GgNmhmeRgCt7NuGx+i31JhtCe5wAGTjX4GyQZ3ig0N
csvF0N/b95vNuU30qRVYYpPLjzuXdFrQb205S0i+e8P3u71dMaMreyiDTOZ43hQzYsZ+8xMMgi6/
zN4B6NsEivIRHMtCn9rHk6WsQn6Mnekp0npkwwCJJQ1LMvn5FaR1YYxzVStATUX0MO0qJ3HEoDtS
I4AzlJNyZGcUWWlVrBe3t+Msg+TIb++zn4HJl6nP4tYe/tovG+GNvqA8k2KfGyv70ght0nIm4Dh7
dIFc+yq207ZbnjiiEUp+yY1S+X6D9RHOx6ZweDDUXT5WbNJMJapHlg78wJmRDGv6FAuO3G5aOhii
NrPSm0bnwXBOj15SfXqq2VmX4TZ50qfPsTSJL6d0Hdh3vEcGwV8HP16oB8zVmAzyk+L/of1hZ/OS
24VSZYSkmcgCNmwDA3vm1y2Qzpa4MfHbTaWYueRjNTLzD8DDEzphy8talhkw99vru7LqhlGI/e2U
syLUi442Qjq9phV0MExPbAW19mAplLD2aKzfy8DMQznBACjDa0Q343LYIFuOu9bMJYjS8oUQ0zTl
3cMSw8U9RsMRiFtkLxEVRy6jL7zy9Jc4Eh80Y1VNqyOVPv7eNj0Q3hmOSlhWNnRAJnL4EeXAaU0R
DK3BlmMIO4VEC6Ng69nuCeNnshYhUjXUZQrHfWruFTX1cloixNu0ZViomcAEl37iX6oihYQNzUv8
a6EYUsQ9ydD2q9EgXgCDa3C4ktE6Dy9TEiBgkETLkLNj4Z9SjmKqWiols7PsjFMZyV2+4hgyhT/z
Yv8QgNGyhv9yBwaO0FEv0y9blsMeR14Odp0d1OBIzRuPIkegXZ9dP92oo91xRUJpr8ZTPWU/9HJ4
+scSUlT46WctViJ1We3SxIvQYULyzpKvw+hWIJAv+QvFtIwMIhmVU8Cyf1l5qbRpLmBfZumd1pib
5vvjp9L/Ahse2iae1R/khnxN9iv5Y07MPYqd3PE6PtOAe/hKsvv/Tpo/vL5ION/UpwJT7dZCbYSU
MFttxysxwxZIAlZaYNiISdEQWTIdDlI41xI2sMuP/+BsORpStAE2pdUC32wssLskWO2Kux2lZLxc
vNn6HuTQPNqSE1uPf4vtk3YZfQ7f8Qz4ht8Y3uXxM7MS6aGdiDCsEMCfVMlOPvuuyzeTYII+giPg
VqScBPZpmI71ySmN0bUUgyMQ/9CZLukeIyP75UqZ09pcHAwMw/7/Tw+7ArC7sUMaRh8Bxb51loY6
HFN10l0rD0VmUXEU/a9C1j9YcAxsPjqRpm6G8etqTE8y3yObyxUAMFhhT/ZferlOEANc470eioGU
DZF8d0PdaTEpLjbG6hgxj40ZY47UW7swV3i8l1UmHqyaZFstDmePk/QrLE6IVEp2EM0TGeEboQ+A
wU1832ReYbXC1TEC7WQi3ArX/Uan+t7mXzYw4tsA4kB36QnhrOi/gNCBoKdiVBzeXKGaXEdSJJn+
PMGfandLYTlXOMRp4RePirfLDvJeejSmintls4hhw+/OSBuyPhpQd5eth41klYYJi5xMWWWQlaPM
avnZmXp02AdPYGZav3O1DlwZe5jTyqInDk5kHW0xrufW2IW0xK+A6jCuSV9pnLB4q+H+/+aK1Ouc
cXyl32UyklwEui6runIZPQLtzxvwT6v4JezBSLulroGzkb7K23hT9bBmXgUtY6McSzTokMXoZiCU
URvYSVujEh5SI/ZWMzLuUrQgiZEI8FIISXiEOD4iNmgDgazOO9UXCD+Ml/uVWvUOswWW8BCtfSL8
cYwjxTG1qR7Fy1wx2U3x4XM1T16+0x56FLDzfF4wOVc4sGkXZt9yYjO+Sal/F3nxSLdF5sfJ6q/V
ZX3R4JBIMlB/QrHJTvMnYHY2W+pl4jij+UNZAI86agRkc/WadfM1tgrr/8se7bl+KUJvc4S3nlDt
inDwcIHMLGw1lBGomR3BqYxNRiTWQkxggkPFqqSA4RQrWBwB6DghTbkzVXMiSnCNTQlDtTDCZhD0
7NpqAYFeU3WADHGnDQfvPSNi96RKseRs4cSqsVj4E0b+A3TdUh2eVkrG1Kvt9B/xbhlja5k+YJ7D
R062qWT/P9jOd+2Qgz93D6trUrfgd4tCywDJ3fL/DN1/rZFlVI7mCDWlm6qW42zpSM22EBf9ooko
WoBEVYG9SDeJ0WHcxY6xBUN03O78QDaEFIwTPPv2Hsj/tX4tOkHhE2Is9pOPdKNRrATc2ymrHxtf
2D/qjUq3ctztcXDGqXMz1TjTu60RMYERv9xL74S57GYjRWrEf+xmZ75iJjzIgMlIZxs9oZOo2F2d
ETKyUnNK1y63/ibuuYDITR0zv+9LFm8JC2v7WkTtIMAKMkOc8TDtJp56+DRZiulDS4Y2omcefjJd
9Y9E4z7ZMp2geLZZ+pv+RSYyhBcQxxRqUnwvie7m+Ipg21kOEIFwFOa9Ls8zP7MNYfuI9b7hha/U
0PjbDK3v1li7WAYNOYwSZd7i/rzqeHPo25uK5uf4QbEauBOvEN8XLtr+XOvPdVLRbgs7Okj3i45D
hjuVd2gvy+IZcrITwZqNh59ZM48b+Mx56YyH9jJxdpNPYDcuOpnwDVz+S58V0SAO92Wdvfe3e3j/
dueOaPyrp9iDqq3X3N3GvCwmvS8TR2XTS6dTCQygW97wjyp2UamPzbYFXP3SjXni2Ui5sI0ly9DY
BVCVFC6HdyN6NV6oVLxpQ8SmonfT5ZV24a4/t4VEXks/LUVMiS7RzTeCqgUofT/bgrU+wt2UUCE+
VPpjSdd0bXp33aC26si2SaFdrlUqLTIXAJUymUHC1yJ7Abn5/CdfpqFXj4wdi4q43EVXw7ZgcqEY
wIWEE6myrR3SkXZA6c5M16Jy0Fdk4fSE5KPB2Di/AYm6dTjkxQ4wDZUmQL/u8TPRPr0x1vtChJab
Yb7sZy6HUC0KRayNeXLJAM4NABvW6E2UXWdZq4bqQa0elgCkII80YpAC9rZvH2oPMH9u8HdPyt/M
NSr4+E7WqEDwxyEA0MqBtbvcLAGEJYz1U3/PziyvlfbXWAOye3lo2AZ/x6tJcHI2kgbyhgebeLAF
+qv//2fFtlTh9pC9JttYv84qY9Wpy/TzTeKGDXFqHj5Wxd/uYLtpo4xSIrWMBDufKPTeFUlkw/H9
ryLJHqapesx2wyjd6hNxc7iAnir2XaNwI1HiR9uKQExmb4pY/2wnYE4dcew4OWwTKyLHoR4a+4UQ
f8vYtr3FJgfaaxPBgq02Uo7t05eHo+44oIWFxloBooAizaryfF+1m1iK1QYp+Rwg1aC6nT/A41uD
Js3Rh5WtqPva3GgVUbsYK9H+C807T/xlsrFnlbpwgyDg0fVURvwI4YMvpE7U3MZjAFFOzY/aSib/
qbLRpr/sSyn7yLk+ZA4Y3k7IaIyrlkvd5xNoRzudBoRLlmnB0kLrqRf1uf/I9QsleCbO4t/0wMSV
zCffmB1OwXZ5/bJBYdrJqXxCLVXNHgfC+IoSzN/kTRhmUMwG5wUvyHyvRjOos6PGQeNq4mTJeozN
IZnZUJ0wv+xHJQ3FDctS3J+Z+eQzfw83CMTGZQcIHS+YbgTluwG3YPUtAo4R/zKKbWICeQcn3vMv
sNW7F7hBPdBO1/EZocKsPDH8KiLzZf82qXYc3YPDs7mFJPpLhwhVHYdYI2Ax/Apj5CfKpkeU0sh5
7o23A5P9NvPO/2h4AlFQPBPnTrUfIZ15RjmCTRzf0hGcug3YI4x1eMJOgTN+ihueLRPMre5aFih2
9wBddZZvJg67iCDvAKQ+fMm6JPm5C/ziDQsK7UcKhJ/g+JmfugCM9BpJXHP5LiNGxaKWN5xaL3pl
E68/JtyPBFh/TaVR4cH30fa5/59Z7jbOoDN4PDetgYDh+fdJ4SFf0gsY1IiMCYYNA8SRn0JdSdK7
fxIGRWUYkZvbTLPhhgZX9XhsHNkU0nVwtjUX9DrC1y3YAHY6RI+A99QODJbpHVACs4dg2JtcZVsD
c+7a/m49NLNbqmedQ2erUbW+CjqJ5w5w11T0Cw7GLw6AlsWgetchjJKafSLhbxC1cA8Dn4Fs8NQU
CKQzjmhEn4GcsJMzE2aMuQumVzOe0WERqYpme1fqh3bkP+IY0FL8nwCFd4af+r/E6t9ffxiZ9StK
SuWAwZuFzxvtYMmcBly8fa0YYiQDyd1gBD97rFx0s/In3xByWgf0ImfUHKXAmG7fb64xL9FHLHyV
e2ITPoKQXjZrIcJWmjabw7wLVg3I2y43Rq+4FRTInMirUE5IosdjHvskyBW+TEgF/FoJcHhD/VDr
vSr53r/zbPI4lEyoumwfnXbWh1OGVjnT/WGcX6tZypdtVpWOWdeOtiV6jHl05fQMqwladQAcqc5X
PLlyQ4t6VuFZ76+70TrN8x+zE3LioXyyq/2YY7TdIQP3CeR669i7KRFfqVl6/Q8Fi02LztMTIAMS
Tc9b7qxcTaNhzEBeYPKyUQpesEsrzFNy2fWP7/uctogngxckZO8piYFRsZT3gR3w1ChE/0BdPCRJ
7NDxs5D+9522jCdRY4mV800qaWrOwRoWdeew0fh6WmKNuTiQLgD8/nBfvyV+D24CFsoobhXgtGjf
UZh4nRQCuZfcjNjWPxBpHT3oNLSaCHE3QgWUVm0cBwigk9P4/E8g1ckLTjeHE8/CFfLgJG8LpjQl
aP6CFEFGVuvfeXuZvzqfyn946vFilRsj2UaHOrHQMnw75KAQi9eCuPDoUUxvV5vNcy9H85Ci4CcB
/W1jCaUoMM96HWj9a9pCo9P2riJcLWImhtiBM7LZ7VdmMxmsllN9v4Z1LHKAV4ouEvdCclEgF5E5
nimSvAysZDbysBOSxhxrJ4KAKwSHBhyrEwAqj8UbXRneqq0Jzrv2VdCv30NabLcVO7z9y6QtwcKX
6QXTgpX5K8Wn/+7alGKh9k069O3mPs3c9IVTzd19GpZ8iGcpvQeP8OrFDE6ndmp/51PteUyRahDc
HaZmIdvSokwahfgPclP4Mu7VjtnSJUZB+Av6VKCtLOOWx9p7rAa6ClNrjbVov+NTmIZuxdTeefnO
Xk7/hUnzwGjTW8DwwhrfVtJiFHmQzlQU/ZB3Ewn3vZ+3PpLbKrBzlorzVyVpx2oqK7WGBMk6G1W2
q1zCb1Tpydp2LelestY5dwuYoZsQPf3kJruqBEohVXmI/+jY4ffpnsUzbWTDpM4IuQMQ1lbJhPw1
hNNO74BgydHkqGD7SELo4kQUG+XtbRZrTg9LA+LSlQH8Pq8Te+giQLcLqFAEVnBSc8aA0MCQ+9XL
vhW04c5tBmW7yuoDFf4WVf9ll1rvVvL6qqf4DTIX/Yc0lXvexsU/tjPeEywm5nOuH2NVvnVVXDWO
cDy6uQSiyDbegOsgDRXY6rZyDIhwsbLJdzhdiG3YUd97ZyD188rXRDchlLXPs9xguOUS7Odx+dKq
26dAtWE5pNqekel3994ymbg57JOexyk1ntuk9aubJTWji/M9TFhKujv+eJrM7Sar6RU3ScnA1413
YC1fgNjqJ7OJlud8/gWbPoEH5D9OvJO8TTLnL62My75XlbQF3fp873jHMYDT+rdWL4BHQaUOSjiO
seFCxdpO8aevOsRQPESLy6ZHbVUB+HEDua5VkSlH5k+ZaK+9L/p0m+rZKMeymWGAu3nFjLJa9GBT
6BFzzhIxBVySdfA2cqMNX0yF8y0B3ZGJRIiMEhpwBnCH8gs76j5ipYcIHtBgYF5Ff9oJMMoHYeAm
1o0RfWIzUY6gbEc+OlOcnZZsWHFOpmoAKE1zdnBUxY8w75A0gFrbLbD/Nzjxhog+CLNGCi652+CR
k//7h8N5Pv0tLdXP0c7P7qnnAHKmBOXFYvLY1sxTI/WSZgfXlc86zwTvpDBnW/M9Di4G4TPTHKZ7
4dwJ7tChd+XifSGv+2di+tug0kCLrTB16MqAbTgomOPuQlvZiiJ+ie+wWjiMI0PidcLrVvaKHU0U
iZJ47msjh+7UrqjOD9Jf60T8+tgec+OleYMduSyoZzOxbvqwSNUBYMqHXV93oRl1zZ8ZCFEI92i6
aH3/V6mboMDzSHK17QTUTkFg1Q4eD55I6/LED8dWzCkMDmZPkSwLUP/wJchmYjzk/Pb76V3K65mK
sn2n2zvM9uTithjrJKj2Ym62Na2JglKvHy7B/MVYjQIcnZRgguNbN/TWX4iVYxmhYOna9oj8ja1p
PhRb6Bb1ax49tQmgDyxPCduNNBCwyKbEM4RHixnUyWNCnhJxztVSOK1wUnOv8DiiE00e52JLHBDL
TrPdxTskydYIvBrmGEQ77EFdTCQQuVGK6lH5BluE1cr91Vg6Aazf9GNc+q2rHB+hiUnp63AJS7zK
nl+yXOxX08EKFiv/Vef4jGV6DmSsDq6iHi0efWk5tEFB2njZgUQ+9OyS+AEEPw31OARLjyi7gqet
qQFii/QrmVIrNm8vZ7dKGoDssmrRuBPeYcxzFrAg6igkbdhbHTXg154EH+YkMfUVB06X9Zb3dVW0
UMdZcJ2Eu5np1aAD2Bd9h87m5FyQLe9NfRRayvk9TWlgqPeHLKYy2zZ5AJtAoSGX8IVNFyPl+SIt
xZNYHQkLN8+9rL3Qio0aZWa/zhgnvZxkDzRb/d04Tdt7G6WDZroZ0wdhBi3JmdPqP5vaSC5m0NZI
mmavN8u88urWACFjjQ26jKzN/5PjLuZSY3C7aoMFA6avTVB5YxMpppty1WZmND+6gDNQvoBOuuhT
i95wIsR2/YGKx5Lc3rmPP9W4oDllHA+NkBCG5W3DYbHcu1RVB5TzGOQGJeqw8mRvEtQSti8VN2Y5
UI0rim+vhE2KdgTlRXp3UMNfWvYsGl7/42Cm0eGCtzqTnEPPSo5PxgCQ8l9E84IYkUFZJC5wGRYl
VIsSrUAsv9U+8g2bdqlmzeRboHM1EwVCsDLq5uSqB3pBJRF/mNFFJ/8e49s03CVMRLWZ06l7bwCO
5X5Z7ePTqGj/MOIYpT6byxIAarELrRJ9ULm/9vejWs3xQk+nMXs6Cu3fYX3ubbVTRAIEiPZG2cbo
w+Z77R3hRzXtq8sVVVpeKXai3LWnfk4xnTIsxkzkhACLaJds+Tc4HZvGhANixLR6mKdmmZHhJiJa
EOwE415REA1eZ5qKOHXvndDmoN4J+diR3BM7h9vPJrSIfdm9ZDzOMvO9Ifx3V33BTC+/JY1ZGiv5
xv8odKoHi+n45CjIKa1/Yw1rKR3IwD+BrOuTCDlL6kdmahm3hQoKG40Ot8xfXTvEQpLqsSOKOFLL
GFaAC+LM/7tUaEFSQDDyvuTxBy+7NpY2hGPqIrbmEKk52Wc+cRr/Mb7ya0z9q3mkyXZDZZDEPGm4
ZLuzCNur0kOoBBUErOUrMgMnsFQ208AX2gpGFxYDFI+xAaOflUINvNPyxS8bJqDMge/tyijUDaj6
zGgmt7l0TlFwKFj3uE8tuzSw23X0HihAJcVWeTNfLxC7Pzr1158k+Zvp5gAPsvaZ6Nh8Q6RRJ7xH
DLf8LzRBtnbFZOUXe9/r1KHkOQH2KBRxb+FFAny8qjH5mTcMFDBJB8IUKSCiZerZgibU9jwDEMLm
ydP/94bPHsdwo7GoLD7auTdISSPY5BRBsdwm+2tsCoJ7eiCl8nP8ijZurRfz/bB2N6xBWW9tgyJH
XFwmxCVUfX/PDHfIq3/5DtdMLTeEUGGxEAu+zMl+QjpeY26tC4WLhyToX3dfWm2IgZdUP8Z9uCDb
zx5Z/eKnN/mRu1m2O36pTxnDnfFoWo1keASApr5koEzQfqqI7xtxlaVnnXbYfF2K8EWgAbHPZ1EP
fzupsOL8cWMae02q32uqGOd3K9ZoR/KAst5AbOIMSbuYOImkfjup12AvBucST8EO63gaIdoJKOK8
7tGK4llvz5hgljnrLXfCeF//kOc9BFjSRAsoRVkYamZo0A4Y18piemVfcC5wL/G/wWENAVUNJ2un
tSsaDURix+fbUYjAnc+pugLtp+fuPKus/aVqUyfR14wxzmCSAyod3MgZF3Ls55SjJPWneP+0ej3i
svLYgSkovgto3gtsjYqIiOSo1dkiU1xT6fxGQHP6pL4/+BqjuMecc2vRItZO9F3lVNCeZZyjbL9U
4e8Ctlu+qiOUdKqIxJnplUz2DWJHCY4HRTOA9sE7XgbwlvxRKuLaw0HfZfxO/dMvAa4yHLka+WRm
On59W903XSY6NtIYeRzGOXgXwUFJgkTLf8g5rEjGXwPVQBr+57oZZzAT4B7K1DYBtDLSMdMz5nkU
dZLwn+UKvol3dpUIxHEK9VTK0WU7xapdAPgGppOt2SHagu278jkHWD98OAga7LgEi+vsH2adjbVY
brYtxbfIHjO0/eur1a0F7xwHsovk1PI0x5k0KK4lfTX0rqcfREtcdeCdtu9xm6/UDFiJx6Insa7p
FNqdA9t5aHgyltunU9St9MvquQhE65I2HiRJyECIRGidM4Wk7GBVnUd4MN/1dricA6sgkk+RoWfO
lW+oltH0njgrT1SFim4UqDWn6kjaxvGdqNgqRXxvBQjrJMN06CS4ZAaqUBjd4uY8g/O1TQsI8H9e
20fQ7a2IP/4r6oZ4E+Y6QB2Cy5Z4u3Qa6tg4dzDazlcLxqMCAi0UjgOT0oS24/ATpe2K578MFQa4
+w1aK4OlnDZBoi4+GamxW1z0dm8ZQe0hM7pX49BghCnKqyPvG7f3izxT/pGBSwtfb913pp5LXPxd
CWAewt84c8u7z83GnO3tcovhSIiEg/UqQT5psRAu+Mc68znoTVN4A2sFHkF3YDZQMPHHHIwKqH2C
fFgndwl6isjKkqwelebSA7pTAkIj9tJo5r3Nsbf8VClw8dTGiKIzejclH2nOOVBnBXYBzo2MMk/d
kJp1tZFfR1zO5pX/adPV4GWkgVOg3H9lv2rL+pirMisw3kdR2OXDdX/5RfV7YrefCa4C9BaMJHJU
iWxZDq5GyX4zawvZLhrrYMR1AzSTX1OhahKDtjHh5EIRRdRX0jSigsqn76KEWvP97Po7mqLzUsD7
jp7o/cgicz725ew7mBYJvxDF3PjtiwkPrOwqEjVRItoJrrhCizCr3hqSv9gezGnKeeLNZifhWO35
kMjjDesU9e7Mn/rfqqPUbQyy1Wb4Xhqek2UNjVGt+rjuyPej4cIwGKTauGZmUScVzo2jFIApYhUR
kVdYaIiv0+7BFQL9xjJ8B+1Iqdi1itignn/xU/iLQ+Huttp1mCGYDBO77m/qC/AtspwnW+W0rIEc
Hu13WaXQGd87TD0ArIxxZaSNMurCf3qHs7n+eLXA4rMJZk6N5XGfG5ZnyXf9vYrEJtBmURcVX8Bv
pfBkt7MiPk0oJmluNIHiTveooLJtQF0gJS02l7fiTj2Jcvus+I4UpN133jhEl5N9JQrNn/OEqPXf
CdE7NrD2VT+xmAU1qHcIhnW5sDrJS12DzWdRySik+y3sqSLCpnjysWEG6Irck8e7qzaIZpikPRi4
xmOygALiazdFeBcHvNttRvb5SAFy8N+dTGFJzcYZhpj3XMpFgbdiDC0l+gerHHwVWbUQQoCOrGmv
C4hKkCtQJ7KW721eenirjYS0IGKU2pH2qZoXBesTJIPpr6JZ7hvv5IgP3DKf65XZCpKdlZB+Kuw4
QmwYGc7o4aYneKmMAzfLJHBL+FqieuKz7A2V0l1SY9JMqmcXEAkCHxLUdveUNvzyXHMtrqilaFRe
qi+A1BA5Dr08AwSRkxCvbVxygpJPWw+LbCOmdSxuYcbHOqN/tR4V3DLlZrNNSy5zbFgIKGCFkoQ5
gDyK4l6GJEszuAuf7T0vBnfADtIgBv4U5A3ckZ9Dcft1uT4G0i8KfIlGLA3+h78ddDG7NJ9crj7h
42/bxZqztAa20Du4BkgQWiOMm9Z4ypcCy8mUv8y3eW43w5XjM66a6nT7k03fHepRkiUAT2qcqBNC
ijb85AnApWNttNsX0HOBlTe7toYrf+4dfxjJe5S5lrtTh8+RgVpWVhs9FO23B+LPaYMAKBpTows4
K3IYi7/G2QbMl5/wMMzH09yNrdJ9ZzeSGEjNT+fGF8XaYmkMtqQfFHKegnJcbVFD6tHVRPXkXP0V
63FBGZRHrzxa59sKGHhiO+kpf2VXTlD3KAQRhej9UN5rFMpf0h9ERyhInng6S/+aOKOejlt+xnF+
20ofYQFCJ7lrcoZ/5jjFUsxMNeEL+AkfmuO+2apC5IoRiNbgNE/+YuIMYJcCTCRGdgzaEObb6J1u
Sgi2Sz4I2W4rQA/VSERDmZK92A1N4EybYncSg5LXVNhUUhoJlII0haHJfkBHkLK06BHJIgw9lNgm
jiWKwQ32bfkDjw7gT5oGKdNTGuqIdFf+hRsSf4hJsej52KQpVhvAielWySFxvC7OG7D8Lku0koIy
9g7WSCJSLtDKR06oyTDVRlBb0N6YJcmFhclW2ixmAQLUujcsj5bXGFQrqxK6w8Zlnz/og4GHwzvT
tVo+i1Osv0HKXGRGPHkCfU4gb4xOUl5DnXoEP2EgN6tbfbTa3JkbFpZROXumaaTAu6sxSuZUq+fC
N805FC9Lzzu80WwePO4lHRezIOSFyFBRfgLH+TDZtqG5DQmL4USWFDFKj2Bk4d3jlsG8Q49SogWx
YPGf8Jl1lAZBkDFa3q9ItZj5t/eXJiAeOrbG3hhZJolYFmLInxBbE+3P5N87ylbgdx6gNIzZUotd
zlm6AnkSnclmGxE9xr+JLNoNKUhkp3CgmKVTfkwDYUqhz6g6krQNVFt6A3TY4oMsR/V3biz4ZFTL
HPp++A8jMIxi95shOJ66jWAHVQdCTRjwc2JRPZ3kZZ+78G/7e2kJrp0qIcwwdYxpUT+PI31y3Pye
6hCylzVf/RtH+JynBN22+Gs5XxfV0pnOht1uBDpgRVkaerKfnEh3mfbWCcXAc1PMyU28rh8rgMQv
PFoYEJRYTZH6NAhufOuOUorJMywwlxBJb/GEPZiCuE38oDwx9yF8tkdG1XV2Td7excDxkFwR7u4R
4Y0XT8bNGu5blDqqjsHreYlji2APRf1SBrbGmrVhGvR3Oy2ggaLJbwPdDFnK+8sEhv5+WKb5B+GU
wbPtnC0sGUmrlJ6zOcS1inW8+Gv9tTQlOzh5fuc0ybfqzCb6lDljlPMKkSWM9I9lEUXUphaLzOqi
ujMivFjDkb0vSvq3SbNqFKjDjFxHvNQrXy4LgVIMziArvgJdBjric9dhZ/LXH5KMI8u+toFUAOjP
K3h1ne9fpmczr548opGP4zJmmj7G3sIGbKaxvTVYd1WGI4D6BTckeouHwpTtsvfuhQVMXyaB55Q9
FM8F0xU1IEP2inUhjSILF+8SJlVSdxMKbmn7HldcblYjv6rakJduDD3ALaA3Z1w23aAdBqlIAYZS
SvX481WtIsk2ExVFel3IAK+VO8IerW4cwWO++6559QmGmp6wpWfLkVOchZWukglx081mZw8l4IpC
YOmaUCO1I5Ml4fo1gvFQ9TVdso7N8GR97K8M1ZLvHwQkRMyyFyWKOF21g/oA2yxJ1gEFLp9rS+vf
Gh8FCfJQ3luA08FAp9KQ7wYkjBPpD9VqTIwuywNdzdQ+MUAemtxDmxrwMoSr5UJI7xKxr6WmE4Yz
YEWyaLZP5sG0DcnmtceQUDSz/dVStxUQY52Tfh0XpE6xOLe/QNt5BJ0P2X4eG6F+46An1aHHdC7Z
JFM9lx5AmFj94/sR3+xwzSIMlckcXm2izyf1PWjirAuOmhIbkGM9evYw40YeDSKR1bDcYXYUYDBR
nbZ4K7058lRrqXXsbV4xdZxWZJBVjdbIeR0fzs/4hNA6d8LwYIzui1pKw7yfn1YZIRRU96kyvlSM
qpkUY7fE+H9GYeIBhaPrT2dR1jfblF4lz1nfqC3yJI88zh2CeOFF8qVAoTeT+rriXAQPrJ/NIY6w
JqCpN/jBeNyiaofKnjmD06xwVvlr6rV+FXGt1pgOZ3bliKjUSVPj1iQ9OBllnqkuLP7CWs4YGqqK
UCLnMApa3O6jvSfvj63HwVw9ZMTC/e7RWjDE84Da3WXjO7T8TQj056PJnSBEON6GRKJ66Gyim7BD
zmarvhV3LwOl+kDJ4TgWZpFMI4SnBiLlrRUcOhKy13Z5HdbI9wbcyS9/rAx1IX21P37vgi2rqCNw
VSZYq4ulCh8q7nDXfwt2U8PYdZhsFUApPkEVH4XNZsF6biAcVeJMEwiLqOY+UeElvXJIXQfVL7MG
+5hqzN36G99CG4YJxuDDtnpQyGvE76/U/IFKy0TWi9h0EgaTPRyau9ZqPwKNVkd5CSMH2KQy4EE1
xs97IiY/y5Uq5AFj1kwrWyp0/jGP001GX6cwg4b9chsFHBRS5vvnhq/+vbfMtFEEiJsoORtH9k+7
Rp32YOIXGKoMWj3cntkVaDC+0sb6ISzbjLoAeSOXdLPFT6ABrWZCngAtU3TbmUSiAiKwqZCggya5
MaSMUNdReGhgQaUKKsuRaTb1yjwoB4IDak/AyDAzpTZcfOPZ2k1jlUCG8ApfYd7Gq8W2vVaOYrHG
CV39/ENZTvSGjIEuBDmbYBIs6OadPHFBWKOMKS1KX/mc3jiE8nocyTdA+a6L9G3E94kqmnpIw5v9
jg7VeVFVtrh6RAMh1xACZW0dvOByk9Yde7hYA53SckjOaOUYyT26RgIRT2ToZt8yG9Xku2VRdPKp
ly2qARZm5rr3/TQnUWrGGPjYKBRvblP78xBF/tSsAKb0wGbJReVT0aTL+WFOS31d/QIGCpOGxZmX
i6zui3/wlEExjRaqSHSNLckKjiq5+Erdhx84kPT/8tIXlvqr2RW+7BS/7F5w9Vn5on8sKR94DmGW
GURFAxNcF3pJ7f0Bd8k1vhr0VNg4c6sFo+Gk9v7QSctf9rEkFF/lsxWBPn2RLxhX7M9GW7oeiGL3
nv6zKRlfMNM+3iAh5byhm0gOYdY17tmTGb1CVBXomFmNcH9avM3yWAtGw/0bmAjp1trSlZ6IW7f+
xSQZ8pVH/ee6BznPYx1fqjEC7GIw+JzQxctAt1BVedgqiBS8Hm+78+xpC7FNUVo3iSybuxu3S3cF
XD0cEeo/HHSJVdVdzfXTJJNo34KTwBAwcoLcbUysmnDk5640owrMxyi1oM4W4NnBhp4VmhIAdyI2
Pak0UxL0g+XieUtboIgQ1Vs2GF1al/6HsH7h270HE2ZHJaa9ZXC8CFoNROw3dlrnmcKK2/OIEKCU
cttZP7Hrmfd3qqeLKhtnrOvfJ4olXwND1fWWZxUuUyfvsJAGKvgAlDuh+kDoo5QCCYuxOHd4TEgL
4N2U2JtTJWIWm/w07QEbIsdtQ8ygc20IQs6HB9Qe/my/af5FGw0+uKFMT2E6zkWB0OL/Q37axTx1
vYe7EBMhZiQtjBfVMYxDQ7koSy36RIjEMBQRWoqhMF1MHH8BdlZ507F0+E9KxYkSD8asr5hjsaze
TJv6eOhPuCuiAhsDfYX1xAxjUGK92KO+2qmogAoHBGyuFibQpX6kLKaoECSQNYtPHhprstLdTXWg
A9LU2LzElhsCPuMKjPyw41mxOPySzMM7R+M3bOVVLkL73hyVvgv9vLh9FjfOvoUYJyoQTY+cSkMf
eHOGXAe53RWbn1YMf52mIg7DcydS7ey+jfrHISnhkgPSMB3Iru//nI5NCPD+E3jvrCpRj3Do3tMP
yXNmB0EQLVtP++vR4+qN+JlSGoICthUQBoPmOKSASHtjK3G5dpuzRb8B+h/AZhPcDT+gCSE8AlVP
6Qu0oN1AGHXboFgfzLR1GkE/sSBDa9xLBS7pBDtocvxJixCpxa50dSntKPLD05JPi1ArRB9Oe8xD
j2AR+UhVzlhtqzeo1WYCHedO9/sIMIH9PVQWOXA/wdFUw4hS5/gsC0TGGw7dFRI+dY6pbEaTqx9V
zbwQ8uFBuRywIw7CvQ53R1iugWzsyhBnoLoIWHGOaxqyw5NciebnsOqZMZva3/XKHF2ir5kdFD64
WfLjybUeZ9XdH6+D4Fl/lITDT4wnYNEMQRLdFWSDxmH3qA/oDxW8HV2hN0BibQRf/OeCS2xER02W
JtyAmzqgSJXVLEXlnui0wW59jr6m8sQkYdVPPETaPtB3Qat5cwJKjlUdFlMGBxNo+UBYU536cFET
x9MUW95DaGBYvufKsBYB6iCwaG4ijVx0ulcfbgLLM0IuaZrUKF63a2VuNpcoCqEflGHveyrOHcYl
sRd3nFh0GiWKsCqV3Zd7dI6caIGqWOrIl8OVde37NtL07nurg3UW0ZXMoRFNqTTAijfau4zdwax7
p/9M/qkI8pGFnonqXr2B1VbbBjzXgCSCYk8frpQjPAqqLSCtJ6qgdYFu/8PyLM6Diig7cyiKl2PI
uop0yVY5ET8Bv5wffdyJs8S4CMkoX9d7a3v5BVF8rTd/LAgzZENse5CmX2Xy67+kh1vAwvfilFu+
2H4jMI+D12Cpm8O8ueHyi/mwRjmXIzTalq+j+wxmhPA7xctr2BZdme8bwbG3tkM1jEtOOCf+Yr8Q
G6j1Qnc0rZc7JnnJq+b/7sKOjj4BEDIEchw7nmPFTeP8ZxdOVBLu0yAyWq077jUAx7ElkbxWheP7
tYAZacZP1sPgCO3DioMfwczvx0IstHCgBZeWpUAz1P10vPh0ynSRC6iZDme/BKtEe4Vh35mRE4uo
5F/yeQia55MRF9/56tkYi5ILK+d3YcmM6oUW5jK5FIy3hAKbcrnoe/mbxpQucWsTj4wQcEzZuZUb
Xh2Rjuhv2vQqGE6OzNS92DzcIiETHXMVWULGnYaHleRABdqNVI3Vfl5zXQkbC0iPhNHX6kLEvl/L
wN0MLkGTqlstu6aIf7sHosHhRRhwebWHdWDu7UeaUIVah7VerAq3elxRQa9WfBcq2Tm1/CCpNZWL
t0TM43vDFkpVk/+5FB5J82VFA2Kkr8WawkQ8Bfc9vehEhuntS74GdDNSvI2H4AHah0jp1UFlB1S1
hamvHHA7fKd4fF3c7iLtQIkAr3+i3Ao6AbkZI/xC4btZDVaXYinLC+GsSgbwXdJ7uMLY7lF4KR3w
7e9B/1J1Tgd068u2AbQQAxoazFifl6YdZwf2d3jUq/F56rRZjjPLyQn4tUqHwYFIFoSw/6/H2XC3
J8OSZ7jazHlWxXG+k3OsU0TMktVSrN0+CQvGUI9MW/I4Qm37SwPwNJFUL1s15s+wCNFh0OwNzYNL
SozNSipGFeVPPUBE1dJ01IRHneUU7jk0FYMsShcEIdfiXcCpRn5e10uZ330hT+2ZbEQq+k7za3vy
BNv4dyLfNhwJlgPSCOXYKNgI9QCYasrUcXsS7RW9rHLqMN6cqzkC2a/bVJsLyH7l9f0zd5T3dHHP
TUjlS5Jv0/7SLExRJDhkqP8Wq7TZUdcpqPFXD+YQSv3JrqPm3VlE+w3lXyDs0r9bMJgH6KLzDByx
6cU6zcvp6GvcvLalWgSH4ptvc4e7OkG+a0iuDYblG4cTlIXK6rUgCL+sgTnaKnC2ANBWSYIQ7pTM
SnfrJNs2odYyLc56ZKrOCeUgfR2nYR6aaKdcRKlKL2ZflPmAiFtiFepWBNsaCNJ5Y9kqZMPz0wG3
9igNSTbJu0x1lF4e5EjAYsgdBO0yDnjluuJJJN6oW5A5gWcYeMEWqjsPyfKWiCD1+SSnEZC4g1hr
JFK1EtaumQy2q3Sy/DdckZsVWaC7GYTLLATz7VrOZ7HxYsyC9pvkE9pk9XGdFnN2S8PlhZCe/BCb
xbKmoL939zc5p+muwRkNaNNKqS0vYnBMB5WeogsBiUqSvp9DWexKWQo/GBiuXF7Pd5xsFDazpOlp
uz2yTf2Qstg0RDgme/Y0IlQXe1YIGeo5UzLHCIRk+xiTiqwEb+DIJn+IFC7y+4bgnk2DE9deJUc4
eds2rarFQK/lppitGX9b/AhEoZVa7Hp5kstvtzFUdjdVuRyhG/AUnort3PiEchfInNZ+pN/L3fB7
tpZdZfUcMhwR1VGRgXCRHNj7Pc9Mb1WjJ3tdw37LOMjKUjdYvotrmedesFZaiW4YKr9s9dtjuXej
Gq/xpTbSeQ5snKtsqbn62jQDUis16a12wf9M3Y9L+6GvtjVdTfIy/1rab8S0Cnd1mXSXZNiQjBGy
e+4YeRPSfn4CD2gpODMB8jf2Jsk7g/OA16lR73jqmEBXLIbBpodO9Ut+QR12MXEFucsCfxAzUlF2
c5VuHOfbkgXz55BtIWKEEhPYd6qWE1SIbHszyPPh/EBVO/0V8ovo1UxkwCxWvdD/r0m/vhjpb8/7
/OMqkrfOsIsCfGoThmo+hPeM4KLXLUGs9PVDUFl+3ENm+CZTgnLLArJxiAtL03Mx8OIan40b/IiJ
sfnj2Xzn+fJ4DTiCADTxGUilGRrKYwUV7CrEn30OOr2oEVtpPScerM7NgoNINkWbBgLciD/QyxlO
R/yyar3oPXoZuPXSzKmh4iKE0tdgsoyT99uBiVio1DP2FHj3kUxw0V+DsC5hA1TLvClUjuHfRMCr
9xn9UbsFebFa2IxlerW/kKQ1EE+sWg2l3udxsbcyC5mCJhosaUktVE9tsbXeogGkXuXdFoaR4b4O
IvvdRHrjeGzgNP1mUsY57PDW+RFdff+FZtfKvuxbaHdnTJvizCXGf8BvqYPqq6/qsS4Uu54vzAiV
4toMHMTolazDVM392JRZq1hRrv/866kO1Bcf4nUg2mJ+vikZI+F2Oe+DzWiRtlel/+fX8W9qsPA3
/npiqakKX6c1uvF6pSQvKC7I44fcv/09Hw1xTNVfmXnvusva8ieh99SXVLzUZx+S/M/LPu15VEkN
0KBcFOwFHyx497F9pHUEcICex9HIeFAaKE9y4zShTydLWX43R7BXhWT6AdCvrPWstrkqA7q1r9iS
K3tB7svuo/vukwwydE0RGB/4z+fg1lrG3ksQGZsJUt4gG+XiRfZPlbWhSLwx86PV8o7SXHhK3p3k
3POe5/A+bFHP+tG9Rb0uElagooUO59/YURusZehBBAryDDSZQE5iqD1PJNvkzquz6ftUFMZwx5Cf
Us1x1tpptSezmp4dlqlNtW420MJpB9BezAstWtApXfb6NUx9Sbc3+a/oQu/uCor/eIwTDuixYaUW
IRpcKZPbJrh3ZGXoKKv73uivX0H7p+umCXUmTr3dgoNdR9PdPXHs2S5CO9JHSAB0jr845ZwEDlC8
2zFDk9lNtg3uFsU3cRQxu1qmXR28CuzT9wbng6raeFuBIWtQnaGKXwsduYxN3oGjz80D5GrflhvT
bKq3GidMQ7xzzFzPipYPzYB8Mcx5qHuqUtfl2lsCbS8LX+tztIP8mr8Uw1IE23Drf5GkF6G4MRRM
pGj1G+aEgRX2dtvW7m4lsuBfweBS9TBvgOj5cobwX7wvxV9q2Bxm+w1TOJwuk1D+jNzvzP1MFpsG
V2bqboa33eH1WiA4T3bQfowOAdZK0vHe6E3Qs4jH6IAojPAH9V5zfUtKzv8FmLNkqGUQQZp8LDSU
suKkkNBnqdYhTD5b9Q3AWJLqIiJWjLIX+6Jwg2G3ApI54omeY2TYE+qkGl26/TWqNy+lnjEZ39Aq
J2ZRXWKaEP2SUSSRd91ExmAxrfU9zkusZS8+kQuMrTQdMjycLCXS6VAwGIP7e4N/LDUNf8gTNtzn
3SbrLVN88REQUybpzp+DOSkV1SmpX/OS5btvLTlOi/UzWYUC3GkSidRAVbesks0I6of5gkNFySod
tc6fIxXD25kyQ9n0EzewQr7iWCnWlbiqbH3wM/wJo/aQJfKo16nwdyl3tzh5t9K6yFPv1KeVKVvj
/N+T+rifVoeaMfT18BmMsk8PRNy/XAOX785IdOFwcgFmutFrV2LSeSI3RR3Zci0c0RauXtRIcyKL
cIH9ohbjfslJiqQC1mdBz1g/Zl5JI+LQGo5nPjuJnsQQZjA1+BR/jsFzzyDwXPa4PftmR+rXBphL
WKIs+xt12zE2j8P4o8F4vqNleojcxrQSdQQEizmcM3kuO1/WnevpEeXHR4SmFpDyhhhVkeblrNV4
Am7Jpc1yaOnMwZKjLYaEnkadk6MZzRwNC+vLmGtVUXBdgBXjaeKmXZYh/ONVMmDVxsbWgsjysWtb
a2t/G3YHEWc3Qh6jebgrmUbiG/XJkJG2tnPjgJkF5DXOiuMhOeUcTQVgyqxEHRLkjT9tDsAidPUr
FqD2iWsphQA01AcUsDxQ/flUiQNYFaq3kjLgQwKymWxOmB10hQsWpn+QkFDKYWadFgI7vCR8Lh3K
n4NejpY8CZwXuegHSVMYjdkQ9NohJU5m8Evdzm/PpekQhigau9b75JmR/NuStCN2Kw9mvfQh5phK
+vsuRrNssX1U4EgUUfgZYyQrwNRsoUb5T+MQe7vqmzjHcwj7vhG1nPZmhgmb0d1X0jibzmsHFaLv
rlTgu+6quIO5bbGX0eRp6RRf8IITrWQbG3mPELK6Mqge0Q2GOHwe8wvDlWmloQy1AN0Y6e5iL16o
dRdooyhLMR4Age0SyZEWnj92yQgmi/5rtQFcOGe9TMOx1KCKNnyvcbR7qIX9X3+cDpiEJP62A340
k3l3F8q839jETxFTuCuYLVdOAEGege6Za2xkyFK0sE25McTBAEGuBEsdLh+du8SYWNDFx/cTKI3b
Xj81OWxWKKZldBd/uirKSjWZTdPlBmGFT91RB6eK9zMaU3gTMKolUuLN4bRm/coOeW00wX7bgugB
tm3Wp1lhjZOGkWsHRCZzEI523QZTmxVLwYGPK7TsUCxH3+2s/t97eXfuldnaSXktU7t3JQSgF/ki
2EcOa9wqepmkPYjNm1qy7qvUiYcOuLDrsgQoQyzsRXpYp95Napt1+lLwNlpW0Nk2DHFS4Xg6u51i
1A8KgWbC3K22931G0on2GeeutILApoCDGa2Xaz+/ZhPlUVSCEQyOj3dnllr8YpxNb0J0RuC7Z/uz
QOhQajaS+/XVOu39d/GNZ6G+mmFaIX6aMPw7ftimu2YXKVZTL4kOSIZXondOByR/L7eUbLyzhvFV
vRiyt0Xx8KLHQCxq4PDg+tR5kB+a9DiI2I13xNYZDZkotsm3cnYR8ZrDpU3uTTHIByajRcIIiyWc
yM49fLlrys6K5pR3GrmeA6pWsAI08HR+LoGsfYt+hcatl1OanJs1+lUxKu/v25EYRytd3bptVxKH
1EWLcsn1hgBnyC7gG88svJWJ/hdQjuYPI33hYbul77VpVwwHeKGzoXlFzigSkjfFuNQBxSLezIxR
YTeMs8JhSqhazqxIyAIGMeVTH81DUqs0F11HyUPL7lK0LbwYwuEJe3AVyTYEI9wmWNbL7ugNTJoX
VQR1qSs7WzBBAQrzww7EQTEq5TkhP4lFSJT2utwHz+OzMU23HDng8GSPPc1GNRPmzF14gIztmvoF
/pxwCPfZps2rzGd3IwmbSZcPR/qjUsPrBWoMavNJqGDXQjIad0q35y4/G77ET9cMtJ/4NEPXmHYE
pJ+cDgKV3B3tLIvXryMLRl2+ZhJK/ak1FH46/9KlmUOvM70LS0DMJzbwlm0UEUJBQzWn1aMVC98W
ysvPYbAfN4/7KO6U+Fgqlb9beVRDm3b5c9DkMh9yzKCZvtYwo4ao06mL4y6Sk/mDfebCckkqgJD5
v32YLivaj3OyHX/kpM2FZUI/Y9Ii7L5HpwyUoeAH5Dslzj97r0s+dRS53UN9TclH1CX8G9HnvHmN
E0ZVV8qIIacYIX3JNzDPwgwTbXQn6ej6/AHAgwuJavsDTGrsdmMozzDDE6B9mf3DOtOgZegk2Bwf
JFv/2iLCO1K9fblWMB4ChSgNl4wFdmr7sOIZ6SQNPeMv4nsy+BIFh/yck2V9TVWTv7HVPpaMYbJR
8bL0n0sJalHfklrQacjUrC2dcmXIc6Yx1X0oQK3Ug2oIBCJDWjm5SgpX/CM3ACWdZ3LvGsxXZbq4
F7ayLoNQgY7r2SAqRYBWtoOeDdll9ToScrNj3OvvBXGbxXBrlAFapkvL7EdxeyKkGG09H/GAtDc/
A6/GRFXTjFrXTon7gx90D/iaIyhmAqt0hP8TE2Vu2oxQ9jAlYk/NN4dNt8LdQWnDVW7pdX6H/czA
cbFEEi8uCJht2z8T0NivFD1aTCSApgtC4my4IhXQG47sgMdGUpiGp2dNBe5Eo1CeSVWQLDIWcOiE
o1n8r9PwooDs817XcXNv1sG1StD/ZV3m91YRLa69uYBL31G4opUzS6iUFB7Sb90mDy8lBndEzVa+
CD4R7z1NiOT1oD6bL2ObuxZz6RcWftWfQgux2ie+/MgWfoSmSRmk1VtNYeDoPojJreh+CJBPtZuk
6T/OobhlmN8Z0xHTdVZ4iD6879Imsfmpx1WJuvjHw2VfEEcQf3EBZNGEmdql0StzH4oIw+Zmvfwv
i17H+kwbBw91rhYkK1D80ywMAmXZFUudeCC5PB8AwUa/AuFjCcVW9dZlD1X3xXA4B/vw0p6VklA5
sr8/DhOJxklTmiE93LoAbgaJ0Txlg1ub5nIC8CIbH2y3m1u4pBXuersw75plb255Gb8ZW0C152m4
CfD0Fdbw4E49YU9sUst2zjQ+GwvAavWezDlNlvpjH3X68qlPrB8kob/qX5/GJV01Tzye1ahmTiv0
VeFEbeP9+NJwwZKnCDqWBHdNHPMVe7WKFQjEY5JJ4K3Vx5oQ10+n/MevzUZLflx5xojq7PVmq2Rb
hhwIxCGIjHZIlxsn93tQHyk9NVaXIrKOwKGzAKySzxE0HFtRYRpJ0GvfMOTjuspe0oDjkaEUKsC7
ViFbDf1Q62DhxSXmm2mM0hraS2HtX9cNETQQ3ndY/EUCasqbwoVGESLREze4TCfIz1pnN7tTMblI
1QbeMup7n3qfo+Ngc2VqH7IYYx/t/OLT3zbE+HGF3uoLsfwMX9VNTT1aN3VaeWxLw/EdGkZt1UHL
m15ZaZ9rStBZkH/7yCJkac+oKhmTHmSXPfleVeMaK0qzUqaYC4sc6QFgJWSfVixA08V7nYCoDXjx
Vx8h+okNBharzesNORRhk+9IUO26eVS5TNYEPK1DSD47CBGtUsULJXUIU4eqzvwtfyI9G1L14HHP
jB6lyOJOiuZRuo1uIPfnp1N7AItIvR0bKpW0USJWNsz54811JV6/T4hiKQczWJK7XFW4VE/Vnh8Q
/dK3JUp3EM02L5BMCp1BCQ0gdF+xCOQ8yMMKR8EKmDFSWzKOqz+UP26dsaR1jPT0E+KRbtpYmW42
H9VfY2UHdlAUReaODjfr/rBR61LC1zn/UlEyRb65g6LBgdUfRxi2x877SVjyzaba49PjgDSxrKDf
w7KhmBEyQKbIQ5byP7osvywEJvpuK4J5F3yImpyqOPufyzYgfvlkpORtjJaQAjfVFWqIjtndwtn0
yp7TGaiMsRqGcT+yD2AIh0YAu8dmDvMSioVGTrRoYmreCkJwzn0M7jUGnHa+i6frsNOZ+Q0D56Am
BDBQMnkuj2g1TV2Qbw5kckvutIOURC0fNoNQY0V6HL9tSYCzABrZ26mmKDwHYmYToMYBMbIZPWtO
ay5kPyKy5R/lL8rmji9DvAgfnMoyDaW+C598sL7xaobuHNdLUwqSNaI5mcF7+0CcwEaQuPdrvnbB
OxCdnK5NPqCYWJUCHrrVw/ps3aRQx5Faq1dRTSoDM0jp06jlSNoTId6GO3oiluQjTnuB4pPqGc1w
z7USQx91M/8XAYoxOsVS3DKRfUprgnqEZ8dcmpzJGignaeboWITEH1wZHDc4KL63DvvC1Nuhx1vz
4TBJ0riiFaTUboskSsDiBDe+kYGTTGbSv3xUXJ/NCqnFVduQ80ygyd19OE2PTHbiHJ3YjREs2zRR
HLgb53eJKe3c9rC35vQpJaH6xxnFOHiyB/cyb7P+rC6S/uJOfbecpmTPAPzr41Lj7ehd2OyX8k8s
SNGKeJnNfxsBV88b2eqrEXS6hlbSS+SPEFmSF+j0ysb/JkWDs57yftCuc7wlNjQw/6VRWKlOhQBE
aAglzHY2YoHmLO45k9iyQzRwIG/kUWS+erlOZeA+Jjla7ioV7Ogr/Jccf1Ni2Q3vXIyHD0FPnLZT
cbDx4qMYzFj42fL0EeqzdYNj7Zv2wH9rA12y4mTlsqMIQWlWG8HUm9j38kXyO3repP4J6Cxbhm6q
6SHCo1bNGhBafPaAiVjFyEF/rwK3ffzOOsMyTikGTtSHTTtemlFJ66gKNaNHVosiGLu1NX2XPRDR
oyr2wIPrjG3g/dWTNtYc+vvR/CA8eA0Tbq3OyUInGZlFn/xApysOXv/k2D8QtPYiBKb7Vxzi6ZJe
pKPwMf9zZKcYpbcXEIzlURyZC7ps990b+kdSpq8gGIwYo/nPAh9Pw8GuuHVVRh2EE3fJiX8Wmxgl
lbTTdcTfHBEh2azm4Af1FqDJzelLvRsHfAQJbIEAMKbQtJkM9AMr4zf0LIkDhce0xXm8s7wcZ+3n
OWfN3cVzDkEB/OSTs3PAySis1krmXJETLpJag1Dbe3XXvG7dZglQzzGEIhx7RtYnK52+Dl4Hgf61
JOMqo5mUWt/nTywB+LI4WpJQ5e1JYnpZ26l+26aTOwFJWe3sNFr4POr07Fga1dWuOMjp9MhvItol
QREc159yhofqqW2wa95Y1ZsCFTuVG/3DV744Mg2YDdCREBLV3DqCGeAlWOT3FLhWCbny3jtdR7Ha
zKwm0SyjM3GncALn0mmKlQq3l+e/7oiLj2eDg3t13d565HbMQY14t6doIRGwG/EE9gg0luNzE0xe
XpxHnavTsERSv496Y5XbQJu7Qc9bfDBzFDN21GzsOiQ2WZ1/5PL8hFed/DC/VZBGrriLnoxf7r9o
gpVjjfq0lAiHYXhI1AXpjJYwISV/tKJdODeJCRMSswuGKjosCGKG1bl8Bb32a9ZqryheUE69AKV/
NC8H82+2HgetYKndEGx3nPuQ7eTRiCd9vWqhghCTGSif+ze+XUCPQXMHqMTcplZX+VaY+FTW8Wym
LdbErO3WuNzNQywIa09QU73v5uE4OoLo9JXTHBPj3x6uzPyIX/lTsGc+6yOXgspEvDTMbhErlN1c
+1vt+/qLMdtGZaN2XoGJW+tG/zN1smL0NZN6q91C00K+RGu6h2I6nIhUIu0xFMtVNdvI/cbM98F5
uN4XLkqkrXi71t738lBhaCkh11DAlcXgHb/doPF8W4a9efnD6rAKvaqvEr8jeecRyQ8eAJhrOV/t
bjL8zOWemCE7ecY0Y1H7PZJ/deB6xjArXKkuCGPra/87tym1PcquoVpHSEZmk4M/iMMRKhUEQma4
fOL+gMDOlrNFujC7A41sxWMNiz03KoXM+wiT6gLCd7Gru0Am2PhpUI4HfgMLV1g+Lm5n9HBPfum1
IabD5y0xwUvKP4Hw3v6MeI4cGg4uRi2KTYR1buWBYQYcAD2Tcrd0dKmUaJFMhjGYxfTTjvlyb0n6
rgihRUuMz/hK0dQkkxaygxmzBEcyUnMJKgi1E1dl8U+8eqvBuPnRLdWEsu0dgHYf6aSrf3re4Sj5
Qh0mrR4Ozr3R9txTjGAXbhBR02G0YRX/rW3aB5SFWwGuwFvKGM3nG5xjp1OhItak/UjIXthkpQJ9
ALJob3Ybu982SE3Og9hFjKwyQEvjsxlfPTyTpLm4E+cCatij9gjOf0I412mZUxnClZvS9CdqwXWn
MsnNFBVrHFiG4VwDW/Uz3EeYC7AANkCUtXDK7OF76DCdlpnalTf6VmKJf2AzcBdG3pXTZB9IEPij
dtzrE3A48QUK+RpRmn4WVWk4KiBPxayM3UKL2LLxRdkvjdFbq6jv9M4z0epyt8GuygYYcsTlaZiG
303+CPZDdRGJ6tQ7Sg8luP8ekMcr6GdpQkLIJOIwcZzKBd7M7r/xAmZGARLS+yWwlLbwufRcr5dP
aIuo9G7rays5hzsjcdDyCqGgQ0fJ0n0YVP2eWzwCxpj78kLgujcCj6aJ+0swWprOksd/B8/8hU9F
0g9qDNq6b4+/C9UXdzGoI0ji7jtX+Ptt9l4iqJIWijZBmZ2BOGYPX2XEHRl0ZumBBtiame/E3099
uCtcxm/U6abSvmZwW7raoFuJBmKcD0CUB63iFA1U7ehfnmxXx5/aCV7kDWkl386BYYXLZyc5aUrC
e135soWyPFXKR3Ur+dFqn2KwQwCZUCC4b/MC8EgGu6nJ5ilu0luRYc+V4LUL7KO/g/S588b65yu3
1r9GJ/mPoDXAgRtHFnvtbk7eN1rXmwJ34tno40qIa8j5MnQ/cSq5Yk30mqy/lK8G6sVGI6VSmKnt
MmJRnJFKnRZY2g7zXVRyGYJ5ltkz7Z69xODlNxF6TMaHxuD/51UB9AbniofuSXx6zU1hVWv+f3Ck
3yyOSMQHf82DjF1KuUBKYNlNwMD0eIxz2iPqpylgoJSVa+773oM4BTQlj7Tq7yBiO5gzJcI9xU1N
q79nbcrED94bkROSa/wNIaXP8lxc3RaYnzLg8FIplB3LQ/7AXTu+8SQGZ/Sc+SlGAmVhRK6j9pch
QNU0yUZWPFmAhqZPmBek7061hj64EL1ACMnQfFYE8OdrvPO9d6LQbcHZ07sZR4UWGOSm8JZwPWne
8Zrzcr38ZA6By/HckHP/SBytFWFMVzALDQU3s4pVIU+O6Dw846w3H9GqLQHChXhVJehYhL3DptDj
t5Y0uehc2irLfBIqW7eN20Y78z3KpiMaFY0fcRYtbqZyrupRpPu4aeXF/yx99VI0Alw9Wlyoz520
pjLycf574pXrUSH/xNeS/pRgtczpKiHGaKydNep5F+imrVcY5gUkwJY7j/9sjLcYJMCJKro87Fdl
bS7Wd36B9D3j/iy2YRsi28J84rbduno34S/RZAZYbxI2AjJU4wgi09loTGitKQhS0LdekrgkWEyu
ytBw7HQBE7RFGC7oqghBqAwj4p2TvA2GJS5deEYVSZt/BEAOvw25Do7/DZwnZAy9zXU/yJixe/Sk
dox2bZqZXLQzrFcjrYUO5qLmCRnI0zZK07dx7c9dVsgWL4AeHOX/NBYYVPyWnqc7sEmhbcBiFVzo
y4dWwT0qgNkc7de0BtndDr/xhu1XVbUlTMSdwBp+aULO5FuNE14r26mrLxKU4GdcAbq9pAnZZAWl
Mb4TQk/9n8vDJCO2IT4YTtciBa84jpqC7brZfOLIYXN/JskfBdeBFdbpQjo/YrhGcG/qVfx9OvYw
gEjNr/2Iu0pgk3BCpbY1EkvtYCgkXzT0RRaotEj9QF7bC6vGYu/V4dm8l86MFFiibvBRbSqniC+c
sxu5cQgUmKBRYRtefa+PgW5DDvrMQa+XtzFfM6x0PpjMO05lvS8zc3FZUpt44RCyBuJRPF3f/1Ix
6DAKc5fCSUtxFRqx2xDFZiOpt2JzYHS2MfzQmaPiU2gHO2A1U99eg5yZsIk52s/0yb3eedbRKedz
jeLvEP13am6H/4HVXQKJwQXiKYjsGfcaxZX3SrFjDmsPZlEW4qFGjShLQ4LBalVY+xIPZ/3LbI49
KlSavdnai1pe+hWRgpML3jiA/42/mcdKSRN/JDev8hnGAP0AsTfOrF3qQiShnd4tWszStu3bRQID
5Lmkn11vwEpTegCJ0qEDzt/vhGfVqvz6O7uG12E94f/i3vD+7c2x4XiFGbVs9QejNEP//EL9HQ8Y
zFS0xJeTvVJ7EJ+m/Y7M6iOBXtHtRpr+m/ATVWro3Pl4+DsoPR4bFLnQRgeIwYWsDQs7HZQ9NNRo
5sUQuGX34buWPfRaEGw3PpJEVCGRIKAuqhZXJJLi+ygDij+jLwFMvpIn3H9eoqoM8qpTmoUUwwPs
D8c1kW7GtfGLQXSzPwPNQJICzR+7lPeShNFT+7mAmM2RPPc5p3F4OhSypJZ9jKqFsI3rB7pEV/N9
uizKCEQsvafQvPvi5/NkRGEpo3QQTse7Gd+cjnNKnvqQokw3eEUO1o18+zc1zbM37ppx4Xsdt64W
t0esSm4wv9KnO/8uGnMK57vucS/u9oBJmEiaOTmmcGyETo5G+jUY9gDKCM/c2TPHjSujmGlHtSCf
2L9USGbRbJsSae4GaP9sH+1eiWLKJOBYmkGtIXs0ky7xQI+DJQujXxJNdb2ryuHWb/lGBRAJIcz0
zbzJ2r9kV4ZVVgd13h9I+28VCaTKc2jofW+pqLEJEI459UMzxtmobFf0+SZK8NVz0a5s1yqy0HxF
7esZ+Rqk4yXZQbMqqsaKbXKqiLjl9si0SK0CC2OccbTiYsnpg695xVDMx26X2/TSlhtm1+H9twmy
YJbSFKFyWPwgXfhhXcg5m90yoPFOip2B9ahz6Kx7bzlxHCZRr1eun4w1IbxxGTWq8HqgavJV8qKa
69CjVTujMHeJJ00eVeeicRHZeqRcFn+Jm/TFJWrMott70JGm6AjeEdr5Y+h+sZ2FmQt26wCHl9iM
f+u62ZeSq34weIzTa34yxqcjyYJGvWG2VKDj3j8qEsxEbkpTKT3aHfhvPT+JOpD0WQ9MXFyb9GHD
DuSLePT8ZDhT8MMzKQQS9PyTpuGXY1OqzgHeiHAk7q3T0LTGJNv4060Oq/LdDV4/ymWDKI6+AJ9s
O0RJ28gQ13zXqEnaQLAQYuRt8u5RCrQhjdS8N1ZH54oKfxboDj+oSaqAqN3O8um598V8S3A084cM
hc8shpaJok7x+T7S4zGzdfWflYqvyg7xH/RMoaVVWevgh1Yxp4e5IyW/UOeu2vuxZViHXmmpLOuf
NOJQ3M4nP2u7e15MIG1B5pQvu6k7j1sqICcwGrIjKkbjyW+Cp3uwVJNuGyVNkn9w0kIftMZmiToG
1KVR0I36a+VwM8lmK17sJdgZ+6FvBReHROhQfZjRghEdWDLXcyw2VohqYCz6gOhRZBwitLrOvwW+
uAzkcTyEK1CoVEWHWU8rwUDz44xogOfDPGZdE9b2SpgXvwPAakmWC2+zq7GqAhUTvIK01to4W/FK
nq+L8aOWhmnSoXiLibcxZ8bkV5CVKiHttmF4YCIORjEWS8ZKyp5WvHt5vpDoez543PfmFxyemJF3
6mUp68MPbkVvcSvmqQH5H7wHLuJXJk9gUvJS0xDdXgdAIn/WZMIvgXYi5TLI4kBDK5Kcz/tjEBAc
XCHbEcvAgcHk4VsIuxsaxZw1j8G2KZ7hUvzhZpdU/06+6gh9s9H+kaNUIXzK8DVG3eYkpsN9Z1vM
Up36acoQCTGsCGh9xqxd+ar4+RjxIqOObTS6qccpHPnWF4OzrZMbDvTNVrzHOyI2gN1HxOU5kBdx
6BMbE0SKQjP1HVgdZBgvb/OLJ5uZfJb+zMCUc8aGvsy3PiX3CnynBK5YGVXPlt/zMqcQX/NSdYEV
2f7I+Dye1SfYD+HN91ZOeUUtmesX+FxJx6FFsvIKWo53wS199HAJIG7PHDBy/u+5yf4yTW8aea9x
2EkoxeLF2zsz4ISCOARlhtFLpufUc55QAdvxc+0o9WVTc3RL+rS+gT/mNHUP9xAAsCIxTnU6DlaQ
kt3XzkcJKELMJ9QXP8h7Uqm54Tlz8fEytbc24hAzsSflH7B8lvsMq2IO5YGz9lZuzOu6J7+pXb9W
VIFXkKCkpVgG5OmwouyK7PWy3I7INhs8brb4PJj29cNWehHc2ZNJ366N/zAPjxd02pEV2aIYc/J3
zKYT3pwzI6066LjpZvlbQwDi/qXYcyt/5Go8i0BhWf94aH7XFIWBK7iFaDailkg9eAvbK/NWkzz4
KaivpIyI1K7yE8fZPxwWn0P+0ilyu2uHe/GbD0QCFWN1XaYdZPFXK2pciCrxkNhqeUQKnQNkde7x
meurXm4cjLYCGvMLSmKKAcbSAOP5YuD8anySZtTgzPfEc1Xe4vNi//nd75fgjz+uF25oX/k+esZb
e7z3/g0viF7mHak5oKtrdb0T8cE9vlDOqQllWO/jKk+77VE2izuf+VycUNnGzZ8w41mzAUnJUPfO
znHFE1/JMUbNcgtYn0D6seYzLogHNiK7Y/0RLfjCJZN9pZD8W3h7vfMBBmVgty7rKdHgD0HmVAcF
4+lnkCozDjnhckvrLASho7fQf3HabBvOzlo0n/aLPNcKoJmZf3jC6jek58a8Pmvl0eXIAlJXYQc5
cYqnWkfROo0ZO4FaWvJFioHg5E+PBjqAIwhDOrVqknX/0rlzf89t/DUCjyrT9MX95JVBzF+3e3LW
rybot7OcUJjVgatfEPQj34rGs5LrcNWTx232VlEN1MlA3sPsUHTOikY85d5nOXfnDA4I8T4rTY1R
nFEDXnklnPORasULyi7wtntl40JEVP4X4WiMpMYWsFm2uomhPyTS7YolAS3DwrAl60/esckuGZ6q
NGcWiza1tPtS6mtB7o9yxjT1DFX2dl0kOu22W1PDM2hIp+tAYnFx0yhSXMSgmbDQ1/HjX+e1Ij+H
f04iH6+ksLM31T6MzikZ8dX8P35tkrPXj4iS0/qK/UvPjKXJIn03WOB2rXJGi95Fc625VYIyERpg
GT8/R29Op+3iUFFmmmpE4F3Jh581KT6wbrLfO5NKcpquLhbCyMlXlv9K7djF0t+phcfsT76Q/dHA
gn4mS9jqlsUkYRtAH2NREngFPOiR8ozOzwQV09QJzeOp8/gbgeiCRe2/INFizFIZ/GBL7dAEC1pv
mrmCG8+PnKslJvS7luoo9DitSqBq6KXuwATSBWo/F33F4OdQKzIZQwWjBfE7JUIo1m/6ZX1gYcfU
e8tNfsglYWfIkGoWtwlPnIbn8O1NdFKoKuK/YUbEp6tbsmwlNcRsoAuLSfxfyFiUsLIsi9oFnmDr
9BDQLEWGmrVWdlwugXz/3N1ytG6/7ojpykm7OF/KvJ+7m4LUbaGJq3mN46FPc2wibjlGjq+Fd3Ka
4qLn+KV5AnEWowed8eTpe/nbbBg7jljSd/3L8NBWew9gj/6CCdCTBRgF2YJwrduVz5IPHwmCqyfT
GcFa7cJGCB0US955zewEtfO5F1SNM/6AIreZcptnmu/fl7WCFa60sjl4lA5EnV1kUJTcAXfGtnIb
gN3ZGi+jnJvakUzJHX0Mng/Cfsl5YoPeBWvDjWrCaVYDYVWZw0oiQtL/wxmkVY5eV8gmM9X5P7Cg
l6qpXYzJr/6GW/K4qCNCNgtzCJa9jTAf8DQ62pak1eYvIwwj4sll2ca3LhomNfyzmf06U0910lXG
cFrhXOe6D/NPFgZMW6ZugvPsBqe4NS7F8vYRlv9zmEiNFl616H8sql2a/+N3+3ArDVsZHCO1Q2gF
5JE+HKoZxfx6wBT8QOpq/xhrIj2UOPvHzG4/i+1Y+jh7sXuEMVzzDT3Q/gdyAoryb4cUD/ntFMiF
tVSTEZBAFhQ7KbEEpCwhI9p2uUUbxQac2+QJz8Ufk7Pl6LiD3uOCIudpuUwzybTEq0VGTKGksTL9
xRKh2oh47glC+i6Lr4uPnZFW8XJqtwB6UoYWkObNXbsPtudm6WCRPna/yG1eK7CxVjP1m/eo8Lva
2QaYftvDtr/1QY4C2Ibp4CJVybweAY1GKdpDWXCTasyRrovObiTGWahmfwbfUowXZmxLjYftFSr5
jwcZdl9odLrhzqVy3lFJPrrKjtJd0D91Q0bmsG0TDTkelvE5Z8noUVpd2y3Y7XP6syYTjjKSn79N
QHJNekeiwh2VjXkl1+RmKbBTWITeGS6TxUpqMzrGjpehQlt4T8n9HMtQPTWMAW3Sfoai+ILIp51y
05iqGsO+OQmMZK2Hh+Wkp0PHNiLNeFUem36OMiTbJV7WCgweCfRG1WaUq4b6HB1b7qKs2D5+p68x
PmMs63h5JKuOO5DeNnbfB49bXN+v9PkHK/sXjFZ9u4a5Ku5p9tc85Aarq4T80h9DCRyohzJGAMFD
fu8FJCDx/4UgoztMggLeJAe6u7R42D1iAp4YGYP6x8Ol4xZdfw6iJyR4VZkV7mgvP4ZjBNrg+Nkh
Zl5RIU+ppfz7wDeOYleMU1qSdva2xrh1wQ3XwO97NmQ2XrptWoh4JRYSKH2BoRVESYlKiaQ439jZ
D1gxXvG9QFVOWwWN0sd81OgjDTIkF8bLuXqHvoJSY3ldTNDT20uLFXL/m5Fz84AfP3kERD9Ta8kA
fDWi8HWqjitt4tB+lkC869/YLH3DZakyu5zXXWmFdFw2BQImNW6CLODzmjxkso6ktfT0lp4EgIwZ
bRhdeE1WY8PjEJ3e+pTY5IYgNs8KXcX1BClG4RWFo2xaMmt+ZinS1jW8zr0Ds8bl9MRKbw9ejIZ0
Qi+VCeEhbowugrBhGpfth/iTP3oliwYmCW9fif1nMq2zA1Cle4YKWFkQXBYsDHcWavNC8ewnPxKt
Sog4AdC3DxfwOub7wG5IOqwiZDan9upmffnQS80ll/ZiPINLQWexum+J1LplSqSg/H4hJhu7BRUh
JumlCxt/CEPhTbvgL3CiafM42NgGluV2oGovqAIqM4dXN9s89H8hB2lbUdSJmujPymeZzo8016rd
eNxugUsAACyBvcjA9HInpUZztjz6A7L6WQ4I1FqZVZbbHqOyyzeFFM1g/bEGL+KGQazfRysygaaO
dFv+MacInq95pqMa5VcfRjnof5iUAuRYdF2L51+lVc+8KPsSbHOQo4lwDxBwBMmNgFW4v/s9jVOa
WeqSPRaCt0okzLUz0MGwVbCU++WC9QlOmbLZHvreQv/sf1hMP8gYVZRs8T3UYrzihMgaklXT0513
QOB0P3qefvNX9hqUG2RWLAAERb3C1V0cmjkAKJEYnZPyyr0sPWSZtxL795vYZVgZUzIBmvQz6Zu4
MZZB8BmjbHFwFwl2d6rfQtGOS6/I4n5btFpKYSNXANzUp2AU7zWCWN5SSLvkUELgQXSM7KuFx6eH
ZX3CbK3txgVZ2YemB7OoXC7diqNB92wmpdY/0GRVWMz9+qgJjC8Ovh+chQk6yyjZEh7gQolBMy6c
pBMjONYgmHbjm0iVS2aDXWskMLSO5n8O3OKKQ38q/JWjVXM7bf/uQgWMSfXkpHyX9ikmIDlIGroh
ovGG0FM3XxaiToy8IsvCyy21S/R5SMywfAr69hFwhVJLju80ulVDFzvQ3tG2AWzlK69MSumS+WNQ
9/k8ODe2lTx6/yvhmLVwV26mlQAlDXbq6h2j4+UfM1OvrCwC6xq2br/c2SPnFmd6T0IFMfsCuMLs
j7E+ASBXKFZGWDkY3aoVl3z2cYKxQ0xp23Yac5Ek3kOmS+P5D/tcegArNQkAiZel1pF6PRP2kwMs
BYBB60bxjnjU4sgEbBa+sq180W7kdibNNH2LxKfiI4eYLym66DbDBrOEdDD2lRfoMi5pPlpWapk1
HRmzBMLNlNSthDAPDcKj5GHcmshcRLaVTOz6X0McBuxCsco3mybfc/IhDb/Klerz48tOiGMNLVUs
mkxGx2DXWwfs1Z514Fnwg1VNXw+NDH0ZBrxmm6k1R+W1TpKXN8zEAP+UOnPid6QXcRLbVkGFgAmc
j/1XlK5jC3tsPwNgstq2jMjzUgkTu35uEWjflGv+2y9ozvueXxbkCgXMnVz3211ZkoL3Jf9KZj+j
Ahej/OuiILPCYR6VKLK5tga2DZOKokKYOf/NVjHtylpeZegDFyAbnrRAf0fVXzWY+Lo4td3V4isr
pomUflpFdx/eN4iyyzSJ6c76W3J76xWlZSdOgZSkZ/8nRJ7wOyh7TBLdQ2yrr/2pU545IERouQJ1
/3b3b3QSy5dgwthST0r/zavuYuqFNsGBBclIW1l8ifEOi7ev83p5spXDceh6i2ogKRGdTH1rMGb2
9JxGgjo2mwK/YqY+clx0M2WPWI1oe6eKIQu3GmzgPHa0VgMiwj9kvqSjVBHXV9mWVIHQ6ySNgD/N
f2N7EArPdpE4p+0Rg/+A7GBzJi9+5sJJNMkSW1R6sbIBtdqrkCO8QyZcyh0wXpnkxHUjF/otSrZz
Kf+U76CPEFS/OcfFDGbDdYsoYgrEhHpt+LyNOK0v9qcSuy+lT6nl//pkHOEzzbg286EzbPqctNB3
AW4pU4qoPbuNsYefDgXbEpkIta9BFwK2Xr4oolr/IEb/Blae7i/K2QBLe1LKYnERakzE9I/jhzMl
7ti1X+mf5hFk+nx48OvbqPjPo/5Gj//M+ff9S9EJy5qMUI4JLQUmBl2GsDGfcWJdSPWOJuSDc12b
dfk1STZ81o756Fm4h8nhBa1wZEYvV9fgjZkhQ2LBdGLw23W8a7xtHu6X0XVlwsyB+KmacAL3XGyE
dXpyBe/nGe79v40mz+jXiAspx/+oy54WL0uPb8DPP2a7p89HscTiaGT8+fpFxRhnB0RxDQ7jNp+8
F+P7WUkqFet0/mW5KEZASSf0OgLXYGT39f6oE+odyRNNnRpH2rpSaFoXIduWBvREAI06V3dcb2Lq
ueBge4DbTGFLqSQXmKYCDOwxdIYDlEC3QRY0r3nZffk8WGfuIfzC78n+f1e2M7omQW/QshWnzHEW
J2kKl0NTaXvrlzG/YiLxqyTF8yv8JMhj3sYMgH64QDx42WCuUN8qRhWDwcZ7Z4AxdxepPVprXZDi
lGacToo68wvggllKYx106o3gUAsFyMLJd4/av/MsjaOpKoILvTKRPO42Pq9WHtAEQ9PRK+C5wf7I
RqWbESILi8qlV2BXim57BD9QhyUKMN40FlmpFWVqMVhqUNKFBMMx6if3uy/wg5+0SEZAsxGZ1OuN
C0atQoJgaLXghEBLFF0AowQ5ql96odjpIk0Bj0RMsbktZZwlrkQxlu/jWm3rgBSWQudSXk04HGd0
JDJtADfI2EDNHJN3vYclOhjnIFRuiZZAh/HHPjADK3bUavTRZ8WAbAsE7bdke1X8MaRBa0lA8Myc
2heFPpD88LzLNBrBl2/a6e3d6ypVb6U8tthUiOeggO6qvLQutwrjpmcLBnFMYZj4E0gnvYOcZNnk
wSZ/7H8hKvuPOuHYeAedqt5EeeW2Rn3tmksbN/OeMqGK97IPHLVkcr6o1XsUwSAxqoncUACjzxVV
0PZn/uHznQX9lgBTpNa8lkhpU3VSjLda0U5QN8z1PZxAWxPfxYyYLMjg8Z/Cv8h60i55sRNQQ2jt
pvISim59JQsmcWQkKf3RFwWTsJfE7Jh2I2qLH6PxfGpBShL6Elc61ExwcFlF+a6yWlbB+gZu+8DV
4bsezitTZYUEDCpVSTkBCTVq/lmq/AszbfI3M34UtellDBdOf7rd43ZkMceQdXJvKwjekMvjczuE
OxRzmOD7kDgGF36of+pYjfQCSVwIZxnES5G5NVJrVDNq5tMWrrCLSNolcQKFC8X4xHTp5okW/mVS
4gyuQqbqGIab5KO5uzjLgLP6hAgG6EwKRY9Ql2dUF30+vs59oY/kusaySWYG4Roh0Q27FgCBd7gI
7EizNk0yh8SDtHGd7MF9iO4BFg5wl63QxJeBdd55MEs32yHfsc8iUxn7Z1r1sCkf/E4Vsb/aybJa
+n4oADrqng0ZCRPLHvHsie5pqEFnlu2QZtDtE+HYtm83BPuQpDZVeklt78mPAV60xruVk+gzvHjM
NbT7xdopX6ULe7Z7SqKdatU9AsarH2rc+JD7B5ZOZRNi3Qj9xI1QgvMsDGYJHRjOooAfBBPEjYC/
ipI3qXtjum+9N/22buyiVxw38Ya2fDtQNVNGMl0boAzJ9ol6FlCS9eEIZXz7o7c9KtYBsxQxMx17
JMl8KtL03AkKhb6oViB/RVhbyASUW3u4KumWTDdhu4oZ/lba4W0SpJ8yivv40H7yAP1mQtRZyh/M
wTWvv+38r8B0+UnpcjHPfBV49K7XHIcpnNKgyU1PNKLiXhzLIdDFhSEnzqsQsoDjeE53QP2p0+2o
AoAuWdyzXrnjWReuiFp4/lpN7C4GOcA2ZMvo9usyacSi1iEIs8fSFo6FxMpQ12sET0TmnNsi+lR/
rJApyNSm8m1AaENek3/Yie3lHY3dzJwCYd+FBCmhyVxA8zzduChyTOPUTUreAMmFq1TeqpW34NwV
ao2GcuaDM4X217qovIA3vZhmmgfWIgKALLm+PunsQHRtsvSRBC25Yy6dreL2nPYPAUayx8dhpepW
7EjIh3bOmwAl5kP8unea9l50cucGLCGfM9wxVddQYIcFGJvXawRAevKMcIDM1F8cdafvKJqoSNH+
W4KZvJaHMuaD8QAeXQIOi8Kb3HYOrAcjCCxWS+TeiXgQZ4sXMa26yoD3NEC6ZjHQ9EHpheXR6vJq
KGhp5HyPJkSLn8ApfPHM+nAcC8H72laN9uLlscP7IcXZyuRNo564MOKbWeDgmeH/pnW5qGy+cPwa
vgFHzmgL4KWHLwfXjqZ92rlh46/nM9j+2O9wRI2YmdQ5OsrUguN68cQTZYrWOeGJB1AiWXZdo0GZ
ZcMr3qB+sEQg3JKwcKBesizNoG6Ms24k7wRM315p0t5PrLfS9wM2vir5LUWHYqeC8QDkndqzaGXq
09Tywu1RTUwK0bGZx/DIQjIbbkQ4wbW11qEwEkWPrbXZAHm+7LRs0FTezt+aq43OcJL/QVH+18tO
/SF+r1osTdojTeRFG++63zJVMTMu0aLnXxbmXU9dLN9ZsXF4lx/QfB/oN3RMIeJro24+ii7i3Bz7
oa70sff1Y9GIbldeSFWHUbnwYMfzRjw2noJ2FN+54DzeinrgTn+UBM4rjpnhKFwYr26Q0FAJZthk
MDeVxIo4z5Y/1g/u99XWLYOHFVkU1adZm6fJqx7h8svgI09zTD8pw/YwVKzlr5qLFSwOETAOx/QT
pyJc49KllndTlbKSLAr+lNUpPtQwR3SZHNS/W3uob2s8Hz4TToT9BPUANI7qBwdXT/NvrnmJwcn0
jIjXjaJTWN8zVer2iU7TLYYcgL8iRzPtjiivqghR0CNWC75cUvAgXMyroI1w4jmjT35WIhXgFNGG
E9wGz8GDPSsUaKDXxujZfcXqSrYoNX0eLvYE3jm7GmdJ91uxDcmCiRPUa+ZSfEdRbHcuBWwaUl+F
Mg/x62sXFthnrbBZ9CKX3uINPupsjWkE7RbOG/YuxqSvDx2IgPBYj4hwZ7AmjvlO0gvhXVSSabmG
/5YwzDKBl3cAIma828thlbCYOlaWktH/A5aMiBt/l8wli43EaWcqHdTYCXXquFtDvJs1nUNAigvG
y3I5oXrFvYS363AsYAKUcyBLsqAcVJOKdBKHusRPEev8hEZ2YjtuAkozteC6c9S5LO1+XajWdDa3
DnfJft49VlxyyJrS6nnhl+jNPumTGwZ34BhR8EHh/KIOC7xMPukXBomxJPhJllCA+tuMGt0eapjH
xLLGhamshbVx3O0NM8223ZbQW/gdukhjB1xxqjLOLMBi7Fl8jFZvP7SRR3zjq5DmaQU5ObEwcbaR
5V8/lck3tNaDrgYCrltfuZ8+pujOa3x/kYIvZmbMpZTNvoEpwQ+eUHP9mwx3gLNyIlV0HInxBul4
khKA0968fQJvdS3d9BJ73BGzdjyutzMhzeSiXwDiJNXvk0EKbV2Tu4J6igT07SZ9+/P3sC6BD0PC
ExQOYb7Uzd/K9xZ+f8rEkx5yVia4USzy5ycWBbh2/+ADlt7Ot15xLp6V4cyi94YFM3vU1iSKKnZM
ZQSfYouM6trmwc8Hrn61RlfwqeUmuDtPVae8NS9NBaVB83e9ehXEkyF1S9IJ+wjoaR1SLJ6PFYOK
hID7ipUn1lvO+mPC6liJWBNEWJ8SrnSCkfZ1bID4CSo4PeMI5oT9xdPMrr3u3e8K7JN3My3ufy62
xGE1wyqAnHeNK2tkfsccoGIRplaOHqyBu8GOsglMB1UIZhMnfPMkcZ7lN9X/wZjuri+Zi5eBUolU
Zx26bntnyDvSBFCIV6tfSXQ38DPUclGufQl1cEQKlPvu10kY6ksbKTTI3yxg6F6QKUeiZi9uTFHB
Erarscwt2CWTuWfBzn9BN1kMY4pA1/D9lGjhVUr+eXIUMRQ70AABfFDlkBOtPC3RZVhxpRC0TOs1
LyNdMBZWAdU1xGomAipQb9ei9Rf3a3YBtH9ibLrIv2F+iPaedc2nX1Mi6q/u2zx6EByog9Z68lOT
4xtVMGgPHkbzNiIZA+7TCCoS2LbO7I4CkSNQZSqmyb6GpHzHHsfMPOqGfshUns4wJL6FflMdVmAK
yiJUIjcSLpXE6e1k9sQyNZ7P7X0AzIqvJcJR0jdJbZjpmmGjiXTRSY9I7Znmh3N324bahvbiQKc1
OpagysgfcLehEnjf/BURQcwcrY6W5RnPFUs+f7FJ21VPv87DdMomKritoVXMFDCzu3m+p9Ekje1x
nSho4wpx6IomUY9Mg8/6Y2BmGMF37fSbEFsEaJEhGgMYk5QAYk2vLWStEn21UsfzecXRtZLHfbDs
KsNE2hjN+ykxkMKMsYrRR6yMYKoJ8ZflR+zsDIw06A+XFprdoMKkxUg77oUvH2xNFYXTxAby+JG/
N2/Nwztc/5ciEU88PGVOSda9yXFfSShbjLDZY4AKWd64keEDuZx4J2tfJqeSkCPm4CExNPrSMpWt
loPXDMLzQOKQl1zO1BoFJQI0XfA4rkKYHi5YAHrBspnkSs37oJHZxxUc6bh2z15arxNcjf/dd6q5
D7I667l89E4kXll/lMNtwOFnE2074EPJ3gGXSWP8FN2rTJuf5CjjeU3gGPyYYPH60y8ci855lc3g
1+GGvj/17wSrLEPeRT5U487J2e6C878cCaLHMnEu0uN8JNwy7g8zmikjCcvNlhv5KBj0VndiUEX2
ZkJ7XkwKiXZ4oORCp6UoEvACiZwGk7XcXL6kbx8QTlCRBsM1FigoK/8V85traSxCOE0NvmtMxVQx
1fbwiem3a/FcRKRKp8FIV4GTk5jKao02tSfJRvB8SJQHlLMbBUWO73FEfd6CR/hubwzW1NPwvLPF
YmkMfl/F2nOQXvdxNEeT2T3UB6vqVmnjgg6djD3x69bwlmyuVy3w1a3W7RKE9mHHg8DPwk+EqHeV
i+D2umB4k3Q8yf91PdfBoKu76STXtIQyXDg+P6T/HYFg5V2XEl/i5rPYYaPpwj5L1uH11PYVwfWy
9xoy3Di+xCTWAkiQfDZYqsYoLu7CdGcWTKDjDHFV2X0IY73GttsN4wOToKsIVcYFlQ7RL5Ck82mn
Dm1kMOD3Ph3+Hx7hOLn3QWH+XUOklY840idopEI48n8gpiOf3NUUsGKG1ktjBquydlcNyP4EP+Gf
mytxnxPtGIlxivZF2xIX5gkPBYGvW51Q/bNv+HKzrJM/zDtNjNDo0g8jaoFyv8CGxiCtJxVuN8bC
xYHHwcXTOEVfmtpRA2OqM5UOw8Iy8nW5Mq/zEXQSV3xMwksrD6kBg3/pnEfJYbTd4/oviQenxSns
9cxjzGpXlS8dsnG+vN/4ArJtzYLXntF6kaDjvR0rVx+No3BnOFnt6u5jiR5NZSi5wjaFcMdA9MXs
EXavaaYT8l/jj9AqjC7eB8HpkGQZu+6e4c7wl773YVi5r73Pipr1KTdGBJyAWMvQ4PHvXxApdOdN
Py8SIeOVIM+NMfwfzicEMp+QERoxe4Jb6elqoXLq4JvxAswwti7q6uJu3nSuNZ+OancdOa7nyXKA
HDpdOwT0KlXrFf/n7YK/M6ZNefs8fNghlfUnsG3Wp5wQE/rDClbYw4urisVsFTaP+6uwNj9BCHlR
gmjjBIxdFo/UB9BXApx7VGr82ogVRwM7W3TBYz5g7rsUChsWq9KIn4KwabtKJDMK0I5im6UtEIDc
yAEDlcw4TC8OaPQZb6kbKrk6kD4KvXWVFKX6cIX9PzHOS2MzwxIhMWQVBaE0YWDS5JftlUONCsKG
6Em/cxZI0aD7OcRzPt9WKvHefjkpgaMdwQloqxawMExY5znBhVuNeAWei+aAnLcO2NFgctSkVFut
WUyCoPoKeQrtGK9DGDZ3GFbzdFuAbSA5Sk3YnO+oUNMDa1agZj/SuSv8j2nFdKRZ2MDcf04OHwif
yJx9JUSIj99V941g5yr/GRaMndb/IcdwwTm5ZklBmp6jV1I1+2NGuo+GmxD3DCNQ8eWqnqyIuxM7
+BtF1xXFhutx8+Efa24+PXkthuuq5miN44ydgFZr8hIknTckw5O3x/NQFlt+CNglkOh3C1PCA+T6
t5to79IjG5681zwArw5y0xHEbB0FvXyAnG12B4Tk6YXCA6Uw8I71M+LXXX5zriXi92AcFebP7Q18
YqqtJhhIudlQiApJTJZKkhLrgazNKaGMJS07u/QnF59N0wQAD+wOPG/dFa1zDYKAgU+p/bf+U1y8
xw1GKn+JXOdmBH15ORzeB3cYmGYZakLrCoiTfRut7LeaopJKjXks0mLkpo6fzySDBByxOIoQD9G3
EE4sPWKJArkUeTO2F6SrZdIGkYBQFdA0TOIkK4+fm9RRcouENqmF0c0Fgj8lGb0rubeM+rpT7uGX
PrL9sEAsViz+iLN5O4SvpjpqsJdCF3R2V/G4iH+rqATwf4ZxKKixo0n9C2+quVkmCnjyDGTA+PRo
y7V04wlh+8ZCv0xLQxTuUvPDtFzE+MZUw+PcGHb9CovYPZeQu3IXcnZRDMdfy16xp5XsZIFrc9Ku
+wHNXp7UGdJq0w3WRkYl6QSKBD20Irys2We7nUi7Q1nXPvvnSR45NVSTNx8CeWrS0l+3IaqOcIQb
I+NLMdWus72JOjoUVfw38g/cceEVzh+t8Jixd8V0u8CB1Ezmthv8y4BAM32DsCtnLJAD5GwgLOnZ
L5rGgzwbhf1IokgzQ967TvyKZIuZWvB01xpW6j3Sl4hdwCEGAR1eoHBoTmrmayxUsq6jUQvhPuZe
Kt/Ys0xe0nEHWkyMmkdbPJhfVha33bz2W1KC95F3yS1hgBl9T0UNurSA3I4pBtYmF0zK4i1HTmws
XC63Ag7AbcKruUGZet+4gmVryv0xL48fTwb40y+qRAX4VUb2q2HUupg3a3DtHeb/TMtyffqn2rV3
/BJig3eeGyUu3MKH8ds56edhYya8Ph2QZVgXq0E6I+AR1GxJYfu3IcgPh5fDFDVkskSvB07pNBNK
YNZBp4FW4lFg6IL6mPax1YCYa7l300RrMPrly0xeWOCkd1zPfwd31eR3NSD6V6ZLe1kxoiolr/5z
hBfKX3PS7qXmfH0trK+m2JGXSYT1Mzq+e3GA25FWT2GZfMisuMMMUXHIG5MHq7Ziz459bXW5kSqK
jFhPjVbRs3zy6XMYxLx0bnfopYAj468x2Vi7QOtVdLGIUoJ73jiD1ABiHato2Z1to7b8+tsBER79
H0P4J7VFj5AvjnkZ6SMioUhQO6wvddEPjiKd/h6/u5WS1JZZ8lpjmABhQWldP/ngquOG1yeUmAN9
h4zNEydc5MHCL8RmnIbZrnIq5nshieU2wM71mGpo7Vpi3CSlWEQouDQ/r5o/dhCTasI5drV41mNd
NrlRslP/YXmU9c20fIKXEIq52Kws9MV8+SFZyswWXJSZoQ2z+wCdjU7H6ZoU783yvE0BaNwvEQ1z
BhSynxQ68bCzLPe/fZa9/+Df/8kaeJsyoQYRzY/jdmiJWas1EmHQctpImgM6Ra5cAGLwepAYl/+H
1nNWGOPlyRnI7qkA4gCG+5s8BItRZIGeDD1ObuZAMFBS4LHbCvvW8NngiaJ1o5+7zKRq9kXDblEu
22lzFu/4TuItOdxlLh4kQ+dd+xki49B8XcFMVpzaLhzRrE2DIrBMhlA6bySuPCXsot9uaag9l8ih
B6i6kCOi6vAUJC21+ta630PeGA4V4PgbxvgOf+aC7T2BIcCRX4E9LURXGv27i4dve0GuliR4dIRH
Znwaq5OG1SSrGP7WGWgKLJgUgOyEpDnTMZIFT6baXwmInQv05xTYz9yg6F/NIrsZEzLtt05WFdd9
m9MC9huIBSQ9PVcC0lxsVC+3TiTql9CCC5pRaKXSV1kCiEgLJIad6SEPXPFeYO2/K13ZVbTf4Wb5
GGTWIdF8nnAuvRfBzLBg5d+ZxV+aaPhcFZe3IDjUsoYXVeqrzxhTb/8EXDsVk2UFTmrk+WAla7rG
0AtYJ0CcVl2Bg2h/UBaPJu4+G0cLcpLJ7nYZ4H7doy4En0NRshSrj8WAM5ZRiMyjXi4aYZCuEDc+
i3s3l3LkuAnIzmSK5Gaw65xYoW/imFBLdQs35swQ3Cfjior4IFBujL+9LIjq8YprLispFu1cgcC+
H0mjNcnkB3chVT9fpI/8LaZfSUk8xSnmor7SPfiY1i123idJuqrJkthyndUvCGMCRX+BN8Pdx7d6
lmXdCBmHDYXwvC3JLosVfQ9i4Ih/jc01Dau+hraAuAUiL/UHgKjBZkGqikLJJN9N7deYFyB2a4T2
gnXE0cvRByfQmavh5tF1HJtLVFTUGx6UqF8Rbn4oq3P8CqoigCskUdg1wNX0iRXdNx2X/6BTUN1r
meFWiuBmM5fnJwVr7JJOI3wqSl2bJDm83QLehVgC264Yrf+8d7Xfn5dEX6fRlbA2YIe5lVxUGvxn
VAKajliuW0ca3apdHxAVLFjHtlq43inBomTcs8FtuQb6f6wCdyTm4fPvW+w4GzgkJfNqmVo7BqDr
nBxCOfsrbfkhyGaQuRoQ6HvF7fkVmdBSY6S4/CRSmGsbdvTxOoDmG/hOYKGYujViKrIrLT2iwWpJ
Dlx9/8AtbUUnKZdHR90Tt5cWND1+8rAcEq51Qn4WS4IWt89ogZqDeBS8NjxVfe3+d4RSKqH0m8G9
avh0qURudWBAPSGGVVpJ5jgKg6cqE7SXmFCnvrOR6NhV3MmJdKlHQi0R6ie6AtNenrDY1zQv4lcJ
1vi5FeRMztbsd+GhhlNk9lwNKcQLX9fl1MDc6b5pqRcgt1GXcGc9DgOqozC3KoUMkig/fLbuOcj0
xxJMkhklQ0c1LZ2oIHL7SLqA0aKRlgdVynMlWDeLryiIrTr+tejJ/OjFuCovzz//rHdZAQgPo7cX
scja/7x+BOFvmPyF0FaBfZh9eFFxMv1mL4UI1GwWpEzmBAXKe7jAivNb2XcVSPARwffB+w58oCrK
Bg/1xUujcaMvgzQBd1ur/FeVPF3wL7fMKEAzG8nF71c/BMIK/pLYbNIwRAPUssAxuUNV+8BaN6rm
CZGNZV26GDAlmGHZ3AGEJbfPsPHBl/Z+8DFbuCm9fmZat5gHOdZybQOvUWxY0r9CsLyh+LRyJ82d
MGmsXNWgR3yPeOy8b+S5pmTA5Y9P+NkBv08jrBz/GudYfBolxS5DRNoPNZf4Hs1es9SAQNNfgEks
Xp6vYp4AUR9cDHlIdVZgxxJ2ZHJ7rrMhh2WoS5fmFF4r9klavWTIxUiH2cUc7mCfSCIc+Ilr6O+P
hLcf8ghZoIOyduX+XpxSuK1oYFP9jh0m10wmd3mopQ7SxC4dvP+9hf604xo0BufMtkNX7VWCXTe3
WSositmUM8fuoGNDOjasxyHKzKV5QXFJ6qQEqZXAS9oMtGW/XYrZE/GHFbxMR+bhIgXzSnLTUQ/y
voBWSbDoEmBogNM3rTwEnvXeNITVGFI/RHeVTmonLoMOIuuRLrG8KdDPciFKErTivPHqqOArCOim
Knbq5qlksOVqV9GYlWzEk+NhsmOs/Csv4kG5z7X5nA1fmlxawu0RhgZYrDJx1IX/OWeN4LEup34i
rPhEXpt5c/ILtFHk8NlpYKHlNRvb7ehcmnoXMXMRROBYqNvda4Wbjnd03ks1/+ahqE+BE7PicyBM
i07HN+5Rs0Yd1xsQEEUgl5YLS1oq0OCcOsrbisuDP7Cx9Z3UOPXe9m1zmkCrf8RYTwMyiTkkrm+k
Up/z/4zhWIzuYbNTEIXbenGEAtk0IxABialN+wWj3GVp37zc9jkvfyayKyI1k/3dqpYmEcTfujXw
mfY0EjNq/+qK5YFUcQ4PE+9ioxspIoo/NCPjlh91Nd5w7Al9xNr6bhLS+RqgIhzI0sbLINYkXdcQ
WYYB66oa32KAk8DW1DBzO5ii47rbELPLRC1czyXmhMRGV7c4m/I3HKBZFScWmPM0Ln65xBckq+P3
vP2Keyscvv0eEY4J2iIMxKA2HOZQu/xRYrMOBTAZE6TtPwG2g3bCJ+DEnQRYihCEFOJeVpbOm16J
slQT4pM7F9e9mNxn4zxqScgylaqr2HL671XwXxLMAM2zK8YXoEX7kclqKTe0JNp3ZKNi04p1VcM+
VzAE0qxFY1cm7ILxLsiydbgPbWk+sERqCdX1/Oem/G/YHpaGUQO0n1YRIxv7y/mM3s/zwvyFBdUm
9UKIZDewrifJipJ7wbbBDUG1RPNSQpAyrVBb6oXpyzkBse4wQ4/LkZcJ7y+YHm/lXi4FDaPlNuvg
tDmoYky/kDswI0ua5hHxo+ROvWxl6wDi25SBrSfdUk1mZSAO9EJz6jOCfPYQCMkjy45P8PSyifB9
l87grQZApEm7qMdFPMq08/trVIgpHmqdG0pr8rjRR+orxmUL6CxOWGDHVp7cKJnq/MuUktnerpYa
zsLj3AL9N97pfRWU0xZ9LiX8tTZ621fU7jrlPCbiORFoxx3BgC6KYdVznrpUel7Vyi+k+co3gBII
j3aJLvzRThcnH7QhcttjOSGf7TwGXkt8HRaKWENHs4AdF5azgMa/OLi5I45uAfpdkLqrwvP7FeI6
ZXHgOLvQjOsvVn+NPyFagzf6hMcel9JBH/D/sBKtVmMTcxeiQ6K0Y7yCPwcODVfgzdwGZfAI7xcp
NITE1EG8T/3Xg89Y3RBuxh23A41aQySOeJyDEAHAvnqiPkTJM+dyaj7UMHjRggNP6Vwcvu0yUrSD
D6ll3c9gq/yZ+RnDNKTgwB5YRFIbggBz/4b8MbmbsF4vQRwRNLTAaKEoyLEJeGhFAUaym/ddRnKB
yfLy69UaiUlV4NdcWPg0nYWNxUPQ4+ctvHFpe2dNfHcoo4kKVkrNWGt7FY7AnzWSujP0tvWhXhaM
oh1QCTEMf+FbxgQUBpbhWJMeFjp6Pr2wynH5S7zz2hj9ohv8lJ3YnDlDnPavDkakijXP67aayWxn
JYL181lvKvniCLiyoVQB5+0Griad3HDBkFYdcS4wjXReRPMzTNcHeFLnlzFuUHHMeytEBlIcdTgr
udFoF1oLcdSqg6aoT3HpqHFSfftzw45IqniPqvsRxcKO9VTWh2FgKyd5C0Sa66yENGjwoyezoABh
AhHSJkPMJyI/3EQbqa6EIzKFlTNU71DEIcyVm8qLGsMK8NPmu5P9dOPMNhPHV/L6f3WOpMB7VpuE
fZW3bYw1yOwm56lEi2FovfQOe6shLvdkvVV0LDiBrSLsBFz01x38EfUdUALXUu3H4VRmLnn7MgRP
JC9sjNWdC5LYO7D452h8DGMT9FRSGlH85P978h9GHwjMYO8XiMpVhG5wTzVEDe27Y3panEl9KSCz
/PAm5UjtGi3ywc2cH1BtjsL5G/s2C8+e/hwJrMqYTtDT7XShZWTXIf2Kqu5zULPqeEU6E593VIMG
EQtdrUJr32kM5oAvReVI3wImvMBI/rtIbXd/PIuW/kqHENs0SbAP4M9H/VjcxBcabLPVyUO6PxLU
6JA/PvVYrnCz+RDo6J9YWDc2e8X8K8+Qae4TVvAMH+DHy5qiTnman6fj/RQV/oLgcqcAmSQQxDVK
w066mPxn8Dco4oKRcMJWs1j6XK7EpJdGaWALq4rBNiq+NG7AxpzUxErzsSNc4I4m4ZChEg+iVIrG
La56KLJZ6/8lfd5gY6+G6qkdPNsUMWO4vav1i9ag1pdI7xCX/rBpEx7Z38JnCnnCRuuFniWh+0yu
YlNnOksvVIcTFQx90jSwEhP+YJSgZjIIrU3R6XdraM+l0Qr2KBSQLCGEvs0wSZp8OEUvbOxbyo+P
nZ7k/re43J5N/qn/GCEZq1JR2ENAE1n5H2qdtHDup3wm6eb7tITwWFQbPrAmwSGRF8va6OKPCVtR
VyOD4CqlencORWeD9QGrWiQEOePbC2yZDuSN/szsF1UxKEiAD7L7ifGFO/lvlNnXqHSTmR8Z+1+R
ZxUE506sFmMnnvTGN8NDESkTaI+h8oboZ9bO5i3hbrZT6+i9enO1Vbgv0BdZ3TrpUVlVaYbbHuuM
K5XXEZzyo7AYrxtBiKhRVBACj8Qlpo8QAFqF9cXWhlDpZgMlB2QNGIZR3AE+DvBYF3Ddb9QifnBk
NodbHQv+y0Wfbdiz+UQkdYr7glQAf3+R7GfUlnuHFfmrYiusjPjHV29pFycByyGRHfDx0ncuyGYL
W6wrlUSjNPeAJuMFRkqD5JU6udeqgDXjp4QJTEf/azTcoswhlhwilezhCltyfImyEqu66uT7HNjl
Fh+D6yWISEcRZatnBfGQ4Oa9+Is9rUvMJlXmCgE5WGWN+QBgzWHmsml1QTHuyHFZPtcVvOyUjp4f
aZtP2W5jI+RBE2IJNNTqDK1I1s6EWCzxwY9zqOozHrqK6GFasIHd7BZ12nkNBFJHtNJKCIziSlnX
94wdiXinJTx22VOMT24vg9wa5RTDE1KEergxOlBVeexBHUBOuwhZiJ5mJNZNv5+CDQbtVMHT2eU2
yEb1I02GVBeGWcCVe70WVVag0OriQjdMQ1PU1JksEmhlpr/IPU9R9pgxZwnHhSxyGjUhzi8OhbaR
NkbXEf7dL7aWBbwCPEqp9tY182P9NktS73S8iWb3TjOwJbTBGio/qYCF9hx+0dFlAIZ7WdeRkJ0h
RddKyuC17GnR+nsmQ0u4WLIOxpNNtEHwC9LuHmFdIkx61TU1+dJBDEhSTJL8q6rO57QIyBNR+mR8
3OGzzhA0fHEhyRESof6kKJ1Yv4Wx1uUcE6kUW/RW1igEbEOD8KZO3+cT3jURspoi4M/KPFkW8gOH
S/3h7ZRulqTCQLljS6kXQNlFiOj3aFVC4HVWiK1uVdt1SapBpzYxclHy0BkV0IzfdM8SleBNDM/F
2nzxOhdC9mwr9QyKDGRfaS/Z/umejoprjfY=
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBDCFIFO36x16DR/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 61 | 90319 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bNIbShH2EA0CHyFd3tcKzqAAHVrbIPwWhMG9NsC+dQUSMA6xt4c379IBpTIXbcWcRu47Z+xjBDyZ
pmPIKJwXiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aHvYZyL6jZFeED4yBNrYXGt5D78L6XKvfv3d1wuLye6gycFxQz5GvWsSx0S6xMB9xfjAd58Otvbz
klFCQAqOIJ1v9j3fyjGrdYiRUTQuApDhC+FsIz/c7IXqHLMU7bYHwJKasO9SrDTWvXQ7ih9U0p2k
1AKMnh+qiHrYpQorG5A=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RiEdSHs/Bt5umPP6K79selbyluJtARUHU0yj5nYfHoqZIAm8WpvDCQm54C/KO7nPLeyv8jHIHHlo
ALGpGGe0PjfMvHDpFSP2vV238cyunFX8V0T9k8bl6wjYh6At9VhihdwfU2o+IX5VBj8SP9UjNVm7
vVF4zMGwAkPIQLbID37yUDY79ZMmCkWbDezMLjj3KJUww291O1rtjgyC9U405d49Oz2JWy3P7QMn
8qdrMZbOorlxSjkf+hkEIpgWhS+pbRjZ8wYGv6o7pRDkDsG3+S5QG9lWf289rXA2RQvNu+gKmbHa
+29rBsgGnvv//KXcwxU1LPRwDeg4UvorpCIeXA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1kXEElfRhCg/jAKI1qgX87/xWqRpS0e1DlrBHXO8aH5H5hRB8yNxfJpWnAEYapsnx3bdBnU1AAyT
aS1HwJVWR+nZKer5YXEg9XX/LwYQGdvNDMOsfvUNry+U7z6Kbe/UEvv6lt1y8KsQyYySOWeC/GkY
gvuKcUlrP9I2nyTJMAM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mYglWFHrB9KUMFOAglZNRnS7Lnvi5gZL2XwL13GIjD89oHQqVk29jGx2KCeeLHh/cuuqyyaX8cnu
wVXmf6095a3qNER/BkizDns2ON7gXlfqDwAiwRQlnbHJVhuv339KnW9GIEeggUZhg16lG/xuic29
kcyTsJU92tL+0bqVkxdCDfWly3o+vB011FmTnOJvdxGOerq/smn5f+CNTSqTx6aWySd4focWp3FP
1IRx8Cjqp34czZQNDbnzZ90IVxyJuFmmDpW8roK21NFNjW7dbg4hrFdS8qcX75ES6c0+1Ad9MDUf
dJImpXUL0bDTxErqK6kqA1RFpvNA/Wd7osKy7g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65120)
`protect data_block
UZbNrxS4mSBhmAa3/X3oJLd1xGA21L5S7fYTS3C4Pl00SQLq0khiWZDE/rMLjNoEn/Q9gqXAkf5r
dS0XkN7psKi4vAgvXgDb6jUyeJQcZaaPu6bEMK2QiZKC2z7AfnWk7MweZnbr+H7GReUnwdm2DK51
MDcXAb9rAcRjGckM+m4YyD4npVSOWgiFba/ZCF/kZcw7zFb9ijQ+VQdl8daOjRzJKdrHK1D2eNf9
0PnNyiU1FyuhGX1RchUAy3ee7ah9wpq2y/z2eKsBDjl6E9tYZixrW46WC7vks9Zm75taH1XlwaMO
CKYBXLPHXoS25FIiforI3jJ4ChKnNpdDRHq7DJkvcgDCtf128Z+0cYoEj4i0Uiqk+PHV2jMY56CZ
jLzIOGBg2v1Cb0GlAZ5JpxHOs+tDnmbC1dfN9ZQxWmmt6lYd38K7ObLvOLlb+SZfrv/mvMLFMOZh
LCWQNCb3wXzbOHvo282/PfA3FRKlCCkMgrpTDuUOJC5r0wN78UqM0P7h8qdPaYt4Gft92w6HbWfl
8SWFMZUVrsEluKz7uqIwA5Y1MBFonm9lvHoe9slSuI19S3eThAFja8oX2KVPB0r5a1M1ERQDMyUO
YxKUgM4reBTzabbXjxvtUmnQSZjA+vsOj+knTLArWKOR6keaTAnQzjX6p+A5kfObnm9bFjPhmXDJ
iWX09FLa/hRH+lEPGs4TRAJvnoQoxgOmk7Cbi8o8sIQ5tRbeQPPW67NP10qeReefMGC1xARho2V8
JKgB5ykmD73sQobWmfG9ATGJLk724K2u6RKyzXvaJRSWh5GLMDLLWFm4yoUo23sQjxmOc1YWy42G
xN5jtvItXgIDYyQHCFHsmt8Cf7InFR4/ipGwwhI0yIewnOpTdUHhU63Su/X16kcX2kdjZa+0ipef
PQJh5HcnenyIgnD/QV0j3cTwiDlMLz0FMnmztT/kIgCpoAtAWGkskdopjV8bSN4XD5FVdayIcfNa
s9Z5730GrRHDCsA0SqbY0AtL6TwO91nARi8dxhEbBBIEUUALlWfUovxkAWJE5Yctz+WCJlP6jkqW
rFvUOzzXdgfJN3JdbNxXxUXXT9YlY8/N4CmgcX2gMkhHD4OpWQ6TBbN52XaOVlg7V9fvu4w55FHi
m/cVGzCN1EPT+61xCn31LxgxoE2JVJAJ544iwW2NvF4B7qV0StyyPNf9xmQcf1DSaaCWIpUOEkaZ
UwfZ+UHM97i/RqQcfgYIzcPonzsncl9Hdh8RvrLNatNqz7PRxkJ2t6i0vt5Jw4FxE1LIjqJp37lX
E63m97NCllBg+LCSOiYUBCGEBgl08bv/00dWT4zCB8rv4R04hAGUy4Ir7UHfQgXqfyoW8Cjwz0jL
jqrKh9LKITt02SWJUlRYpEfE0L1kjf8ZllJGoHVtiQRrbgFrl4myYmb76Sol+0Sn0jLWi0C3Wai4
LoKxAvicVXyC7SdwKOY7Hq7XdzuCeV9YfueO1D5IcvfRxQwYBmTXrdE/1TL7vY2Ria00EBfrJT6o
QabZw4upbGGuBE/ofODUWCT+iUy4nH7ohJgWtQ3nXbcMxGd/x0azGmLwNOs1Rd/aDxDJ6qgflrMv
m9xUJmNjQlJt5+gaoJZq+8zXK2l8AAMT9/5HBPNJiYIsAIWteyv91YzOtXO5Ni4sv4W8FSAo5V02
VUWp6ZGYEWnqDHLbygEZj24es+kY726v7PZwffJ5tHxDnrqYIjCFRipPQVvw3juT8Us8WzRsVXhx
aYa7iz+vGaDoVySo1M7nUbExvslkbSmJBH56nAxtjX+nv79/w/aB/o9xFBPGeYGXQnbbuZs/w82x
/HJYz1chqR1opC36GbHHxnDBGdXUeE0/eL5Qe0jLERRMuXleX18gIOhvIZdQPe255isxx0HydhAq
WPsH9IFZ5/GRmyUYYpLPaRrKvoItNs1j+5JHqKbhk912CuCFKAPo3V8vMsca1necdW4sJrejr5d8
sIyNo1v9Fy+ytjx2mlt7/I5u0nuV17+retHsEELPd8xps6xXcT4kGXIs3oqMu2QPtfb9FcHzSxba
+i0/Ii6oI0e3iJKrj5nGDdDw36xDPiudwP6tgaexhfzcsz/CoO+Zb6a9XEdFUFJFZPHx975wfOj6
/XULNYhnno8vXhao6J+HcywhnsvXbdO9qLur8ljzAjALm2zSqr1jokwJqGlYM9N6bMDFQepDXUFx
GUaE2G/Kxn84JlxJgLzMYSl/2gNomUVjvGOVdLLqIaYrS9Gc63Avw/cG0Hu1AAI2RyPhWheLaTAm
Vns+bdl8N3uhotXMGr3UpAwepwqlzuHh5syyEKYXL+JAs6TlkWer8oGJsKdRuSmrsUQYOZ0btvvt
hDQTSy85DsP+0BP32TseifmlDIiDv+CjMJt+k/vSmyU2FAkOH72wVG0qBzRKbUC6IPlYrnaYJLsS
Y9jLu4+OSZI1FQHnHStL994BMlgrvvUpQSU7YqWXVRmsuBc9dEP+3D/eMWqJ5vXxAHThoU/1AJ7e
SRBzpf7g7uT/VwwWIadimOrsdJvZ5A3yH8xbMDjo771psFV3xH/vs/6eeZIpaVOl+UoY6nCiJgRG
npoSYiVxXG6RkPdI0s8pvfNBFLvNQus/Aisf5w7Px3pV2RCEFjcUhqdjgyRwFOOwhkhf2/sd2osj
6s+gogUydB6QITrIe104Jo3cqzc/nI4/fowat9+lLRbrTjcoJtxqUTBYpDFuh3v4ipP41DneFEJt
DyqdPG5mx7GuuXk4bjGwn8n6cy+K/kfYun1U/eZ+HPU09iVCQv5EAk8yjOlvvTDcH6QmVRM6NsZI
PleWfMb5hg4AD8KqBd25vxamesKjqtZKR7H/we25CX1/+a838gzulGPzqb7U4rpL5DVTxac69aEm
gmvGHdWHieSsgoAKMmvtvNx/RHjpxlM2x1JOEAkdOdeZu4TDKAp/N/LMaqk5uXMU10fv3SFnvIUC
+MxlAF4s1uF4w/rkBP50WNAbhKsnJhosP4leXbSocFfjSVBUulaAaD0dIrsoUZ9IpjZYbxUxYpZk
p+m9P21xIdRTGLZ29Yifp65VcNOjA7uszdrrs6N+1QKJV+7frqHcdE/d/tyBrdy4EQyRdDQqnW5o
WhxtFb5DX4pS6YQJ1qO61KXA66W9h4jbhAKqGKgOEwjQKAD9G6LEAYPF/wWdp2mob/G/hfnem3Dr
boGSAzj3DACHF1cWhkgQXdbiFxuS6USN5amcsjZ0W/pEduCBDjoKumcNGfl86FqbRr4NVYvJWmyE
xydb48w5sBxM3CwlI4vgJMxBXwAp87YoHNkAtLdMOUcd3BCCVUqUDF3xGKovIlkbf8bwKCKNXvKM
6iy576fCjZTe32MCGigVBxJTTnVY0LmvtYicYG83a+8XmYkKAIsBniCTEsbKBnG1wsdEBLBgX+QL
U1IWID/4tqeshDpcdfA8dDz7BelrtuQTOrU1nQgoRabFRTlF+q+jof4TZd2TK1o2iOAYCjmy6Cp5
q0FmFNlJaiJmgxxn3+g/+sl1Pd9zEWlqulbTZFb+YQ+UcHkvpVDAgZSgEXhMriD9x4xF3+F9RHC2
ztaWGpSpLaJkFT9DAGLv89suWCU+7m3XZLT73HVbmVdRJ9+8GE495u6aralHA3UHw8xsRIAm0STC
46HUHc2zpSgWCw7VbfUJUdqyj277rEn5aatMXNTDiotCNEL7J7RU4lGUVE38xk3BroOUVdASwUts
Dub7eGlXF5BfXHgXn0Fml/d5uCpqstDBMhulEa1s4ak/btXL4YyYlD6zu/QVoNsYdzDuwHp2/Oet
PPP5wyb7BY+YFkbLoLKMv92SPY7QAlkbC2yxqyqRJuzyhF15VDq6lknh6blwHPx1AzTfHisXe2n9
BML847+c0MkZwBPnqDTQuEXUvYmJcA0kSEDtuUXTH+aFICXnsOMis+Jy85iFc/MXYn5aKl25B7P1
+PdBZYngWUQlG+M4CVlNEsy2/nJ/F6QZdU6vWv+qDKowCG+n2Hrf2BJXFQiky6uoKO2fzGYpP4/v
Y2Lw7jenBzZu8G+8s6lPgVnLMJimQSILbTAbOBTzGqYthkso+zXwakQUm7V6tiCeujAatEucxj5X
V1tXxSJyK4G/+tH/R5eU5bt05FaEJUut+8HuQFxi7Iz25YO9qKu5GwG3A2JV4lWB3tqEvbJABNK4
QRqTHOP6IY92Ry5KR5mJb7NpJfVURUM4R7yVG6aD5DM7IOiPY2805lelOkJQahAXz+g03ROvEj7y
vRHj+dHBQLVGvNvl1jfKNGCUWn3ahrxI7A2eGU0vUVAhs4nSfgG1QjC2YMqEVG/xn709uoaqiN5p
Lde2mKjMevATOn/t3UMXfOl2yCR86PWVSfaqrhiTKTt4sjAYRbx1siAApqDDoOjwNulB+S+2q7Tp
HJydgu3j9O6ib2GBO2eAMWef3H0ZWyIGZSqBaOWKbtklDAiL5S7rgafCsOzyZqtIbh6KGZYmx3oo
SmUuVmQetapF88SP/tfbL7hC4HkbWJbZ8Hp55H+EVmpiugvkaD69Lbzv2nC5bS/OgXZwQhmQ5hNU
IvENlcBCa7geKJFb425glhBfBSGMOK3om8tPyiXWgEQ+As125H7eFgEJ+hhQOGE4p9xtX2LZlbFI
2M5hht49GC7YwHbrnJMPznwVKOPlQ/KsfqBuSa3M7tlxeSGyko+jk/5YvDbhG+wQvCYjGoGiM2CB
fajXv4ZrfoPeu9/V6gX91v0Ewqsbhu3LvCoVZ509iYfn2g88CIE/zzDO7vSwqZ45nQebSn/fqTrj
BA7YW267ZwVJF8oor9sPAEVPx2H1R5PzDsK0CUeoTRDRZlUsjAI+zwLzpj3ZmO769fL+5bYUWWSy
tmvN/btFTV2LCxc13WSTJzE9sbzO7tKZbsaN5LwDtc7OBLK6rPL+jttKGzeQ4Qqd18xwh2Pwp31z
7zOVyPpTNAc3D7p+sc44vLKLfznV1/n8h9EEY8FSq2caFFdilsx97NjgiUg79nwtQoIO+cKI/YYv
/TFOfkySNpeBRj/wv7BES3Uetjr1tJhl3A3ZkE675+PNgGEVV7vfHbWK5Sx0NCAy5uiqUpfsWAp7
a7xeRYJ/ZKkgdL2ZG42He0y+HZ4g5gZEdyb5OKerKByCh2LbeS7hzrfAERY6nuKygHtOzAFJVFyg
aKtSApm+ZuSJ4ASdd7VxcEkP9cvWMb+lQH0PpdTiQsBSwRnPXngzZcapZ+IeDMkw113YF0wMFDzK
Vt+x3extWVm5p5cmyBcRgtbYpsFiY7apjZjSgPGEciyF1wMNC/S+BB7ScFyHqvZQj4Iw/lyEKJE6
nzlzBb4wyIAqmz5UoX8lKk9BSLenOUrRR24F4JeGTjBPRw9h8eaoCB+abt7m8TQJIL9PKGtTSGYu
fTuRH7Ii4jqxVIZCdYzbzTkwsbD5FEz4dlRAfVnP8Mjsa1nvzhS0A2Y9xeBhHTm/EVXGt5mSAZ1v
HJs+5xtysvLLL0F/vfcWixXPhbgkoCRGHhdjJi54Blz2Hu8yAVzj986/KeyS2+VHqsSQZbbW5gds
n0adW+gJ00yIlKA5qseWI4H6bSNSILoDx8lgcpyhQjfhphOVe7LFlqUa7BuB5CxFJVjVeOCDv0xf
OsYO1DXb9rGJ8vO1MFCMhvpWUxKXeB2Z+Ti9P7qIVFYY3Dvzb/aJFmF3l2pm2sKcJo9OA076HY96
0D/OUyYxuorREJWJDxeYecBqFdszCm444cHaCpz0ctDfgK96D3BSSBkLGPmTAVSR6TGezmUBF2Nu
wYZwiBTQkAZ8ocsmyg8IuKyML/hbmgvVO9pANxCKU0JUYcwDv5pniaoqolmg42cM2sgYyBOXsLZR
yv60V6ucThqDOPe7wwfq5IMfNiaJeR4fhHdcO8P9AW4P8tzZPk6n+ZXN63vQgiYLeUP/Q3hCJjDN
N/hfPLtf44uL+yse4IxB5qdcCLnmpVEvSyjAHR2nU6JY4NwMoKpHXi3EG4TLR5y+hY0vqXOEKaD8
+fWIHUoQZ9dSpMOkcWoTVBqnSH+XIXoGkkqLwZ5P0X+sC1TZRFS7EPIHj9gDw5JgfPf7VVjcnNg+
bJRjMXKp0IrPfrjxi/gNAHT1eChjLxvXFq94QOmQGqoJM4415PDw63Sg8e3JjK2q5VbKREQTwJJP
S0ArGMgkL7+1mtC2i6LRE61rfRsNbfsMefi04m0Ngl9q5qsbBEaIgDFJf+Usu5VaOCn9dHU07CFN
Bf/MpBf5RPJVth0aLIRTTrzlyhtMrDrpzCpzKVxd85+vyhVXEVJCbOyXd7DCojgbSRZbQ7lho8y+
4gfOdXjvtFOh9tPsbqu0FPa4BYi62hjZRH2lj+MsHPJ9MuopstdikVUaNz4tHmiADX2MTdlZzG1j
ygGByxv6g82ugU5Lncor4W2u0U8dM34qRbRgSNppCiYAt2nwo4w22mSR8rLxo1vKSKArvwRni/bf
hYcpDmMxfuDCQ9iUhku/pKQS7GQxgb5BmGBJxsLOqn3OVN2sucpIQijd2Hw8IbFtKL0pFIWushji
4uGy4xGJVbDZ1bVxnXiRtp8JLTDSAQVfraIfiwOupbFyUcfdtdgIv/STLHHyeppgsQvdzY5B+vAH
rdfoNn/1wP4HxjjfF9V2kOkLdmei337qXahXZIQITExpCj/yhfmGKeRfYSbAdF2dpImmMm4a9ucK
3KoEVG0gmFClz0mZe+nper0zn/RY8+HoH4BmFZkNtMyoOwUmc+eGWhnay2KQdbMYC7ZVIMRkwv1L
dyobYj3RsC9KE8gK49K/XwDtQ6HCAz1AXzV5u62iLDSWznRAiAZgFqbGmByUKTd39xemCVHXyFv+
x+AEjeD+7jHYEn8C1IIldJ5HxDapb3f8xo8FHjfugNnZIeWW5OCnNlpj0GjrgDc1RiVWnPn11iq/
sgZg9jPi29ZSzmm9oI0gnMrpTZRuoEsg6QNFkU6boHnEcK4Ic6RcxQ8gc6taVW959XUzpX3CLiFP
dHaZ92Zk1H9d9oVd84oDJq2kCykaiJhZdBve9qA0M8ViZ+qCzwchvI6rNL9DQtQwokIxtNoEDWyy
tdJLWBXFRma4EXv8W/dIelkwwS57d1faEqJ2gxqQ6B8ZrtUAgdw5V58SZKRN5tqeRvK0GjfexLxU
wodaVKtC5NcXdYpa09HJB3uLd53aojfo7pDMcrYUVQ2Qm8KXQB/M/mRbP1JTUTlbor6h262q5rWp
pezDMR5riFeaf7n8jgONnzbT7d97NKJhi3djXOAwtAooo/kpJxl4gNhZgy17OWJ9j+I2HFDR/dUk
qah2loubyR5OfnmtAu9yA4GFNtUQph4Qg/rwfN+pi3HH/Ehr9V9F4zq3f6srXc9s9sOph851EOqh
q2mFrP7x16fXpjbHPklmTiugnmq45r02GK3GIuKLFFa2nSkjHYCCO/80gexGiioZWWKxS4lKYn2A
8jr49pOo+m1IrDyU8fdNZTAMLVfzGXRokuj1m2kOH0gV/14HVcBG4uCl9oq3RZ9eNQOIfhEmHH80
ZbR0Jhyqi2jlQMUhPGjVA6QLZpD3sG3zYKGpWmVxGxAeJi0vdJJofxzYNOQ5p2EDluUG/sklzxuo
YRauV8B1EUkEPfQhQ6C17zr8523KMuDNs13Kk4NVHZz0mEivfRBDvwElesF6g/hxHlc4tH/zBXoF
9lEw8ScEnMOiM/XbCVbjn0fnBvwF55LRE2Sr9WQHi+YRJRcBBRQE8mXSgpUU0454G91TPhsQ7WZZ
dKyOfRS1B9JVDMAQRTfx9eAbIP7yIGnXzmFEGGk7F+YWWV9chsFBAA8MNvzrMG40N1shPJk5WUb9
Illkg1a9sbLrHHB8ql0WePNb/bHw1yXQggBmuHCtgOhU2FRWOms1W1omAkXe2Abq+7GSh9VZGq+u
m+y35O2AssAaQoiviQyRN/CkBs1phtTja37sAFKp64FOlKI9aHvNlLjW3vul3iktNWmESt9Wd1+c
Al7wNbiczlTD7yqqKjJb0h00sjS90vbQGJnhE+K+LBKg//d6+Yf1b9rdbuG2HNHD/kvprl+ymywX
QCYOPK3+u00SolQIVCndmBO++CvbNn7arLyP1Piyte6qq22A3tio4pyWl4s6CVoW1mnay0p1qLHe
Sk4qvDYQnplJNWZfTSQsH87GN1XtXFbot0XqHSuFyjbwi2dzA4rrzVdu7vq9hSODnMLWkn++2Bhc
LsXCq5pYQh+fd1ShtgAf1rY7Jp3ZyouxUN96s6fsQZ7VIjEYSvkAgRAHtLS34eYzBTrzu17rtikJ
hUGqS9kS8fL4Sgj5Gu+xvNUuqCeF0ox/FvrPNoaQc3GP8sqPcnxRftYVHBSvlE+ph8F08qNy9USp
m1+G2pqXyTH0GGw+sFR+wIaz/WXqwphROhLuYXsKNaJmu5CjAl1NIGItFZ7sAM4iWupJnnaruVK5
xAw7k7mglVBa4ZXRmtm6T51VBmeGzQ0M8F8z9B1uWP8z/o8r5MMUlKSUsbHbOzO/PFtmVMRxJy4r
1Ngudi2v+ub3ILDqUwoMWRLRjkqGb+BmE6YuypKe0BJc8391MJP63QBeFJEQyA+iuVxOK1LW9Uow
fVxHb6UA0gxmgEx7Mt4x/BoGKo16utTd7v/EbEVycAkOWZcHKKhO9x8dMKODuH5oZrk8WFIBj0c/
h154CjgTvPobOtu0ILQVNHdeV8CWmzWZWxcc18YvshnjLu1v9MrIce78BblkWJO3DTnKDihVFhgI
AM9IeW8hqL11rYVHz1lJM739vF0nFnwTRo2HHJFu/6lVbfy6sLAmqOID/bl+OcbBzDO3UrPRoyGv
d38sczo8R6uJr8frv46Pg//kgIrEpn8Hc9f3zFqbiO7DitL+EHIii4auBg/pC8BPSunD6yNNu00u
0+A8eJDCRysalxz1EwQukaFfRFR44nZ7WW0v1wrGWnFl6W2spgkHngnAOmcHW7NG238tvyB9HW3k
043/8v+XIkD6z4CZJYrrhF5niwVf/HXL/eS3X+y+HGvzE/dhxnDBpF7x34hHILmW9/xz3kWVVQLD
yHouwsoaZWq8ahtulUrzTzkaxJBlVB62Fqs9hJXO6fk7Kq3k70vVMnpzRjBkW0saCEUjqV36GpVW
2iuEW5ud/9WGyYHFzSg2FYjADHokQjs4dLypj4KMQHPwpwdVzAMsWwqE8vytsUV/TIuGpLY+MIdZ
8uaxXge4ZJ+JXFQqeICq2Fhv7/Ihs6Q3P6UTlhnGHbxQlP0QzJUEo5TXlXa8ujalLLOoB68Y+J8i
/8TRyHda0SVHyHWFyp7maDi144yAjbS89xpSHuD9lNgLXMbe74AZ55wAgD/oCCNDF0SPBPky5qma
KqE8WCV6h2CkN+HrC6AgHF69mZ+qjmMRO5h2P6bjb+os8snBp393jiFuewhEbo/xsBYIhBFN3Tvm
M72P2LEVnMyguso5WnkEpfP1S11oZpSul4YdJs1QPNhmcr4jnpAN9bEjSldwL1FqgC7PYp9bDrbe
TJoHTKQ36ctwAR6SRjpoPxcmWrUMnoI0rcieNLKLN7vZajvi6SGODkBHBON1kTJ0el7zOYWztfdU
fgjatO6dE2od8CSLvBqR7dVVpGIiCBGw+g3MwAgyCB1QNvyoc2nNM8AcqTi0GCljfK8QvunGfiDi
JqI3uO2zNx+QZcCxXN1IO6bSUYI1c1TimmRPs2a65vELggupdWgeAheBPO0OatgA6vev2gWm/q2w
WhCQeHuNZrMDVdir2LckagkMvipS5drgPUQpfI3SJOgupgrdKCfaZSsoWKfe/cbNp9GXk6Hb7L9q
xkbsIrfdIef9k6Zl3+JRzdXyP5kjno37rXAKC4WZYI7ePFxPrSz7hL1b9+S8ua0kRjkpxrmV0dUe
LK0fizjuTqPl+gKW21aBBUbipvFCqUrqdmXkn9QoHHUsEgf9pDaL1IlTiacBX+Di9eP75WzctYLI
5HdKG7DxIevBFr7xlkRr55jk1zDUN6ht7wgs6RtxZjuUv8PpjtrCmcOO8D5OxDa2z5uPB713+wwR
0A9KGC1OvrDf7/+YLO7KR+OkR1LPlkCZJk6HWREIsCWGPiHCYxyDxvwkyFi1qP5kW3SFfpDLBTg/
LhuczbVPmDQjR7xD9JpSk4n2BqXuZ6t4JsuFBdZ+TnIzZwXpppqSAsLEpM4WTgwXkI5pKW4VW2+a
5vOIkuT0Fz8jIPeGBivWQYWTsro1Hj1+6RSZhlpHFMFfO7E61O/p+somAucX0HId7q1wlIPS0Eqh
+Rwu7xXBjHlDTJ7Xv78r3EAQwM9O5lACgFTqbvulO253T0WzZZLxPk/J2/5aN0wY1wtsVFeE53yK
ktnD9VHsLhnU8ZaXRFwOEELEWgFrtq3Asz65AjWNGCj52XPAk7hrHw+RCARvVVZ7QZGu7IxCjiWo
ev7CtHwE59aOQaqWD3Zi5IbOVL2wTWwWG3nYj7rgJFcBNSi4m3ItYrBKZ5pPwZBWPPWuhffsxkRS
LI3BghBde/Clan0gANntYwWk1XWGvdObj7kHutb8rcLOthMKCU6xU+ddlBor0XPB3D5SxG+M4hKY
AZy+7OZuUUKvk8iP4s/kG9/Pojhfro+zkGgzoxS0prXUEAgY9oO+jhpwbYYkU24gefSTNTkMbfx/
zlEOwwY+Na/JHaISwLE85B29SeIAakE58oEKZnNFgEytDIIQ/KUhjppa3IVR+vwwCrW1AyyCdeOW
gEL7sJfHSLwKCZUzMbSAo0IjRNC1ecDVo+JVA/kIiLzjAcgWamBvKQUd0qxyIi03lsPi8tmN65Vc
taZL/cGfrrYy0NauwnWhmcxRj+cfWnBKyLVz9njMM32vwnK8MAeo8Kg7KZ+bd6DocmCGDK4Bcrm/
i2k3CphYWrZnOXeeA42kQ5Ah8eWYpRcSYJpnEXviu5wryqveyGTphRPz/YxrDD01IQ21SPR48Tfb
9p8tU7TybwioXm6aSft+Y2pSaPmGFzxemPofQPhrdqd8vSCm9HO4jukqt1feYJX3L4gtZiSnx2Bq
+kqLL9TXLdD7FfecWElHWneatF7jvDsvXd/5HBDwcJINuZsksFA4aj69sXRlkLma7ILyimXkqZo6
Pc6AQI6mIoy/+Ztzq4YJCWbUlYvCEjQBtLjPdGPLe5SMkrDYeYuCfeVXW74zO4huH46K6Cn/LVdq
mwsDBbI8ugnPI3vezMen5nYv1375K3S7UkRX21DkppG5trB9yLMosTqTCa/dZ6oS7KJ4S3cnTQAI
e9TzHpoRaIIVi8tARoSPzLS2HzJGwbzFyBmB/DQrMBkaoH/6hqNiiwPpipgEVt6Vp7Z2mIY5OSvy
/YJUr/uTDy9GS6uXQRRZoWd3yhJfATOvf6xOXsE60aGJzNI2Nzla6Z6COpwPPaKxTJZ8wuz5sQLB
b+GBROHxVV3wC/dTBZ5Dc2aUmpkGy3IjyMnCgGMemv1fH4I2wtnwocyu8rbMFSRsRhBQOzWlKYKi
doplWxzWUxfU9XGQNcyjMtHWYjrYHPqV3tSAsj/o6lQoV+RnQIWd8aQqXTEkhJIPqTYL5h/Y+y55
tEhaQ6KpbbxbH+WmismLgzy2vNeU5HTkZaLj752GqDbzZEAw61Z+1AehFFm6ocFUVDs1XHji41IO
A5XdyXXsp9TepCe5Hf3LzC3IAqtOTb4obx9gqOiqEYGqC9DfmNvmscd/8Q/17tdX30VAjT+gQsUr
ABj/EBDwgi3gi5+/AxMXtdrt/U71Wdc33QZinDE5qIEQTQ5wwGXosJRPKA/5tHUbC48BRYhgkINj
4HissckXbaIGb0QOI0v59JoMfx671D/Cj5wt8k9yvi5BXIgRvCuBZmXY0FLIN7xtgogQzQ6cXEPF
8lcguHNpQSO5S2A6zUe7giSaUJmvexC5W5sQ525klbNWVkkFMTDei7BmSUkGXTA8z6TOqTsUI0iy
YUW+b430k0CAzJlgyPoLlhLJZp39Ha74l1STT5xvm/jZnuwnq2LVF1booeNo5+pj7MpS7iibMwE0
fsTiH4W+mUIyJbwvHxSf4hGSHFTNji16oM9HGtuyrXcUjftuoN3f8S/LX7OX3yVBLKCOAUcqXlFi
7kxKDDMogenDjZbCqRtmxahQMYeXo3kBQUwhwTr38c7ka044BRR5Z31Ps777JblJ7W5n4vDKDCnF
NIh5GBE9e95yzht0JbPiQfNO44s8CmnU0zzw3yqBPLta6MV4wITOStc3ZT6KlQjq7cXOJhm7Sed7
4/9+gWEiGbTXVWIGkt3mfE7GJJ/Swyv1VWZFJY9TKo9FQHGxtSPDQeC9eqkCaR5uZ8cSOd/fHyEd
xxNp8qRcvYD5QEBS1qATVEuHOZ7ksXdhmXKe1dr9F6dbIqXZUIxeUzjMAG6jT6T71FIkFCjHl5+Q
M5q59QCLpzA0CfoNkpdPtDtbTswqxRUFkSdusVnxtPWiJUAltyA0R31h9Oi/Irulbygl6YkBtSQU
G7+PVHiqlYTV1TLfYCQHyK/h/JTiAltemFhKKO2Q0cv87Z5N9WWx0oQTgXpWQ7HMl7OCo+NAbpQO
3Ibdn6/0HbgMg2SCSggkJOwJzawR6LRVHySgbTtr0/2pDKdvq4RBaWv5apqTm7OeErD+BZMj4pqY
sbpzoUxsQQq5OP2d/FaSBrbHIIL7v4UXpvS9jbWD0mMHZDsoNF8AVcgbaiEfTnIdNT6VKJZnc+QM
nnKl18wiSadDzYSo6PgUGqHNklw5M6MBuQbcusRzvVblnmkmDVy14BtzPIBvm4BYTo55mJiokJZU
1eTqmggnPas0HaO0ybaCq+aodhWuv28u2uYGpbZnffNg9q1VtBJnwiZNoCHNKmHqO9DiqHI8ytBg
HqquMjbmz1tDwcJPBjmnPzMPd6aEnLF7Ax7UQgVJgB0IOyP8oqc0D0WxcTVX5f2EGqt60CF/HL+8
oh9lZHC0kOewqyxnthhNDw6WQDA9Y1U/a1Bxx/20ax4EiwUfrGORjRJKOIiYg48u7VEAL7P1CsmY
GUzvm9p3XR0dwps4Csv5ozki93T5QdfHXwa7/nugrGpZMtMwuU/kLw3IxXkNjAUT8Z8Jzj2Xi9+G
hBWV3TyE0jIhlGIrpfXHy7a4MtP9zGpL7WE70H0PMlmcwats/LfajQ+6pK5Ajg3XiFc3+RIZM7MZ
8Fi2N+JE3CKqnSC8aAfwCU4WnbridEwgOBbTyT2Nw8r3IyBHQ3jzCAYksJl10UGgmBhBQdELIzCG
kW4mmbxAAcGICdtW4+BNIyT9OTVCT6YWmaI0NQ6e1v6bj1hgLDfix4Rm2rqxuaCEDONdjuVU3dan
V6dVTuhMM4+HdnIQ0pLFWs3SsCPl5SG7ymUdakcg60M6zcQHG9ZmlzMq0s2SbTdfftMsYVQyfZrJ
GF1kVCw7j8o7o85qlugX2ThKTx2VO8/SultcF6CWhLzjNSxVRlZS25oxiTl3o1mk7CcRQG0tn8cf
7NV7IRZz87Fl4186CQOCNye/AO+wzgQZJzEJi8Arp1EBo0ueFe0IhrdldtEC/5ewiyFYMPe4Opbi
vYmfU7s9kV5c3itgGiF9jEr0C07TZmihszSJsm+uphcxXXDsgBc7SfnEhgOn7bfWdmMnbvZE2KTr
4MeAtoX3jxRbcyFDoNhdr0e/lHVmXtqvuH/JJTYjadx4APrwyvJUFoSQhPFqiEgcL6qtMqjN2/Ba
xKwSv203q4b9h3F5x6tNp39oD/LPXfVWtM5nybxglAXh6WHa2ZITrLincgCFFONqqakU611gMRfI
+noZVA87fQ89Be7+5JyCDiryYbhRaxY6R0Vl7EyjPnaVYDcisY0/iV65mhXFbFHhFl9uOLNnokKO
XqevUk1Ip/XQLvshi5xrqqwg1jjttGxUGq5VCJYhp4CrHX5gIY69Qw12vZqYkCH2GYdtNoa7FXjT
Jzj5UWZscux/QkSrYJ02jwFi9NGN/Je/pUqolxs822D5Yjvv2tVF7rcqe4kOOxu4K8RJ/mia2nrL
5J2F4QhH/F/XYBUVFAwIlKhkaC3zVFOqpU615/SF8gJQWOCLKfwVCSpVRoiahlxvY+v6Mpmeg++4
EcG0CqgytttfJzpHCi47B392sJ7tNxDVcKM/AqIDKF3UzmcSOIh34ZVhIZoAczyghIqdtYBGXtWk
d/oBTKdVxwNCMHRmQF56m78bfKOOCVv80QPttKC6AMcq1K+b18T3S9Upau6iGOiaUgbtUFwG7w82
VPvzV9I8XNAHfhSpzuqegXq9Yhq6l5+gU+0MxQ5IYZJwLD3PitkeAQ9i2Ax/p37FABe9oytEYQCS
HBaj6re9PwlIgZzb9s7RxbRd8MjrXOmS7VwmM9x6KVgYn4lZw6bkJ+/91qu+69rsaIaQQdDwc5VC
co1/sk7BHDvALpKW/HQRjFhn6nZrQJhTpI6Nqen5Qcocpicr7V0YEONCJlIjplr/n/X2zYWdXhj4
TdfWQaUghQxhRPTEfR0FiKpYnnP08C9+T78UtHKWeOPmzrF+M9OAF+atFLy2vv45ewr/gaFSJ+vf
eJAn4IIbEAU0COIQCo/cdnr58pFhEFvHHOXTjHIAveigqUnNsUCiulmnAP0z9Fl5vkzmL/gE6L9P
fYUTcPttu0aI0jv/Z/TWjKCrq+EFTDyWmw+nnKvRO8KIBb5Sk7mJfjNA/5HG6KKkY+DNvXS6tCHC
d06Tv70sJXt9N56Xd+ZxsZ15hOPpBPARrVyekSDCW5I/GrsJxw+JvMZGSGXSMt8gZLB96B7GtGJm
fUNPal4lKozB8SS9N6B/tG5HAi2uDzyX1LCzulMvZ8REbG30ewnxjekyPIS76DpP4HT0Klrg8lXp
kVKfcbl5IPNaQgVd+ZmcbtbYOnVvAY987MW8yZWi0H6xxT6eccxIpii4C930Xx9mK29wYJN0XkNt
X+7MxS/aJsVDauXlkL2ThzYjaMLEzTkvKu6LUvSeFoX5ruqjOE3x+tgbhc0taQQT8dhPsOgbxEIv
VMXm5PIPkGPdXpi4pnb+Lq8jSlRu4VFCfWWukbQAi0n/VdwywmiZgmcEpWI/pQqZZbGy407to3Zz
mhgIw3Na2jub5ZyW5XE+0jBuRCfZVFB9nXMXTuyBcVMhnWVKHetfF4i4bKeTXRcMCwz/zwg1+dpN
YjpR3DoYgsZstpclqJZnqA5XErt2hyFJooI3CEB880Aj8UTb9in6hj+AAwmZF7jEgcsQo809S9m+
etEFCRmjbF/kOhQEjzvTULbrVpEmKfsSoqboB3fGt8+/wtKUE5M5BaKfsAbhVwTmZX2fsxwQSI/m
pp7auDoOgzgcgPXrFItLHcdKUgxN8VrfVDg5AheJQH/LITf9Xz4u2vCoh3ax0KIJAgZ395MD/VaE
08Tl2i+jwNAY0f5Ji36f/MToPew8TqKu98EbmCkbm+SXjCeGAZOJHJe6FtxlrplXwwvPX77xUISO
0IejfaFSo3XEeXayUgWgZZKdST+7ggVw0U4Vo4slhdkP9KgkwuczlKHx3c00zDRYIm2O6mnUAAcG
hOXCIsYPZXFC0ftlpOU9vqivArBAfoRprAPzyDsCfMlFFC0jTNWt/8Ht9tMKwGqJ4uQL4tNizY9D
h6jUov13DVQQdOeI/mlojuGTlFjuZ5RNwtmNm4NaYbFQgQJgOv/EI5lTJE3ngGyrAudiiyK7SHnq
FMuI1THnPqJIRsSQH3+VdMD/6m5nAdzPlVeXauWlsue5K/5wrJklgehRYV/WDAwlnCYB3DuXwGci
gF3Ug5BVi/puLx//Eori7uSgwd7tP0nGBnFiHstjrwGBRnSEqK88ELf9RPf0kQWjIutD3QhSzDFI
9PuV1Xik+q1EebA8Y1MU3MBqxIoXPx1xP4mRHHvqt/335ooJPKPcoXEL7eDYwXHTpj7QdeHehZYu
Hksw2P7cmH3IlRvcQGYnTB8Q2fLsWeInuorqn5navSgqvXcy+ga+V1iSeK1VVZe2CkvZlRfReH8t
nx+YRSjTkB8U3QqzLe9xrS7tpMKXVgQdrTFn87WDveHLskcdr7L+A7zCqN57iA1SSuFUZPT0U9FH
EZvajRp7WbmzJQlWE4n69r48a1VT2zWwMlE4CzDthg5dfn9gsqV8OssM8eVFXMj+598dq48ZC6vI
aADCQm4m8xgKwo0FR6gGAecUltX+ICTxjpDCvALBuMEAATbji3dz8TRdW4MBu3nyEUjBXxq6rhml
7E1yOKBz3ArvGhEt1Uwge+EbvBbnNHSoB3pOxXavZtOegaBFeIE4cVO7/TWUADWgmaX6j8OcGw+u
c0iZQc1TQZQsP6ZtHt4SfrtRgH/JHQn63USj1ofIdjaY3jJB4W2OdY/xEQ0QNGvDeRimUi2YI7WF
sFmYKpgfsytwqwgtWDCsTjfKSuDMVn6unfZI88Dl37NQE8fpHTiLPSyktWXomOykCpCeyFY2kH/T
BZ/n//GcF5Ews/9MuXcqqy1e3fWM16x5Gnq2vaPeovKyikzjPTuN+MQ2EqdwFtnHOk8Zna1YdjL6
T7wDydDYarqz8IZ/S6uWW0QHTFuOn0wLyEo2TzpbbnCDxkxE7+xHWy/e7dEtc6x5ZjqpBO7XaDEJ
JRl3HJny5xCUveviFPjoStiUiLGYWVS9UOjOEV/7fQznpnfM6lUeJtFL49oK/DwJWlVnDjibhWw8
PGB3e2K1AsUg6RTpHa5wUUD1qLYHjO0+bsE/C+crcFulC4tTVxD8FTdUTexaNDQ8csfFQ95g2rmP
N0A06VCH91GJXqUHrMGcOA5eD4CKJeqV55xnXnJT0UvJJOsmv1j50YwRP5KN6xPIH+cU6gJENXY+
b6TkXfDsgYM9UbFHy/BG36T2o6Xbug4JB4WmgsnWmFeZp+V+tr9+xSMeG0BqKSq+1Xf08TN0c9Ri
nBl1td4EFR/5NvMOs8G823MEAajz/S3mEJh0WCLJZRH+zoRqC0e6FPdgS9JaFITM/TSCqM+jK7BX
tC43Szc4mxSPpB2ZvbKzrvZ9IToOTxsiHY5txq6XaoVAKdzstgefxJTZpCBe9gmCusj4/0EcpKHJ
iYGCphv8iXzcdcV5ZcddNq0QT7bL2erdzxrd+uhSS8SHsF4sCGt1Q9azTlx+PXp28xfHC9JoqwLE
ia83uM7VWLGPDlLNFXruHA2pefXoQYoljCwRkhZF74IIB7zM1VwgDVkIafkhr6LTyef9qw5OJuyj
QOyYu7SxSiyHMW/iaZg+B1JsTb0QAJoVgRd5g0x5ibiNYhQnyDdZpNBeSE2hzq6C7RbHoVEKL5m9
EkbytjcHzDG3jtB034SKLmWsoTvSEHoS2TdkGYJbZuRhcN2bPM4/njTEjh8orBRh8TxzbAcTBQqf
hvI37n6Tth8X8L/vUj6QLSwNuIdiciPR8wQCLpnCR2bFzI7YoovYKtu6SWSyMKPcLsVWwS3QbrIn
WPhTdkdzDixjOkv2qyOmJB8YEWN4lLJADbqpxUgrhtPn1c34YXsGPZiNUFbkG/kM24zP4UylZUV7
8SBsV9nL5SP013iv1Ov9sl9UVv36nZ8yGi1gZ4v2ITTsaGA7cDGg4sgyu0lMJYn1kyvfg/lFNG8r
I6YiGPaSMmAzz6pChdVFNTduO4LbFkadGmObmznEPohA0dv85ESJF5/ZcmsY2uIo1Bog97v2fVuN
2TckuVOg/RIqvedYpFP0QVqBCkXUKzJUFm2Z09uvVzn1oTCW1PeXoljE59xyWDkfn/5rkTludr2X
jDRsykTLpLKjNJDT0W2y7jKrA4g8i9TT5eYbGVF2bIaMIv985pRQzSOP9fFjKzGnnYICE2gLpla3
S+RSHwIkvvXx9kOocjLf1paTqTAJOcQKGSvcA+g9s93opGR/RRqZ8qpmXp1lHV0Mk+EjLVpNDk1m
pmaihwvB3DI5gG1vJYwlOdadeaZ1JJ9EvnMrf5NSwWKWnf2mRulWXDm72fMi1CeNY68ahhplCJGg
PTn8wvtwQNnz0+LXkCUQUpvCKYiz5YENuvoWFFbPU8DtCC0Mk7sstasbGnnz2NEyQ8lPUBu9HRDP
wQClK+yARLTWMdUcDkYCQpsFx1jVmqph+eKMkEbR2XY1yMqnj2ZSur1/zCPZfcgDulA4fbIAOaRO
czrTbDCVebrzOVCqfFLFjo8YdGP/iP04cff5pAO+JfQbQalk1kGzn425LRyeAEHWNTZ584iP7r2N
CzEsQsg9oJiiSP9e+XURTsqSFTCtVEWw79Qm7+uLmfKXwwJ2VUlmCLYz9T1DW17Tu53ZpPmA27xi
PNXvakQt3epBXOmO0LSvntLfL1dz5pQlgReBrBY0QRxD1AV/pEzAeb0veIMChrMZGr5LnFM9uZQb
QnREVEMtsUTMmqaFhDyWMXsAFeBg0mUQSBECs6rAeJD3NHmpOWPYcV66JQ9MlSTs0MzsP3CKyKcr
5WRheTJQy+1Usx9jXVZn4naN5wTeb5i36iEJ0ZPz1sgYsP9WojUVHqsQxgYFmgdAlbj6tDry0N3j
gm3zrysvEta5j71yNIhhAS1D4vX+vkDR5x//oSNMb4zAZuawQDchxAbtn5b4ffua4MjGf6DvfuW5
+Ji3/80Lbdf6dKII3RBTNawAN86xvHA0LV6qyLNLA1KR3uSyXh5LWoIWtwdTbVj9/XSQilnrIw6+
OaMHMz+o43oqdvFKQLriDEit+rSTNX1OVQzB4lNJwCeLzKmzM/wbu2AUYYHv+/+6AfLGZTg1yAV9
OI73+NXZ2UM1wkmKV1GJmZx9igNHnZf1E9MeGMa4kAiqhK4WPeYy2J2umhSpl8tkNcbAnV80fvd1
yslU90yacbWnw1CDlN9cJ49aVtnR+N7QUVpxf57lU6PA2scdQwnqnYF1bmOoeGHouBPgBJoMnyaz
twB4kjLKVs1ZjTgiOte4YA0y1WMY20rOjinIyMr6a4mFiz8FXo3BRjdWIrd+kWGX8UhdAI1x1Xy9
Sjwpm9DwSRTBTR4jiKEn5IL05Bee2d15V+LRl+102gT9AsKmB4VoPPxwWrsbgug9pI/20m02jKb2
mK1sQqYtDlw9sw6/MKqT/BKbN20ylEnyqObB4egS8BfgF93gKPta/kn01eTZvmAtpAJR4C8hF54p
GfYKegNntnmVCJgjNDndbZYvHQ2ad1jvSpm+pBXI2a322rIXqhM5nOv8fL5ogsDEk2Ki6XQhkKtR
NC1xDfVZmvGmZ0RqY/drQxim+fSzvv4KqBJx6vpnwotPqYvfHQmz0B0iJteBVFuSJDD2iuDVaZwl
cLH0bF6+vrJEAJGAepeP0wrZY6h4VXUGY4UvFOuCaoCU9wYbpYfPGNYUkm/PZ25X6cCcP0DPs+Oa
eZMjpeubWFz8pIXpSNkn96lOAdS5VcgwNo/UGP+KC776/kV7dR2tjvCGEuaoRW/yw10yIXZqbbR8
fhU3kCfkBeA5Bxb85/aPsaEmagmIVY4lUjSQZFnSzTcn/h0VhDW/bIaQ8cnP/2LKL0AAbNLNoEhj
UvL0U6X4J8RseyMglhcGmEHbcKmvsgWQLYHdiQZO6q8B1QLCSOIDxtydK5EceJcFXSGlxALBwiEw
Q6PwPc7jsrsVZnHWjhM+YQRrHWoYPTWRyNcdnJPBrBsFyDEvxJH5Vhroo/Y71AK2GvcmoZfAsjkn
PBUIawQGy5vKPFtFngnFG0zzrgn7s/iHP6VdKZ0r96RgUKnmp9EiPOgW6HAJ+iq2BCT1sWM7pIyz
1RX1j7OgsFriAMtKUhIStRcKtViYvJYaYoeFN9n7QnAk8DhuSdh90KNlLXIvrHcl0tCcw5glKw5n
Ok/7uPGBpo0pRympUMzyg57zkgIqhbXels5BOJVio9YMwScheaGD7PjigPvqYvfMPMFgwSHm2Hs+
y/0RfsNPYuGW5Qpz8fBkA88vJIcp6b5Dxns3MDSISRTpp22gbO7AfIlKwLp5z2//wr2N/y2+5sxv
5cU/igy1MRtBSzwk6pHV3QOg0j7c4P/wxPzLsBWjFZ8t6mA+wDtkP+9UHRhLwrwJplIqGHdrxlOQ
cCmctKGM+XFR6UmUaHjvG76cDDlPGGgX7wsKvC3w+rzooyYEydyUtEmlstSGps00n1efBONSh0C5
O8snSTVeQPltY7VQwgKyA85czzxIGQN3h55G5xFBhXmTEu48WtxugmBy27I/u1FSpNJy4az99tzd
Ych0PRPrSdK4hNDQaQKU8N5ZnYEJrKC056s5ruvPdecIms5BsagVUNSmCbHSkPvPcP5OpqTu0cGH
wHKegh6th34Iu6Q8q6ovrGOmhJJyihQxjGXsfF9PIaNLYw/fC3ZuuBBof99YrAuYe12JYpmI0rxX
9QMg4prlN6NQMtjaaBtbajWprez284YPWOlhE1/TGQZ/lAMgzQxyT3i4uFU7YJ88T7b7gmV4K4bO
RX5iUSICauTQ11L7LzFkmfheZhHKIQ5w5zum89+n+jSrtlAEGjGWmNHH956DjeLQGGg9FEZey/2d
4ctsMLr42NAdBddvClnGIu6HiZqpiUpxNsEgCEw6U6zIa/Wm1vDyRL419mFFuJwQajRHPe1QLIx4
6zImXh0x3/5gUj2o1ft8+EzSOLlvQ+ZdSi2Fc7kPlMT1JDGLPUmZHFTWXs8xocfJmUlOUoXwo/Ae
mYv2GsUepKQdv/e6Zsi/qExj9w/l1CZwJGm5Bo20mAR+HL4XqHdIeu2nf5es7p3nbaKmhtW+Twt1
UzkpiztNgo6cVask/KHgR9ugageKx/y2jZZ6WZ6MwSWqSARZIaGFQ7dOizV3R75+cGslfYndDJti
D3q8Htv/m8FHF11In5H0f0iGmXFxHmfpvdljJDh076x85YHfi88RWXDDB8u25VGnpt6prF6XGv4u
EfzojsQmlbMhM2UoIwgglK3lpmEBZLQ0sBUh+XOotrah/Fi8eMfXzV0MDM8MZUuzvRvqiqZB9XF1
K2lK+H+fu4PQ430u9DvRUm3oylt1o3VvlfmYx0gJoWdUcJVfXsnNML0G/hFku8PeShjhTU9flUNM
KPhtXotB4QeMpuXyDx/k3Hinh8v+FwbX3puIDEoqfOj3vuhwHf1lezRXCGRC2J319ufDOu3dl57L
C8mZgRU+Y3Hcq4Fvd5RRXR3HqXGCJTat9C3kIaEEWpMx1mNB0xnIx2+I2nM/YW3lneWT8dv47hki
CRbDtN1EJ09rOg4Imb4CfxJzwDmDFScllSATPLRQhQ7GamYZH+2+oVH8UV1I57t//eNethXXWzvJ
TFaIESUu8BCTsBe9TuqayOP5+6UKi3aYL6nsr0bJD+IXSq0WDxEgWaxW4KSgaG7tnttmQoRvkhT+
G8Px4VGxEoZSYFCgwh/cueaZud93KvIeMPV+7CMAqMtpwSnYlviZR9NCoVkelNNFBnJ/NsgnZaEI
P7Qr+VTeMcSyDT39PzcfLMWqlgB12FJg3dkaUIX75Z/DQxUaVZ+PYPRdpC6AStI9342h3knYGaLP
70O+WCoEZBAr0T3RL9X973fZfKtmE2qF5MwKWxrkeTORmE/3A8yzEhl/A27s9UHyZflUxsPVoBHc
tOmuhN6W2RnscaiuL3l8OPq0rdM25c2FCK8eF6args80DxdCpqygUw43TbliYqFvP9w//Cwc7nHN
LtyF9VrHroiqAiz77AaaH4hobRhiZMloGlxmrsYw5ArmlpEv2GLXnowwAexfWXWWH+AXtwrTrs0y
DVr+vjIEj1F1GOjRJaAq0C0sA5PJv4SpeSmuiEMqnBc3E6OROl0PJsUSAfRIk66/5GVrv9qYPQ61
K2AEsqm3oKScg1byB8LfBscnW8STatYIO8FkSuRka201HlXAWU2iY1VivMywyt4B01qNl0mLSATi
6IN+vp5/kRODj6noXBQQtJE8GQ9zRa6TVoMhMz2NUJpG513yHxpS7waov8RGQ2qMvftMeLn07ier
2fMilHE/y75+DXYr4POc3I+NciZh2alugJKLp+XbkgWgQUDJKX/KIp8o4twUWxmLFYtCxjHOiveE
L+KP7bzIQIR2L+b3cz/mKjMWEUSorCCnavS/1TOiISruQvy/Cubv8bMoHhGmmZQuBW7n4Z3PVWH9
VRmwsjD4h6CMR2VdlZ7Z0+pu6CH4d37l6pVLGSflsGcAqFreQdZ6yXP4uH+yBq/ovTWQcakpM2gm
f8iNiraGDbkjHuGDLHhh8KUnN/ZIWbhP/l1fs7pkUKnfpDbsWy7m0D192k8ZR+EAOJW53FU6dpzK
7zYRt/aKbJwH/RA9xDNSiKl0vdgLbHNvBNSvyvmwpTSsA24Pbv88nhflUh92dAY5HekmMD3Io6qn
u22qjQp67/BSUA5IQrZOVm1nmfXRcVpW0iFkLT6PB1x8U9OusaUx/WwRssnRRB5hQHXMjTaOzudK
FuRLc7y5wJsz3RDSEW7g4CKhAkJz4nbxQYHTqRuN56c0W+CTwllVVJ3C/UGa4ixDFR4rCIqN9NJv
gXSN9jwgdKz9yUk9KQx5wbEZKvTrCgVVyd3Gs1zho+FmTM6Fbnkib8FZZ4+hp+QAORGiKCfclp2U
PvyE2dui8HENm0kdY+LHa8B8JHEuJhLathEr+el50TVALigepUUtfLPws+zpds60843uau+8k1nW
ccaMNLuix3fHjv/m/ni7OSswJzwhzsOP9Vlcp9UgLfXRx4k5xJnrb+UX+XVEPdMcP+aQD+PUBPlT
oFjcGdMHezQqF9j5X67RGlzdttkCmXxIPO4n8PFFMl57DlrpXhn+eZRSZVsbHvGWJncQi05Df9xt
aFcUqgygN5YWTWrtCKL3DxgI3A3+n75DnATlwo/z551L9JgLYHG0Il29NLEfVAxFaglT2aQiK7A6
Sf7pEfbuvcpNqa42q1LWzi3Jl7r4mT0jbMT7oyuNKOpL77VpF2XyP5StJOLLT7Bc12ei+tAan9+L
Hi7p/vb9IPsLgF1BSNrgdx2t4XwGVJfFn83A2hHe/9eHIRpD9a2jMjCbGVFQftw3wO/0cBnffYJA
PuK53PmRrRYIe/GQ78tOvah3bHmSeoXpYo9VmCOWzTxlYKJVRKUc4pw4b+1s8GCmf4Ub+9USsnVe
FxixLmEzGtU8oX7P81uSGcUNXz6xVChCU/9J6ziHDk6BvGCk4y9evpcZmkzUTZsOtfL4COdK7DKF
HB7stRL3aHM0sojmQ6rBkLPHSvSzJ6/7h0xWxYYlOIDYgTOvrvmmHl5JOUR1nwEN5IqEwV9v4MpC
S+9c5yArufI0ls7vMotcsJ7Op2Z+2UkQJXOg/o7pM3opz/0afciamG8ywfySIMWdFcQSocjRrmSi
9Fo3ycpzFRpfxqhiBk0tAvfAB8MSWvkrNBPNEpzvsIQfPDSECkk36CYW4OUriAesWlPwoWpdLXhJ
LgKYBBuuForXm4+JQxeqAlU6vebHnSupAzA/Ln91n+cMNclcgDfX/9KyxBKLDoF1mBnhMZf0w27Y
dU3wIZv+64WepSwQiOuScH35wIk8WjVen/ZLkXMRzrp3/QDhPIdQvs3xGk32QNxguILoBllxNX0D
+Youx1gN8eOblOyvkf5VlwG8Zo9ZAeqaU48/J3iFzPlqwuSrcqNKEK3d/rUX4tJfVI4ROKgJUcO7
Vd4BD4kZcZNe88KcHOksDIWRQ+nr8yVKeai1PHbZPoUAeKoC/EFOdEJENKDbJFaNANGmYdVULsLb
/vdU3J6MB2+LnesSLumuZTg6Yy6l/24JOQWjNks+FYzJv/XXxUmXHvDka7xpUB+ghUG4/oUZAlNS
ZHUIXxP4or3QMbMmfS7kHvqQLTC1Z8dZLhjk5UDo+PrZVp6Zg8ZPt5sff/P72Hz6oSE84nXJxKjI
SIvwNtxuuR5ngJUzpkj4c/BLWxXIH4z/cHYch6BzcsaJ1lsJYmV8jaJ46yfjtzO/5fD3EuczhNq5
Ab0f7KyDrPYNPvSgaTgQ1VPQMj8p0EYwOSN/yVW1bi9uWxKQMkefGQYXd7xl9bkEdlanZSrBosJF
tnL4gyw+mUWXo6p6T4Z5U4jnbFasmwzR5KKGYeUd4x59kN6C0uFRT4RPlx/KDkr9NtVKnfdk8UCX
315/AjPG+LC47tXcwRLbU04wHEM/Y5bHBAKyaLuWESeQ1xwpl1bzcsWm+3GfHoLLlahuvC9R63Nh
ub8S7UZXnAaQfqrtbzWkRih1dBNRgT3j3mYjqsFD4VER5tgCvHgtB8+oX9KXYeD2OQa+NjBYJokF
8mZ+YJeozJG3IUguj74KsdJzAiHlhbbauV4UsM32PFLhvaoI8Q2XL8fuhsvyWg86XwFl7ew0Lo3Y
qq3yCLnlgL/FuphA38kyINFP2Kk9/Y3cvUHL7qXuXYECyEN8Yka/rr8qYyzbzvOWpCGcdNCYCg35
DsjZ7Q/CCjxT/1ea9vSXqDAdnLqunpCWIr6eIda/g78knkGZbzTxbaUGBnHGkg9slmOhDY+KZwBW
Z14BFnQjAqQnqRQ8Y0VsM7kqRbG2dKU50jQaKExucaWGd0Vw4D1dhKsce4mcIi5HYlqgzv+u2hC0
bWUzauNSd1M9STjOHWA4czZCvzA3ET3SLHqp08TMChLN8x0WdCuTrs4sz3hQTsyFhumijDVvgvwf
TgcRCt6rTIzrDeumFDC3TFn1jzBwdunpzGkkTtSneYLtK+9SDMeswfvWqzHkWiXJ+BWpb76j5zM8
DvxZSK8mmvqKa3fJXazGenP4U/BuquIYJLUVAmgxN1lgtgl6QnfVlI40VOnSRAdXKHsKBGQktfj1
pI05+yqS2LP97p7a6uJiBLhSWNWKT/kCV1eWICj2USldyZqKfHpve7T0gJlxlbEsdFejpobTknr1
qhOPWQxVP3os5B/4+8DVVuiTqGWGxwx/vo10bV0mWtpIiFjJQNjtiMMMrDI3ia7cn2zgSnAP5ion
cIoAnydQAo14CpYT0gua/bew9J3w1ku8zWhwbsPMyrQBTZnAVAILS/1POyvlx/Y1I9YSTweixAj2
K/I0symDFhD4K+tfa3zh7oq8s85A8w6fJnxt75Rs513R7xhscVdJDnc9lE/gQoR6136/ddS8ADoZ
z1heI38Mo0W1KoDcNs0HHwZ0jyiNIKiDVuDyHfNfaJogcxz9DCwQMo6AaLNC9gqCAWNNr7yjW6GK
g8eLXZMKLUIsBFTpMTlVeGdE1oHZRXBaQ3RUe8TVWLl7ntqRJ+HiKKQU5SEYfpXM7/FyCXEEM3Xg
raQzma6/QYCeybLpcyYxzMPXS6HZJvuYT9uP/KZvS8dRa0k/THdraQz2KWmmGW+3YWKaEh1HVF0M
p2Qqmd6Tr90ZgU62bXfkjwj1HjaGdLjtq8cOz0l7CVjsyhVAbJvtfqkiPg+/BdlLWZhGw4+69Wlz
dUEzpSYMZdCNW/FIIM0HjpQU3687eJ0IViN0dXHKR6Hb4Vd/AU808QT3XZ328pNZBMX7DgnETc+i
xC+Kiovyx95szAsxRAsjKYQ2lv9Pq8JCWqPUk0jLxbertDbPRwXsA4uPyoRCY54xbMItxRLfMTGW
ZeQI8X5dDFKLD19i/KmlDdr1mTvzpfSeHMjmLEtzWSO7guHBCMOgU6e5RMlQFYvcftzu3ADwH737
WoElUYfqvnHuYA/D/XbDTvViShTAaKApLTucrppzIdVanHVh+cvuU5nu6nmtbopaxYcfqj3j7LPO
bGzNioO+GlgiGwn91tVgrDcwrOv3UHfDpZ6ZXkjkGRj1jg+NDiOTSwF7lDlGM1AEWzotgiTr/6hr
ax0TVYKnXP7hZNe3Kv3TPqYIkBV2GBi0wlfoAK0r/BAoxd8yB0yuseqwVzENE/d6+rlwH96lLM2I
e/po5BEm8dUecPQ6sbYBFBd2nI+Cznab1IZP9X6kjiJRKs0a5IYi/obkuX0t8pT1CRhXe0hEx3nu
C3Ub0kx2uO8YFeQOMKg/TgWP5c+X53WmWPyQNAuV9F1IG/hQqjRozYerg8jhcpZR5aVTEqqLJhCg
DdTk677t9J7imV8BsoSjrRChUM4ZvMEEkpMkOmbMInnYOBjc4CPc2aGvHVDUC9WE+mXydA4LkSvt
3df7xeNR7zyIVRY8iEck4yMMiLIqxXMvEct95I58uCe5/r5jZWpibQAkxytwRLUIMXzLbLAlZPyp
+jmpRXP3Mwg0OqSdjYLxhlz/ATqNCU9U8gGTlsQ4/yGVW5IldFf9UE/Y65wxaLEq+IQh0UD+i64j
FCGrHhSunAQpjso9r8cH15K61PN3yMmztgPSPdzb1XB5QIqNQqJgNt84/U73o1BrUu77KMCu7eef
q4mOusTAydpHPiK7JJdQc2Nl2gppoDN4LIBV4JCmDd90xnkfbraKLRzTlZ6miznoFgR2d+LmOtIP
trgwIwQAYYhDt5alpuI90U6Io97OXtD7hJRqPHgc0KnZBA0Obvz1OIcCJNfCdVyc2c5Wk6v4t7qM
NM3mBQub/vE4XxFPQtVIRMkL5sbT2Y1gm9OrtrkHngALgJEmtunFKcO3d04h5D9wqVl7FoiaSH2p
y+EG5ays7tEnrmVUyXFWo/an5StV2PxjdtN2yXlluVImfHCAXIFVz7c0m/zvQnPlukZrBtFG465Y
mUZFbnwClzWUEhhxsmxT9Zj/V/Aseb8uY3eBn3tT4p1VtzKtR0twvCmfAzCW4m4WM2l2AR/prHow
5UZdlSPg6oCZt/HI+LtmTL2313FxwgTNfdlsnWGfCyrIsH+fo5gFY5YO4wp3kilTwo9BmeqTiaJ4
qXyQscGSKJeUrT++yGI4s2x3iL3tsaEVEeckiGd0kwMmbX0t06VUknwlCu1zgcsI8Nq67QHWQHc0
waWJ9Ef1ZocqUQdegMfpuFcS/hDEDcthrSLSndEDOxIgjiUpAiXlAGxNZHRHm1/YtAAyQ9GgseRC
K8kx0rlQR2v+Fu+o2WWIyIxUAXYbbm1RsOZQSolkzQ3VMtMzM+a7vc5swfkrCXUT3lgT5RV52mko
s6hpFcdVNTD/AkNYVwsMtUhv0K7GlI0aJ0JLdu6Gsu3AL5OMNp37FU3qy6N8MqsYhm/Nhz6QslJE
nMLOdEJp8FzrDLGwwynDUAhjL7NBormkTjxcD4jDp8XmSzDqkPi7LOaDTiz8r0ah7TrxpByn2MQT
RVgivUrPIgEIMSLXfyRo5/9jVunIyizt86fPTg6emLbora2z1ZIW267TXIp8uREX2htu+qq3Z6sa
jIs0ukCfFXQgomrQDAe6T1fenmRi9g/5kZOqmao0P3tJcU4C/C2BbQtwN8MKcOJkDtAa9dwX+OmK
SLAAqreMnRus0Vg0JciwS35zfTMn5FQRTSE4huIU701EM049+e8JFKRoRkHx+0KFA4QXEfMjerps
woFdZXcaAzzXFHEB2Y9BBgrpU+xropB7rp2FOtNYydhT0OmhnzQ61cE8sbr9IPbvHNuwdlBJkTqS
3eAjw+9aLSmAthTGiWkB93lQGtp03O8OuRSEToBu1pwnRZdaM3ovku14xFl4hrJcruK66JM09cZf
6s6WTb3iaqyZFP6uymAJ6rx4tNuF2yPLJ9OSMp63yKPi/b0t2HulonTrHV+nr0BleipoghzKYEUJ
OQhsWonk0fMmpgsJIQmiJT5lRmjeWjJGvPAN3HU/QEISNh1skL2GKzsa+2hSSvWEarLHFv3F3j/K
l903ArKB9wJn6XE5WsCGgt3SWY8rUkPqEjYxtY/NtIiDM2MFzwNag6XjkStdPemzgVXwLxbvPnN4
Oo3M82tCZoN9Gbm6xs+30aYjMWpUhlMXFkbal+43NASFPsEP9CblmmprOq0xFP736t4rThmT1O3/
i1XZIHtPvcfp9Gy7JQ22AywhiNevZTxoFOvBbrdmpyLEFP6NGWqNS5YuFLdxGsoGU8+TpeiEKZ/N
ZyWrkpb2yua71PUvYNSsGCnGoio6V5rgLkUPB77QsIsrWRjjuJq/nv9zuLZ6Lv8u7i+jIjnD/4kz
Q5A8AICvf6k9zsXrF5n/c2IWb78OwX4bk3Te1g2jjqcRk6AinpP2t2z2XC2tfZOrWXjav/K88FhA
RfPIQByt2N7yC+3sLNIX1uDjKFysXdUkBPheZ4HIm6jgtyJQEJWmLU1JeBcycPxWY129YKO0IZJx
7WVjcHq4uXhGTEaH1LUwBh7IZ/TYhoOZ9UaiIKavD7qnIMNIZGDcbuDPkYkyfvT1GngwWnhNSPyx
a2Fv6pGEp225on54pySh81fnTFGXqcW6FTmmDw/tWf3dYV4TVT1FbnCegb8AfKuxH1EGV7tmXclT
h1Qu334L/IgzS80VZjD9UIFLxt5L6SfQ8gTUvWy8voOfi6yaYh49Z5Eqy71Rv6fVbpOZyXzTQxRH
ZJG5b0R14kjDLC+ROf3lWqOMd+5fgGS4TLqtky2Bk9aYUtFNzvAPB6Q/xlPBi+B48e5x1mPXR3oR
ZO1XW9nZE0Uvijt8sdCPKzIaS0LkRMUMPn2VY0kbyFECdThv8dAjs8hMgJe79ON5DwCJgRaoKB0P
dNAqyP/n4eTDI1hsa/JYoiDJpTPH7CwRL8StTBBSGWzRKpc8CfsH/gvqWE0visSmYyQhXPXn6nJO
D3myws20JY8sUXiydWkp1kvITTR9OkNWRU0N8NP2DNeijZ7Z70fHAvLkMG8WKCNoVnDMQn5UBHDp
Qrz3hCOaPVXHoqK8yzORYCQvtNyzpYEl258C7vZc4WVhBegGkYhVd8a3gHvK63lXcNOe6IZ7KSQL
BfrA2NnH/7wbRDzCRdcLHLQKTK3AtHzBl/0f0e3fIv+3BP2Fea3E6C2AdpPMnoDO9fn3zQ44MW0I
9KgwF5oq7gJqnY3xkFssEucV+x5ZGGv2q3y7vi8GBeJAH8KwgudfOwy/GbJvIMYxlHMwLBBjUHR3
6ziKyJkuX42vnsfKZUbR+r/dbMqHToKYdvcZmBsDlSDEFZvKz54T9Sk+uk5RRJmPIEWLnh5rbO0C
9FZBxo5UnXVBOU9dbNEjAMhRNlQxH+n9LXn0m7f2HP0RXv/CXT62IkL7ia8SpuJLb60ZPZ3a2/Ad
wxRb1DdT8HuMTtyTSz/Srxf9ul3L8m1tHU+yWhM57Ea40CWmIpjTWYSIqOkiqkEIaApuB/IteyU0
2lFSXs+JOkqWmuKDrqL3K/sd1iddMRbYW+cvyrUXSZbggVBxEjOfshUJ8y2maaiFVCCS1KYV1zRw
q+O1CVGNm6dESdI42LDt9acfS/aI2Q6LTC/aMiw/7fSa8S3MvIXaVj/OnSC+z2jXdiBlXAhHzRtg
+BjsKvvOo5cFQ/Arwgu15I+7OziqySZx3sbNoWgrjRemM2G3FCvQvx2B++F3Iti8SK6uhwi4r9jm
NB4NU51HEcI6R8eL8POexwW4/XPOHBbD16uemW0xmpie3v3/B52YgCLf3GN/PE9yNoAQKGo2Dcj5
R2G4vm+WYI+bgSqOrHJPtV3KOiCKiYSxnMz1/jvbRc/2SCAZLm7D2NieMJY4eLbNIAUfXWLDpO3n
S1JNr1aKPggwIFqUtn8kYegUVe+bWlP2GKe1SQVNjwlvJNHG8VVl21spb7HIvPwUJRV1bcUYkESw
jBuKkyrHxmANiGsCTaFqkY7qfDhrg6QSXFgbN6QQZUk5PG7gDwIgeyyO7xoC6oeBkWqLhIayIXk4
aqLoPhNGHlIExF4LUIij2GP3u0Rc58xCTZ6tuqP0A3WOWlsleMG4zWbe/k2q0yoyckvQcVx6DOsQ
UErQ4Sz47oN8mqvkAcTx40l7ShSt2Ns3hJwfHHKC6O7ZxX/jpABhGuoTcb7i3Nxm2f5CSaXTCEtI
WWC4wDu8rnuDo/mc7rLcl+OK9QX5yVMPxLUf1XNKMzdrcZoCrJs2c9ofFhTSSsXbaxV0pDbBb3Hu
+1Ff54LEBQSGhuNtXj8MY6tw9tHz/kRmQTsrZQLe+cjeLdh8xi+Y9c/+/smi/UsfE5TdzYZm3umt
ftpgkn61UZ94FehkVPnDZJfHsdBxkh4BMiYuEDjIp1xuCF1WmjUkgDw7Do3ZdzI6qYRleHCGEjvl
RvOYyFjyWPRXMJ3WqLWztd08V3nLy48tpHxpJxu2FMC4krOsTJa6F79TfJudnZJ+6302IxtDhB0R
bh5mHZCRUB9D+Y3cfbgxouBQ+H4PLEnSmzLq+JZywgt1RlI1U+kgWqGR9ZkzEPhAZ2s34vMd9zOr
et68PqatOWOMUqnlRABaHIlIHM+pW9X/nHpNNtNHG0T/W8oil/+VuEfqGJFm9DA2GW8b/Fm5KEL1
roWyBlPFDPWXwl7JjhwYOf4r/Klb/t7DmplCBMZlq8M14bBuyLg6zKlH6uZ41iKmnp12Rh63eNPN
G9V+BG14BvYD8aN6M5rf2gvMmO5F/ClQIEeoNy5Ad8BRDXU0sphpALtiNr4Y1tvmRh0F/K1aE/9j
Sr8gfAhi8hTH1fSFWoPCFRFGtv5E5XOk00IlexO3myOris5L9jYF9CbYyKPIw1JqdW/uNpY0IubE
KsaE6w1pIhI/kr0IzZEu2lQQg1g04DdiS2BgiNxMoDd7+l2tc7LCLF9trXZ5D1Ntav1kbEkqIWOg
VrNPGbUeGwykfVSDFQX+V2pYvLNj2M9IAmqOdx20SkMmWSDik19bqQpqSDEFcDwKfei9kAlKBWJv
IQIS0v7pzA6zJYO6XQ+5mrbcCVKVwIzJhcOFOy1ET6ArumP6PK2HCMfo+y6j4CxEOBqT/jSO340s
y+GtZ1Mp4zj1fymnh6OL0OeQKBwqQXSyPK62ysi4t1kIwnn221ll5+w86wzi5EH+3VNHRVWwYl23
2o0WtDTKOcVMfgzga4gaX4IvJcvHqNd7fgHSbbtKYc5kiHYJs6e3fP376Hr6E73xbHHYMeCZmHSr
6I2qQsC+roxejSUn7bt+FxN8/uaJLkCguXy5GWTOie2llGhLL9UEzie+Zj+DSw9c0AXPv3JnG993
vaKUR5KOt9jNT0TizGPbqV382ukm71ZN8z97eao1iiUFnPOYguZQoU9CrU+1RnqxMwwV3h76mRm8
1QJ/W5NLeBxG7Z7LEdIWlwwhBelTXiC53/QtjH6tjGwLFtbZTW1XGaNae2F0O5j8/DON1W5ow+31
Clxf2ojonWrl21sTpFaOR8MxqdQDZfggustV3WYsxJzxrA+rTWK940cI6Jz9Z29FpbhnOiGndEd8
2x6jf9/7QoDbW3ZCXE2zokG6/HZCvPf/+SRX15R0TN4B6T7T/T8EL+LgnKT270jA5Fq0Lv7PlamB
yoc1lXllegWE69vzy/LVWbq/OV0jUcscq5Qp0VdABtedNWi0bML+T3mJUC03BnbkKOLs9YEsOj/t
4DxKPoMlfelQ68zeuE0clVl6a3KVgmibivB/21E1riMye6z6M7IAoKIjftOyz9ITuoiDqt3dr11t
dKAUR88VHpg0bluiUEeOxMnlrSZVnvQ+Lr5Yr64T6ezVHsyj5T5ru1IlE6glaT8CWzqLHXDZ8pwk
9ia+VoLT4bPgkkp8GghzIPIDrUkHbGbHR4sl0ccxpZm8iEcZUPCfE70dd/tenehcHL4fbywXP/xg
BGylIuLebZO9uf4MtQZiBcvPSDujW3phW2wslgSBPMZj/MEfSRpbyqBQyQoe5k9HWf3Br94nJK4u
iVbUcmFCju9PnDPwthf0wakqvWFfK+oNKAJAiZScfpdhcVHcGMaw3nouGz8gyi7CmGcEbaYUM5qa
dCtQu0LcsVXHaTcivW4I5tTm+/u9Gbri8mfeLIJFOgng1pEBoIzl/AdC1VkSppl3vlzFn9Mbp2yB
oMz1S4Ax49WLo2/IRuXsj0y0RsqIh/5kn1SdVwYZ7oPwcKHbzFupwunw9EhRURrJwmdvpD0mZBBA
VuvFuT4Va0R/SEvIu4cmabSWiIKXaa3Edq+qubD9fSysgRGo3qsi9uRo5gTjo68hsZxtijrAbKMn
vr/HJsTLpJxLnLBJUf++ba3XbGnFx4Emwl0393A7NKSCm2ayI/6a59GJ5RKE3Lst0TJsKxWEnR+o
+3det9xTaGUSzmdsoMH2ruOUo/6+fyJQcsmFlepsi6XSxeEnpF5qeUp768wk4rHwJ+1+pvbuNd5J
1cv9GuJOMPre3xLMMRJPbYknlakOGlGS7CjMuQrtdapUXfZQP5pjPb9Qd1Cxb6zEB/inE9aiw4Oi
Fvqcm2PENdJYvEs7i3mz0ycOaHM2WLn+XblUwhPXZRGwUIRLVna64K795xuQKCMz0R2c4NWvfZwh
cWuGHZMh5MV5sNU4TU+UVXcq/8r55FXSwMNpS/VIB1NkUDb7HyKTTo4j9A+sm2Dc9ltBF9HhmmtM
CVdiT8KwXWdwNuZU6Dzn3UtGt8GNjiiqpII9n2nP4kas63d37/CzFy8EnZ1Z45z9hWRc2Hvd/93l
LBCTTuEG/xcyLoDAnhhWZ20+5BoZbXZXASOxZfJthfZZq/zw212ZnmCjW682JGFGpHh1lW+H2WOH
70Q4f7hevEVFh16jpHh4NRdIN3HBWEse65shCWwkf1/HG2io44vjK9M7veTLgcX7YrQK8gOd/gJ2
BNfJVJQn/+Oodi7ri6v+HOk6LktDrzpb6dhX4BDGyemCOnVc+lWSwPbwIWYgPUuFFZIqEYnHifDv
PepHtDW1b7KQVb0IEiJhoN73E3EaiqJeVEiRn+CUIK9VZgsYHiH+SQ4qUT9BzZF0e4GvxTaHDPDw
ixfkZrEJ7UQvVYqvjV28pUtKEDtlH/S9423Xh8wxo0vhqbd67mPgP3tzqGzF64UID0h2WNJh3pBv
RhHmGcmCR2kdHS5aVRwJhmZIMSfNono3hT51HZ6x3lfnV/fO2Mfn43maSrjgtJGRPAbnPlBlkEl8
gVE2F4ImNKb5toCKYqWuk2pa/nOlm/AslPBN/MTSRucUVOaIkLpJ9DuRAJiFP0AfjhHbGkg29V9E
p+b/WF9Am+H7VX3BNFobgBPJ8/WCCnZ6V0Y6WNV2xxJtlBDSxUb6xmXYDP2swo+8beRp7ExVZHdT
4RUnYalKTIEGf8Lj6lZj1xO/1J13NuK4dSM2BHcByxF4TbtEoBE3la8Z7sfSxbg1FRYhpBPdcFRW
1e0e7dq+/4bcirbPBeLgiwELXOm4JllDMq1jusiy8RX4CmDhJ6/h8MjH9vQeh5qyw+s5Duf7RUyX
THXQKFUnWIn6udaqIQIbvjTMQQ7t492VkCoV9+KLay8/7lIO0rfjV9CkF2RYL73HW9cBNQlAvcxI
7nwGjSUDHM8rpVTHcSGY8ZxJgtb92JAAppwMHeiEXEaA9Hw4eGMNbiZLGHBITK4i51SuTYtshVKx
7Qxw1PiuqJlo4AsllEr7f2BrWBV2gjpt8JVdD6reavGITArhzlP25gkc5ENYXnebRAqFRI8TFshO
gzll55+6F1jSSY147uz5yHqQaij/nj0Qsq8BB/qnFBBCHg3NUj0ED8624kUkFqmKL1UA8aL3Ttp0
hEmPP+XtPdD5/2oBtHjoh11qotOZYcbm89k8F6q5hPt3Hv+0ByfxdMkSoGi8DP8o0isXThIRA5S9
Ae/xMszcOvJKxNuBhpK8spJXuqIyA9WZ+NaVmu23bSgsng51lttLAjwAfH+EOndu0Od8CnH86sNX
3Nmnw519xpKydRV1B2b9pWq/IxYoARJAgVAqrVrL9Q7RICycdhnmVIpuDF6dUnGSg5IvtqygBzqi
b/WO41xorGWucDZgWh9RKBcIwgW2lcbAo4vUsNm7Su80+IGK6mCN2BGjYMmVtyz85EAkioRa2asy
cg5pFLnWkbKS1B7YszSL2MRGhf3eLURhI1mS+8AiOhfR8Cw04TFhf1SGe3I3vex3sRVlXBGjbwDT
MlpN/Q3EQqnRkcQDE7vqpo8IJd489OAbreDeUDP+uwT3ZnBL20mkW0KjJbn1DUBrXA0ZSKsMODKO
EaehPkE/cIuOaRyhzBN5SSmIJU6u3B+/2NGRNPbB5/afoXA6UMV4KKp0WPVjJ8lmh2bg+8fxey9S
NdvJFwGrcZnegVgAVXiJd6+kwim5+JdtsLPQ5VxJuEK7N0fczearXNSXdMK6crxKkZM58ZViai9r
q7AMrOvSU1pxqftmal4a01cYLNjoraf07yWRxr1iW2Ij537OulBf+mE5kr0QOwmVPbO/6mzgcokv
ENgc/4fUHXNlZFctyPu8liHAzOs2xdmC7ccvS6wCtvrjPHRUznSQeZaHBsdWDTDS7eu8kJ4Lcmjw
UZeOgC69IsRVIK/4GVzw4q08/QvQlI7MqtFYFLHu0b0tLf0Hsc7i1Q6U7MOT9b273m0QmObSS+Y9
FdJiPWXiQwC24bMuW/GPDVlrze258kc7kwKZXBftzmyp8JQgeO6fVFfcDtgCPRW6FcF+q2T3xTxV
scc826oh2VweP2BNzopp/Hyf7CA90Ly0fuKm9+1M5eG6/YfzwGuTBOiPfl3JVd+QH5auP6/qAIJz
ifiVJNCg0trxsUkG5ij6wu0bXWDBEauV5wZKqLF48iS1osiPTbnTMRM4lvskCNY8vOxS+647Wo1p
gipCdjwzodQnd+NeaTwP5KXNT8e936drGQP3tHYlYzo3UBOppjyZGSAs4CsLVqe4i6o4iclCk/+Y
G1mGIkhorUrlAaDjXqZdhBzfe24R7jDWw//3aLFCwQMQ16ODsOuvO7e68qTVT4i7sKiq4eItvrAc
XKAoKugfZS7PKaofRUE9lq8vQsUusBWTdv6pd45MW579gYZqcqJW6zfHop1TZ40+RhKalwo9DI73
T9Tpxl91mcAaKXRlP6jIer8fGv12AR8Of48wbO2gLyuRlpkOnBLcpjP9GuPquBZqK93BU6d5eN7V
SyxTw9V7Uq9u0RQfclT96KrSgO6ASjXNyKPBL1klsGJ1qrvQZe2RpZDKpdArVINw4PpC/Fg/Wrfg
CIeOb/h2iHOWELaTw99k7lH3Noqc8rPJP4jtRIJGh94NwOewU7gmLHtcaQDvTo8GIxHtlGA7NC5g
BYRX12RkIZhIZcFnjtKinVlwmdLe9Hr+TgaLdkgFdBey8QLWxmiP1/NKfil2EcLgXpUYxSO3tylo
+OrWOupXexHj6Ct3O5fUF6txNcxf0ZmtEzAfY5Njq/Cfa38oMcmobhqOsAWgtAyH8JYlf2pbyOP2
fYfIeGiBWbXgjza1Bn05tKBTImTRzLmXfTFKiMUjUPdd/qksO5vymZ3zLHnfZN40BfBB1nahSQ20
d+Tn3OpHZA96G8egObirtX7LlL1vSWAo2sXOvu4/ALl2TuXqcQzuR6OTHw/ibtTCnEvPC18VB6Rc
0ZKZXhk+en2r2o+pC9tWvVLH+n7bylpwKZvHGbRTZbSSj/2E3TPkGPvGer9POrCJBq+1N2hUAQKQ
vwcXentC0IvBZ70rpQP9Sfpjj0T1t1bdt1yzN9+AUpfOE+BWTqmswyvQMi9+EHsSkMqnd/Acn1uN
wgSvdKowXRSZxxTg62/gd5pn+FSaYxQV8K3BE5jPYJgxREBoGlxtz/e9w6l8/rLrC6wJ+m5Qw5r/
kVmTGNMflbBMzzTpZHeiOwslvRhuMNbmgdJVAI1nFYpYpdgaR2T2+01UIw9+5JOaKFzJaJGhpbFz
ALKVfgTbZbtH5NouL8/QkU7NTNN08GM2LqXbyMkGePyn6E98tbKA32wgSYL/OFohKM7rdRkWHIQy
Z17F3GPvXXhDdJ5MUUxmGfSPGptdHowtmHz3ZTN8aDMYijQjdOkSsVluhfF3N7Fh8HCleF+11UEL
W9CYGmJyPBA/sFb4zINpr6hXo2oKUk2mpGLWtEooUqfV4BIiI44WDtYfv4vhF20WAZw/MES1u9uz
cMvCbovl+1xVIbKgcEwQsIZZ22OM8BfQTMXiK2FSUQFgCilnIHnAXsPXnuMmNsOC392QyA0eTTOn
ojH2kAwoTnTczvhajKhjdqQeswKXErOuf3TInE1wRnO0HbYhwqQPkOZP+lM2nDYFYN/gZO7DhxwH
obSREeVZn4pNzCnaylleFor5ZRf38lvCfjfip5NWwaj236gjH+9cn/SDiu6kBFGJM7w7nWggClZN
b0ZZBvPbPTCxjwIUUtBjv+Hw35aF/idEKKqBbTluGQArgZAtOJT8f32QVfxUN6Cyj4kLKQA+Cv/4
vAgah2lULjmfnATzn/tdSWFoe4PuzVPgps7B0YUPq1dH4VeX67SxeaPnaq6RXSpW1IoQ9gW41P/B
SgXBBWtBogL/rzEWU+mAcZ9YIvc08XYkBVpPqqFkCd83Vaf0jGctGiVI0zblVTBQqPTLyDpPX9oq
f0XEfbY5kAbl2xg4mQGBEWkKsiC+pF2AyaOFEOxcgGgw0bLkGrwVBPIh3HYoQfQiB5VUmOl7LyAv
AK9DWI6rYbM6k70HIVANyv/9PlV+bwe5raJ5P5j6mf+1zQ+LiGbKavSb2BNGgA9S9ewX9XStiJpm
gHRXofqIybV8fn2gYuCx3Oo00A7cJbu7oDgRBiuxPJlNjOJzq7RtaDT+Fe3qwRdOzAKMxGOUu+1/
tELz05dTnVFaCj5Ni2GrF4dCTMvcm3/SB2l4j+r0re42Th7UobS2vsY1BZQMh+hHyZsD3BOLxEwD
g6MHhyJd7V3mPjTyPrtLh8jXCE4aDjyBkR+5k1c3ltjH725wN+H+iTke9PHx2YE6QQESvPgv+6AS
81zNdFdo9KRiTBa3z6CRhXuXKKJWCO3I7uHCMI+Ysd+Y8NYkQv42AJVfqzi11JAkVqFtF05RzR57
sd5H3YfHrY/4q2TV3RV2Ql1NMSvzQafD54oku7jX4rpIGshpBHBaBtvQgTVQbl5bWW5PjA5FtSqU
3qjKjIu6EYVIwdYoihD30uuk3ETQi6y0xRoydLLI2ORVHuD3znf4cKGyOEdKSK1DCHav6v15ZoqX
2gI3DBgltO84xlGH7QIJSsL5yBeYDc8AbemJ5p5yPpf0ikc53Hde+Z8OKoeoieFo/njjRPWIG62L
GIv68Ks0wLucpnXxZdtHY7w49ObgoEhv6o1J2NRywTffemejoCWV1nNfZ13REDt0smL0IDKakDdb
ssOkQpNq+MPK7ix8np+4NwSuzqGG0UZGgGUzt4t6Rj4ZSZhwYk8zBr4lFKY3SuirQsQy7/F5MWRY
9fEGBZvM0ryfYVe5dzQYPl5O1zPUyKRC0/Xa/SxTvv7lZhi6ibJaFmgPBlIlnn7XOIZiOGBpj3ll
y80sU2a1CNHUCs+axY/cfg2B+UzQPQOGHvhPBmSGCDtjMTtSfrCLNBuqJmuFkbZzh1kDy4GINaBA
QG+k0ByKSSoTtliTGOL7Dwe666WbdwfLhXvoYVjDX7p+FwHYv/OyJ5eNPNN0aZsj9rV1KoKpyK5s
Q0lbY8h3TR9GvUN2ueG6tg+O4mBd452veXaA9Xo/saGnsyqmjq09ZJDcB95vlf+0rPM5SVtxgRJX
bkZ5AsVKilPF+zVzYHfUj/O25b7FQZPIaFxMnNYriZy/UJ2uStG+SpEN+wUFJKMQAOIJ2CgCxJpp
ZwoB+UrBJgzPzEjt6Z2y8YvPwG5IfcLiH2YXjdfWFiR0gOmJtYDern28S9T8C2NmfTZd+VTlx2XY
l2MTZk4rekI9ZvH6178hE52lPeJK9SM49+DFXazBKEiIIsOum76TWhbMGPOqEki3izZrLSjvD1ry
DE0xVa94QoqLtLXpaY3/CzJr3zTg+J5gNcsRDmTTeJxQ73lRJc8iGd+ejlNv4iZ+NKqerg73EKy3
zZqos/gaj921yChu8hDgq/FRqBaNuOamKQKPrKIoY4/o+40dE9RFcrktpTlU8t12RiC3p8fcGMUX
02ZK/mGpOhKF9jNQQ9CuSMzv+YW/gPvlznY/GOaEvty7/4Qj80muvku/PwNWOCgs0gprRfXFtyUF
HEaxEKSd6E0SohD94akHJKi7dUovCa5nwZAFTo0z2fSt9I5wHhfBiH7EQs3tZSu58c2LDSSlCXAW
3mhPDT5N2QBCSdFnvcC1w5T0PRXygGyNqPcTGSvO9OgusGQDjGmmK3CaEjofmkXkFIdnK4p7+Rl0
Z3xxyz+eL7BCE3qu5q3NFf8Lsq3+7c1qya9/iybfW8Zeyxb32R9M+Zt+Eoui+WwrHW210PUT5Wy6
0iTHWXmMaXCk8wDUGLw5QsX1L3KJfnBb7CPr1mB0x6XKAXHqAd0xCFhBAwxR56Bw0z4sOOWhSfUe
A49RKEdwf1JmPIPPyGfNw72YVPAN8cGbbXoGCnMTnCFy/B5mRpS5ts9blXB12nF+pSVbjmh1ysn8
FHoEbXvVYYYNl19btLV0i+XNwj8z6k3z2lUPT7zSoCfb7sgAcVfocr27Wmprk+itD7BqgbfUrdV4
nUsVclsV5tUMTW5MVFyBeHZG6TVDS9dFfecDGBTUaU93lkuD25aATEEccFPZgg719fojNah26wjn
93XVpRpo6hGHPtqwAIo78ZAfRQmY155viCO8vDM3YkkDzsmJeXHNqRjSGIoAmWbQ0pxKan+5ZpY5
1RMMWdbB+ynn7FoJ3J0WImfzi0BcU5/ph+WAF+W8Ei9k6bKJhnwqTebD9cxHbi0Zb1XMI3oZv9Ha
Epouwi/9ZTaja4QMQd3H9/bhDZpaBCd5HUZKBh46MReVudxbqSkvbxv3wJXFIfFTNrH78bQKvnjG
pQwXLo81L99U/yDlZKmWAJzUHY/atWYxcV3Hnbo/vGfKY0u0qicxZbz1gndWrTX0GCE5wKKuHIdZ
xZzGWeENiwHvQ1ZBIp+h9e2rkAEL5wJPnVh95jwiVk5STi1ltyCTwLh4jEnNeWzSI0iZY8VJHnMt
5vxVLh3z1ZZ8TtAB7pSHQQZ6PCFTh2JCJUdXyc3h/AkAPmvczyftVFM03VF8mn3XxsdIHpbqg2KR
PM3Dko9w4BtuvSpFCInh7djoJhcI7brDEo43M4RrkJNWbVGj9SPl49Tsx70uv4WfsBxSjLgebJZA
VTWoSbrjZA+yAvg63zpUjQysHxf7Ofqyva4eZFEX001U+U+svso3ghWogp/ewcdQaRYIGw3cbSQY
FOqXDkgdLa9vwBlifr1wG3hLfcL66FqjcRoQrp99G+CcSObKjN4hhTIMIkB2WyFo0slOAlu/2SVQ
lkotSJbsQaC9ZmN2/0Dm45nYHDKzdC/Bq4vT+3AkDpabVOCTaXjwINdO8dq6DZqlDJHU5/NeUa3T
+pUufnLcy7mw0G3W5nIyd9htxfj4czzgK2Rr1PS0kxb/Xyh9RkX04M6iQHtvwMGcEDOvzO4PKJd8
pIVT1Ff3rMBWA00ShAwxXh7BMA4VL0HmJ5nkVjcJRhKz+e0GFCxIwU/KlSo4bGS6tadh0ngEqocG
zNwRVTYn5QrUt46LL5O5hQIvq4QMWfN0l/Dfy2elhSXlQWEhYO1z/qYAsXH3k4stJnNqjL2SfLDE
VfJ3T8KwUSvEedwNWOKoWPORpPo0rJwhjj+Do1KSMBnP9kuZwTpS6i0aAnRCyZv3HV1oDRYH2JGW
15PAixHWjl2USd6i2On+4IVm/bTDgGse2KGzOXqQXAqHAgQB6Vrqae2pJmBrlyCUKWnEV5Mx7I6M
Q8Pk8pwgG3yZZ3uvHfMxrKdYZ6Dgpq+w6ej5Tx7jBVayhOZtGIfRY7Cq5c1hm/S+FnOagjlfhDy8
IbvuLrsckkgBjbWOSwOUfqskkMz19AodEHg+xxOngMXNZ4iwfGOPaPtP+0G6YjM3qmGG11LjINLG
FzU3qZ/VNIVX9UvpX/54m1Jan5oSlgCF3ZiAxA6e7gEfmw+Tn8ECkBJyHFRg7q8cAAuKhW1qDpGN
GEhxVDtikTIgaPy1hbwQG2SZigpXbvLsEqhFUlhqhs6XxqyJkLV4sVOemNDABDf6We5pPmVnUHrd
GgFKwkJtEazJFXVCCRzXIT2m99zBJfF+MJ7K1C7VZ5ybEtNMLP40YV2c5G1SQ4m3JMiTQflFCqO3
mxrsyAWgV7L6eK24YYr93enI2XS+CV6GCv3PQxlGfBAxxDKu4Wu1dsL7JAUfSH3Rocq1Fso52dwx
ZGz4Hv3kXn1Pwmw8ijneuDvHKTiTZetafRk8rhP2VGvcdQa51Vz8bPWqZvyFp8y2DWyh5gcoypyZ
pkeDjf1sW3Agq331rvpfrP+Xc1atoI7dc6ZydeywaPRFnAKScSFZXeDVp3W4p3NTYXoU8v098q3e
97wsgu2+xUL/ZGjbEFEN5xM0wkBlFKmAfBEN0dN2Ga2FV4Jhn7hUkMdEjsGR9IKIcYRBjOaYm2Y0
+8bygrky8wA0YXAmb/GKgpsceOi5PgiPuQQAkBsC2s5E1FeDXlcqQ9V32AGMBTWJyhXwnHvR3X9F
5xM/dYhMHnRvkP4VUNNv0KqmGl364zXdUXR8VhWGHHXUkzhpJp9ebeMgmKLS7eS0bxvU/swSZlVP
mSET0gZfagl7laRFJNGH8gmTf6J5uarq+AlXfviCZV1+j0uqCh9oFzMFK7OjtBrB07GuaYcvhjVe
NWlFd2m83t4SvHmWVDiHweKtHX+TrqCSgjn/3xQAau2LCrJtQ5+44wWnX9FMjlyh4UC72BJAYcdz
FEt+/94SjJEqL+rXspp+gjXrYz2McWseMYp9XTAHnkIg9/0IJR0cwj+xPZpe84geipYaifgxBukK
t2d1E6vlgZxGqQsDPaXTCmhNqj31MFGN8s8gRRh75/8nEoAZPAjy+2i/c849h0DdtR2MXhn0DMLr
GqZczXEF1pnK/sE7/8LfwJIrd/2V9q0H/3rYtctVZbPuaSXUHnZBhGl5BsBh0u+2I7VIihK+WWZR
trUEVaIJdzP3aKPanbW0xfvCxCbuOCp6TYcZhFnQZy/zjpQ4nRjUrtl3U4vEzRyf+wHb8ZKof9L/
QC4q8emIy/Qg70CTIxPGR3XxMo5YSdj6caU4xqZWwINp70kpb8C6kOlKw4fnoLbsX7c+zx+cTSD2
lLfPf+sfdLL0IfLEJIpCQFzxOVAfEamt9FCQZKAhmenrjnJjeGEaVgbTUJE3xkFcvNzyqDzu28f1
72fW7FDLpU+gs3Knc7G54m4Omj19tRk4jrU4TIxMWayQzBFvF701jOV9opVxjKwqOZErHqMFriQW
sw5Qa8H28+TkF9Pa6UzI78dl9u3grb4Ztxt769th08QLqKB+IL3CoCldpbPEl5K4fFnPocVnarRo
drSXwlDWgr2A02DYblaRBLyGDaaV3xcYfF5IEo3WkTD38bm6PfsYPpnPgyjYz0/pe6p6YrdBIpnC
+BfN1BlvbFCSzZ1l7HfqBNgAH9HQO3S7apdopNciDdkX02imCJ33upO2FyLoT16SvwDNhX3CUF7E
c4MmuMTSEOpK1wraLRkotQOAx0HxUAAfxS3oFp/5TJD8SgEtdusgpkvSEB5DSVTBGkOH+gsJWW3P
aYI1sHqXx9sL2hlaUqW3utQDApyxotdcAimcZQ+oaoNbwXpzdayT/LlNQwytjfrp64EWQJBvXPR8
wWLa50PjFQNyOLcXvL5P9Ov60S7gIvkHa0D1OTVYwNqIpITYDRSKzE9o+T9S780spr2L4lYiOJaa
ZfrcL26/5AOxYHDgYLu3Ri6KT6nnm1N1gANHvwgTVt/e7ZJf/RfVB1OvxxJg7O5R92oQvbllbW1u
VYYDi0531I/WUVqjIHGLlS7173YtAAK8br91SXW9rTVuqINsGhgPm/XqZxd3o69n7XXupqkMM7di
ch/mWRfAU0p3Zs/guong0y/EyUzi2ufEO0WzzgTqPzmR3so8H+dLgMYDlFbLfQwoVRZZWiWlIuWH
xPtLp8NAdl+1iAM0j129aTP4BxDb8qq5B+nL9yy6aAzHG49gvkZBRIVXl3hUVoSGyU5dxSVJ2Arx
Gvz/gw4Oe9cF2nwOmd9E3kPHeGFUWyp+uFQm1FlclG+aQPyjgRBW+4w5Fsw8frGJQ+6EjPdEq2Pq
lKMYAojvd95MSic9qk2ElTUdWQe/UBbR/827bzYu/Kv/6atiLMrVLYb2VKrTei60FxUJZl4hLk6+
ZpB+pDLZgZKT5fItmwVJXxeruCEL8gAfsxM/rDZZi0/ixeVCutdBekKXHRYYEzeF5YFPwcVRkvqW
vGqlYgpWcMuLq/wUM0n3Ol37DJDTKsVty4N1tXs0OnOhXckhakn+ZeCg4wRMUzGg/huAYU/aP2Xr
S4Dxm189ZG+lOMD+XX3AJdQTq9F1hWtrC1GgNmhmeRgCt7NuGx+i31JhtCe5wAGTjX4GyQZ3ig0N
csvF0N/b95vNuU30qRVYYpPLjzuXdFrQb205S0i+e8P3u71dMaMreyiDTOZ43hQzYsZ+8xMMgi6/
zN4B6NsEivIRHMtCn9rHk6WsQn6Mnekp0npkwwCJJQ1LMvn5FaR1YYxzVStATUX0MO0qJ3HEoDtS
I4AzlJNyZGcUWWlVrBe3t+Msg+TIb++zn4HJl6nP4tYe/tovG+GNvqA8k2KfGyv70ght0nIm4Dh7
dIFc+yq207ZbnjiiEUp+yY1S+X6D9RHOx6ZweDDUXT5WbNJMJapHlg78wJmRDGv6FAuO3G5aOhii
NrPSm0bnwXBOj15SfXqq2VmX4TZ50qfPsTSJL6d0Hdh3vEcGwV8HP16oB8zVmAzyk+L/of1hZ/OS
24VSZYSkmcgCNmwDA3vm1y2Qzpa4MfHbTaWYueRjNTLzD8DDEzphy8talhkw99vru7LqhlGI/e2U
syLUi442Qjq9phV0MExPbAW19mAplLD2aKzfy8DMQznBACjDa0Q343LYIFuOu9bMJYjS8oUQ0zTl
3cMSw8U9RsMRiFtkLxEVRy6jL7zy9Jc4Eh80Y1VNqyOVPv7eNj0Q3hmOSlhWNnRAJnL4EeXAaU0R
DK3BlmMIO4VEC6Ng69nuCeNnshYhUjXUZQrHfWruFTX1cloixNu0ZViomcAEl37iX6oihYQNzUv8
a6EYUsQ9ydD2q9EgXgCDa3C4ktE6Dy9TEiBgkETLkLNj4Z9SjmKqWiols7PsjFMZyV2+4hgyhT/z
Yv8QgNGyhv9yBwaO0FEv0y9blsMeR14Odp0d1OBIzRuPIkegXZ9dP92oo91xRUJpr8ZTPWU/9HJ4
+scSUlT46WctViJ1We3SxIvQYULyzpKvw+hWIJAv+QvFtIwMIhmVU8Cyf1l5qbRpLmBfZumd1pib
5vvjp9L/Ahse2iae1R/khnxN9iv5Y07MPYqd3PE6PtOAe/hKsvv/Tpo/vL5ION/UpwJT7dZCbYSU
MFttxysxwxZIAlZaYNiISdEQWTIdDlI41xI2sMuP/+BsORpStAE2pdUC32wssLskWO2Kux2lZLxc
vNn6HuTQPNqSE1uPf4vtk3YZfQ7f8Qz4ht8Y3uXxM7MS6aGdiDCsEMCfVMlOPvuuyzeTYII+giPg
VqScBPZpmI71ySmN0bUUgyMQ/9CZLukeIyP75UqZ09pcHAwMw/7/Tw+7ArC7sUMaRh8Bxb51loY6
HFN10l0rD0VmUXEU/a9C1j9YcAxsPjqRpm6G8etqTE8y3yObyxUAMFhhT/ZferlOEANc470eioGU
DZF8d0PdaTEpLjbG6hgxj40ZY47UW7swV3i8l1UmHqyaZFstDmePk/QrLE6IVEp2EM0TGeEboQ+A
wU1832ReYbXC1TEC7WQi3ArX/Uan+t7mXzYw4tsA4kB36QnhrOi/gNCBoKdiVBzeXKGaXEdSJJn+
PMGfandLYTlXOMRp4RePirfLDvJeejSmintls4hhw+/OSBuyPhpQd5eth41klYYJi5xMWWWQlaPM
avnZmXp02AdPYGZav3O1DlwZe5jTyqInDk5kHW0xrufW2IW0xK+A6jCuSV9pnLB4q+H+/+aK1Ouc
cXyl32UyklwEui6runIZPQLtzxvwT6v4JezBSLulroGzkb7K23hT9bBmXgUtY6McSzTokMXoZiCU
URvYSVujEh5SI/ZWMzLuUrQgiZEI8FIISXiEOD4iNmgDgazOO9UXCD+Ml/uVWvUOswWW8BCtfSL8
cYwjxTG1qR7Fy1wx2U3x4XM1T16+0x56FLDzfF4wOVc4sGkXZt9yYjO+Sal/F3nxSLdF5sfJ6q/V
ZX3R4JBIMlB/QrHJTvMnYHY2W+pl4jij+UNZAI86agRkc/WadfM1tgrr/8se7bl+KUJvc4S3nlDt
inDwcIHMLGw1lBGomR3BqYxNRiTWQkxggkPFqqSA4RQrWBwB6DghTbkzVXMiSnCNTQlDtTDCZhD0
7NpqAYFeU3WADHGnDQfvPSNi96RKseRs4cSqsVj4E0b+A3TdUh2eVkrG1Kvt9B/xbhlja5k+YJ7D
R062qWT/P9jOd+2Qgz93D6trUrfgd4tCywDJ3fL/DN1/rZFlVI7mCDWlm6qW42zpSM22EBf9ooko
WoBEVYG9SDeJ0WHcxY6xBUN03O78QDaEFIwTPPv2Hsj/tX4tOkHhE2Is9pOPdKNRrATc2ymrHxtf
2D/qjUq3ctztcXDGqXMz1TjTu60RMYERv9xL74S57GYjRWrEf+xmZ75iJjzIgMlIZxs9oZOo2F2d
ETKyUnNK1y63/ibuuYDITR0zv+9LFm8JC2v7WkTtIMAKMkOc8TDtJp56+DRZiulDS4Y2omcefjJd
9Y9E4z7ZMp2geLZZ+pv+RSYyhBcQxxRqUnwvie7m+Ipg21kOEIFwFOa9Ls8zP7MNYfuI9b7hha/U
0PjbDK3v1li7WAYNOYwSZd7i/rzqeHPo25uK5uf4QbEauBOvEN8XLtr+XOvPdVLRbgs7Okj3i45D
hjuVd2gvy+IZcrITwZqNh59ZM48b+Mx56YyH9jJxdpNPYDcuOpnwDVz+S58V0SAO92Wdvfe3e3j/
dueOaPyrp9iDqq3X3N3GvCwmvS8TR2XTS6dTCQygW97wjyp2UamPzbYFXP3SjXni2Ui5sI0ly9DY
BVCVFC6HdyN6NV6oVLxpQ8SmonfT5ZV24a4/t4VEXks/LUVMiS7RzTeCqgUofT/bgrU+wt2UUCE+
VPpjSdd0bXp33aC26si2SaFdrlUqLTIXAJUymUHC1yJ7Abn5/CdfpqFXj4wdi4q43EVXw7ZgcqEY
wIWEE6myrR3SkXZA6c5M16Jy0Fdk4fSE5KPB2Di/AYm6dTjkxQ4wDZUmQL/u8TPRPr0x1vtChJab
Yb7sZy6HUC0KRayNeXLJAM4NABvW6E2UXWdZq4bqQa0elgCkII80YpAC9rZvH2oPMH9u8HdPyt/M
NSr4+E7WqEDwxyEA0MqBtbvcLAGEJYz1U3/PziyvlfbXWAOye3lo2AZ/x6tJcHI2kgbyhgebeLAF
+qv//2fFtlTh9pC9JttYv84qY9Wpy/TzTeKGDXFqHj5Wxd/uYLtpo4xSIrWMBDufKPTeFUlkw/H9
ryLJHqapesx2wyjd6hNxc7iAnir2XaNwI1HiR9uKQExmb4pY/2wnYE4dcew4OWwTKyLHoR4a+4UQ
f8vYtr3FJgfaaxPBgq02Uo7t05eHo+44oIWFxloBooAizaryfF+1m1iK1QYp+Rwg1aC6nT/A41uD
Js3Rh5WtqPva3GgVUbsYK9H+C807T/xlsrFnlbpwgyDg0fVURvwI4YMvpE7U3MZjAFFOzY/aSib/
qbLRpr/sSyn7yLk+ZA4Y3k7IaIyrlkvd5xNoRzudBoRLlmnB0kLrqRf1uf/I9QsleCbO4t/0wMSV
zCffmB1OwXZ5/bJBYdrJqXxCLVXNHgfC+IoSzN/kTRhmUMwG5wUvyHyvRjOos6PGQeNq4mTJeozN
IZnZUJ0wv+xHJQ3FDctS3J+Z+eQzfw83CMTGZQcIHS+YbgTluwG3YPUtAo4R/zKKbWICeQcn3vMv
sNW7F7hBPdBO1/EZocKsPDH8KiLzZf82qXYc3YPDs7mFJPpLhwhVHYdYI2Ax/Apj5CfKpkeU0sh5
7o23A5P9NvPO/2h4AlFQPBPnTrUfIZ15RjmCTRzf0hGcug3YI4x1eMJOgTN+ihueLRPMre5aFih2
9wBddZZvJg67iCDvAKQ+fMm6JPm5C/ziDQsK7UcKhJ/g+JmfugCM9BpJXHP5LiNGxaKWN5xaL3pl
E68/JtyPBFh/TaVR4cH30fa5/59Z7jbOoDN4PDetgYDh+fdJ4SFf0gsY1IiMCYYNA8SRn0JdSdK7
fxIGRWUYkZvbTLPhhgZX9XhsHNkU0nVwtjUX9DrC1y3YAHY6RI+A99QODJbpHVACs4dg2JtcZVsD
c+7a/m49NLNbqmedQ2erUbW+CjqJ5w5w11T0Cw7GLw6AlsWgetchjJKafSLhbxC1cA8Dn4Fs8NQU
CKQzjmhEn4GcsJMzE2aMuQumVzOe0WERqYpme1fqh3bkP+IY0FL8nwCFd4af+r/E6t9ffxiZ9StK
SuWAwZuFzxvtYMmcBly8fa0YYiQDyd1gBD97rFx0s/In3xByWgf0ImfUHKXAmG7fb64xL9FHLHyV
e2ITPoKQXjZrIcJWmjabw7wLVg3I2y43Rq+4FRTInMirUE5IosdjHvskyBW+TEgF/FoJcHhD/VDr
vSr53r/zbPI4lEyoumwfnXbWh1OGVjnT/WGcX6tZypdtVpWOWdeOtiV6jHl05fQMqwladQAcqc5X
PLlyQ4t6VuFZ76+70TrN8x+zE3LioXyyq/2YY7TdIQP3CeR669i7KRFfqVl6/Q8Fi02LztMTIAMS
Tc9b7qxcTaNhzEBeYPKyUQpesEsrzFNy2fWP7/uctogngxckZO8piYFRsZT3gR3w1ChE/0BdPCRJ
7NDxs5D+9522jCdRY4mV800qaWrOwRoWdeew0fh6WmKNuTiQLgD8/nBfvyV+D24CFsoobhXgtGjf
UZh4nRQCuZfcjNjWPxBpHT3oNLSaCHE3QgWUVm0cBwigk9P4/E8g1ckLTjeHE8/CFfLgJG8LpjQl
aP6CFEFGVuvfeXuZvzqfyn946vFilRsj2UaHOrHQMnw75KAQi9eCuPDoUUxvV5vNcy9H85Ci4CcB
/W1jCaUoMM96HWj9a9pCo9P2riJcLWImhtiBM7LZ7VdmMxmsllN9v4Z1LHKAV4ouEvdCclEgF5E5
nimSvAysZDbysBOSxhxrJ4KAKwSHBhyrEwAqj8UbXRneqq0Jzrv2VdCv30NabLcVO7z9y6QtwcKX
6QXTgpX5K8Wn/+7alGKh9k069O3mPs3c9IVTzd19GpZ8iGcpvQeP8OrFDE6ndmp/51PteUyRahDc
HaZmIdvSokwahfgPclP4Mu7VjtnSJUZB+Av6VKCtLOOWx9p7rAa6ClNrjbVov+NTmIZuxdTeefnO
Xk7/hUnzwGjTW8DwwhrfVtJiFHmQzlQU/ZB3Ewn3vZ+3PpLbKrBzlorzVyVpx2oqK7WGBMk6G1W2
q1zCb1Tpydp2LelestY5dwuYoZsQPf3kJruqBEohVXmI/+jY4ffpnsUzbWTDpM4IuQMQ1lbJhPw1
hNNO74BgydHkqGD7SELo4kQUG+XtbRZrTg9LA+LSlQH8Pq8Te+giQLcLqFAEVnBSc8aA0MCQ+9XL
vhW04c5tBmW7yuoDFf4WVf9ll1rvVvL6qqf4DTIX/Yc0lXvexsU/tjPeEywm5nOuH2NVvnVVXDWO
cDy6uQSiyDbegOsgDRXY6rZyDIhwsbLJdzhdiG3YUd97ZyD188rXRDchlLXPs9xguOUS7Odx+dKq
26dAtWE5pNqekel3994ymbg57JOexyk1ntuk9aubJTWji/M9TFhKujv+eJrM7Sar6RU3ScnA1413
YC1fgNjqJ7OJlud8/gWbPoEH5D9OvJO8TTLnL62My75XlbQF3fp873jHMYDT+rdWL4BHQaUOSjiO
seFCxdpO8aevOsRQPESLy6ZHbVUB+HEDua5VkSlH5k+ZaK+9L/p0m+rZKMeymWGAu3nFjLJa9GBT
6BFzzhIxBVySdfA2cqMNX0yF8y0B3ZGJRIiMEhpwBnCH8gs76j5ipYcIHtBgYF5Ff9oJMMoHYeAm
1o0RfWIzUY6gbEc+OlOcnZZsWHFOpmoAKE1zdnBUxY8w75A0gFrbLbD/Nzjxhog+CLNGCi652+CR
k//7h8N5Pv0tLdXP0c7P7qnnAHKmBOXFYvLY1sxTI/WSZgfXlc86zwTvpDBnW/M9Di4G4TPTHKZ7
4dwJ7tChd+XifSGv+2di+tug0kCLrTB16MqAbTgomOPuQlvZiiJ+ie+wWjiMI0PidcLrVvaKHU0U
iZJ47msjh+7UrqjOD9Jf60T8+tgec+OleYMduSyoZzOxbvqwSNUBYMqHXV93oRl1zZ8ZCFEI92i6
aH3/V6mboMDzSHK17QTUTkFg1Q4eD55I6/LED8dWzCkMDmZPkSwLUP/wJchmYjzk/Pb76V3K65mK
sn2n2zvM9uTithjrJKj2Ym62Na2JglKvHy7B/MVYjQIcnZRgguNbN/TWX4iVYxmhYOna9oj8ja1p
PhRb6Bb1ax49tQmgDyxPCduNNBCwyKbEM4RHixnUyWNCnhJxztVSOK1wUnOv8DiiE00e52JLHBDL
TrPdxTskydYIvBrmGEQ77EFdTCQQuVGK6lH5BluE1cr91Vg6Aazf9GNc+q2rHB+hiUnp63AJS7zK
nl+yXOxX08EKFiv/Vef4jGV6DmSsDq6iHi0efWk5tEFB2njZgUQ+9OyS+AEEPw31OARLjyi7gqet
qQFii/QrmVIrNm8vZ7dKGoDssmrRuBPeYcxzFrAg6igkbdhbHTXg154EH+YkMfUVB06X9Zb3dVW0
UMdZcJ2Eu5np1aAD2Bd9h87m5FyQLe9NfRRayvk9TWlgqPeHLKYy2zZ5AJtAoSGX8IVNFyPl+SIt
xZNYHQkLN8+9rL3Qio0aZWa/zhgnvZxkDzRb/d04Tdt7G6WDZroZ0wdhBi3JmdPqP5vaSC5m0NZI
mmavN8u88urWACFjjQ26jKzN/5PjLuZSY3C7aoMFA6avTVB5YxMpppty1WZmND+6gDNQvoBOuuhT
i95wIsR2/YGKx5Lc3rmPP9W4oDllHA+NkBCG5W3DYbHcu1RVB5TzGOQGJeqw8mRvEtQSti8VN2Y5
UI0rim+vhE2KdgTlRXp3UMNfWvYsGl7/42Cm0eGCtzqTnEPPSo5PxgCQ8l9E84IYkUFZJC5wGRYl
VIsSrUAsv9U+8g2bdqlmzeRboHM1EwVCsDLq5uSqB3pBJRF/mNFFJ/8e49s03CVMRLWZ06l7bwCO
5X5Z7ePTqGj/MOIYpT6byxIAarELrRJ9ULm/9vejWs3xQk+nMXs6Cu3fYX3ubbVTRAIEiPZG2cbo
w+Z77R3hRzXtq8sVVVpeKXai3LWnfk4xnTIsxkzkhACLaJds+Tc4HZvGhANixLR6mKdmmZHhJiJa
EOwE415REA1eZ5qKOHXvndDmoN4J+diR3BM7h9vPJrSIfdm9ZDzOMvO9Ifx3V33BTC+/JY1ZGiv5
xv8odKoHi+n45CjIKa1/Yw1rKR3IwD+BrOuTCDlL6kdmahm3hQoKG40Ot8xfXTvEQpLqsSOKOFLL
GFaAC+LM/7tUaEFSQDDyvuTxBy+7NpY2hGPqIrbmEKk52Wc+cRr/Mb7ya0z9q3mkyXZDZZDEPGm4
ZLuzCNur0kOoBBUErOUrMgMnsFQ208AX2gpGFxYDFI+xAaOflUINvNPyxS8bJqDMge/tyijUDaj6
zGgmt7l0TlFwKFj3uE8tuzSw23X0HihAJcVWeTNfLxC7Pzr1158k+Zvp5gAPsvaZ6Nh8Q6RRJ7xH
DLf8LzRBtnbFZOUXe9/r1KHkOQH2KBRxb+FFAny8qjH5mTcMFDBJB8IUKSCiZerZgibU9jwDEMLm
ydP/94bPHsdwo7GoLD7auTdISSPY5BRBsdwm+2tsCoJ7eiCl8nP8ijZurRfz/bB2N6xBWW9tgyJH
XFwmxCVUfX/PDHfIq3/5DtdMLTeEUGGxEAu+zMl+QjpeY26tC4WLhyToX3dfWm2IgZdUP8Z9uCDb
zx5Z/eKnN/mRu1m2O36pTxnDnfFoWo1keASApr5koEzQfqqI7xtxlaVnnXbYfF2K8EWgAbHPZ1EP
fzupsOL8cWMae02q32uqGOd3K9ZoR/KAst5AbOIMSbuYOImkfjup12AvBucST8EO63gaIdoJKOK8
7tGK4llvz5hgljnrLXfCeF//kOc9BFjSRAsoRVkYamZo0A4Y18piemVfcC5wL/G/wWENAVUNJ2un
tSsaDURix+fbUYjAnc+pugLtp+fuPKus/aVqUyfR14wxzmCSAyod3MgZF3Ls55SjJPWneP+0ej3i
svLYgSkovgto3gtsjYqIiOSo1dkiU1xT6fxGQHP6pL4/+BqjuMecc2vRItZO9F3lVNCeZZyjbL9U
4e8Ctlu+qiOUdKqIxJnplUz2DWJHCY4HRTOA9sE7XgbwlvxRKuLaw0HfZfxO/dMvAa4yHLka+WRm
On59W903XSY6NtIYeRzGOXgXwUFJgkTLf8g5rEjGXwPVQBr+57oZZzAT4B7K1DYBtDLSMdMz5nkU
dZLwn+UKvol3dpUIxHEK9VTK0WU7xapdAPgGppOt2SHagu278jkHWD98OAga7LgEi+vsH2adjbVY
brYtxbfIHjO0/eur1a0F7xwHsovk1PI0x5k0KK4lfTX0rqcfREtcdeCdtu9xm6/UDFiJx6Insa7p
FNqdA9t5aHgyltunU9St9MvquQhE65I2HiRJyECIRGidM4Wk7GBVnUd4MN/1dricA6sgkk+RoWfO
lW+oltH0njgrT1SFim4UqDWn6kjaxvGdqNgqRXxvBQjrJMN06CS4ZAaqUBjd4uY8g/O1TQsI8H9e
20fQ7a2IP/4r6oZ4E+Y6QB2Cy5Z4u3Qa6tg4dzDazlcLxqMCAi0UjgOT0oS24/ATpe2K578MFQa4
+w1aK4OlnDZBoi4+GamxW1z0dm8ZQe0hM7pX49BghCnKqyPvG7f3izxT/pGBSwtfb913pp5LXPxd
CWAewt84c8u7z83GnO3tcovhSIiEg/UqQT5psRAu+Mc68znoTVN4A2sFHkF3YDZQMPHHHIwKqH2C
fFgndwl6isjKkqwelebSA7pTAkIj9tJo5r3Nsbf8VClw8dTGiKIzejclH2nOOVBnBXYBzo2MMk/d
kJp1tZFfR1zO5pX/adPV4GWkgVOg3H9lv2rL+pirMisw3kdR2OXDdX/5RfV7YrefCa4C9BaMJHJU
iWxZDq5GyX4zawvZLhrrYMR1AzSTX1OhahKDtjHh5EIRRdRX0jSigsqn76KEWvP97Po7mqLzUsD7
jp7o/cgicz725ew7mBYJvxDF3PjtiwkPrOwqEjVRItoJrrhCizCr3hqSv9gezGnKeeLNZifhWO35
kMjjDesU9e7Mn/rfqqPUbQyy1Wb4Xhqek2UNjVGt+rjuyPej4cIwGKTauGZmUScVzo2jFIApYhUR
kVdYaIiv0+7BFQL9xjJ8B+1Iqdi1itignn/xU/iLQ+Huttp1mCGYDBO77m/qC/AtspwnW+W0rIEc
Hu13WaXQGd87TD0ArIxxZaSNMurCf3qHs7n+eLXA4rMJZk6N5XGfG5ZnyXf9vYrEJtBmURcVX8Bv
pfBkt7MiPk0oJmluNIHiTveooLJtQF0gJS02l7fiTj2Jcvus+I4UpN133jhEl5N9JQrNn/OEqPXf
CdE7NrD2VT+xmAU1qHcIhnW5sDrJS12DzWdRySik+y3sqSLCpnjysWEG6Irck8e7qzaIZpikPRi4
xmOygALiazdFeBcHvNttRvb5SAFy8N+dTGFJzcYZhpj3XMpFgbdiDC0l+gerHHwVWbUQQoCOrGmv
C4hKkCtQJ7KW721eenirjYS0IGKU2pH2qZoXBesTJIPpr6JZ7hvv5IgP3DKf65XZCpKdlZB+Kuw4
QmwYGc7o4aYneKmMAzfLJHBL+FqieuKz7A2V0l1SY9JMqmcXEAkCHxLUdveUNvzyXHMtrqilaFRe
qi+A1BA5Dr08AwSRkxCvbVxygpJPWw+LbCOmdSxuYcbHOqN/tR4V3DLlZrNNSy5zbFgIKGCFkoQ5
gDyK4l6GJEszuAuf7T0vBnfADtIgBv4U5A3ckZ9Dcft1uT4G0i8KfIlGLA3+h78ddDG7NJ9crj7h
42/bxZqztAa20Du4BkgQWiOMm9Z4ypcCy8mUv8y3eW43w5XjM66a6nT7k03fHepRkiUAT2qcqBNC
ijb85AnApWNttNsX0HOBlTe7toYrf+4dfxjJe5S5lrtTh8+RgVpWVhs9FO23B+LPaYMAKBpTows4
K3IYi7/G2QbMl5/wMMzH09yNrdJ9ZzeSGEjNT+fGF8XaYmkMtqQfFHKegnJcbVFD6tHVRPXkXP0V
63FBGZRHrzxa59sKGHhiO+kpf2VXTlD3KAQRhej9UN5rFMpf0h9ERyhInng6S/+aOKOejlt+xnF+
20ofYQFCJ7lrcoZ/5jjFUsxMNeEL+AkfmuO+2apC5IoRiNbgNE/+YuIMYJcCTCRGdgzaEObb6J1u
Sgi2Sz4I2W4rQA/VSERDmZK92A1N4EybYncSg5LXVNhUUhoJlII0haHJfkBHkLK06BHJIgw9lNgm
jiWKwQ32bfkDjw7gT5oGKdNTGuqIdFf+hRsSf4hJsej52KQpVhvAielWySFxvC7OG7D8Lku0koIy
9g7WSCJSLtDKR06oyTDVRlBb0N6YJcmFhclW2ixmAQLUujcsj5bXGFQrqxK6w8Zlnz/og4GHwzvT
tVo+i1Osv0HKXGRGPHkCfU4gb4xOUl5DnXoEP2EgN6tbfbTa3JkbFpZROXumaaTAu6sxSuZUq+fC
N805FC9Lzzu80WwePO4lHRezIOSFyFBRfgLH+TDZtqG5DQmL4USWFDFKj2Bk4d3jlsG8Q49SogWx
YPGf8Jl1lAZBkDFa3q9ItZj5t/eXJiAeOrbG3hhZJolYFmLInxBbE+3P5N87ylbgdx6gNIzZUotd
zlm6AnkSnclmGxE9xr+JLNoNKUhkp3CgmKVTfkwDYUqhz6g6krQNVFt6A3TY4oMsR/V3biz4ZFTL
HPp++A8jMIxi95shOJ66jWAHVQdCTRjwc2JRPZ3kZZ+78G/7e2kJrp0qIcwwdYxpUT+PI31y3Pye
6hCylzVf/RtH+JynBN22+Gs5XxfV0pnOht1uBDpgRVkaerKfnEh3mfbWCcXAc1PMyU28rh8rgMQv
PFoYEJRYTZH6NAhufOuOUorJMywwlxBJb/GEPZiCuE38oDwx9yF8tkdG1XV2Td7excDxkFwR7u4R
4Y0XT8bNGu5blDqqjsHreYlji2APRf1SBrbGmrVhGvR3Oy2ggaLJbwPdDFnK+8sEhv5+WKb5B+GU
wbPtnC0sGUmrlJ6zOcS1inW8+Gv9tTQlOzh5fuc0ybfqzCb6lDljlPMKkSWM9I9lEUXUphaLzOqi
ujMivFjDkb0vSvq3SbNqFKjDjFxHvNQrXy4LgVIMziArvgJdBjric9dhZ/LXH5KMI8u+toFUAOjP
K3h1ne9fpmczr548opGP4zJmmj7G3sIGbKaxvTVYd1WGI4D6BTckeouHwpTtsvfuhQVMXyaB55Q9
FM8F0xU1IEP2inUhjSILF+8SJlVSdxMKbmn7HldcblYjv6rakJduDD3ALaA3Z1w23aAdBqlIAYZS
SvX481WtIsk2ExVFel3IAK+VO8IerW4cwWO++6559QmGmp6wpWfLkVOchZWukglx081mZw8l4IpC
YOmaUCO1I5Ml4fo1gvFQ9TVdso7N8GR97K8M1ZLvHwQkRMyyFyWKOF21g/oA2yxJ1gEFLp9rS+vf
Gh8FCfJQ3luA08FAp9KQ7wYkjBPpD9VqTIwuywNdzdQ+MUAemtxDmxrwMoSr5UJI7xKxr6WmE4Yz
YEWyaLZP5sG0DcnmtceQUDSz/dVStxUQY52Tfh0XpE6xOLe/QNt5BJ0P2X4eG6F+46An1aHHdC7Z
JFM9lx5AmFj94/sR3+xwzSIMlckcXm2izyf1PWjirAuOmhIbkGM9evYw40YeDSKR1bDcYXYUYDBR
nbZ4K7058lRrqXXsbV4xdZxWZJBVjdbIeR0fzs/4hNA6d8LwYIzui1pKw7yfn1YZIRRU96kyvlSM
qpkUY7fE+H9GYeIBhaPrT2dR1jfblF4lz1nfqC3yJI88zh2CeOFF8qVAoTeT+rriXAQPrJ/NIY6w
JqCpN/jBeNyiaofKnjmD06xwVvlr6rV+FXGt1pgOZ3bliKjUSVPj1iQ9OBllnqkuLP7CWs4YGqqK
UCLnMApa3O6jvSfvj63HwVw9ZMTC/e7RWjDE84Da3WXjO7T8TQj056PJnSBEON6GRKJ66Gyim7BD
zmarvhV3LwOl+kDJ4TgWZpFMI4SnBiLlrRUcOhKy13Z5HdbI9wbcyS9/rAx1IX21P37vgi2rqCNw
VSZYq4ulCh8q7nDXfwt2U8PYdZhsFUApPkEVH4XNZsF6biAcVeJMEwiLqOY+UeElvXJIXQfVL7MG
+5hqzN36G99CG4YJxuDDtnpQyGvE76/U/IFKy0TWi9h0EgaTPRyau9ZqPwKNVkd5CSMH2KQy4EE1
xs97IiY/y5Uq5AFj1kwrWyp0/jGP001GX6cwg4b9chsFHBRS5vvnhq/+vbfMtFEEiJsoORtH9k+7
Rp32YOIXGKoMWj3cntkVaDC+0sb6ISzbjLoAeSOXdLPFT6ABrWZCngAtU3TbmUSiAiKwqZCggya5
MaSMUNdReGhgQaUKKsuRaTb1yjwoB4IDak/AyDAzpTZcfOPZ2k1jlUCG8ApfYd7Gq8W2vVaOYrHG
CV39/ENZTvSGjIEuBDmbYBIs6OadPHFBWKOMKS1KX/mc3jiE8nocyTdA+a6L9G3E94kqmnpIw5v9
jg7VeVFVtrh6RAMh1xACZW0dvOByk9Yde7hYA53SckjOaOUYyT26RgIRT2ToZt8yG9Xku2VRdPKp
ly2qARZm5rr3/TQnUWrGGPjYKBRvblP78xBF/tSsAKb0wGbJReVT0aTL+WFOS31d/QIGCpOGxZmX
i6zui3/wlEExjRaqSHSNLckKjiq5+Erdhx84kPT/8tIXlvqr2RW+7BS/7F5w9Vn5on8sKR94DmGW
GURFAxNcF3pJ7f0Bd8k1vhr0VNg4c6sFo+Gk9v7QSctf9rEkFF/lsxWBPn2RLxhX7M9GW7oeiGL3
nv6zKRlfMNM+3iAh5byhm0gOYdY17tmTGb1CVBXomFmNcH9avM3yWAtGw/0bmAjp1trSlZ6IW7f+
xSQZ8pVH/ee6BznPYx1fqjEC7GIw+JzQxctAt1BVedgqiBS8Hm+78+xpC7FNUVo3iSybuxu3S3cF
XD0cEeo/HHSJVdVdzfXTJJNo34KTwBAwcoLcbUysmnDk5640owrMxyi1oM4W4NnBhp4VmhIAdyI2
Pak0UxL0g+XieUtboIgQ1Vs2GF1al/6HsH7h270HE2ZHJaa9ZXC8CFoNROw3dlrnmcKK2/OIEKCU
cttZP7Hrmfd3qqeLKhtnrOvfJ4olXwND1fWWZxUuUyfvsJAGKvgAlDuh+kDoo5QCCYuxOHd4TEgL
4N2U2JtTJWIWm/w07QEbIsdtQ8ygc20IQs6HB9Qe/my/af5FGw0+uKFMT2E6zkWB0OL/Q37axTx1
vYe7EBMhZiQtjBfVMYxDQ7koSy36RIjEMBQRWoqhMF1MHH8BdlZ507F0+E9KxYkSD8asr5hjsaze
TJv6eOhPuCuiAhsDfYX1xAxjUGK92KO+2qmogAoHBGyuFibQpX6kLKaoECSQNYtPHhprstLdTXWg
A9LU2LzElhsCPuMKjPyw41mxOPySzMM7R+M3bOVVLkL73hyVvgv9vLh9FjfOvoUYJyoQTY+cSkMf
eHOGXAe53RWbn1YMf52mIg7DcydS7ey+jfrHISnhkgPSMB3Iru//nI5NCPD+E3jvrCpRj3Do3tMP
yXNmB0EQLVtP++vR4+qN+JlSGoICthUQBoPmOKSASHtjK3G5dpuzRb8B+h/AZhPcDT+gCSE8AlVP
6Qu0oN1AGHXboFgfzLR1GkE/sSBDa9xLBS7pBDtocvxJixCpxa50dSntKPLD05JPi1ArRB9Oe8xD
j2AR+UhVzlhtqzeo1WYCHedO9/sIMIH9PVQWOXA/wdFUw4hS5/gsC0TGGw7dFRI+dY6pbEaTqx9V
zbwQ8uFBuRywIw7CvQ53R1iugWzsyhBnoLoIWHGOaxqyw5NciebnsOqZMZva3/XKHF2ir5kdFD64
WfLjybUeZ9XdH6+D4Fl/lITDT4wnYNEMQRLdFWSDxmH3qA/oDxW8HV2hN0BibQRf/OeCS2xER02W
JtyAmzqgSJXVLEXlnui0wW59jr6m8sQkYdVPPETaPtB3Qat5cwJKjlUdFlMGBxNo+UBYU536cFET
x9MUW95DaGBYvufKsBYB6iCwaG4ijVx0ulcfbgLLM0IuaZrUKF63a2VuNpcoCqEflGHveyrOHcYl
sRd3nFh0GiWKsCqV3Zd7dI6caIGqWOrIl8OVde37NtL07nurg3UW0ZXMoRFNqTTAijfau4zdwax7
p/9M/qkI8pGFnonqXr2B1VbbBjzXgCSCYk8frpQjPAqqLSCtJ6qgdYFu/8PyLM6Diig7cyiKl2PI
uop0yVY5ET8Bv5wffdyJs8S4CMkoX9d7a3v5BVF8rTd/LAgzZENse5CmX2Xy67+kh1vAwvfilFu+
2H4jMI+D12Cpm8O8ueHyi/mwRjmXIzTalq+j+wxmhPA7xctr2BZdme8bwbG3tkM1jEtOOCf+Yr8Q
G6j1Qnc0rZc7JnnJq+b/7sKOjj4BEDIEchw7nmPFTeP8ZxdOVBLu0yAyWq077jUAx7ElkbxWheP7
tYAZacZP1sPgCO3DioMfwczvx0IstHCgBZeWpUAz1P10vPh0ynSRC6iZDme/BKtEe4Vh35mRE4uo
5F/yeQia55MRF9/56tkYi5ILK+d3YcmM6oUW5jK5FIy3hAKbcrnoe/mbxpQucWsTj4wQcEzZuZUb
Xh2Rjuhv2vQqGE6OzNS92DzcIiETHXMVWULGnYaHleRABdqNVI3Vfl5zXQkbC0iPhNHX6kLEvl/L
wN0MLkGTqlstu6aIf7sHosHhRRhwebWHdWDu7UeaUIVah7VerAq3elxRQa9WfBcq2Tm1/CCpNZWL
t0TM43vDFkpVk/+5FB5J82VFA2Kkr8WawkQ8Bfc9vehEhuntS74GdDNSvI2H4AHah0jp1UFlB1S1
hamvHHA7fKd4fF3c7iLtQIkAr3+i3Ao6AbkZI/xC4btZDVaXYinLC+GsSgbwXdJ7uMLY7lF4KR3w
7e9B/1J1Tgd068u2AbQQAxoazFifl6YdZwf2d3jUq/F56rRZjjPLyQn4tUqHwYFIFoSw/6/H2XC3
J8OSZ7jazHlWxXG+k3OsU0TMktVSrN0+CQvGUI9MW/I4Qm37SwPwNJFUL1s15s+wCNFh0OwNzYNL
SozNSipGFeVPPUBE1dJ01IRHneUU7jk0FYMsShcEIdfiXcCpRn5e10uZ330hT+2ZbEQq+k7za3vy
BNv4dyLfNhwJlgPSCOXYKNgI9QCYasrUcXsS7RW9rHLqMN6cqzkC2a/bVJsLyH7l9f0zd5T3dHHP
TUjlS5Jv0/7SLExRJDhkqP8Wq7TZUdcpqPFXD+YQSv3JrqPm3VlE+w3lXyDs0r9bMJgH6KLzDByx
6cU6zcvp6GvcvLalWgSH4ptvc4e7OkG+a0iuDYblG4cTlIXK6rUgCL+sgTnaKnC2ANBWSYIQ7pTM
SnfrJNs2odYyLc56ZKrOCeUgfR2nYR6aaKdcRKlKL2ZflPmAiFtiFepWBNsaCNJ5Y9kqZMPz0wG3
9igNSTbJu0x1lF4e5EjAYsgdBO0yDnjluuJJJN6oW5A5gWcYeMEWqjsPyfKWiCD1+SSnEZC4g1hr
JFK1EtaumQy2q3Sy/DdckZsVWaC7GYTLLATz7VrOZ7HxYsyC9pvkE9pk9XGdFnN2S8PlhZCe/BCb
xbKmoL939zc5p+muwRkNaNNKqS0vYnBMB5WeogsBiUqSvp9DWexKWQo/GBiuXF7Pd5xsFDazpOlp
uz2yTf2Qstg0RDgme/Y0IlQXe1YIGeo5UzLHCIRk+xiTiqwEb+DIJn+IFC7y+4bgnk2DE9deJUc4
eds2rarFQK/lppitGX9b/AhEoZVa7Hp5kstvtzFUdjdVuRyhG/AUnort3PiEchfInNZ+pN/L3fB7
tpZdZfUcMhwR1VGRgXCRHNj7Pc9Mb1WjJ3tdw37LOMjKUjdYvotrmedesFZaiW4YKr9s9dtjuXej
Gq/xpTbSeQ5snKtsqbn62jQDUis16a12wf9M3Y9L+6GvtjVdTfIy/1rab8S0Cnd1mXSXZNiQjBGy
e+4YeRPSfn4CD2gpODMB8jf2Jsk7g/OA16lR73jqmEBXLIbBpodO9Ut+QR12MXEFucsCfxAzUlF2
c5VuHOfbkgXz55BtIWKEEhPYd6qWE1SIbHszyPPh/EBVO/0V8ovo1UxkwCxWvdD/r0m/vhjpb8/7
/OMqkrfOsIsCfGoThmo+hPeM4KLXLUGs9PVDUFl+3ENm+CZTgnLLArJxiAtL03Mx8OIan40b/IiJ
sfnj2Xzn+fJ4DTiCADTxGUilGRrKYwUV7CrEn30OOr2oEVtpPScerM7NgoNINkWbBgLciD/QyxlO
R/yyar3oPXoZuPXSzKmh4iKE0tdgsoyT99uBiVio1DP2FHj3kUxw0V+DsC5hA1TLvClUjuHfRMCr
9xn9UbsFebFa2IxlerW/kKQ1EE+sWg2l3udxsbcyC5mCJhosaUktVE9tsbXeogGkXuXdFoaR4b4O
IvvdRHrjeGzgNP1mUsY57PDW+RFdff+FZtfKvuxbaHdnTJvizCXGf8BvqYPqq6/qsS4Uu54vzAiV
4toMHMTolazDVM392JRZq1hRrv/866kO1Bcf4nUg2mJ+vikZI+F2Oe+DzWiRtlel/+fX8W9qsPA3
/npiqakKX6c1uvF6pSQvKC7I44fcv/09Hw1xTNVfmXnvusva8ieh99SXVLzUZx+S/M/LPu15VEkN
0KBcFOwFHyx497F9pHUEcICex9HIeFAaKE9y4zShTydLWX43R7BXhWT6AdCvrPWstrkqA7q1r9iS
K3tB7svuo/vukwwydE0RGB/4z+fg1lrG3ksQGZsJUt4gG+XiRfZPlbWhSLwx86PV8o7SXHhK3p3k
3POe5/A+bFHP+tG9Rb0uElagooUO59/YURusZehBBAryDDSZQE5iqD1PJNvkzquz6ftUFMZwx5Cf
Us1x1tpptSezmp4dlqlNtW420MJpB9BezAstWtApXfb6NUx9Sbc3+a/oQu/uCor/eIwTDuixYaUW
IRpcKZPbJrh3ZGXoKKv73uivX0H7p+umCXUmTr3dgoNdR9PdPXHs2S5CO9JHSAB0jr845ZwEDlC8
2zFDk9lNtg3uFsU3cRQxu1qmXR28CuzT9wbng6raeFuBIWtQnaGKXwsduYxN3oGjz80D5GrflhvT
bKq3GidMQ7xzzFzPipYPzYB8Mcx5qHuqUtfl2lsCbS8LX+tztIP8mr8Uw1IE23Drf5GkF6G4MRRM
pGj1G+aEgRX2dtvW7m4lsuBfweBS9TBvgOj5cobwX7wvxV9q2Bxm+w1TOJwuk1D+jNzvzP1MFpsG
V2bqboa33eH1WiA4T3bQfowOAdZK0vHe6E3Qs4jH6IAojPAH9V5zfUtKzv8FmLNkqGUQQZp8LDSU
suKkkNBnqdYhTD5b9Q3AWJLqIiJWjLIX+6Jwg2G3ApI54omeY2TYE+qkGl26/TWqNy+lnjEZ39Aq
J2ZRXWKaEP2SUSSRd91ExmAxrfU9zkusZS8+kQuMrTQdMjycLCXS6VAwGIP7e4N/LDUNf8gTNtzn
3SbrLVN88REQUybpzp+DOSkV1SmpX/OS5btvLTlOi/UzWYUC3GkSidRAVbesks0I6of5gkNFySod
tc6fIxXD25kyQ9n0EzewQr7iWCnWlbiqbH3wM/wJo/aQJfKo16nwdyl3tzh5t9K6yFPv1KeVKVvj
/N+T+rifVoeaMfT18BmMsk8PRNy/XAOX785IdOFwcgFmutFrV2LSeSI3RR3Zci0c0RauXtRIcyKL
cIH9ohbjfslJiqQC1mdBz1g/Zl5JI+LQGo5nPjuJnsQQZjA1+BR/jsFzzyDwXPa4PftmR+rXBphL
WKIs+xt12zE2j8P4o8F4vqNleojcxrQSdQQEizmcM3kuO1/WnevpEeXHR4SmFpDyhhhVkeblrNV4
Am7Jpc1yaOnMwZKjLYaEnkadk6MZzRwNC+vLmGtVUXBdgBXjaeKmXZYh/ONVMmDVxsbWgsjysWtb
a2t/G3YHEWc3Qh6jebgrmUbiG/XJkJG2tnPjgJkF5DXOiuMhOeUcTQVgyqxEHRLkjT9tDsAidPUr
FqD2iWsphQA01AcUsDxQ/flUiQNYFaq3kjLgQwKymWxOmB10hQsWpn+QkFDKYWadFgI7vCR8Lh3K
n4NejpY8CZwXuegHSVMYjdkQ9NohJU5m8Evdzm/PpekQhigau9b75JmR/NuStCN2Kw9mvfQh5phK
+vsuRrNssX1U4EgUUfgZYyQrwNRsoUb5T+MQe7vqmzjHcwj7vhG1nPZmhgmb0d1X0jibzmsHFaLv
rlTgu+6quIO5bbGX0eRp6RRf8IITrWQbG3mPELK6Mqge0Q2GOHwe8wvDlWmloQy1AN0Y6e5iL16o
dRdooyhLMR4Age0SyZEWnj92yQgmi/5rtQFcOGe9TMOx1KCKNnyvcbR7qIX9X3+cDpiEJP62A340
k3l3F8q839jETxFTuCuYLVdOAEGege6Za2xkyFK0sE25McTBAEGuBEsdLh+du8SYWNDFx/cTKI3b
Xj81OWxWKKZldBd/uirKSjWZTdPlBmGFT91RB6eK9zMaU3gTMKolUuLN4bRm/coOeW00wX7bgugB
tm3Wp1lhjZOGkWsHRCZzEI523QZTmxVLwYGPK7TsUCxH3+2s/t97eXfuldnaSXktU7t3JQSgF/ki
2EcOa9wqepmkPYjNm1qy7qvUiYcOuLDrsgQoQyzsRXpYp95Napt1+lLwNlpW0Nk2DHFS4Xg6u51i
1A8KgWbC3K22931G0on2GeeutILApoCDGa2Xaz+/ZhPlUVSCEQyOj3dnllr8YpxNb0J0RuC7Z/uz
QOhQajaS+/XVOu39d/GNZ6G+mmFaIX6aMPw7ftimu2YXKVZTL4kOSIZXondOByR/L7eUbLyzhvFV
vRiyt0Xx8KLHQCxq4PDg+tR5kB+a9DiI2I13xNYZDZkotsm3cnYR8ZrDpU3uTTHIByajRcIIiyWc
yM49fLlrys6K5pR3GrmeA6pWsAI08HR+LoGsfYt+hcatl1OanJs1+lUxKu/v25EYRytd3bptVxKH
1EWLcsn1hgBnyC7gG88svJWJ/hdQjuYPI33hYbul77VpVwwHeKGzoXlFzigSkjfFuNQBxSLezIxR
YTeMs8JhSqhazqxIyAIGMeVTH81DUqs0F11HyUPL7lK0LbwYwuEJe3AVyTYEI9wmWNbL7ugNTJoX
VQR1qSs7WzBBAQrzww7EQTEq5TkhP4lFSJT2utwHz+OzMU23HDng8GSPPc1GNRPmzF14gIztmvoF
/pxwCPfZps2rzGd3IwmbSZcPR/qjUsPrBWoMavNJqGDXQjIad0q35y4/G77ET9cMtJ/4NEPXmHYE
pJ+cDgKV3B3tLIvXryMLRl2+ZhJK/ak1FH46/9KlmUOvM70LS0DMJzbwlm0UEUJBQzWn1aMVC98W
ysvPYbAfN4/7KO6U+Fgqlb9beVRDm3b5c9DkMh9yzKCZvtYwo4ao06mL4y6Sk/mDfebCckkqgJD5
v32YLivaj3OyHX/kpM2FZUI/Y9Ii7L5HpwyUoeAH5Dslzj97r0s+dRS53UN9TclH1CX8G9HnvHmN
E0ZVV8qIIacYIX3JNzDPwgwTbXQn6ej6/AHAgwuJavsDTGrsdmMozzDDE6B9mf3DOtOgZegk2Bwf
JFv/2iLCO1K9fblWMB4ChSgNl4wFdmr7sOIZ6SQNPeMv4nsy+BIFh/yck2V9TVWTv7HVPpaMYbJR
8bL0n0sJalHfklrQacjUrC2dcmXIc6Yx1X0oQK3Ug2oIBCJDWjm5SgpX/CM3ACWdZ3LvGsxXZbq4
F7ayLoNQgY7r2SAqRYBWtoOeDdll9ToScrNj3OvvBXGbxXBrlAFapkvL7EdxeyKkGG09H/GAtDc/
A6/GRFXTjFrXTon7gx90D/iaIyhmAqt0hP8TE2Vu2oxQ9jAlYk/NN4dNt8LdQWnDVW7pdX6H/czA
cbFEEi8uCJht2z8T0NivFD1aTCSApgtC4my4IhXQG47sgMdGUpiGp2dNBe5Eo1CeSVWQLDIWcOiE
o1n8r9PwooDs817XcXNv1sG1StD/ZV3m91YRLa69uYBL31G4opUzS6iUFB7Sb90mDy8lBndEzVa+
CD4R7z1NiOT1oD6bL2ObuxZz6RcWftWfQgux2ie+/MgWfoSmSRmk1VtNYeDoPojJreh+CJBPtZuk
6T/OobhlmN8Z0xHTdVZ4iD6879Imsfmpx1WJuvjHw2VfEEcQf3EBZNGEmdql0StzH4oIw+Zmvfwv
i17H+kwbBw91rhYkK1D80ywMAmXZFUudeCC5PB8AwUa/AuFjCcVW9dZlD1X3xXA4B/vw0p6VklA5
sr8/DhOJxklTmiE93LoAbgaJ0Txlg1ub5nIC8CIbH2y3m1u4pBXuersw75plb255Gb8ZW0C152m4
CfD0Fdbw4E49YU9sUst2zjQ+GwvAavWezDlNlvpjH3X68qlPrB8kob/qX5/GJV01Tzye1ahmTiv0
VeFEbeP9+NJwwZKnCDqWBHdNHPMVe7WKFQjEY5JJ4K3Vx5oQ10+n/MevzUZLflx5xojq7PVmq2Rb
hhwIxCGIjHZIlxsn93tQHyk9NVaXIrKOwKGzAKySzxE0HFtRYRpJ0GvfMOTjuspe0oDjkaEUKsC7
ViFbDf1Q62DhxSXmm2mM0hraS2HtX9cNETQQ3ndY/EUCasqbwoVGESLREze4TCfIz1pnN7tTMblI
1QbeMup7n3qfo+Ngc2VqH7IYYx/t/OLT3zbE+HGF3uoLsfwMX9VNTT1aN3VaeWxLw/EdGkZt1UHL
m15ZaZ9rStBZkH/7yCJkac+oKhmTHmSXPfleVeMaK0qzUqaYC4sc6QFgJWSfVixA08V7nYCoDXjx
Vx8h+okNBharzesNORRhk+9IUO26eVS5TNYEPK1DSD47CBGtUsULJXUIU4eqzvwtfyI9G1L14HHP
jB6lyOJOiuZRuo1uIPfnp1N7AItIvR0bKpW0USJWNsz54811JV6/T4hiKQczWJK7XFW4VE/Vnh8Q
/dK3JUp3EM02L5BMCp1BCQ0gdF+xCOQ8yMMKR8EKmDFSWzKOqz+UP26dsaR1jPT0E+KRbtpYmW42
H9VfY2UHdlAUReaODjfr/rBR61LC1zn/UlEyRb65g6LBgdUfRxi2x877SVjyzaba49PjgDSxrKDf
w7KhmBEyQKbIQ5byP7osvywEJvpuK4J5F3yImpyqOPufyzYgfvlkpORtjJaQAjfVFWqIjtndwtn0
yp7TGaiMsRqGcT+yD2AIh0YAu8dmDvMSioVGTrRoYmreCkJwzn0M7jUGnHa+i6frsNOZ+Q0D56Am
BDBQMnkuj2g1TV2Qbw5kckvutIOURC0fNoNQY0V6HL9tSYCzABrZ26mmKDwHYmYToMYBMbIZPWtO
ay5kPyKy5R/lL8rmji9DvAgfnMoyDaW+C598sL7xaobuHNdLUwqSNaI5mcF7+0CcwEaQuPdrvnbB
OxCdnK5NPqCYWJUCHrrVw/ps3aRQx5Faq1dRTSoDM0jp06jlSNoTId6GO3oiluQjTnuB4pPqGc1w
z7USQx91M/8XAYoxOsVS3DKRfUprgnqEZ8dcmpzJGignaeboWITEH1wZHDc4KL63DvvC1Nuhx1vz
4TBJ0riiFaTUboskSsDiBDe+kYGTTGbSv3xUXJ/NCqnFVduQ80ygyd19OE2PTHbiHJ3YjREs2zRR
HLgb53eJKe3c9rC35vQpJaH6xxnFOHiyB/cyb7P+rC6S/uJOfbecpmTPAPzr41Lj7ehd2OyX8k8s
SNGKeJnNfxsBV88b2eqrEXS6hlbSS+SPEFmSF+j0ysb/JkWDs57yftCuc7wlNjQw/6VRWKlOhQBE
aAglzHY2YoHmLO45k9iyQzRwIG/kUWS+erlOZeA+Jjla7ioV7Ogr/Jccf1Ni2Q3vXIyHD0FPnLZT
cbDx4qMYzFj42fL0EeqzdYNj7Zv2wH9rA12y4mTlsqMIQWlWG8HUm9j38kXyO3repP4J6Cxbhm6q
6SHCo1bNGhBafPaAiVjFyEF/rwK3ffzOOsMyTikGTtSHTTtemlFJ66gKNaNHVosiGLu1NX2XPRDR
oyr2wIPrjG3g/dWTNtYc+vvR/CA8eA0Tbq3OyUInGZlFn/xApysOXv/k2D8QtPYiBKb7Vxzi6ZJe
pKPwMf9zZKcYpbcXEIzlURyZC7ps990b+kdSpq8gGIwYo/nPAh9Pw8GuuHVVRh2EE3fJiX8Wmxgl
lbTTdcTfHBEh2azm4Af1FqDJzelLvRsHfAQJbIEAMKbQtJkM9AMr4zf0LIkDhce0xXm8s7wcZ+3n
OWfN3cVzDkEB/OSTs3PAySis1krmXJETLpJag1Dbe3XXvG7dZglQzzGEIhx7RtYnK52+Dl4Hgf61
JOMqo5mUWt/nTywB+LI4WpJQ5e1JYnpZ26l+26aTOwFJWe3sNFr4POr07Fga1dWuOMjp9MhvItol
QREc159yhofqqW2wa95Y1ZsCFTuVG/3DV744Mg2YDdCREBLV3DqCGeAlWOT3FLhWCbny3jtdR7Ha
zKwm0SyjM3GncALn0mmKlQq3l+e/7oiLj2eDg3t13d565HbMQY14t6doIRGwG/EE9gg0luNzE0xe
XpxHnavTsERSv496Y5XbQJu7Qc9bfDBzFDN21GzsOiQ2WZ1/5PL8hFed/DC/VZBGrriLnoxf7r9o
gpVjjfq0lAiHYXhI1AXpjJYwISV/tKJdODeJCRMSswuGKjosCGKG1bl8Bb32a9ZqryheUE69AKV/
NC8H82+2HgetYKndEGx3nPuQ7eTRiCd9vWqhghCTGSif+ze+XUCPQXMHqMTcplZX+VaY+FTW8Wym
LdbErO3WuNzNQywIa09QU73v5uE4OoLo9JXTHBPj3x6uzPyIX/lTsGc+6yOXgspEvDTMbhErlN1c
+1vt+/qLMdtGZaN2XoGJW+tG/zN1smL0NZN6q91C00K+RGu6h2I6nIhUIu0xFMtVNdvI/cbM98F5
uN4XLkqkrXi71t738lBhaCkh11DAlcXgHb/doPF8W4a9efnD6rAKvaqvEr8jeecRyQ8eAJhrOV/t
bjL8zOWemCE7ecY0Y1H7PZJ/deB6xjArXKkuCGPra/87tym1PcquoVpHSEZmk4M/iMMRKhUEQma4
fOL+gMDOlrNFujC7A41sxWMNiz03KoXM+wiT6gLCd7Gru0Am2PhpUI4HfgMLV1g+Lm5n9HBPfum1
IabD5y0xwUvKP4Hw3v6MeI4cGg4uRi2KTYR1buWBYQYcAD2Tcrd0dKmUaJFMhjGYxfTTjvlyb0n6
rgihRUuMz/hK0dQkkxaygxmzBEcyUnMJKgi1E1dl8U+8eqvBuPnRLdWEsu0dgHYf6aSrf3re4Sj5
Qh0mrR4Ozr3R9txTjGAXbhBR02G0YRX/rW3aB5SFWwGuwFvKGM3nG5xjp1OhItak/UjIXthkpQJ9
ALJob3Ybu982SE3Og9hFjKwyQEvjsxlfPTyTpLm4E+cCatij9gjOf0I412mZUxnClZvS9CdqwXWn
MsnNFBVrHFiG4VwDW/Uz3EeYC7AANkCUtXDK7OF76DCdlpnalTf6VmKJf2AzcBdG3pXTZB9IEPij
dtzrE3A48QUK+RpRmn4WVWk4KiBPxayM3UKL2LLxRdkvjdFbq6jv9M4z0epyt8GuygYYcsTlaZiG
303+CPZDdRGJ6tQ7Sg8luP8ekMcr6GdpQkLIJOIwcZzKBd7M7r/xAmZGARLS+yWwlLbwufRcr5dP
aIuo9G7rays5hzsjcdDyCqGgQ0fJ0n0YVP2eWzwCxpj78kLgujcCj6aJ+0swWprOksd/B8/8hU9F
0g9qDNq6b4+/C9UXdzGoI0ji7jtX+Ptt9l4iqJIWijZBmZ2BOGYPX2XEHRl0ZumBBtiame/E3099
uCtcxm/U6abSvmZwW7raoFuJBmKcD0CUB63iFA1U7ehfnmxXx5/aCV7kDWkl386BYYXLZyc5aUrC
e135soWyPFXKR3Ur+dFqn2KwQwCZUCC4b/MC8EgGu6nJ5ilu0luRYc+V4LUL7KO/g/S588b65yu3
1r9GJ/mPoDXAgRtHFnvtbk7eN1rXmwJ34tno40qIa8j5MnQ/cSq5Yk30mqy/lK8G6sVGI6VSmKnt
MmJRnJFKnRZY2g7zXVRyGYJ5ltkz7Z69xODlNxF6TMaHxuD/51UB9AbniofuSXx6zU1hVWv+f3Ck
3yyOSMQHf82DjF1KuUBKYNlNwMD0eIxz2iPqpylgoJSVa+773oM4BTQlj7Tq7yBiO5gzJcI9xU1N
q79nbcrED94bkROSa/wNIaXP8lxc3RaYnzLg8FIplB3LQ/7AXTu+8SQGZ/Sc+SlGAmVhRK6j9pch
QNU0yUZWPFmAhqZPmBek7061hj64EL1ACMnQfFYE8OdrvPO9d6LQbcHZ07sZR4UWGOSm8JZwPWne
8Zrzcr38ZA6By/HckHP/SBytFWFMVzALDQU3s4pVIU+O6Dw846w3H9GqLQHChXhVJehYhL3DptDj
t5Y0uehc2irLfBIqW7eN20Y78z3KpiMaFY0fcRYtbqZyrupRpPu4aeXF/yx99VI0Alw9Wlyoz520
pjLycf574pXrUSH/xNeS/pRgtczpKiHGaKydNep5F+imrVcY5gUkwJY7j/9sjLcYJMCJKro87Fdl
bS7Wd36B9D3j/iy2YRsi28J84rbduno34S/RZAZYbxI2AjJU4wgi09loTGitKQhS0LdekrgkWEyu
ytBw7HQBE7RFGC7oqghBqAwj4p2TvA2GJS5deEYVSZt/BEAOvw25Do7/DZwnZAy9zXU/yJixe/Sk
dox2bZqZXLQzrFcjrYUO5qLmCRnI0zZK07dx7c9dVsgWL4AeHOX/NBYYVPyWnqc7sEmhbcBiFVzo
y4dWwT0qgNkc7de0BtndDr/xhu1XVbUlTMSdwBp+aULO5FuNE14r26mrLxKU4GdcAbq9pAnZZAWl
Mb4TQk/9n8vDJCO2IT4YTtciBa84jpqC7brZfOLIYXN/JskfBdeBFdbpQjo/YrhGcG/qVfx9OvYw
gEjNr/2Iu0pgk3BCpbY1EkvtYCgkXzT0RRaotEj9QF7bC6vGYu/V4dm8l86MFFiibvBRbSqniC+c
sxu5cQgUmKBRYRtefa+PgW5DDvrMQa+XtzFfM6x0PpjMO05lvS8zc3FZUpt44RCyBuJRPF3f/1Ix
6DAKc5fCSUtxFRqx2xDFZiOpt2JzYHS2MfzQmaPiU2gHO2A1U99eg5yZsIk52s/0yb3eedbRKedz
jeLvEP13am6H/4HVXQKJwQXiKYjsGfcaxZX3SrFjDmsPZlEW4qFGjShLQ4LBalVY+xIPZ/3LbI49
KlSavdnai1pe+hWRgpML3jiA/42/mcdKSRN/JDev8hnGAP0AsTfOrF3qQiShnd4tWszStu3bRQID
5Lmkn11vwEpTegCJ0qEDzt/vhGfVqvz6O7uG12E94f/i3vD+7c2x4XiFGbVs9QejNEP//EL9HQ8Y
zFS0xJeTvVJ7EJ+m/Y7M6iOBXtHtRpr+m/ATVWro3Pl4+DsoPR4bFLnQRgeIwYWsDQs7HZQ9NNRo
5sUQuGX34buWPfRaEGw3PpJEVCGRIKAuqhZXJJLi+ygDij+jLwFMvpIn3H9eoqoM8qpTmoUUwwPs
D8c1kW7GtfGLQXSzPwPNQJICzR+7lPeShNFT+7mAmM2RPPc5p3F4OhSypJZ9jKqFsI3rB7pEV/N9
uizKCEQsvafQvPvi5/NkRGEpo3QQTse7Gd+cjnNKnvqQokw3eEUO1o18+zc1zbM37ppx4Xsdt64W
t0esSm4wv9KnO/8uGnMK57vucS/u9oBJmEiaOTmmcGyETo5G+jUY9gDKCM/c2TPHjSujmGlHtSCf
2L9USGbRbJsSae4GaP9sH+1eiWLKJOBYmkGtIXs0ky7xQI+DJQujXxJNdb2ryuHWb/lGBRAJIcz0
zbzJ2r9kV4ZVVgd13h9I+28VCaTKc2jofW+pqLEJEI459UMzxtmobFf0+SZK8NVz0a5s1yqy0HxF
7esZ+Rqk4yXZQbMqqsaKbXKqiLjl9si0SK0CC2OccbTiYsnpg695xVDMx26X2/TSlhtm1+H9twmy
YJbSFKFyWPwgXfhhXcg5m90yoPFOip2B9ahz6Kx7bzlxHCZRr1eun4w1IbxxGTWq8HqgavJV8qKa
69CjVTujMHeJJ00eVeeicRHZeqRcFn+Jm/TFJWrMott70JGm6AjeEdr5Y+h+sZ2FmQt26wCHl9iM
f+u62ZeSq34weIzTa34yxqcjyYJGvWG2VKDj3j8qEsxEbkpTKT3aHfhvPT+JOpD0WQ9MXFyb9GHD
DuSLePT8ZDhT8MMzKQQS9PyTpuGXY1OqzgHeiHAk7q3T0LTGJNv4060Oq/LdDV4/ymWDKI6+AJ9s
O0RJ28gQ13zXqEnaQLAQYuRt8u5RCrQhjdS8N1ZH54oKfxboDj+oSaqAqN3O8um598V8S3A084cM
hc8shpaJok7x+T7S4zGzdfWflYqvyg7xH/RMoaVVWevgh1Yxp4e5IyW/UOeu2vuxZViHXmmpLOuf
NOJQ3M4nP2u7e15MIG1B5pQvu6k7j1sqICcwGrIjKkbjyW+Cp3uwVJNuGyVNkn9w0kIftMZmiToG
1KVR0I36a+VwM8lmK17sJdgZ+6FvBReHROhQfZjRghEdWDLXcyw2VohqYCz6gOhRZBwitLrOvwW+
uAzkcTyEK1CoVEWHWU8rwUDz44xogOfDPGZdE9b2SpgXvwPAakmWC2+zq7GqAhUTvIK01to4W/FK
nq+L8aOWhmnSoXiLibcxZ8bkV5CVKiHttmF4YCIORjEWS8ZKyp5WvHt5vpDoez543PfmFxyemJF3
6mUp68MPbkVvcSvmqQH5H7wHLuJXJk9gUvJS0xDdXgdAIn/WZMIvgXYi5TLI4kBDK5Kcz/tjEBAc
XCHbEcvAgcHk4VsIuxsaxZw1j8G2KZ7hUvzhZpdU/06+6gh9s9H+kaNUIXzK8DVG3eYkpsN9Z1vM
Up36acoQCTGsCGh9xqxd+ar4+RjxIqOObTS6qccpHPnWF4OzrZMbDvTNVrzHOyI2gN1HxOU5kBdx
6BMbE0SKQjP1HVgdZBgvb/OLJ5uZfJb+zMCUc8aGvsy3PiX3CnynBK5YGVXPlt/zMqcQX/NSdYEV
2f7I+Dye1SfYD+HN91ZOeUUtmesX+FxJx6FFsvIKWo53wS199HAJIG7PHDBy/u+5yf4yTW8aea9x
2EkoxeLF2zsz4ISCOARlhtFLpufUc55QAdvxc+0o9WVTc3RL+rS+gT/mNHUP9xAAsCIxTnU6DlaQ
kt3XzkcJKELMJ9QXP8h7Uqm54Tlz8fEytbc24hAzsSflH7B8lvsMq2IO5YGz9lZuzOu6J7+pXb9W
VIFXkKCkpVgG5OmwouyK7PWy3I7INhs8brb4PJj29cNWehHc2ZNJ366N/zAPjxd02pEV2aIYc/J3
zKYT3pwzI6066LjpZvlbQwDi/qXYcyt/5Go8i0BhWf94aH7XFIWBK7iFaDailkg9eAvbK/NWkzz4
KaivpIyI1K7yE8fZPxwWn0P+0ilyu2uHe/GbD0QCFWN1XaYdZPFXK2pciCrxkNhqeUQKnQNkde7x
meurXm4cjLYCGvMLSmKKAcbSAOP5YuD8anySZtTgzPfEc1Xe4vNi//nd75fgjz+uF25oX/k+esZb
e7z3/g0viF7mHak5oKtrdb0T8cE9vlDOqQllWO/jKk+77VE2izuf+VycUNnGzZ8w41mzAUnJUPfO
znHFE1/JMUbNcgtYn0D6seYzLogHNiK7Y/0RLfjCJZN9pZD8W3h7vfMBBmVgty7rKdHgD0HmVAcF
4+lnkCozDjnhckvrLASho7fQf3HabBvOzlo0n/aLPNcKoJmZf3jC6jek58a8Pmvl0eXIAlJXYQc5
cYqnWkfROo0ZO4FaWvJFioHg5E+PBjqAIwhDOrVqknX/0rlzf89t/DUCjyrT9MX95JVBzF+3e3LW
rybot7OcUJjVgatfEPQj34rGs5LrcNWTx232VlEN1MlA3sPsUHTOikY85d5nOXfnDA4I8T4rTY1R
nFEDXnklnPORasULyi7wtntl40JEVP4X4WiMpMYWsFm2uomhPyTS7YolAS3DwrAl60/esckuGZ6q
NGcWiza1tPtS6mtB7o9yxjT1DFX2dl0kOu22W1PDM2hIp+tAYnFx0yhSXMSgmbDQ1/HjX+e1Ij+H
f04iH6+ksLM31T6MzikZ8dX8P35tkrPXj4iS0/qK/UvPjKXJIn03WOB2rXJGi95Fc625VYIyERpg
GT8/R29Op+3iUFFmmmpE4F3Jh581KT6wbrLfO5NKcpquLhbCyMlXlv9K7djF0t+phcfsT76Q/dHA
gn4mS9jqlsUkYRtAH2NREngFPOiR8ozOzwQV09QJzeOp8/gbgeiCRe2/INFizFIZ/GBL7dAEC1pv
mrmCG8+PnKslJvS7luoo9DitSqBq6KXuwATSBWo/F33F4OdQKzIZQwWjBfE7JUIo1m/6ZX1gYcfU
e8tNfsglYWfIkGoWtwlPnIbn8O1NdFKoKuK/YUbEp6tbsmwlNcRsoAuLSfxfyFiUsLIsi9oFnmDr
9BDQLEWGmrVWdlwugXz/3N1ytG6/7ojpykm7OF/KvJ+7m4LUbaGJq3mN46FPc2wibjlGjq+Fd3Ka
4qLn+KV5AnEWowed8eTpe/nbbBg7jljSd/3L8NBWew9gj/6CCdCTBRgF2YJwrduVz5IPHwmCqyfT
GcFa7cJGCB0US955zewEtfO5F1SNM/6AIreZcptnmu/fl7WCFa60sjl4lA5EnV1kUJTcAXfGtnIb
gN3ZGi+jnJvakUzJHX0Mng/Cfsl5YoPeBWvDjWrCaVYDYVWZw0oiQtL/wxmkVY5eV8gmM9X5P7Cg
l6qpXYzJr/6GW/K4qCNCNgtzCJa9jTAf8DQ62pak1eYvIwwj4sll2ca3LhomNfyzmf06U0910lXG
cFrhXOe6D/NPFgZMW6ZugvPsBqe4NS7F8vYRlv9zmEiNFl616H8sql2a/+N3+3ArDVsZHCO1Q2gF
5JE+HKoZxfx6wBT8QOpq/xhrIj2UOPvHzG4/i+1Y+jh7sXuEMVzzDT3Q/gdyAoryb4cUD/ntFMiF
tVSTEZBAFhQ7KbEEpCwhI9p2uUUbxQac2+QJz8Ufk7Pl6LiD3uOCIudpuUwzybTEq0VGTKGksTL9
xRKh2oh47glC+i6Lr4uPnZFW8XJqtwB6UoYWkObNXbsPtudm6WCRPna/yG1eK7CxVjP1m/eo8Lva
2QaYftvDtr/1QY4C2Ibp4CJVybweAY1GKdpDWXCTasyRrovObiTGWahmfwbfUowXZmxLjYftFSr5
jwcZdl9odLrhzqVy3lFJPrrKjtJd0D91Q0bmsG0TDTkelvE5Z8noUVpd2y3Y7XP6syYTjjKSn79N
QHJNekeiwh2VjXkl1+RmKbBTWITeGS6TxUpqMzrGjpehQlt4T8n9HMtQPTWMAW3Sfoai+ILIp51y
05iqGsO+OQmMZK2Hh+Wkp0PHNiLNeFUem36OMiTbJV7WCgweCfRG1WaUq4b6HB1b7qKs2D5+p68x
PmMs63h5JKuOO5DeNnbfB49bXN+v9PkHK/sXjFZ9u4a5Ku5p9tc85Aarq4T80h9DCRyohzJGAMFD
fu8FJCDx/4UgoztMggLeJAe6u7R42D1iAp4YGYP6x8Ol4xZdfw6iJyR4VZkV7mgvP4ZjBNrg+Nkh
Zl5RIU+ppfz7wDeOYleMU1qSdva2xrh1wQ3XwO97NmQ2XrptWoh4JRYSKH2BoRVESYlKiaQ439jZ
D1gxXvG9QFVOWwWN0sd81OgjDTIkF8bLuXqHvoJSY3ldTNDT20uLFXL/m5Fz84AfP3kERD9Ta8kA
fDWi8HWqjitt4tB+lkC869/YLH3DZakyu5zXXWmFdFw2BQImNW6CLODzmjxkso6ktfT0lp4EgIwZ
bRhdeE1WY8PjEJ3e+pTY5IYgNs8KXcX1BClG4RWFo2xaMmt+ZinS1jW8zr0Ds8bl9MRKbw9ejIZ0
Qi+VCeEhbowugrBhGpfth/iTP3oliwYmCW9fif1nMq2zA1Cle4YKWFkQXBYsDHcWavNC8ewnPxKt
Sog4AdC3DxfwOub7wG5IOqwiZDan9upmffnQS80ll/ZiPINLQWexum+J1LplSqSg/H4hJhu7BRUh
JumlCxt/CEPhTbvgL3CiafM42NgGluV2oGovqAIqM4dXN9s89H8hB2lbUdSJmujPymeZzo8016rd
eNxugUsAACyBvcjA9HInpUZztjz6A7L6WQ4I1FqZVZbbHqOyyzeFFM1g/bEGL+KGQazfRysygaaO
dFv+MacInq95pqMa5VcfRjnof5iUAuRYdF2L51+lVc+8KPsSbHOQo4lwDxBwBMmNgFW4v/s9jVOa
WeqSPRaCt0okzLUz0MGwVbCU++WC9QlOmbLZHvreQv/sf1hMP8gYVZRs8T3UYrzihMgaklXT0513
QOB0P3qefvNX9hqUG2RWLAAERb3C1V0cmjkAKJEYnZPyyr0sPWSZtxL795vYZVgZUzIBmvQz6Zu4
MZZB8BmjbHFwFwl2d6rfQtGOS6/I4n5btFpKYSNXANzUp2AU7zWCWN5SSLvkUELgQXSM7KuFx6eH
ZX3CbK3txgVZ2YemB7OoXC7diqNB92wmpdY/0GRVWMz9+qgJjC8Ovh+chQk6yyjZEh7gQolBMy6c
pBMjONYgmHbjm0iVS2aDXWskMLSO5n8O3OKKQ38q/JWjVXM7bf/uQgWMSfXkpHyX9ikmIDlIGroh
ovGG0FM3XxaiToy8IsvCyy21S/R5SMywfAr69hFwhVJLju80ulVDFzvQ3tG2AWzlK69MSumS+WNQ
9/k8ODe2lTx6/yvhmLVwV26mlQAlDXbq6h2j4+UfM1OvrCwC6xq2br/c2SPnFmd6T0IFMfsCuMLs
j7E+ASBXKFZGWDkY3aoVl3z2cYKxQ0xp23Yac5Ek3kOmS+P5D/tcegArNQkAiZel1pF6PRP2kwMs
BYBB60bxjnjU4sgEbBa+sq180W7kdibNNH2LxKfiI4eYLym66DbDBrOEdDD2lRfoMi5pPlpWapk1
HRmzBMLNlNSthDAPDcKj5GHcmshcRLaVTOz6X0McBuxCsco3mybfc/IhDb/Klerz48tOiGMNLVUs
mkxGx2DXWwfs1Z514Fnwg1VNXw+NDH0ZBrxmm6k1R+W1TpKXN8zEAP+UOnPid6QXcRLbVkGFgAmc
j/1XlK5jC3tsPwNgstq2jMjzUgkTu35uEWjflGv+2y9ozvueXxbkCgXMnVz3211ZkoL3Jf9KZj+j
Ahej/OuiILPCYR6VKLK5tga2DZOKokKYOf/NVjHtylpeZegDFyAbnrRAf0fVXzWY+Lo4td3V4isr
pomUflpFdx/eN4iyyzSJ6c76W3J76xWlZSdOgZSkZ/8nRJ7wOyh7TBLdQ2yrr/2pU545IERouQJ1
/3b3b3QSy5dgwthST0r/zavuYuqFNsGBBclIW1l8ifEOi7ev83p5spXDceh6i2ogKRGdTH1rMGb2
9JxGgjo2mwK/YqY+clx0M2WPWI1oe6eKIQu3GmzgPHa0VgMiwj9kvqSjVBHXV9mWVIHQ6ySNgD/N
f2N7EArPdpE4p+0Rg/+A7GBzJi9+5sJJNMkSW1R6sbIBtdqrkCO8QyZcyh0wXpnkxHUjF/otSrZz
Kf+U76CPEFS/OcfFDGbDdYsoYgrEhHpt+LyNOK0v9qcSuy+lT6nl//pkHOEzzbg286EzbPqctNB3
AW4pU4qoPbuNsYefDgXbEpkIta9BFwK2Xr4oolr/IEb/Blae7i/K2QBLe1LKYnERakzE9I/jhzMl
7ti1X+mf5hFk+nx48OvbqPjPo/5Gj//M+ff9S9EJy5qMUI4JLQUmBl2GsDGfcWJdSPWOJuSDc12b
dfk1STZ81o756Fm4h8nhBa1wZEYvV9fgjZkhQ2LBdGLw23W8a7xtHu6X0XVlwsyB+KmacAL3XGyE
dXpyBe/nGe79v40mz+jXiAspx/+oy54WL0uPb8DPP2a7p89HscTiaGT8+fpFxRhnB0RxDQ7jNp+8
F+P7WUkqFet0/mW5KEZASSf0OgLXYGT39f6oE+odyRNNnRpH2rpSaFoXIduWBvREAI06V3dcb2Lq
ueBge4DbTGFLqSQXmKYCDOwxdIYDlEC3QRY0r3nZffk8WGfuIfzC78n+f1e2M7omQW/QshWnzHEW
J2kKl0NTaXvrlzG/YiLxqyTF8yv8JMhj3sYMgH64QDx42WCuUN8qRhWDwcZ7Z4AxdxepPVprXZDi
lGacToo68wvggllKYx106o3gUAsFyMLJd4/av/MsjaOpKoILvTKRPO42Pq9WHtAEQ9PRK+C5wf7I
RqWbESILi8qlV2BXim57BD9QhyUKMN40FlmpFWVqMVhqUNKFBMMx6if3uy/wg5+0SEZAsxGZ1OuN
C0atQoJgaLXghEBLFF0AowQ5ql96odjpIk0Bj0RMsbktZZwlrkQxlu/jWm3rgBSWQudSXk04HGd0
JDJtADfI2EDNHJN3vYclOhjnIFRuiZZAh/HHPjADK3bUavTRZ8WAbAsE7bdke1X8MaRBa0lA8Myc
2heFPpD88LzLNBrBl2/a6e3d6ypVb6U8tthUiOeggO6qvLQutwrjpmcLBnFMYZj4E0gnvYOcZNnk
wSZ/7H8hKvuPOuHYeAedqt5EeeW2Rn3tmksbN/OeMqGK97IPHLVkcr6o1XsUwSAxqoncUACjzxVV
0PZn/uHznQX9lgBTpNa8lkhpU3VSjLda0U5QN8z1PZxAWxPfxYyYLMjg8Z/Cv8h60i55sRNQQ2jt
pvISim59JQsmcWQkKf3RFwWTsJfE7Jh2I2qLH6PxfGpBShL6Elc61ExwcFlF+a6yWlbB+gZu+8DV
4bsezitTZYUEDCpVSTkBCTVq/lmq/AszbfI3M34UtellDBdOf7rd43ZkMceQdXJvKwjekMvjczuE
OxRzmOD7kDgGF36of+pYjfQCSVwIZxnES5G5NVJrVDNq5tMWrrCLSNolcQKFC8X4xHTp5okW/mVS
4gyuQqbqGIab5KO5uzjLgLP6hAgG6EwKRY9Ql2dUF30+vs59oY/kusaySWYG4Roh0Q27FgCBd7gI
7EizNk0yh8SDtHGd7MF9iO4BFg5wl63QxJeBdd55MEs32yHfsc8iUxn7Z1r1sCkf/E4Vsb/aybJa
+n4oADrqng0ZCRPLHvHsie5pqEFnlu2QZtDtE+HYtm83BPuQpDZVeklt78mPAV60xruVk+gzvHjM
NbT7xdopX6ULe7Z7SqKdatU9AsarH2rc+JD7B5ZOZRNi3Qj9xI1QgvMsDGYJHRjOooAfBBPEjYC/
ipI3qXtjum+9N/22buyiVxw38Ya2fDtQNVNGMl0boAzJ9ol6FlCS9eEIZXz7o7c9KtYBsxQxMx17
JMl8KtL03AkKhb6oViB/RVhbyASUW3u4KumWTDdhu4oZ/lba4W0SpJ8yivv40H7yAP1mQtRZyh/M
wTWvv+38r8B0+UnpcjHPfBV49K7XHIcpnNKgyU1PNKLiXhzLIdDFhSEnzqsQsoDjeE53QP2p0+2o
AoAuWdyzXrnjWReuiFp4/lpN7C4GOcA2ZMvo9usyacSi1iEIs8fSFo6FxMpQ12sET0TmnNsi+lR/
rJApyNSm8m1AaENek3/Yie3lHY3dzJwCYd+FBCmhyVxA8zzduChyTOPUTUreAMmFq1TeqpW34NwV
ao2GcuaDM4X217qovIA3vZhmmgfWIgKALLm+PunsQHRtsvSRBC25Yy6dreL2nPYPAUayx8dhpepW
7EjIh3bOmwAl5kP8unea9l50cucGLCGfM9wxVddQYIcFGJvXawRAevKMcIDM1F8cdafvKJqoSNH+
W4KZvJaHMuaD8QAeXQIOi8Kb3HYOrAcjCCxWS+TeiXgQZ4sXMa26yoD3NEC6ZjHQ9EHpheXR6vJq
KGhp5HyPJkSLn8ApfPHM+nAcC8H72laN9uLlscP7IcXZyuRNo564MOKbWeDgmeH/pnW5qGy+cPwa
vgFHzmgL4KWHLwfXjqZ92rlh46/nM9j+2O9wRI2YmdQ5OsrUguN68cQTZYrWOeGJB1AiWXZdo0GZ
ZcMr3qB+sEQg3JKwcKBesizNoG6Ms24k7wRM315p0t5PrLfS9wM2vir5LUWHYqeC8QDkndqzaGXq
09Tywu1RTUwK0bGZx/DIQjIbbkQ4wbW11qEwEkWPrbXZAHm+7LRs0FTezt+aq43OcJL/QVH+18tO
/SF+r1osTdojTeRFG++63zJVMTMu0aLnXxbmXU9dLN9ZsXF4lx/QfB/oN3RMIeJro24+ii7i3Bz7
oa70sff1Y9GIbldeSFWHUbnwYMfzRjw2noJ2FN+54DzeinrgTn+UBM4rjpnhKFwYr26Q0FAJZthk
MDeVxIo4z5Y/1g/u99XWLYOHFVkU1adZm6fJqx7h8svgI09zTD8pw/YwVKzlr5qLFSwOETAOx/QT
pyJc49KllndTlbKSLAr+lNUpPtQwR3SZHNS/W3uob2s8Hz4TToT9BPUANI7qBwdXT/NvrnmJwcn0
jIjXjaJTWN8zVer2iU7TLYYcgL8iRzPtjiivqghR0CNWC75cUvAgXMyroI1w4jmjT35WIhXgFNGG
E9wGz8GDPSsUaKDXxujZfcXqSrYoNX0eLvYE3jm7GmdJ91uxDcmCiRPUa+ZSfEdRbHcuBWwaUl+F
Mg/x62sXFthnrbBZ9CKX3uINPupsjWkE7RbOG/YuxqSvDx2IgPBYj4hwZ7AmjvlO0gvhXVSSabmG
/5YwzDKBl3cAIma828thlbCYOlaWktH/A5aMiBt/l8wli43EaWcqHdTYCXXquFtDvJs1nUNAigvG
y3I5oXrFvYS363AsYAKUcyBLsqAcVJOKdBKHusRPEev8hEZ2YjtuAkozteC6c9S5LO1+XajWdDa3
DnfJft49VlxyyJrS6nnhl+jNPumTGwZ34BhR8EHh/KIOC7xMPukXBomxJPhJllCA+tuMGt0eapjH
xLLGhamshbVx3O0NM8223ZbQW/gdukhjB1xxqjLOLMBi7Fl8jFZvP7SRR3zjq5DmaQU5ObEwcbaR
5V8/lck3tNaDrgYCrltfuZ8+pujOa3x/kYIvZmbMpZTNvoEpwQ+eUHP9mwx3gLNyIlV0HInxBul4
khKA0968fQJvdS3d9BJ73BGzdjyutzMhzeSiXwDiJNXvk0EKbV2Tu4J6igT07SZ9+/P3sC6BD0PC
ExQOYb7Uzd/K9xZ+f8rEkx5yVia4USzy5ycWBbh2/+ADlt7Ot15xLp6V4cyi94YFM3vU1iSKKnZM
ZQSfYouM6trmwc8Hrn61RlfwqeUmuDtPVae8NS9NBaVB83e9ehXEkyF1S9IJ+wjoaR1SLJ6PFYOK
hID7ipUn1lvO+mPC6liJWBNEWJ8SrnSCkfZ1bID4CSo4PeMI5oT9xdPMrr3u3e8K7JN3My3ufy62
xGE1wyqAnHeNK2tkfsccoGIRplaOHqyBu8GOsglMB1UIZhMnfPMkcZ7lN9X/wZjuri+Zi5eBUolU
Zx26bntnyDvSBFCIV6tfSXQ38DPUclGufQl1cEQKlPvu10kY6ksbKTTI3yxg6F6QKUeiZi9uTFHB
Erarscwt2CWTuWfBzn9BN1kMY4pA1/D9lGjhVUr+eXIUMRQ70AABfFDlkBOtPC3RZVhxpRC0TOs1
LyNdMBZWAdU1xGomAipQb9ei9Rf3a3YBtH9ibLrIv2F+iPaedc2nX1Mi6q/u2zx6EByog9Z68lOT
4xtVMGgPHkbzNiIZA+7TCCoS2LbO7I4CkSNQZSqmyb6GpHzHHsfMPOqGfshUns4wJL6FflMdVmAK
yiJUIjcSLpXE6e1k9sQyNZ7P7X0AzIqvJcJR0jdJbZjpmmGjiXTRSY9I7Znmh3N324bahvbiQKc1
OpagysgfcLehEnjf/BURQcwcrY6W5RnPFUs+f7FJ21VPv87DdMomKritoVXMFDCzu3m+p9Ekje1x
nSho4wpx6IomUY9Mg8/6Y2BmGMF37fSbEFsEaJEhGgMYk5QAYk2vLWStEn21UsfzecXRtZLHfbDs
KsNE2hjN+ykxkMKMsYrRR6yMYKoJ8ZflR+zsDIw06A+XFprdoMKkxUg77oUvH2xNFYXTxAby+JG/
N2/Nwztc/5ciEU88PGVOSda9yXFfSShbjLDZY4AKWd64keEDuZx4J2tfJqeSkCPm4CExNPrSMpWt
loPXDMLzQOKQl1zO1BoFJQI0XfA4rkKYHi5YAHrBspnkSs37oJHZxxUc6bh2z15arxNcjf/dd6q5
D7I667l89E4kXll/lMNtwOFnE2074EPJ3gGXSWP8FN2rTJuf5CjjeU3gGPyYYPH60y8ci855lc3g
1+GGvj/17wSrLEPeRT5U487J2e6C878cCaLHMnEu0uN8JNwy7g8zmikjCcvNlhv5KBj0VndiUEX2
ZkJ7XkwKiXZ4oORCp6UoEvACiZwGk7XcXL6kbx8QTlCRBsM1FigoK/8V85traSxCOE0NvmtMxVQx
1fbwiem3a/FcRKRKp8FIV4GTk5jKao02tSfJRvB8SJQHlLMbBUWO73FEfd6CR/hubwzW1NPwvLPF
YmkMfl/F2nOQXvdxNEeT2T3UB6vqVmnjgg6djD3x69bwlmyuVy3w1a3W7RKE9mHHg8DPwk+EqHeV
i+D2umB4k3Q8yf91PdfBoKu76STXtIQyXDg+P6T/HYFg5V2XEl/i5rPYYaPpwj5L1uH11PYVwfWy
9xoy3Di+xCTWAkiQfDZYqsYoLu7CdGcWTKDjDHFV2X0IY73GttsN4wOToKsIVcYFlQ7RL5Ck82mn
Dm1kMOD3Ph3+Hx7hOLn3QWH+XUOklY840idopEI48n8gpiOf3NUUsGKG1ktjBquydlcNyP4EP+Gf
mytxnxPtGIlxivZF2xIX5gkPBYGvW51Q/bNv+HKzrJM/zDtNjNDo0g8jaoFyv8CGxiCtJxVuN8bC
xYHHwcXTOEVfmtpRA2OqM5UOw8Iy8nW5Mq/zEXQSV3xMwksrD6kBg3/pnEfJYbTd4/oviQenxSns
9cxjzGpXlS8dsnG+vN/4ArJtzYLXntF6kaDjvR0rVx+No3BnOFnt6u5jiR5NZSi5wjaFcMdA9MXs
EXavaaYT8l/jj9AqjC7eB8HpkGQZu+6e4c7wl773YVi5r73Pipr1KTdGBJyAWMvQ4PHvXxApdOdN
Py8SIeOVIM+NMfwfzicEMp+QERoxe4Jb6elqoXLq4JvxAswwti7q6uJu3nSuNZ+OancdOa7nyXKA
HDpdOwT0KlXrFf/n7YK/M6ZNefs8fNghlfUnsG3Wp5wQE/rDClbYw4urisVsFTaP+6uwNj9BCHlR
gmjjBIxdFo/UB9BXApx7VGr82ogVRwM7W3TBYz5g7rsUChsWq9KIn4KwabtKJDMK0I5im6UtEIDc
yAEDlcw4TC8OaPQZb6kbKrk6kD4KvXWVFKX6cIX9PzHOS2MzwxIhMWQVBaE0YWDS5JftlUONCsKG
6Em/cxZI0aD7OcRzPt9WKvHefjkpgaMdwQloqxawMExY5znBhVuNeAWei+aAnLcO2NFgctSkVFut
WUyCoPoKeQrtGK9DGDZ3GFbzdFuAbSA5Sk3YnO+oUNMDa1agZj/SuSv8j2nFdKRZ2MDcf04OHwif
yJx9JUSIj99V941g5yr/GRaMndb/IcdwwTm5ZklBmp6jV1I1+2NGuo+GmxD3DCNQ8eWqnqyIuxM7
+BtF1xXFhutx8+Efa24+PXkthuuq5miN44ydgFZr8hIknTckw5O3x/NQFlt+CNglkOh3C1PCA+T6
t5to79IjG5681zwArw5y0xHEbB0FvXyAnG12B4Tk6YXCA6Uw8I71M+LXXX5zriXi92AcFebP7Q18
YqqtJhhIudlQiApJTJZKkhLrgazNKaGMJS07u/QnF59N0wQAD+wOPG/dFa1zDYKAgU+p/bf+U1y8
xw1GKn+JXOdmBH15ORzeB3cYmGYZakLrCoiTfRut7LeaopJKjXks0mLkpo6fzySDBByxOIoQD9G3
EE4sPWKJArkUeTO2F6SrZdIGkYBQFdA0TOIkK4+fm9RRcouENqmF0c0Fgj8lGb0rubeM+rpT7uGX
PrL9sEAsViz+iLN5O4SvpjpqsJdCF3R2V/G4iH+rqATwf4ZxKKixo0n9C2+quVkmCnjyDGTA+PRo
y7V04wlh+8ZCv0xLQxTuUvPDtFzE+MZUw+PcGHb9CovYPZeQu3IXcnZRDMdfy16xp5XsZIFrc9Ku
+wHNXp7UGdJq0w3WRkYl6QSKBD20Irys2We7nUi7Q1nXPvvnSR45NVSTNx8CeWrS0l+3IaqOcIQb
I+NLMdWus72JOjoUVfw38g/cceEVzh+t8Jixd8V0u8CB1Ezmthv8y4BAM32DsCtnLJAD5GwgLOnZ
L5rGgzwbhf1IokgzQ967TvyKZIuZWvB01xpW6j3Sl4hdwCEGAR1eoHBoTmrmayxUsq6jUQvhPuZe
Kt/Ys0xe0nEHWkyMmkdbPJhfVha33bz2W1KC95F3yS1hgBl9T0UNurSA3I4pBtYmF0zK4i1HTmws
XC63Ag7AbcKruUGZet+4gmVryv0xL48fTwb40y+qRAX4VUb2q2HUupg3a3DtHeb/TMtyffqn2rV3
/BJig3eeGyUu3MKH8ds56edhYya8Ph2QZVgXq0E6I+AR1GxJYfu3IcgPh5fDFDVkskSvB07pNBNK
YNZBp4FW4lFg6IL6mPax1YCYa7l300RrMPrly0xeWOCkd1zPfwd31eR3NSD6V6ZLe1kxoiolr/5z
hBfKX3PS7qXmfH0trK+m2JGXSYT1Mzq+e3GA25FWT2GZfMisuMMMUXHIG5MHq7Ziz459bXW5kSqK
jFhPjVbRs3zy6XMYxLx0bnfopYAj468x2Vi7QOtVdLGIUoJ73jiD1ABiHato2Z1to7b8+tsBER79
H0P4J7VFj5AvjnkZ6SMioUhQO6wvddEPjiKd/h6/u5WS1JZZ8lpjmABhQWldP/ngquOG1yeUmAN9
h4zNEydc5MHCL8RmnIbZrnIq5nshieU2wM71mGpo7Vpi3CSlWEQouDQ/r5o/dhCTasI5drV41mNd
NrlRslP/YXmU9c20fIKXEIq52Kws9MV8+SFZyswWXJSZoQ2z+wCdjU7H6ZoU783yvE0BaNwvEQ1z
BhSynxQ68bCzLPe/fZa9/+Df/8kaeJsyoQYRzY/jdmiJWas1EmHQctpImgM6Ra5cAGLwepAYl/+H
1nNWGOPlyRnI7qkA4gCG+5s8BItRZIGeDD1ObuZAMFBS4LHbCvvW8NngiaJ1o5+7zKRq9kXDblEu
22lzFu/4TuItOdxlLh4kQ+dd+xki49B8XcFMVpzaLhzRrE2DIrBMhlA6bySuPCXsot9uaag9l8ih
B6i6kCOi6vAUJC21+ta630PeGA4V4PgbxvgOf+aC7T2BIcCRX4E9LURXGv27i4dve0GuliR4dIRH
Znwaq5OG1SSrGP7WGWgKLJgUgOyEpDnTMZIFT6baXwmInQv05xTYz9yg6F/NIrsZEzLtt05WFdd9
m9MC9huIBSQ9PVcC0lxsVC+3TiTql9CCC5pRaKXSV1kCiEgLJIad6SEPXPFeYO2/K13ZVbTf4Wb5
GGTWIdF8nnAuvRfBzLBg5d+ZxV+aaPhcFZe3IDjUsoYXVeqrzxhTb/8EXDsVk2UFTmrk+WAla7rG
0AtYJ0CcVl2Bg2h/UBaPJu4+G0cLcpLJ7nYZ4H7doy4En0NRshSrj8WAM5ZRiMyjXi4aYZCuEDc+
i3s3l3LkuAnIzmSK5Gaw65xYoW/imFBLdQs35swQ3Cfjior4IFBujL+9LIjq8YprLispFu1cgcC+
H0mjNcnkB3chVT9fpI/8LaZfSUk8xSnmor7SPfiY1i123idJuqrJkthyndUvCGMCRX+BN8Pdx7d6
lmXdCBmHDYXwvC3JLosVfQ9i4Ih/jc01Dau+hraAuAUiL/UHgKjBZkGqikLJJN9N7deYFyB2a4T2
gnXE0cvRByfQmavh5tF1HJtLVFTUGx6UqF8Rbn4oq3P8CqoigCskUdg1wNX0iRXdNx2X/6BTUN1r
meFWiuBmM5fnJwVr7JJOI3wqSl2bJDm83QLehVgC264Yrf+8d7Xfn5dEX6fRlbA2YIe5lVxUGvxn
VAKajliuW0ca3apdHxAVLFjHtlq43inBomTcs8FtuQb6f6wCdyTm4fPvW+w4GzgkJfNqmVo7BqDr
nBxCOfsrbfkhyGaQuRoQ6HvF7fkVmdBSY6S4/CRSmGsbdvTxOoDmG/hOYKGYujViKrIrLT2iwWpJ
Dlx9/8AtbUUnKZdHR90Tt5cWND1+8rAcEq51Qn4WS4IWt89ogZqDeBS8NjxVfe3+d4RSKqH0m8G9
avh0qURudWBAPSGGVVpJ5jgKg6cqE7SXmFCnvrOR6NhV3MmJdKlHQi0R6ie6AtNenrDY1zQv4lcJ
1vi5FeRMztbsd+GhhlNk9lwNKcQLX9fl1MDc6b5pqRcgt1GXcGc9DgOqozC3KoUMkig/fLbuOcj0
xxJMkhklQ0c1LZ2oIHL7SLqA0aKRlgdVynMlWDeLryiIrTr+tejJ/OjFuCovzz//rHdZAQgPo7cX
scja/7x+BOFvmPyF0FaBfZh9eFFxMv1mL4UI1GwWpEzmBAXKe7jAivNb2XcVSPARwffB+w58oCrK
Bg/1xUujcaMvgzQBd1ur/FeVPF3wL7fMKEAzG8nF71c/BMIK/pLYbNIwRAPUssAxuUNV+8BaN6rm
CZGNZV26GDAlmGHZ3AGEJbfPsPHBl/Z+8DFbuCm9fmZat5gHOdZybQOvUWxY0r9CsLyh+LRyJ82d
MGmsXNWgR3yPeOy8b+S5pmTA5Y9P+NkBv08jrBz/GudYfBolxS5DRNoPNZf4Hs1es9SAQNNfgEks
Xp6vYp4AUR9cDHlIdVZgxxJ2ZHJ7rrMhh2WoS5fmFF4r9klavWTIxUiH2cUc7mCfSCIc+Ilr6O+P
hLcf8ghZoIOyduX+XpxSuK1oYFP9jh0m10wmd3mopQ7SxC4dvP+9hf604xo0BufMtkNX7VWCXTe3
WSositmUM8fuoGNDOjasxyHKzKV5QXFJ6qQEqZXAS9oMtGW/XYrZE/GHFbxMR+bhIgXzSnLTUQ/y
voBWSbDoEmBogNM3rTwEnvXeNITVGFI/RHeVTmonLoMOIuuRLrG8KdDPciFKErTivPHqqOArCOim
Knbq5qlksOVqV9GYlWzEk+NhsmOs/Csv4kG5z7X5nA1fmlxawu0RhgZYrDJx1IX/OWeN4LEup34i
rPhEXpt5c/ILtFHk8NlpYKHlNRvb7ehcmnoXMXMRROBYqNvda4Wbjnd03ks1/+ahqE+BE7PicyBM
i07HN+5Rs0Yd1xsQEEUgl5YLS1oq0OCcOsrbisuDP7Cx9Z3UOPXe9m1zmkCrf8RYTwMyiTkkrm+k
Up/z/4zhWIzuYbNTEIXbenGEAtk0IxABialN+wWj3GVp37zc9jkvfyayKyI1k/3dqpYmEcTfujXw
mfY0EjNq/+qK5YFUcQ4PE+9ioxspIoo/NCPjlh91Nd5w7Al9xNr6bhLS+RqgIhzI0sbLINYkXdcQ
WYYB66oa32KAk8DW1DBzO5ii47rbELPLRC1czyXmhMRGV7c4m/I3HKBZFScWmPM0Ln65xBckq+P3
vP2Keyscvv0eEY4J2iIMxKA2HOZQu/xRYrMOBTAZE6TtPwG2g3bCJ+DEnQRYihCEFOJeVpbOm16J
slQT4pM7F9e9mNxn4zxqScgylaqr2HL671XwXxLMAM2zK8YXoEX7kclqKTe0JNp3ZKNi04p1VcM+
VzAE0qxFY1cm7ILxLsiydbgPbWk+sERqCdX1/Oem/G/YHpaGUQO0n1YRIxv7y/mM3s/zwvyFBdUm
9UKIZDewrifJipJ7wbbBDUG1RPNSQpAyrVBb6oXpyzkBse4wQ4/LkZcJ7y+YHm/lXi4FDaPlNuvg
tDmoYky/kDswI0ua5hHxo+ROvWxl6wDi25SBrSfdUk1mZSAO9EJz6jOCfPYQCMkjy45P8PSyifB9
l87grQZApEm7qMdFPMq08/trVIgpHmqdG0pr8rjRR+orxmUL6CxOWGDHVp7cKJnq/MuUktnerpYa
zsLj3AL9N97pfRWU0xZ9LiX8tTZ621fU7jrlPCbiORFoxx3BgC6KYdVznrpUel7Vyi+k+co3gBII
j3aJLvzRThcnH7QhcttjOSGf7TwGXkt8HRaKWENHs4AdF5azgMa/OLi5I45uAfpdkLqrwvP7FeI6
ZXHgOLvQjOsvVn+NPyFagzf6hMcel9JBH/D/sBKtVmMTcxeiQ6K0Y7yCPwcODVfgzdwGZfAI7xcp
NITE1EG8T/3Xg89Y3RBuxh23A41aQySOeJyDEAHAvnqiPkTJM+dyaj7UMHjRggNP6Vwcvu0yUrSD
D6ll3c9gq/yZ+RnDNKTgwB5YRFIbggBz/4b8MbmbsF4vQRwRNLTAaKEoyLEJeGhFAUaym/ddRnKB
yfLy69UaiUlV4NdcWPg0nYWNxUPQ4+ctvHFpe2dNfHcoo4kKVkrNWGt7FY7AnzWSujP0tvWhXhaM
oh1QCTEMf+FbxgQUBpbhWJMeFjp6Pr2wynH5S7zz2hj9ohv8lJ3YnDlDnPavDkakijXP67aayWxn
JYL181lvKvniCLiyoVQB5+0Griad3HDBkFYdcS4wjXReRPMzTNcHeFLnlzFuUHHMeytEBlIcdTgr
udFoF1oLcdSqg6aoT3HpqHFSfftzw45IqniPqvsRxcKO9VTWh2FgKyd5C0Sa66yENGjwoyezoABh
AhHSJkPMJyI/3EQbqa6EIzKFlTNU71DEIcyVm8qLGsMK8NPmu5P9dOPMNhPHV/L6f3WOpMB7VpuE
fZW3bYw1yOwm56lEi2FovfQOe6shLvdkvVV0LDiBrSLsBFz01x38EfUdUALXUu3H4VRmLnn7MgRP
JC9sjNWdC5LYO7D452h8DGMT9FRSGlH85P978h9GHwjMYO8XiMpVhG5wTzVEDe27Y3panEl9KSCz
/PAm5UjtGi3ywc2cH1BtjsL5G/s2C8+e/hwJrMqYTtDT7XShZWTXIf2Kqu5zULPqeEU6E593VIMG
EQtdrUJr32kM5oAvReVI3wImvMBI/rtIbXd/PIuW/kqHENs0SbAP4M9H/VjcxBcabLPVyUO6PxLU
6JA/PvVYrnCz+RDo6J9YWDc2e8X8K8+Qae4TVvAMH+DHy5qiTnman6fj/RQV/oLgcqcAmSQQxDVK
w066mPxn8Dco4oKRcMJWs1j6XK7EpJdGaWALq4rBNiq+NG7AxpzUxErzsSNc4I4m4ZChEg+iVIrG
La56KLJZ6/8lfd5gY6+G6qkdPNsUMWO4vav1i9ag1pdI7xCX/rBpEx7Z38JnCnnCRuuFniWh+0yu
YlNnOksvVIcTFQx90jSwEhP+YJSgZjIIrU3R6XdraM+l0Qr2KBSQLCGEvs0wSZp8OEUvbOxbyo+P
nZ7k/re43J5N/qn/GCEZq1JR2ENAE1n5H2qdtHDup3wm6eb7tITwWFQbPrAmwSGRF8va6OKPCVtR
VyOD4CqlencORWeD9QGrWiQEOePbC2yZDuSN/szsF1UxKEiAD7L7ifGFO/lvlNnXqHSTmR8Z+1+R
ZxUE506sFmMnnvTGN8NDESkTaI+h8oboZ9bO5i3hbrZT6+i9enO1Vbgv0BdZ3TrpUVlVaYbbHuuM
K5XXEZzyo7AYrxtBiKhRVBACj8Qlpo8QAFqF9cXWhlDpZgMlB2QNGIZR3AE+DvBYF3Ddb9QifnBk
NodbHQv+y0Wfbdiz+UQkdYr7glQAf3+R7GfUlnuHFfmrYiusjPjHV29pFycByyGRHfDx0ncuyGYL
W6wrlUSjNPeAJuMFRkqD5JU6udeqgDXjp4QJTEf/azTcoswhlhwilezhCltyfImyEqu66uT7HNjl
Fh+D6yWISEcRZatnBfGQ4Oa9+Is9rUvMJlXmCgE5WGWN+QBgzWHmsml1QTHuyHFZPtcVvOyUjp4f
aZtP2W5jI+RBE2IJNNTqDK1I1s6EWCzxwY9zqOozHrqK6GFasIHd7BZ12nkNBFJHtNJKCIziSlnX
94wdiXinJTx22VOMT24vg9wa5RTDE1KEergxOlBVeexBHUBOuwhZiJ5mJNZNv5+CDQbtVMHT2eU2
yEb1I02GVBeGWcCVe70WVVag0OriQjdMQ1PU1JksEmhlpr/IPU9R9pgxZwnHhSxyGjUhzi8OhbaR
NkbXEf7dL7aWBbwCPEqp9tY182P9NktS73S8iWb3TjOwJbTBGio/qYCF9hx+0dFlAIZ7WdeRkJ0h
RddKyuC17GnR+nsmQ0u4WLIOxpNNtEHwC9LuHmFdIkx61TU1+dJBDEhSTJL8q6rO57QIyBNR+mR8
3OGzzhA0fHEhyRESof6kKJ1Yv4Wx1uUcE6kUW/RW1igEbEOD8KZO3+cT3jURspoi4M/KPFkW8gOH
S/3h7ZRulqTCQLljS6kXQNlFiOj3aFVC4HVWiK1uVdt1SapBpzYxclHy0BkV0IzfdM8SleBNDM/F
2nzxOhdC9mwr9QyKDGRfaS/Z/umejoprjfY=
`protect end_protected
| gpl-3.0 |
luebbers/reconos | core/pcores/xps_osif_v2_01_a/hdl/vhdl/xps_osif.vhd | 1 | 46708 | ------------------------------------------------------------------------------
--
-- \file xps_osif.vhd
--
-- Wrapper to connect OSIF to PLBv46
--
-- Mostly generated using Xilinx tools.
--
-- \author Enno Luebbers <[email protected]>
-- \date 11.08.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Original Xilinx header follows:
--
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: xps_osif.vhd
-- Version: 2.01.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 27 14:11:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
library osif_core_v2_01_a;
use osif_core_v2_01_a.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity xps_osif is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
-- C_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_HIGHADDR : std_logic_vector := X"00000000";
-- C_SPLB_AWIDTH : integer := 32;
-- C_SPLB_DWIDTH : integer := 128;
-- C_SPLB_NUM_MASTERS : integer := 8;
-- C_SPLB_MID_WIDTH : integer := 3;
-- C_SPLB_NATIVE_DWIDTH : integer := 32;
-- C_SPLB_P2P : integer := 0;
-- C_SPLB_SUPPORT_BURSTS : integer := 0;
-- C_SPLB_SMALLEST_MASTER : integer := 32;
-- C_SPLB_CLK_PERIOD_PS : integer := 10000;
-- C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 64;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
-- C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM1_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- burst mem interface
burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
burstWrData : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstRdData : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstWE : out std_logic;
burstBE : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
-- FIFO access signals
o_fifo_clk : out std_logic;
o_fifo_reset : out std_logic;
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic;
-- bus macro control
bmEnable : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DCR Bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0); -- chipscope
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- sys_clk : in std_logic;
-- sys_reset : in std_logic;
-- SPLB_Clk : in std_logic;
-- SPLB_Rst : in std_logic;
-- PLB_ABus : in std_logic_vector(0 to 31);
-- PLB_UABus : in std_logic_vector(0 to 31);
-- PLB_PAValid : in std_logic;
-- PLB_SAValid : in std_logic;
-- PLB_rdPrim : in std_logic;
-- PLB_wrPrim : in std_logic;
-- PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
-- PLB_abort : in std_logic;
-- PLB_busLock : in std_logic;
-- PLB_RNW : in std_logic;
-- PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
-- PLB_MSize : in std_logic_vector(0 to 1);
-- PLB_size : in std_logic_vector(0 to 3);
-- PLB_type : in std_logic_vector(0 to 2);
-- PLB_lockErr : in std_logic;
-- PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- PLB_wrBurst : in std_logic;
-- PLB_rdBurst : in std_logic;
-- PLB_wrPendReq : in std_logic;
-- PLB_rdPendReq : in std_logic;
-- PLB_wrPendPri : in std_logic_vector(0 to 1);
-- PLB_rdPendPri : in std_logic_vector(0 to 1);
-- PLB_reqPri : in std_logic_vector(0 to 1);
-- PLB_TAttribute : in std_logic_vector(0 to 15);
-- Sl_addrAck : out std_logic;
-- Sl_SSize : out std_logic_vector(0 to 1);
-- Sl_wait : out std_logic;
-- Sl_rearbitrate : out std_logic;
-- Sl_wrDAck : out std_logic;
-- Sl_wrComp : out std_logic;
-- Sl_wrBTerm : out std_logic;
-- Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- Sl_rdWdAddr : out std_logic_vector(0 to 3);
-- Sl_rdDAck : out std_logic;
-- Sl_rdComp : out std_logic;
-- Sl_rdBTerm : out std_logic;
-- Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
-- attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
-- attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity xps_osif;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of xps_osif is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
--USER_LOGIC needs this parameter
--constant BURST_BASEADDR : std_logic_vector := C_BASEADDR or X"00004000";
--constant BURST_HIGHADDR : std_logic_vector := C_BASEADDR or X"00007FFF";
--constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
--(
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR, -- user logic master space high address
--ZERO_ADDR_PAD & BURST_BASEADDR, -- user logic memory space 0 base address
--ZERO_ADDR_PAD & BURST_HIGHADDR -- user logic memory space 0 high address
--ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
--ZERO_ADDR_PAD & C_MEM1_HIGHADDR -- user logic memory space 1 high address
-- );
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
-- constant USER_MST_NUM_REG : integer := 1;
-- constant USER_NUM_REG : integer := USER_MST_NUM_REG;
-- constant USER_NUM_MEM : integer := 1;
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
--0 => pad_power2(USER_MST_NUM_REG), -- number of ce for user logic master space
-- 0 => 1
--1 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
--2 => 1 -- number of ce for user logic memory space 1 (always 1 chip enable)
-- );
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
--constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
--constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32, 64, or 128)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_DWIDTH;
------------------------------------------
-- Inhibit the automatic inculsion of the Conversion Cycle and Burst Length Expansion logic
-- 0 = allow automatic inclusion of the CC and BLE logic
-- 1 = inhibit automatic inclusion of the CC and BLE logic
------------------------------------------
constant IPIF_INHIBIT_CC_BLE_INCLUSION : integer := 0;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
--constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
--constant USER_MST_CS_INDEX : integer := 0;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
--constant USER_MEM0_CS_INDEX : integer := 1;
--constant USER_MEM0_CS_INDEX : integer := 0;
--constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
--constant USER_CE_INDEX : integer := USER_MST_CE_INDEX;
--constant USER_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- signal ipif_Bus2IP_Clk : std_logic;
-- signal ipif_Bus2IP_Reset : std_logic;
-- signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_IP2Bus_WrAck : std_logic;
-- signal ipif_IP2Bus_RdAck : std_logic;
-- signal ipif_IP2Bus_AddrAck : std_logic;
-- signal ipif_IP2Bus_Error : std_logic;
-- signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_Bus2IP_RNW : std_logic;
-- signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
-- signal ipif_Bus2IP_Burst : std_logic;
-- signal ipif_Bus2IP_BurstLength : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
-- signal ipif_Bus2IP_WrReq : std_logic;
-- signal ipif_Bus2IP_RdReq : std_logic;
-- signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
-- signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
-- signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Type : std_logic;
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_sof_n : std_logic;
signal ipif_Bus2IP_MstRd_eof_n : std_logic;
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_sof_n : std_logic;
signal ipif_IP2Bus_MstWr_eof_n : std_logic;
signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
-- signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_BurstLength : std_logic_vector(0 to 8) := (others => '0');
-- signal user_Bus2IP_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_Bus2IP_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_RdAck : std_logic;
-- signal user_IP2Bus_WrAck : std_logic;
-- signal user_IP2Bus_Error : std_logic;
signal task_clk_internal : std_logic;
signal task_reset_internal : std_logic;
-- single word data input/output
signal mem2osif_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal osif2mem_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- addresses for master transfers
signal mem_localAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
signal mem_targetAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
-- single word transfer requests
signal mem_singleRdReq : std_logic;
signal mem_singleWrReq : std_logic;
-- burst transfer requests
signal mem_burstRdReq : std_logic;
signal mem_burstWrReq : std_logic;
signal mem_burstLen : std_logic_vector(0 to 11);
-- status outputs
signal mem_busy : std_logic;
signal mem_rdDone : std_logic;
signal mem_wrDone : std_logic;
---------
-- local FIFO control and data lines
---------
signal fifomgr_read_remove : std_logic;
signal fifomgr_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_read_wait : std_logic;
signal fifomgr_write_add : std_logic;
signal fifomgr_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_write_wait : std_logic;
-- bus macro control signal
signal bmEnable_i : std_logic;
-- incoming task signals (can be disabled via bmEnable_i)
signal osif_task2os_vec_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal burstRdData_i : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
begin
---------
-- set task clock/reset
---------
task_clk <= task_clk_internal;
task_reset <= task_reset_internal;
-- propagate bus macro enable signal (COMPATIBILITY with older tool chains)
bmEnable <= bmEnable_i;
-- gate incoming task signals with bmEnable_i
gate_incoming : process(bmEnable_i, osif_task2os_vec, burstRdData)
begin
if bmEnable_i = '1' then
osif_task2os_vec_i <= osif_task2os_vec;
burstRdData_i <= burstRdData;
else
osif_task2os_vec_i <= (others => '0');
burstRdData_i <= (others => '0');
end if;
end process;
--------------------------------------
-- memory bus controller core
--
-- PLBv46
---------------------------------------
mem_plb46_i : entity xps_osif_v2_01_a.mem_plb46
generic map
(
-- Bus protocol parameters
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_AWIDTH => C_MPLB_AWIDTH,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
--C_NUM_CE => USER_MST_NUM_REG,
C_BURST_AWIDTH => C_BURST_AWIDTH
)
port map
(
clk => task_clk_internal,
reset => task_reset_internal,
-- data interface ---------------------------
-- burst mem interface
o_burstAddr => burstAddr,
o_burstData => burstWrData,
i_burstData => burstRdData_i,
o_burstWE => burstWE,
o_burstBE => burstBE,
-- single word data input/output
i_singleData => osif2mem_singleData,
o_singleData => mem2osif_singleData,
-- control interface ------------------------
-- addresses for master transfers
i_localAddr => mem_localAddr,
i_targetAddr => mem_targetAddr,
-- single word transfer requests
i_singleRdReq => mem_singleRdReq,
i_singleWrReq => mem_singleWrReq,
-- burst transfer requests
i_burstRdReq => mem_burstRdReq,
i_burstWrReq => mem_burstWrReq,
i_burstLen => mem_burstLen,
-- status outputs
o_busy => mem_busy,
o_rdDone => mem_rdDone,
o_wrDone => mem_wrDone,
-- PLBv46 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk => MPLB_Clk,
Bus2IP_Reset => MPLB_Rst,
Bus2IP_MstError => ipif_Bus2IP_Mst_Error,
Bus2IP_MstLastAck => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_MstRdAck => PLB_MRdDAck,
Bus2IP_MstWrAck => PLB_MWrDAck,
Bus2IP_MstRetry => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_MstTimeOut => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
IP2Bus_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_MstBE => ipif_IP2Bus_Mst_BE,
IP2Bus_MstBurst => ipif_IP2Bus_Mst_Type,
IP2Bus_MstBusReset => ipif_IP2Bus_Mst_Reset,
IP2Bus_MstBusLock => ipif_IP2Bus_Mst_Lock,
IP2Bus_MstNum => ipif_IP2Bus_Mst_Length,
IP2Bus_MstRdReq => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWrReq => ipif_IP2Bus_MstWr_Req,
-- Ports for Local Link
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => IPIF_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => ipif_IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Type => ipif_IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity osif_core_v2_01_a.osif_core
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => 12,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_NUM_CE => 2, --isnt used in USER_LOGIC
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => interrupt,
busy => busy,
blocking => blocking,
-- task interface
task_clk => task_clk_internal,
task_reset => task_reset_internal,
osif_os2task_vec => osif_os2task_vec,
osif_task2os_vec => osif_task2os_vec_i,
-- FIFO manager access signals
o_fifomgr_read_remove => fifomgr_read_remove,
i_fifomgr_read_data => fifomgr_read_data,
i_fifomgr_read_wait => fifomgr_read_wait,
o_fifomgr_write_add => fifomgr_write_add,
o_fifomgr_write_data => fifomgr_write_data,
i_fifomgr_write_wait => fifomgr_write_wait,
-- memory access signals
o_mem_singleData => osif2mem_singleData,
i_mem_singleData => mem2osif_singleData,
o_mem_localAddr => mem_localAddr,
o_mem_targetAddr => mem_targetAddr,
o_mem_singleRdReq => mem_singleRdReq,
o_mem_singleWrReq => mem_singleWrReq,
o_mem_burstRdReq => mem_burstRdReq,
o_mem_burstWrReq => mem_burstWrReq,
o_mem_burstLen => mem_burstLen,
i_mem_busy => mem_busy,
i_mem_rdDone => mem_rdDone,
i_mem_wrDone => mem_wrDone,
-- bus macro control
o_bm_enable => bmEnable_i,
-- MAP USER PORTS ABOVE THIS LINE ------------------
sys_clk => MPLB_Clk,--sys_clk,
sys_reset => MPLB_Rst,--sys_reset,
-- DCR Bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON
);
-----------------------------------------------------------------------
-- fifo_mgr_inst: FIFO manager instantiation
--
-- The FIFO manager handles incoming push/pop requests to the two
-- hardware FIFOs attached to the OSIF. It arbitrates between
-- local hardware-thread-initiated requests and indirect bus accesses
-- by other hardware threads.
-----------------------------------------------------------------------
fifo_mgr_inst : entity xps_osif_v2_01_a.fifo_mgr
generic map (
C_FIFO_DWIDTH => C_FIFO_DWIDTH
)
port map (
clk => sys_clk,
reset => sys_reset, -- we don't want a thread reset command to flush
-- the FIFOs, therefore no thread_reset_i!
-- local FIFO access signals
i_local_read_remove => fifomgr_read_remove,
o_local_read_data => fifomgr_read_data,
o_local_read_wait => fifomgr_read_wait,
i_local_write_add => fifomgr_write_add,
i_local_write_data => fifomgr_write_data,
o_local_write_wait => fifomgr_write_wait,
-- "real" FIFO access signals
o_fifo_read_en => o_fifo_read_en,
i_fifo_read_data => i_fifo_read_data,
i_fifo_read_ready => i_fifo_read_ready,
o_fifo_write_en => o_fifo_write_en,
o_fifo_write_data => o_fifo_write_data,
i_fifo_write_ready => i_fifo_write_ready
);
--------
-- set FIFO clock/reset
--------
o_fifo_clk <= sys_clk;
o_fifo_reset <= sys_reset;
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, user_IP2Bus_DataX ) is
-- begin
-- case ipif_Bus2IP_CS is
-- when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data & user_IP2Bus_DataX;
-- when "010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
-- end process IP2BUS_DATA_MUX_PROC;
-- user_Bus2IP_Data <= ipif_Bus2IP_Data(0 to USER_MST_DWIDTH-1);
-- user_Bus2IP_DataX <= iBus2IP_Data(USER_MST_DWIDTH to C_MPLB_DWIDTH-1);
-- ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
-- ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
-- ipif_IP2Bus_Error <= user_IP2Bus_Error;
-- user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
-- user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_pipebuf.vhd | 1 | 3869 | --------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_pipebuf
-- Architectures: lipif_pipebuf_rtl
-- Description:
-- This module provides a buffer for the acknowledge-request flow within
-- a pipeline. In effect it is a FIFO with a fixed depth of two.
--
-- Dependencies:
--
-- Revision:
-- 13.3.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_pipebuf is
generic (
C_DATA_WIDTH : integer := 64;
C_EN_SRL16 : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
-- Previous (input) stage I/O
prevReq_i : in std_logic;
prevRdy_o : out std_logic;
prevData_i : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Next (output) stage I/O
nextReq_o : out std_logic;
nextRdy_i : in std_logic;
nextData_o : out std_logic_vector(C_DATA_WIDTH-1 downto 0)
);
end lipif_mst_pipebuf;
architecture lipif_mst_pipebuf_rtl of lipif_mst_pipebuf is
-- Primary and secondary valid signals indicate if data is valid
signal valid_prim : std_logic;
signal valid_sec : std_logic;
begin
prevRdy_o <= not valid_sec;
nextReq_o <= valid_prim;
EN_SRL16: if(C_EN_SRL16) generate
signal srl_ce : std_logic;
begin
srl_ce <= prevReq_i and not valid_sec;
SRL_FIFO: for i in 0 to C_DATA_WIDTH-1 generate
SRL16E_I: SRL16E
generic map (
INIT => X"0000"
)
port map (
CLK => clk,
CE => srl_ce,
D => prevData_i(i),
Q => nextData_o(i),
A0 => valid_sec,
A1 => '0',
A2 => '0',
A3 => '0'
);
end generate SRL_FIFO;
end generate EN_SRL16;
NEN_SRL16: if(not C_EN_SRL16) generate
-- Registers for primary and secondary data
signal data_prim : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal data_prim_nxt : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal data_sec : std_logic_vector(C_DATA_WIDTH-1 downto 0);
begin
nextData_o <= data_prim;
data_prim_nxt <= data_sec when(valid_sec='1') else prevData_i;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
data_prim <= (others=>'0');
data_sec <= (others=>'0');
else
-- Handle Primary Stage
if(nextRdy_i='1' or valid_prim='0') then
data_prim <= data_prim_nxt;
end if;
-- Handle Secondary Stage
if(nextRdy_i='1' or valid_sec='0') then
data_sec <= prevData_i;
end if;
end if;
end if;
end process;
end generate NEN_SRL16;
-- Generate valid signals
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
valid_prim <= '0';
valid_sec <= '0';
else
-- Handle Primary Stage
if(nextRdy_i='1' or valid_prim='0') then
valid_prim <= valid_sec or prevReq_i;
end if;
-- Handle Secondary Stage
if(nextRdy_i='1' or valid_sec='0') then
valid_sec <= valid_prim and prevReq_i and not nextRdy_i;
end if;
end if;
end if;
end process;
end lipif_mst_pipebuf_rtl;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/TESTBENCH_ac97_core.vhd | 4 | 14282 | -------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read_strobe, reg_write_strobe : std_logic := '0';
signal reg_error : std_logic := '0';
signal reg_busy, reg_data_valid : std_logic;
signal play_left_accept, play_right_accept : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15) := (others =>'0');
signal PCM_Playback_Right: std_logic_vector(0 to 15) := (others => '0');
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
model : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Strobe => reg_read_strobe, --
AC97_Reg_Write_Strobe => reg_write_strobe, --
AC97_Reg_Busy => reg_busy, --
AC97_Reg_Error => reg_error, -- d
AC97_Reg_Read_Data_Valid => reg_data_valid, -- d
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Playback_Left_Accept => play_left_accept, -- d
PCM_Playback_Right_Accept => play_right_accept, -- d
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
CODEC_RDY => CODEC_RDY
);
-- simulate a 20 ns reset pulse
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
register_if_process: process
begin
--PCM_Playback_Right_Valid <= '0';
--PCM_Playback_Left_Valid <= '0';
reg_read_strobe <= '0';
reg_write_strobe <= '0';
reg_addr <= (others => '0');
--PCM_Playback_Left <= (others => '0');
--PCM_Playback_Right <= (others => '0');
-- wait for codec ready
test_no <= 0;
wait until CODEC_RDY='1';
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Perform a register write (to reset register)
test_no <= 1;
reg_addr <= "0000010";
reg_write_data <= X"A5A5";
wait until clk'event and clk='1';
reg_write_strobe <= '1';
wait until clk'event and clk='1';
reg_write_strobe <= '0';
reg_addr <= "0000000";
reg_write_data <= X"0000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
-- Perform a register read
test_no <= 2;
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
reg_addr <= "0000010";
wait until clk'event and clk='1';
reg_read_strobe <= '1';
wait until clk'event and clk='1';
reg_read_strobe <= '0';
reg_addr <= "0000000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
test_no <= 3;
-- -- set default values
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- test_no <= 1;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 2;
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 3;
-- -- send a read command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_read <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_read <= '0';
-- wait;
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- Test process
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
play_data_process: process
type register_type is array(0 to 31) of std_logic_vector(15 downto 0);
variable play_data : register_type := (
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000",
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000"
);
variable count : integer := 0;
begin
wait until codec_rdy = '1';
for count in 0 to 31 loop
PCM_Playback_Left <= play_data(count);
PCM_Playback_Right <= play_data(count);
wait until play_left_accept = '1' and
play_right_accept = '1' and clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
end loop;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
| gpl-3.0 |
luebbers/reconos | demos/demo_multibus_ethernet/hw/hwthreads/third/physical/v6_gtxwizard_gtx_orig.vhd | 1 | 35802 | -------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : v6_gtxwizard_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module V6_GTXWIZARD_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity V6_GTXWIZARD_GTX is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out std_logic;
RXCHARISK_OUT : out std_logic;
RXDISPERR_OUT : out std_logic;
RXNOTINTABLE_OUT : out std_logic;
RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN_IN : in std_logic;
RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(7 downto 0);
RXRECCLK_OUT : out std_logic;
RXRESET_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXELECIDLE_OUT : out std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET_IN : in std_logic;
RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE_IN : in std_logic;
TXCHARDISPVAL_IN : in std_logic;
TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(7 downto 0);
TXOUTCLK_OUT : out std_logic;
TXRESET_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end V6_GTXWIZARD_GTX;
architecture RTL of V6_GTXWIZARD_GTX is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(2 downto 0);
signal rxcharisk_float_i : std_logic_vector(2 downto 0);
signal rxdisperr_float_i : std_logic_vector(2 downto 0);
signal rxnotintable_float_i : std_logic_vector(2 downto 0);
signal rxrundisp_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(2 downto 0);
signal txrundisp_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTX Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(7 downto 0);
txdata_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);
----------------------------- GTX Instance --------------------------
gtxe1_i :GTXE1
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
TX_OVERSAMPLE_MODE => (FALSE),
TXPLL_COM_CFG => (x"21680a"),
TXPLL_CP_CFG => (x"0D"),
TXPLL_DIVSEL_FB => (2),
TXPLL_DIVSEL_OUT => (2),
TXPLL_DIVSEL_REF => (1),
TXPLL_DIVSEL45_FB => (5),
TXPLL_LKDET_CFG => ("111"),
TX_CLK25_DIVIDER => (5),
TXPLL_SATA => ("00"),
TX_TDCC_CFG => ("00"),
PMA_CAS_CLK_EN => (FALSE),
POWER_SAVE => (GTX_POWER_SAVE),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (TRUE),
TX_DATA_WIDTH => (10),
TX_USRCLK_CFG => (x"00"),
TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
TXOUTCLK_DLY => ("0000000000"),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('0'),
PMA_TX_CFG => (x"80082"),
TX_BUFFER_USE => (TRUE),
TX_BYTECLK_CFG => (x"00"),
TX_EN_RATE_RESET_BUF => (TRUE),
TX_XCLK_SEL => ("TXOUT"),
TX_DLYALIGN_CTRINC => ("0100"),
TX_DLYALIGN_LPFINC => ("0110"),
TX_DLYALIGN_MONSEL => ("000"),
TX_DLYALIGN_OVRDSETTING => ("10000000"),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC => ("000"),
TXGEARBOX_USE => (FALSE),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE => ("DIRECT"),
TX_IDLE_ASSERT_DELAY => ("101"),
TX_IDLE_DEASSERT_DELAY => ("011"),
TXDRIVE_LOOPBACK_HIZ => (FALSE),
TXDRIVE_LOOPBACK_PD => (FALSE),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL => ("1111"),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0 => ("11010"),
TX_DEEMPH_1 => ("10000"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => (FALSE),
RXPLL_COM_CFG => (x"21680a"),
RXPLL_CP_CFG => (x"0D"),
RXPLL_DIVSEL_FB => (2),
RXPLL_DIVSEL_OUT => (2),
RXPLL_DIVSEL_REF => (1),
RXPLL_DIVSEL45_FB => (5),
RXPLL_LKDET_CFG => ("111"),
RX_CLK25_DIVIDER => (5),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (TRUE),
RX_DATA_WIDTH => (10),
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV1"),
RXRECCLK_DLY => ("0000000000"),
RXUSRCLK_DLY => (x"0000"),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (TRUE),
CDR_PH_ADJ_TIME => ("10100"),
OOBDETECT_THRESHOLD => ("011"),
PMA_CDR_SCAN => (x"640404C"),
PMA_RX_CFG => (x"05ce048"),
RCV_TERM_GND => (FALSE),
RCV_TERM_VTTRX => (FALSE),
RX_EN_IDLE_HOLD_CDR => (FALSE),
RX_EN_IDLE_RESET_FR => (TRUE),
RX_EN_IDLE_RESET_PH => (TRUE),
TX_DETECT_RX_CFG => (x"1832"),
TERMINATION_CTRL => ("00000"),
TERMINATION_OVRD => (FALSE),
CM_TRIM => ("01"),
PMA_RXSYNC_CFG => (x"00"),
PMA_CFG => (x"0040000040000000003"),
BGTEST_CFG => ("00"),
BIAS_CFG => (x"00000"),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"),
DFE_CFG => ("00011011"),
RX_EN_IDLE_HOLD_DFE => (TRUE),
RX_EYE_OFFSET => (x"4C"),
RX_EYE_SCANMODE => ("00"),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (1),
COMMA_10B_ENABLE => ("0001111111"),
COMMA_DOUBLE => (FALSE),
DEC_MCOMMA_DETECT => (TRUE),
DEC_PCOMMA_DETECT => (TRUE),
DEC_VALID_COMMA_ONLY => (FALSE),
MCOMMA_10B_VALUE => ("1010000011"),
MCOMMA_DETECT => (TRUE),
PCOMMA_10B_VALUE => ("0101111100"),
PCOMMA_DETECT => (TRUE),
RX_DECODE_SEQ_MATCH => (TRUE),
RX_SLIDE_AUTO_WAIT => (5),
RX_SLIDE_MODE => ("OFF"),
SHOW_REALIGN_COMMA => (FALSE),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (1),
RX_LOS_THRESHOLD => (4),
RX_LOSS_OF_SYNC_FSM => (FALSE),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (FALSE),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (TRUE),
RX_EN_IDLE_RESET_BUF => (TRUE),
RX_EN_MODE_RESET_BUF => (TRUE),
RX_EN_RATE_RESET_BUF => (TRUE),
RX_EN_REALIGN_RESET_BUF => (FALSE),
RX_EN_REALIGN_RESET_BUF2 => (FALSE),
RX_FIFO_ADDR_MODE => ("FULL"),
RX_IDLE_HI_CNT => ("1000"),
RX_IDLE_LO_CNT => ("0000"),
RX_XCLK_SEL => ("RXREC"),
RX_DLYALIGN_CTRINC => ("0100"),
RX_DLYALIGN_EDGESET => ("00010"),
RX_DLYALIGN_LPFINC => ("0110"),
RX_DLYALIGN_MONSEL => ("000"),
RX_DLYALIGN_OVRDSETTING => ("10000000"),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN => (2),
CLK_COR_DET_LEN => (2),
CLK_COR_INSERT_IDLE_FLAG => (FALSE),
CLK_COR_KEEP_IDLE => (FALSE),
CLK_COR_MAX_LAT => (18),
CLK_COR_MIN_LAT => (14),
CLK_COR_PRECEDENCE => (TRUE),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_1_1 => ("0110111100"),
CLK_COR_SEQ_1_2 => ("0001010000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0110111100"),
CLK_COR_SEQ_2_2 => ("0010110101"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_USE => (TRUE),
CLK_CORRECT_USE => (TRUE),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW => (1),
CHAN_BOND_2_MAX_SKEW => (1),
CHAN_BOND_KEEP_ALIGN => (FALSE),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_CFG => ("00000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => (FALSE),
CHAN_BOND_SEQ_LEN => (1),
PCI_EXPRESS_MODE => (FALSE),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS => (52),
SAS_MIN_COMSAS => (40),
SATA_BURST_VAL => ("100"),
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"),
TRANS_TIME_RATE => (x"ff"),
TRANS_TIME_TO_P2 => (x"064")
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => LOOPBACK_IN,
RXPOWERDOWN => RXPOWERDOWN_IN,
TXPOWERDOWN => TXPOWERDOWN_IN,
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open,
RXGEARBOXSLIP => tied_to_ground_i,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA(3 downto 1) => rxchariscomma_float_i,
RXCHARISCOMMA(0) => RXCHARISCOMMA_OUT,
RXCHARISK(3 downto 1) => rxcharisk_float_i,
RXCHARISK(0) => RXCHARISK_OUT,
RXDEC8B10BUSE => tied_to_vcc_i,
RXDISPERR(3 downto 1) => rxdisperr_float_i,
RXDISPERR(0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 1) => rxnotintable_float_i,
RXNOTINTABLE(0) => RXNOTINTABLE_OUT,
RXRUNDISP(3 downto 1) => rxrundisp_float_i,
RXRUNDISP(0) => RXRUNDISP_OUT,
USRCODEERR => tied_to_ground_i,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open,
RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
RXENCHANSYNC => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => RXCLKCORCNT_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCOMMADET => open,
RXCOMMADETUSE => tied_to_vcc_i,
RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN,
RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN,
RXSLIDE => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i,
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => rxdata_i,
RXRECCLK => RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => RXRESET_IN,
RXUSRCLK => tied_to_ground_i,
RXUSRCLK2 => RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMON => open,
DFEDLYOVRD => tied_to_vcc_i,
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => tied_to_vcc_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_ground_i,
IGNORESIGDET => tied_to_ground_i,
RXCDRRESET => tied_to_ground_i,
RXELECIDLE => RXELECIDLE_OUT,
RXEQMIX => "0000000111",
RXN => RXN_IN,
RXP => RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => RXBUFRESET_IN,
RXBUFSTATUS => RXBUFSTATUS_OUT,
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
RXDLYALIGNDISABLE => tied_to_ground_i,
RXDLYALIGNMONENB => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => tied_to_ground_i,
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
RXDLYALIGNUPDSW => tied_to_ground_i,
RXENPMAPHASEALIGN => tied_to_ground_i,
RXPMASETPHASE => tied_to_ground_i,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i,
RXOVERSAMPLEERR => open,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => tied_to_ground_i,
GTXRXRESET => GTXRXRESET_IN,
MGTREFCLKRX => MGTREFCLKRX_IN,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
PERFCLKRX => tied_to_ground_i,
PLLRXRESET => PLLRXRESET_IN,
RXPLLLKDET => RXPLLLKDET_OUT,
RXPLLLKDETEN => tied_to_vcc_i,
RXPLLPOWERDOWN => tied_to_ground_i,
RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
RXRATE => tied_to_ground_vec_i(1 downto 0),
RXRATEDONE => open,
RXRESETDONE => RXRESETDONE_OUT,
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS => open,
RXVALID => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPMODE(0) => TXCHARDISPMODE_IN,
TXCHARDISPVAL(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL(0) => TXCHARDISPVAL_IN,
TXCHARISK(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK(0) => TXCHARISK_IN,
TXENC8B10BUSE => tied_to_vcc_i,
TXKERR => open,
TXRUNDISP => open,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => "1000000000000",
MGTREFCLKFAB => open,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN => "11111111111111111111",
TSTOUT => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKPCS => open,
TXRESET => TXRESET_IN,
TXUSRCLK => tied_to_ground_i,
TXUSRCLK2 => TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100",
TXDIFFCTRL => "0000",
TXINHIBIT => tied_to_ground_i,
TXN => TXN_OUT,
TXP => TXP_OUT,
TXPOSTEMPHASIS => "00000",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => "0000",
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => TXBUFSTATUS_OUT,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => tied_to_vcc_i,
TXDLYALIGNMONENB => tied_to_ground_i,
TXDLYALIGNMONITOR => open,
TXDLYALIGNOVERRIDE => tied_to_ground_i,
TXDLYALIGNRESET => tied_to_ground_i,
TXDLYALIGNUPDSW => tied_to_vcc_i,
TXENPMAPHASEALIGN => tied_to_ground_i,
TXPMASETPHASE => tied_to_ground_i,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => tied_to_ground_i,
GTXTXRESET => GTXTXRESET_IN,
MGTREFCLKTX => MGTREFCLKTX_IN,
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PERFCLKTX => tied_to_ground_i,
PLLTXRESET => PLLTXRESET_IN,
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TXPLLLKDET => TXPLLLKDET_OUT,
TXPLLLKDETEN => tied_to_vcc_i,
TXPLLPOWERDOWN => tied_to_ground_i,
TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(1 downto 0),
TXRATEDONE => open,
TXRESETDONE => TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH => tied_to_ground_i,
TXDETECTRX => tied_to_ground_i,
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXPDOWNASYNCH => tied_to_ground_i,
TXSWING => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i
);
end RTL;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_fifo.vhd | 4 | 12653 | -------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_fifo.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-- TESTBENCH_ac97_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_fifo.vhd
--
-- Description: Simple testbench for ac97_fifo
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_fifo is
end TESTBENCH_ac97_fifo;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_fifo is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
-- IP Interface
signal Bus2IP_Addr : std_logic_vector(0 to 31);
signal Bus2IP_Clk : std_logic;
signal Bus2IP_CS : std_logic;
signal Bus2IP_Data : std_logic_vector(0 to 31);
signal Bus2IP_BE : std_logic_vector(0 to 3);
signal Bus2IP_RdCE : std_logic;
signal Bus2IP_Reset : std_logic;
signal Bus2IP_WrCE : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal Interrupt : std_logic;
signal Bit_Clk : std_logic;
signal Sync : std_logic;
signal SData_Out : std_logic;
signal SData_In : std_logic;
signal AC97Reset_n : std_logic;
signal test_no : integer;
signal IP_READ : std_logic_vector(0 to 31);
signal sample : integer := 0;
begin -- behavioral
uut_1 : ac97_model
port map (
AC97Reset_n => ac97reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut : ac97_fifo
generic map (
C_INTR_LEVEL => 1,
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
Interrupt => Interrupt,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
clkgen_2: process
begin
Bus2IP_Clk<= '0';
wait for 5 ns;
Bus2IP_Clk<= '1';
wait for 5 ns;
end process;
-- simulate a reset
opb_rst_gen: process
begin
Bus2IP_Reset <= '1';
wait for 20 ns;
Bus2IP_Reset <= '0';
wait;
end process opb_rst_gen;
-- IP bus
IP_proc: process
begin
test_no <= 0;
Bus2IP_RdCE <= '0';
Bus2IP_WrCE <= '0';
Bus2IP_CS <= '0';
Bus2IP_ADDR <= (others => '0');
Bus2IP_DATA <= (others => '0');
IP_READ <= (others => '0');
-- skip some time slots before performing a bus cycle
for i in 100 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
-- Test 7. Reset CODEC
test_no <= 7;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000010", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000000", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Test 1. Wait until codec ready is found (ready status)
test_no <= 1;
while IP_READ(26) /= '1' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
for i in 50 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
end loop;
-- Test #2: Clear FIFO status & read status again
test_no <= 2;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #6: Write data into playback fifo
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 6;
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
-- Test #3: Read AC 97 register
wait until sync'event and sync='1';
test_no <= 3;
-- Write to AC97_CTRL_ADDR (perform a AC97 "read")
-- Address = "41" (lower 7 bits)
-- Read = 1 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_00C1", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- read from the status register until transfer is complete
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Now read the value of the data register returned
read_ip(Bus2IP_Clk, IP2Bus_Data, REG_DATA_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #4: Write AC 97 register
for i in 128 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 4;
write_ip(Bus2IP_Clk, REG_DATA_WRITE_OFFSET, X"0000_8001",
Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Write to AC97_CTRL_ADDR (perform a AC97 "write")
-- Address = "41" (lower 7 bits)
-- Read = 0 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_0041", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Test #5: Read Playback data
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 5;
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #8 - Interrupt
test_no <= 8;
-- Clear FIFO & read status
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Fill FIFO
for i in 512 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
-- Enable interrupts
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, ENABLE_PLAY_INT_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Wait until an interrupt occurs
wait until Interrupt'event and Interrupt = '1';
-- Wait for a few more samples
for i in 3 downto 0 loop
wait until sync'event and sync='1';
end loop;
-- Put some more data into the Fifo and make sure the interrupt goes away
for i in 8 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
wait;
end process;
end behavioral;
| gpl-3.0 |
luebbers/reconos | demos/sort_demo_inv_pr/hw/sort8k/sort8k.vhd | 3 | 6182 | --
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8k is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8k;
architecture Behavioral of sort8k is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/sim/c_sub.vhd | 4 | 5274 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0;
USE c_addsub_v12_0.c_addsub_v12_0;
ENTITY c_sub IS
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END c_sub;
ARCHITECTURE c_sub_arch OF c_sub IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF c_sub_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 15,
C_B_WIDTH => 15,
C_OUT_WIDTH => 15,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 1,
C_B_CONSTANT => 0,
C_B_VALUE => "000000000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END c_sub_arch;
| gpl-3.0 |
luebbers/reconos | demos/particle_filter_framework/hw/src/framework/observation.vhd | 1 | 41201 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- CHANGE 1 OF 7
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input/measurement data address
input_data_address : in std_logic_vector(0 to 31);
-- get data block
get_data_needed : out std_logic;
get_data_address : out std_logic_vector(0 to 31);
get_data_length : out integer;
-- receive data block
receive_data_en : in std_logic;
receive_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- recieved data
receive_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_READ_NEXT_PARTICLE,
STATE_READ_NEXT_PARTICLE_2,
STATE_READ_NEXT_PARTICLE_3,
STATE_READ_NEXT_PARTICLE_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_DATA,
STATE_GET_DATA_2,
STATE_GET_DATA_3,
STATE_GET_DATA_4,
STATE_GET_DATA_5,
STATE_GET_DATA_6,
STATE_GET_DATA_ACK,
STATE_GET_DATA_ACK_2,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2 );
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
--signal local_ram_cache_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := "00000000000000000001111110000000";
--signal local_ram_cache_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "11111100000";
signal local_ram_address_part_1_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "00000000000";
signal local_ram_address_part_2_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "10000000000";
signal local_ram_address_current_part_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "10000000000";
--signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 64;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- counter for particle data
signal counter : integer := 0;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data length
signal get_data_length : integer := 0;
-- input data needed signal
signal get_data_needed : std_logic := '0';
-- word data address
signal get_data_address : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- word data enable
signal receive_data_en : std_logic := '0';
-- word address
signal receive_data_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- word_ack
signal receive_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
-- number of get data bursts
signal number_of_data_bursts : integer := 0;
-- length of last get data burst
signal length_of_last_data_burst : integer := 0;
-- data burst counter
signal data_burst_counter : integer := 0;
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- -- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, get_data_needed=>get_data_needed,
get_data_address=>get_data_address, get_data_length=>get_data_length,
receive_data_en=>receive_data_en, receive_data_address=>receive_data_address,
receive_data_ack=>receive_data_ack,
init=>init, enable=>enable, finished=>finished);
-- -- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_TASK_BURST_AWIDTH-1);
--
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
--
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- 1) read data from information struct + load parameter
--
-- 2) receive message m
--
-- 3) set current address for input data
--
-- 4) load current particle (into local rahttp://www.eintracht.de/aktuell/m, starting address (others=>'0'))
--
-- 5) start user process for observation extraction
--
-- 6) wait for finished signal of user process
--
-- 7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- 8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- 9) send message m
--
-- 9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--variable get_data_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_data_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
enable <= '0';
parameter_loaded <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
new_particle <= '0';
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
state <= STATE_LENGTH_LAST_BURST;
when STATE_LENGTH_LAST_BURST =>
--! calculate number of reads (1 of 2)
length_of_last_burst <= observation_size mod 128;
state <= STATE_LENGTH_LAST_BURST_2;
when STATE_LENGTH_LAST_BURST_2 =>
--! calculate number of reads (2 of 2)
length_of_last_burst <= length_of_last_burst / 8;
state <= STATE_READ_OBSERVATION_ARRAY_ADDRESS;
when STATE_READ_OBSERVATION_ARRAY_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_INPUT_DATA_LINK_ADDRESS;
end if;
when STATE_READ_INPUT_DATA_LINK_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
state <= STATE_READ_PARAMETER_SIZE;
end if;
when STATE_READ_PARAMETER_SIZE =>
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= STATE_COPY_PARAMETER;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_PARAMETER =>
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
state <= STATE_COPY_PARAMETER_ACK;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when STATE_COPY_PARAMETER_2 =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= STATE_COPY_PARAMETER;
when STATE_COPY_PARAMETER_ACK =>
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
state <= STATE_WAIT_FOR_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
parameter_loaded <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= STATE_READ_INPUT_DATA_ADDRESS;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_INPUT_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
state <= STATE_READ_NEXT_PARTICLE;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= STATE_READ_NEXT_PARTICLE;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_NEXT_PARTICLE =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
counter <= particle_size / 4;
local_ram_address_if <= local_ram_start_address_if;
state <= STATE_READ_NEXT_PARTICLE_2;
when STATE_READ_NEXT_PARTICLE_2 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
o_RAMWEObservation <= '0';
if (counter > 0) then
state <= STATE_READ_NEXT_PARTICLE_3;
counter <= counter - 1;
else
state <= STATE_START_EXTRACT_OBSERVATION;
end if;
when STATE_READ_NEXT_PARTICLE_3 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
reconos_read (done, o_osif, i_osif, particle_array_address, particle_data_var);
if done then
state <= STATE_READ_NEXT_PARTICLE_4;
particle_data <= TO_INTEGER(SIGNED(particle_data_var));
particle_array_address <= particle_array_address + 4;
end if;
when STATE_READ_NEXT_PARTICLE_4 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
o_RAMDataObservation <= STD_LOGIC_VECTOR(TO_SIGNED(particle_data, 32));
state <= STATE_READ_NEXT_PARTICLE_2;
-- when STATE_READ_NEXT_PARTICLE =>
-- --! read next particle to local ram (writing the first 128 bytes to the local ram)
-- reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, particle_array_address);
-- if done then
-- particle_array_address <= particle_array_address + particle_size;
-- state <= STATE_START_EXTRACT_OBSERVATION;
-- end if;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_START_EXTRACT_OBSERVATION =>
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= STATE_START_EXTRACT_OBSERVATION_WAIT;
when STATE_START_EXTRACT_OBSERVATION_WAIT =>
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_EXTRACT_OBSERVATION =>
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= STATE_WRITE_OBSERVATION;
elsif get_data_needed = '1' then
state <= STATE_GET_DATA;
end if;
when STATE_GET_DATA =>
--! calculate number of full bursts and length of last bursts
number_of_data_bursts <= get_data_length / 4;
state <= STATE_GET_DATA_2;
when STATE_GET_DATA_2 =>
--! calculate number of full bursts and length of last bursts
if (local_ram_address_current_part_if = local_ram_address_part_1_if) then
local_ram_address <= local_ram_start_address + 4096;
local_ram_address_if <= local_ram_address_part_2_if;
local_ram_address_current_part_if <= local_ram_address_part_2_if;
else
local_ram_address <= local_ram_start_address;
local_ram_address_if <= local_ram_address_part_1_if;
local_ram_address_current_part_if <= local_ram_address_part_1_if;
end if;
--number_of_data_bursts <= number_of_data_bursts + 2;
current_address <= get_data_address;
state <= STATE_GET_DATA_3;
when STATE_GET_DATA_3 =>
--! calculate number of full bursts and length of last bursts
o_RAMWEObservation <= '0';
enable <= '1';
if (number_of_data_bursts > 0) then
state <= STATE_GET_DATA_4;
number_of_data_bursts <= number_of_data_bursts - 1;
else
state <= STATE_GET_DATA_ACK;
end if;
when STATE_GET_DATA_4 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
reconos_read_s (done, o_osif, i_osif, current_address, ram_data);
if done then
state <= STATE_GET_DATA_5;
current_address <= current_address + 4;
end if;
when STATE_GET_DATA_5 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
o_RAMDataObservation <= ram_data;
state <= STATE_GET_DATA_3;
when STATE_GET_DATA_ACK =>
--! wait for acknowledgement
receive_data_en <= '1';
receive_data_address <= local_ram_address_current_part_if;
enable <= '1';
state <= STATE_GET_DATA_ACK_2;
when STATE_GET_DATA_ACK_2 =>
--! wait for acknowledgement
if receive_data_ack = '1' then
receive_data_en <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- when STATE_GET_DATA =>
-- --! calculate number of full bursts and length of last bursts
-- number_of_data_bursts <= get_data_length / 128;
-- length_of_last_data_burst <= get_data_length mod 128;
-- state <= STATE_GET_DATA_2;
--
--
-- when STATE_GET_DATA_2 =>
-- --! calculate number of full bursts and length of last bursts
-- if (length_of_last_data_burst > 0) then
-- length_of_last_data_burst <= length_of_last_data_burst + 8;
-- end if;
-- if (local_ram_address_current_part_if = local_ram_address_part_1_if) then
-- local_ram_address <= local_ram_start_address + 4096;
-- local_ram_address_current_part_if <= local_ram_address_part_2_if;
-- else
-- local_ram_address <= local_ram_start_address;
-- local_ram_address_current_part_if <= local_ram_address_part_1_if;
-- end if;
-- state <= STATE_GET_DATA_3;
--
--
-- when STATE_GET_DATA_3 =>
-- --! calculate number of full bursts and length of last bursts
-- length_of_last_data_burst <= length_of_last_data_burst / 8;
-- data_burst_counter <= 0;
-- if (get_data_address(29) = '0') then
-- -- double word aligned address
-- current_address <= get_data_address;
-- receive_data_address <= local_ram_address_current_part_if;
-- else
-- -- no double aligned address (=> change it)
-- current_address <= get_data_address - 4;
-- receive_data_address <= local_ram_address_current_part_if + 1;
-- end if;
-- state <= STATE_GET_DATA_4;
--
--
-- when STATE_GET_DATA_4 =>
-- --! read full data burst / last data burst
-- if (data_burst_counter < number_of_data_bursts) then
-- state <= STATE_GET_DATA_5;
-- data_burst_counter <= data_burst_counter + 1;
-- else
-- if (length_of_last_data_burst > 0) then
-- state <= STATE_GET_DATA_6;
-- else
-- state <= STATE_GET_DATA_ACK;
-- end if;
-- end if;
--
--
-- when STATE_GET_DATA_5 =>
-- --! read full data burst
-- reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_address);
-- if done then
-- current_address <= current_address + 128;
-- local_ram_address <= local_ram_address + 128;
-- state <= STATE_GET_DATA_4;
-- end if;
--
--
-- when STATE_GET_DATA_6 =>
-- --! read last data burst (with defined length)
-- reconos_read_burst_l(done, o_osif, i_osif, local_ram_address, current_address, length_of_last_data_burst);
-- if done then
-- state <= STATE_GET_DATA_ACK;
-- end if;
--
--
-- when STATE_GET_DATA_ACK =>
-- --! wait for acknowledgement
-- receive_data_en <= '1';
-- state <= STATE_GET_DATA_ACK_2;
--
-- when STATE_GET_DATA_ACK_2 =>
-- --! wait for acknowledgement
-- if receive_data_ack = '1' then
-- receive_data_en <= '0';
-- state <= STATE_EXTRACT_OBSERVATION;
-- end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WRITE_OBSERVATION =>
--! write observation (init)
number_of_bursts <= number_of_bursts_remember;
local_ram_address <= local_ram_start_address;
--write_histo_en <= '1';
state <= STATE_WRITE_OBSERVATION_2;
when STATE_WRITE_OBSERVATION_2 =>
--! write observation (check burst number)
if number_of_bursts > 0 then
-- more full bursts needed
state <= STATE_WRITE_OBSERVATION_3;
number_of_bursts <= number_of_bursts - 1;
elsif length_of_last_burst > 0 then
-- last burst needed (not full)
temp4 <= length_of_last_burst * 8;
state <= STATE_WRITE_OBSERVATION_4;
else
-- no last burst needed (which is not full)
state <= STATE_MORE_PARTICLES;
end if;
when STATE_WRITE_OBSERVATION_3 =>
--! write observation (write bursts)
reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
if done then
observation_array_address <= observation_array_address + 128;
local_ram_address <= local_ram_address + 128;
state <= STATE_WRITE_OBSERVATION_2;
end if;
when STATE_WRITE_OBSERVATION_4 =>
--! write observation (write last burst)
reconos_write_burst_l(done, o_osif, i_osif, local_ram_address, observation_array_address, length_of_last_burst);
if done then
state <= STATE_MORE_PARTICLES;
observation_array_address <= observation_array_address + temp4;
local_ram_address <= local_ram_address + temp4;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_MORE_PARTICLES =>
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= STATE_MORE_PARTICLES_2;
enable <= '0';
when STATE_MORE_PARTICLES_2 =>
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= STATE_READ_NEXT_PARTICLE;
else
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
state <= STATE_SEND_MEASUREMENT_1;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
if (time_start < time_stop) then
time_measurement <= time_stop - time_start;
state <= STATE_SEND_MEASUREMENT_2;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
if (done and success) then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | support/threads/shared/rank_filter3x3.vhd | 1 | 3179 | --
-- \file rank_filter3x3.vhd
--
-- Configurable 3x3 rank filter
--
-- \author Andreas Agne <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rank_filter3x3 is
Port (
shift_in : in STD_LOGIC_VECTOR (23 downto 0);
shift_out : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
ien : in std_logic;
rst : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture Behavioral of rank_filter3x3 is
signal row_a : std_logic_vector(23 downto 0);
signal row_b : std_logic_vector(23 downto 0);
signal row_c : std_logic_vector(23 downto 0);
signal pixels : std_logic_vector(71 downto 0); -- 9 pixels x 8 bit
-- instant sorting
function get_pixel( pixels : std_logic_vector(71 downto 0);
rank : std_logic_vector(3 downto 0)) return std_logic_vector
is
variable s : std_logic_vector(3 downto 0);
variable pixel_j : std_logic_vector(7 downto 0);
variable pixel_k : std_logic_vector(7 downto 0);
begin
for j in 0 to 8 loop -- for each pixel j
s := X"0";
pixel_j := pixels(j*8 + 7 downto j*8);
for k in 0 to 8 loop -- for each pixel k
pixel_k := pixels(k*8 + 7 downto k*8);
if k < j and pixel_k >= pixel_j then
s := s + 1;
elsif k > j and pixel_k > pixel_j then
s := s + 1;
end if;
end loop;
if s = rank then
return pixel_j;
end if;
end loop;
return X"00";
end function;
begin
pixels <= row_a & row_b & row_c;
shift : process(clk, rst)
begin
if rst = '1' then
row_a <= (others => '0');
row_b <= (others => '0');
row_c <= (others => '0');
elsif rising_edge(clk) then
if ien = '1' then
row_a <= shift_in;
row_b <= row_a;
row_c <= row_b;
end if;
shift_out <= get_pixel(pixels, rank);
end if;
end process;
end Behavioral;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBDCFIFO36x16DR/synth/DPBDCFIFO36x16DR.vhd | 8 | 38573 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBDCFIFO36x16DR IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END DPBDCFIFO36x16DR;
ARCHITECTURE DPBDCFIFO36x16DR_arch OF DPBDCFIFO36x16DR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DPBDCFIFO36x16DR_arch : ARCHITECTURE IS "DPBDCFIFO36x16DR,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "DPBDCFIFO36x16DR,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=36,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=36,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=3,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 36,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 36,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 3,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBDCFIFO36x16DR_arch;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_core.vhd | 7 | 24894 | -------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
| gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/User_Demo/src/hdl/Dbncr.vhd | 1 | 2323 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:11:29 03/06/2013
-- Design Name:
-- Module Name: dbncr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents a debouncer and is used to synchronize with the system clock
-- and remove glitches from the incoming button signals
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Dbncr is
generic(
NR_OF_CLKS : integer := 4095 -- Number of System Clock periods while the incoming signal
); -- has to be stable until a one-shot output signal is generated
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic
);
end Dbncr;
architecture Behavioral of Dbncr is
signal cnt : integer range 0 to NR_OF_CLKS-1;
signal sigTmp : std_logic;
signal stble, stbleTmp : std_logic;
begin
DEB: process(clk_i)
begin
if rising_edge(clk_i) then
if sig_i = sigTmp then -- Count the number of clock periods if the signal is stable
if cnt = NR_OF_CLKS-1 then
stble <= sig_i;
else
cnt <= cnt + 1;
end if;
else -- Reset counter and sample the new signal value
cnt <= 0;
sigTmp <= sig_i;
end if;
end if;
end process DEB;
PLS: process(clk_i)
begin
if rising_edge(clk_i) then
stbleTmp <= stble;
end if;
end process PLS;
-- generate the one-shot output signal
pls_o <= '1' when stbleTmp = '0' and stble = '1' else '0';
end Behavioral;
| gpl-3.0 |
luebbers/reconos | demos/demo_multibus_ethernet/hw/hwthreads/third/v6_emac_v1_4_block.vhd | 1 | 22232 | -------------------------------------------------------------------------------
-- Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_emac_v1_4_block.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is the block-level wrapper for the Virtex-6 Embedded
-- Tri-Mode Ethernet MAC. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a hardware test environment.
--
-- The block-level wrapper:
--
-- * instantiates appropriate PHY interface modules (GMII, MII,
-- RGMII, SGMII or 1000BASE-X) as required per the user
-- configuration;
--
-- * instantiates some clocking and reset resources to operate
-- the EMAC and its example design.
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
-- further information.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity declaration for the block-level wrapper
-------------------------------------------------------------------------------
entity v6_emac_v1_4_block is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- Client receiver interface
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
-- Auto-Negotiation interrupt
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end v6_emac_v1_4_block;
architecture TOP_LEVEL of v6_emac_v1_4_block is
-------------------------------------------------------------------------------
-- Component declarations for lower hierarchial level entities
-------------------------------------------------------------------------------
-- Component declaration for the primitive-level EMAC wrapper
component v6_emac_v1_4 is
port(
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT : out std_logic;
CLIENTEMACRXCLIENTCLKIN : in std_logic;
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXDVLDMSW : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT : out std_logic;
CLIENTEMACTXCLIENTCLKIN : in std_logic;
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
CLIENTEMACTXDVLDMSW : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- Clock signals
GTX_CLK : in std_logic;
PHYEMACTXGMIIMIICLKIN : in std_logic;
EMACPHYTXGMIIMIICLKOUT : out std_logic;
-- SGMII interface
RXDATA : in std_logic_vector(7 downto 0);
TXDATA : out std_logic_vector(7 downto 0);
MMCM_LOCKED : in std_logic;
AN_INTERRUPT : out std_logic;
SIGNAL_DETECT : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
ENCOMMAALIGN : out std_logic;
LOOPBACKMSB : out std_logic;
MGTRXRESET : out std_logic;
MGTTXRESET : out std_logic;
POWERDOWN : out std_logic;
SYNCACQSTATUS : out std_logic;
RXCLKCORCNT : in std_logic_vector(2 downto 0);
RXBUFSTATUS : in std_logic;
RXCHARISCOMMA : in std_logic;
RXCHARISK : in std_logic;
RXDISPERR : in std_logic;
RXNOTINTABLE : in std_logic;
RXREALIGN : in std_logic;
RXRUNDISP : in std_logic;
TXBUFERR : in std_logic;
TXCHARDISPMODE : out std_logic;
TXCHARDISPVAL : out std_logic;
TXCHARISK : out std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the GTX wrapper
component v6_gtxwizard_top
port (
RESETDONE : out std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic;
POWERDOWN : in std_logic;
RXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXCHARDISPMODE : in std_logic;
TXCHARDISPVAL : in std_logic;
TXCHARISK : in std_logic;
TXDATA : in std_logic_vector (7 downto 0);
TXUSRCLK2 : in std_logic;
TXRESET : in std_logic;
RXCHARISCOMMA : out std_logic;
RXCHARISK : out std_logic;
RXCLKCORCNT : out std_logic_vector (2 downto 0);
RXDATA : out std_logic_vector (7 downto 0);
RXDISPERR : out std_logic;
RXNOTINTABLE : out std_logic;
RXRUNDISP : out std_logic;
RXBUFERR : out std_logic;
TXBUFERR : out std_logic;
PLLLKDET : out std_logic;
TXOUTCLK : out std_logic;
RXELECIDLE : out std_logic;
TXN : out std_logic;
TXP : out std_logic;
RXN : in std_logic;
RXP : in std_logic;
CLK_DS : in std_logic;
PMARESET : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
-- Power and ground signals
signal gnd_i : std_logic;
signal vcc_i : std_logic;
-- Asynchronous reset signals
signal reset_ibuf_i : std_logic;
signal reset_i : std_logic;
signal reset_r : std_logic_vector(3 downto 0);
-- Client clocking signals
signal rx_client_clk_out_i : std_logic;
signal rx_client_clk_in_i : std_logic;
signal tx_client_clk_out_i : std_logic;
signal tx_client_clk_in_i : std_logic;
-- Physical interface signals
signal emac_locked_i : std_logic;
signal mgt_rx_data_i : std_logic_vector(7 downto 0);
signal mgt_tx_data_i : std_logic_vector(7 downto 0);
signal signal_detect_i : std_logic;
signal elecidle_i : std_logic;
signal resetdone_i : std_logic;
signal encommaalign_i : std_logic;
signal loopback_i : std_logic;
signal mgt_rx_reset_i : std_logic;
signal mgt_tx_reset_i : std_logic;
signal powerdown_i : std_logic;
signal rxclkcorcnt_i : std_logic_vector(2 downto 0);
signal rxchariscomma_i : std_logic;
signal rxcharisk_i : std_logic;
signal rxdisperr_i : std_logic;
signal rxnotintable_i : std_logic;
signal rxrundisp_i : std_logic;
signal txbuferr_i : std_logic;
signal txchardispmode_i : std_logic;
signal txchardispval_i : std_logic;
signal txcharisk_i : std_logic;
signal gtx_clk_ibufg_i : std_logic;
signal rxbufstatus_i : std_logic;
signal rxchariscomma_r : std_logic;
signal rxcharisk_r : std_logic;
signal rxclkcorcnt_r : std_logic_vector(2 downto 0);
signal mgt_rx_data_r : std_logic_vector(7 downto 0);
signal rxdisperr_r : std_logic;
signal rxnotintable_r : std_logic;
signal rxrundisp_r : std_logic;
signal txchardispmode_r : std_logic;
signal txchardispval_r : std_logic;
signal txcharisk_r : std_logic;
signal mgt_tx_data_r : std_logic_vector(7 downto 0);
-- Transceiver clocking signals
signal usrclk2 : std_logic;
signal txoutclk : std_logic;
signal plllock_i : std_logic;
-------------------------------------------------------------------------------
-- Attribute declarations
-------------------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_r : signal is "TRUE";
-------------------------------------------------------------------------------
-- Main body of code
-------------------------------------------------------------------------------
begin
gnd_i <= '0';
vcc_i <= '1';
---------------------------------------------------------------------------
-- Main reset circuitry
---------------------------------------------------------------------------
reset_ibuf_i <= RESET;
-- Synchronize and extend the external reset signal
process(usrclk2, reset_ibuf_i)
begin
if (reset_ibuf_i = '1') then
reset_r <= "1111";
elsif usrclk2'event and usrclk2 = '1' then
if (plllock_i = '1') then
reset_r <= reset_r(2 downto 0) & reset_ibuf_i;
end if;
end if;
end process;
-- Apply the extended reset pulse to the EMAC
reset_i <= reset_r(3);
---------------------------------------------------------------------------
-- Instantiate GTX for SGMII or 1000BASE-X PCS/PMA physical interface
---------------------------------------------------------------------------
v6_gtxwizard_top_inst : v6_gtxwizard_top
PORT MAP (
RESETDONE => resetdone_i,
ENMCOMMAALIGN => encommaalign_i,
ENPCOMMAALIGN => encommaalign_i,
LOOPBACK => loopback_i,
POWERDOWN => powerdown_i,
RXUSRCLK2 => usrclk2,
RXRESET => mgt_rx_reset_i,
TXCHARDISPMODE => txchardispmode_r,
TXCHARDISPVAL => txchardispval_r,
TXCHARISK => txcharisk_r,
TXDATA => mgt_tx_data_r,
TXUSRCLK2 => usrclk2,
TXRESET => mgt_tx_reset_i,
RXCHARISCOMMA => rxchariscomma_i,
RXCHARISK => rxcharisk_i,
RXCLKCORCNT => rxclkcorcnt_i,
RXDATA => mgt_rx_data_i,
RXDISPERR => rxdisperr_i,
RXNOTINTABLE => rxnotintable_i,
RXRUNDISP => rxrundisp_i,
RXBUFERR => rxbufstatus_i,
TXBUFERR => txbuferr_i,
PLLLKDET => plllock_i,
TXOUTCLK => txoutclk,
RXELECIDLE => elecidle_i,
TXN => TXN,
TXP => TXP,
RXN => RXN,
RXP => RXP,
CLK_DS => CLK_DS,
PMARESET => reset_ibuf_i
);
RESETDONE <= resetdone_i;
--------------------------------------------------------------------------
-- Register the signals between EMAC and transceiver for timing purposes
--------------------------------------------------------------------------
regrx : process (usrclk2, reset_i)
begin
if reset_i = '1' then
rxchariscomma_r <= '0';
rxcharisk_r <= '0';
rxclkcorcnt_r <= (others => '0');
mgt_rx_data_r <= (others => '0');
rxdisperr_r <= '0';
rxnotintable_r <= '0';
rxrundisp_r <= '0';
txchardispmode_r <= '0';
txchardispval_r <= '0';
txcharisk_r <= '0';
mgt_tx_data_r <= (others => '0');
elsif usrclk2'event and usrclk2 = '1' then
rxchariscomma_r <= rxchariscomma_i;
rxcharisk_r <= rxcharisk_i;
rxclkcorcnt_r <= rxclkcorcnt_i;
mgt_rx_data_r <= mgt_rx_data_i;
rxdisperr_r <= rxdisperr_i;
rxnotintable_r <= rxnotintable_i;
rxrundisp_r <= rxrundisp_i;
txchardispmode_r <= txchardispmode_i after 1 ns;
txchardispval_r <= txchardispval_i after 1 ns;
txcharisk_r <= txcharisk_i after 1 ns;
mgt_tx_data_r <= mgt_tx_data_i after 1 ns;
end if;
end process regrx;
-- Detect when there has been a disconnect
signal_detect_i <= not(elecidle_i);
--------------------------------------------------------------------
-- GTX clock management
--------------------------------------------------------------------
-- 125MHz clock is used for GT user clocks and used
-- to clock all Ethernet core logic
usrclk2 <= CLK125;
-- GTX reference clock
gtx_clk_ibufg_i <= usrclk2;
-- PLL locks
emac_locked_i <= plllock_i;
-- SGMII client-side transmit clock
tx_client_clk_in_i <= usrclk2;
-- SGMII client-side receive clock
rx_client_clk_in_i <= usrclk2;
-- 125MHz clock output from transceiver
CLK125_OUT <= txoutclk;
--------------------------------------------------------------------------
-- Instantiate the primitive-level EMAC wrapper (v6_emac_v1_4.vhd)
--------------------------------------------------------------------------
v6_emac_v1_4_inst : v6_emac_v1_4
port map (
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT => rx_client_clk_out_i,
CLIENTEMACRXCLIENTCLKIN => rx_client_clk_in_i,
EMACCLIENTRXD => EMACCLIENTRXD,
EMACCLIENTRXDVLD => EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW => open,
EMACCLIENTRXGOODFRAME => EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME => EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP => EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => EMACCLIENTRXSTATSBYTEVLD,
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT => tx_client_clk_out_i,
CLIENTEMACTXCLIENTCLKIN => tx_client_clk_in_i,
CLIENTEMACTXD => CLIENTEMACTXD,
CLIENTEMACTXDVLD => CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW => gnd_i,
EMACCLIENTTXACK => EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE => CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN => CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION => EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT => EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY => CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => CLIENTEMACPAUSEVAL,
-- Clock signals
GTX_CLK => usrclk2,
EMACPHYTXGMIIMIICLKOUT => open,
PHYEMACTXGMIIMIICLKIN => gnd_i,
-- SGMII interface
RXDATA => mgt_rx_data_r,
TXDATA => mgt_tx_data_i,
MMCM_LOCKED => emac_locked_i,
AN_INTERRUPT => EMACANINTERRUPT,
SIGNAL_DETECT => signal_detect_i,
PHYAD => PHYAD,
ENCOMMAALIGN => encommaalign_i,
LOOPBACKMSB => loopback_i,
MGTRXRESET => mgt_rx_reset_i,
MGTTXRESET => mgt_tx_reset_i,
POWERDOWN => powerdown_i,
SYNCACQSTATUS => EMACCLIENTSYNCACQSTATUS,
RXCLKCORCNT => rxclkcorcnt_r,
RXBUFSTATUS => rxbufstatus_i,
RXCHARISCOMMA => rxchariscomma_r,
RXCHARISK => rxcharisk_r,
RXDISPERR => rxdisperr_r,
RXNOTINTABLE => rxnotintable_r,
RXREALIGN => '0',
RXRUNDISP => rxrundisp_r,
TXBUFERR => txbuferr_i,
TXCHARDISPMODE => txchardispmode_i,
TXCHARDISPVAL => txchardispval_i,
TXCHARISK => txcharisk_i,
-- Asynchronous reset
RESET => reset_i
);
end TOP_LEVEL;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_0_0/src/c_sub/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd | 8 | 26624 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17968)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s2BraRl5yqev8NeFIIJvKVX4DsxUVtRt0gxaUA4HJU3QkGcFWN8ltyyN
eZENAg1aPJvuM9otTlAPJOEupJ06Pe8q6xbj/ASBb3t6oCJXTdKue0Fsav4SBwDJmeO0QNpaeJXf
wEuU0k4C3xLZXjrrDYEgWYGXIBpRGc5a37HF136OCc/MDkg1jB0DpHNDCSsK/07W6IXBhcwM/hh3
UpNrhpKXnyb3ZtmrdSX78pZtYYO6Qp9FoPYWJxFOSF8MgqF6ZwG67qqv8ljSqBKc86+Z1w6fIczb
C8D2drUfdI38DVCNh9eYuq/dWNR7xJP8DuSATWksDRq8duIQA6HuSMpukqPLjmBnljWZuzvB5HJS
Ige4+3VnrYL2ELNefngYwu0TfBLXFXjxksae4hSQcVxZ7wM51z113irLI+dJWaOv+JloYoh6wN9+
074yzAncwUrKJfqu6VsxH9/FqQYL0vK1CS4f1nvTlM8Qf4jWnZj/FQtu5kGznKDV+DVR0NzXn0CU
40IO+DNrdXLP95TaYDz7yPMyVMGgh5pHkdfaYFMCgR4rWpWQn4G7s3sID6UpokAfA1V6HffqA9WR
mHN9VvuvK1lnaD4dxa4R2NmEvbmF6MBVrvnrDkEZCn8feVIUMdtoN2pYiFhIRBvw3AxHrHjfdkbU
LSa29bbILWiZpS0vgdXvPLDBQ57BcC5Vo5NM2UVTBi3pF9LdU6OrDTz2wRcCNhmBHcZydx8vUfKc
UHIVxuGEkcce6bQNvbNM5zX2dj88Mwwu03LIuO8f8aupo+MhXlLzorBAlCKynR/4Fb+PERyCh4au
+eggMFqWo1BmD2Y1NxAIdyT708XAdUSz475eVOobESh+XTVbzG5uyns3LUi+iO4o7p/O3ZYdkfXd
Iemz/tugwnYNIzA0mYzOOvO0+9grKRXTTBxNUAMITZA1W8jEvtYbv0P251llzg3sXKATPwQOLN7j
6teTuCSVZAEJC9HxqCR54ONglbqexaHVarzAc+/cOfEmt51HUog1fxibXvPrV346bpyJAIEqjKdA
Wp2iJh7bRiUqstJur8JIusssSaYapNBKoQEHrqCeEmMeCDe5d0YBenqewW9Q6CR8lkEH7+3gb0Ih
QhK1eGTcQRLui45ZbJm8JiDEQJQ9K7dYmvmRt7axm6qiqdfeCRBAAnotEc8jkfBLnAdProYWmOxR
o9VKxjkr1OtSLMpNeUxUgu6DCLAOBSUfDHhXDXjLJLV7k47IFz/bC4WfsI5f+IrGlgGhahGpgx4Y
PpXAQPriX/h5RapyU+iUrg/uZ/gylI7HiuexX3ZtX7C6ZwVwbAZfqPl26muLg3+ySJhiCmrJ39J3
lrzy1GdIr5AZwKFlzvEu2HDMW5HvJBh/XrLYFe1j5YnS2JcZ/ACJyFqOOxXGVcAQkA3puS8t2yGW
3LoLjK8c78BG9q/eMyOp/OOtDCi3I1ogBzOE3AK1+ABU6tEspXIWMXcELYwRABREAQav8WCvJ3Cp
1bvIk3e+enqKTklDhobg8KSIU8VvxWu3ESHCeOytzJh0s35bf8sK23DOk7wOkc14rs9HQ6k5bkjG
hiaOyRbr70y3pp/enG7RRewmczyC38Oiq7u84AaICeXLeTIFWFsOT5cps9ixLEwhu3a5UZ25C6/N
1iXS/VBML9Hu3TLs3daFCQT4F9Y5klNPFZEulZ6vD9WMgCrOS0R5pWVcfJCF//RRg2pVtiX8dAP6
/Q+XSLeuC3uFULzxpbU9wRf1Fy7l3Uz0P/RHDefSDX8HlbKCDmMlxzIYUg0vy6hb9YeZXIRh/ZTL
HnF85jwk/+r983WmPAIZiNv6ck1GGShi7Hm7JeeCw3CeAp2euvXLt3aVvk9pmZuGV+G+5xOdVgSu
AJTCaj37x/Gu9kEc5KxvMBOADa3bJucN6QJCR2QoZ+s0GgY5LJBQg5tPwRzvloRcgTjK7Gv4+8eq
0h5uk+IVcOryrKkuRr4MS13MvMsfm8OUySzjciEJdu7YEkzBC+85cl07zEQ3Ho+zgh2inYU1zxdC
ABe6KDZEvJdRj81KY+WUP9mUu+reto6Z5gO3Ve0Hvimn3hO79Gqulc1FgkozLrO3NEyYanrJaNQx
rtFkKnjsmE2zOWSNW82zA24wJUvTsYh9kKqtsAjHjd82xG5scvZ2BKVFmOeU9fSbbDbcPPA+llLq
JbhJb+405w/17oOqmaqpnAW8y66XbxCJXXcc3+VWyh1qpCw8QLxwDg+P8O3QopmWqC2XX2ojjkl9
O7Dl4hWRhQu9jgTO7Il8FRHDcK1DAugqFEvuLZVG9AHtXHUniW2MSzyOQ+iUFJDz0gruzv7IXsyp
My+mQir821ML5Ca+xYBAIKwFLeaQ9D9q59fNnq5p3Xk9TS90WWAJddqNUKI3Gn6l7Sq51bYIGM5b
lLfD6iurnzR5nMMdzMaqwKNgH3tUeb9KOvPAqqlj7psbPjCECGeQys+ZgviUJLTyVqk6H4ahh9l2
TfE9E256hzSGPMeLwuFuU6dgv7C/W35RkBsvEL7fmPbsG1l7RZs9SllI5hmb9/NOrzjerxhwfMPC
Z3zxnVoZ7J3Be0QnQNA1WsWLqcpkwmpb1sH7B5fg9UgyrpgUZcacVpf0C2Ke1RsDe/VprMDD5Dky
ApIT4aJjKklUi9GkKIsBANZYvZsNLtgJf6NUqm2HlRPhILau+78TFeThGOdMb0yo0aS993+Awc+q
Gxap1mOQWX27eqNCEvt3+3TAi52FAzTZYJwTuTpD9b1bLhJ84bVXKBOOlgzZJksVsfKgUaOAPyzL
2cCku0MnIgtU6O9E3ylX2v0djSDO9aAiaVbCtgESOfy5B+4dC59pBotaZQOdkPvAsTMlR4SujEvc
OtBguLbBePuqyyRwngCliougFTZdsJi6csslPCi/WT+ubCXBAEom7892O4ShQpORkeUFRo798J9/
DRuS8FsKYTWhNgmAV0wbHd+nvntf3gjQhnD0SoXfmjO6b3bUfe1gy860tzRq+9/fPwNblb1ZnmiU
RWHosxhuZ0hDRfSxfUgqn3p4MH1ClbtCczsG2cRBdZyKRkoiENeRHmqlBKZpFUkXb/WEhwq0q1oy
8CFnOZtY/YJlKOo+wjhEB1l8GvU2HG2o+VE4zaFvaFKNNHmPbAUGM4WyQEV4B2bVi7/YlSp0Z82U
+sOjGDS/1sX6GcMjwGvHSRg55jdgcEpQj7X62PBJ42GZcllJ6Qh/FZRI9IomucW2vmdKojLO6gog
1WBldRB2nYDksr2KRZsgfF7ksoAHUqh7W6QANUm51BcptfrNUjYmyDSUaI7MtPmXKKGWoMhfHD63
L0vieenqUfeYBN+GYRq/k6KF4LOVM5bMcdYvyN08oAsKfd6vor3jddxHCx1sEGBEoh6nD42MhZJD
rv72MiUg/yR3chI6j1+I5u9dhrIqx3xLQ+gCxFaHAKCuHuecIn1GUu2BKjVfh5uEdMe27+7NzlM+
I9VHYMDSBtOcTmaHLR5KwUUlmahaeozXPxeV+LtTN3XMX4gBjSWYOGdGGa0fiPbzl1NlotkbJJaO
rGDx/+9CYzKCATx9gjF6SZCxopW4OoaDYN9YJyjJuKmuv9grcutbnQpylWa9bY7lu5MNkT3jSWHp
u7pMKhkrLlC1qFBRC3MyguuqtDSbv8Pdk3ITT9EUXWeX1wgnAHPJZjxrDCP+nyjX03eCkfW7iV9O
gz+XEtB9g3yNaG6R+eWho3GzJDjLICVsPB1ahyoo3bFkXjcrkuE59hlfEs97NAW3BAUshxK0XDRk
mnX2wbsknuiD/kqH0i+Ws1/95bo8OVUdARXFKiH2KdMUD3niFuC6XWha2yhNp6phPNSgueqFngBi
AdmsxLYMcPXvUPt3OH874VVoCYyGek+FbVdTTkDVJpxNpdhzavHnAAnRkJLlfP9auqe3oMvK/RzI
vPkqZb3qfDjiLXWQTiEg5HzGRoxyc0eLwj71dWUDZFqGw39MYpsTncHkKSbU43XwqIQkNNgS0+OB
S/cSx199j+An3Xz8vOsK/uojC0fj6M5eRcyhcuSfVuE0VMNGHZcoOx034PK8B6DTgJyRFkmSKgL6
aTh2EcXrOuhCSHOvH/CfcqQQy7F+1Kl7wddUq2YCr2HIBlph/Asdg2y/pd4sh2prf1r3v0WpFgkT
TOzvaORB+zT3ko7UBWlwGW2FZptCBL8A9aiTuIUy4XQjWwEmTmprUJJqtsl5RWiUxpgFcfTApO0M
WJ1t1h6LPxFQf8IpB462QQXyRhPmd1xSA5LOqf/LN3AYxOqZ3AgSW6F56nrbps+IuexJ+jK13vwd
NjJhe65VELVjh0XZEu9Og+7lP9eXQ2POvBc7/8uXdapcM60dwvT4X2kD1vAjlweIrijdBWWbZh7w
tRAJGRB6ODb7K6YyGR0/hkG07kIqwTHXh5GEV1MNXyYtbJ7QxPtMSoKT5aSIiURZFM3SJV+/L2wD
GM6zZz+7E7YeFt4V3lvleMLfwDpneG2MeJRXFiw+AwG/e4CMxTUYdUeraHoBY8poYRO6mJFOYefe
+BWWFrUluTkDohLIBikZEr2qFyyrKnegStd2GUr83C3qT/IfZvlH9el7rD+mqCPDuWGWE1D5ZnWZ
ln+4/FBRaFGLCGfhrNu5P96slheDZZwVMUe+keXm9opcP7XmSmUN1sOCoWXKxlWtib1ZbP8Hz22g
to+vyGJt1Z1n0leUnz3ciKYWuo2rgyrCGhwykAcI1gFpLoP9IYAgLPUtqD2yOwXCb9SQ/vkEiwve
cj7ZK9UW6d6+0QMwiIOKB5fdKUtW4SS9EfFGrIsYdcithbVKFsC7LXzfrIuh2v9HljTzQBWB0LtU
b7yqAZJlN6MjM2+MbKZt010V6OvM4SbHRY7q7lp/TYwLXXZxpsU5Bg/axo4fB/umDK3DErGJJb2Z
/fwoZXyDPa9AObUBYB5O2i5HE9LaMPu9qW6epO5hNwYoQZclSIyPYHZ1PwhB+iWXkX+WulcI9TK6
hmMn+tZMO80S9N68QfxTwkOLWbEAPW3PaPNpR81VJ3DLWimtLCcvDd9qPWuEt6HwWAMbwFdp/UAQ
Su9XwvM0CW1hxUHAFhWf+TvC5z95BHio1C9DFYdPZCd8+zWX3IjPHEqECrYb8D4KRXo2Fde6+ORF
mVZLHUxIsyCDjOL3WnyRljGn3ySn+yqNjvMxAmCR/wJkdMh5WcoWbSWNfk73eIV7CUUdODc7ZkeT
89blfXnTWVJ94bQrBfSh2R6SdTvcpEPeVzCW32bUQu0Q1QEsN40yzyjBq7qVvTunmu6/h6sGuNdu
KGm5be0Nxseq7dwxPEMIq+r6Ox27C4+4zm5MqadSOYGnCuIlnzNfcS+eZo7dt5q+nYQHYVyul9ij
vIgyExqcK3zXzZE3yACe4JXMxbK7hMCjHvb/zqEDccF/LnnVroIDr+JnfjS3IyvaI3dJSP+ZYDq/
KsqlW8LcAbyH+N6Ddgf1xb4/qEUG2BmKQxsYr3LmPTGJ1sIOpSlniyLjP25Z7qV/tGCrN9PV+cSa
uN96RQDMzg3Hhy20Cl4256nhXuXmdHGy1OvaerY55kxut7QuChjAURn9boAXD7mlcyYUorlMSyKE
sejrrGjQozXTiGzF8l2hYQPT6c3SZma5bT5ZVEhn4c3/FBxmyJ87IGyQAHkVjGufehG7TYtiuOiR
mwtF9NjoooTb3le4PZgUoFU3luI6RbwmrUuHKNqTHAT0nIF0eLo6+zelCyrKl+2SdpJ9NM7xH6Wp
SH9MUP0vHJZnI6kZmXbXEmjQiVBbjLur8cWJXLYwqpK9EWYk+k5jrA9zCQ5aOa+jqb/ckAtWCH6d
zsAcDywDfWIWtkWcG6WDEuqV9WvpqQA2vyD425MgjMNq4wS3V4xYoDgZEcRkGZQi2QNIs7vFTu5g
0hn6ICJCOKSyX8djPEPHTxUh1hqQT8oooPssiLqSGBaFT8SlNb34LmJi2Sc6axtJi9xeE4NEKbyT
dBD82/yQASohbAjd35ACvi+RfY6v150fTyQTol6MCxglszUMMlLQLj3u7teWKHkdT5JL4g1HPBTU
uIBMOu60//xo5Av343xlT/YBox10II+GQnkF2n2t7QiZuMJdDfjIrOde0APMQkzSbDHMwXangnTT
cEUbURfXDHFsnF/ovBQ8Zkuom8egS5sbwum2NRTN1C1B2xNN/jKLeKwVDezNTZjSVmJR3QOw/w/j
n3QW280uAZVkEqBxoDXVTgZ/Q6O2SSp7Y0A0i3dlxEf1qcQ89ncgcFi9TuIOeCfU/+InzEHGc2jb
G0oQcRC7NSKAW7fylLM2CfWCxYNMjCK7YwHoEg0s7x+ej95eWVXP3MGSkofD+wVvGrsbJkCdg2fD
1GEWGrKtGfgO0B7X/xZJwgfw5JtToCUIB0IPyOs+yhadHYgm0Oxi9DodL/5p+aSMJPoV4+Mz4Lw0
SZBiy4DllU5bY/65J2xhsd7mmlCmaI8VP659gWDPaSJf9RIr+UNQzEi65lhr/ukhE/zwLlGTmTSM
5xyWT+VUge1VMcWNogxb/6PxVOOrmyoMn1+OA+pA9RDyt27F7GYSnmvtpl+70+i5lVBaU3NdM2TP
YQirpA4TPLTToNPI3MRTYgW5R8K+divzGxA4sN7o04hl8cUWS/04mVK/iPPomy4Mkj4KL6J5QDHQ
zoENCOrLnplTwzbL4zfP7eOyP0LEwcozkUR2nmoIXToixurVvMvugVo/8aG2EWYj80FDoah00Klj
U0lHtwEnvbeZNqpn50epVhjG/YLSK7dY2/CtAUG9k1ef9nI6jYqV7CbfOgBFUdLYCA74ZsPJY1dC
dyz7h1ecNXPuS8Zpb1fIWFSqVOCjH8dOdm78UCUZs9ZpOGwt6OrmA8mD8ybrzbHRTakqCoGHJO+v
FhwLncIIGuxuCRXExuLrbhLpLELjU4KVEjEg6hlfH+BengrVP0NJtl9FE4R7BB5errBh7yHdAern
IFaxICtC86orS70ZqujYs62rmcZqzxh+fwr74SUHp7tf+m4JIEHIhiZOOlKRBfDyzyYTXcgNO/1P
wTWIKmvFQCgMMKR5ua9xcgYULAmoPbLAKYShxJSjFkvNvC6Ptoyg8pr2j5zLWzG2cP7ukU4iE6nP
1WfiPlAe/i2mhFNzxU3Wc1oWuvWosMWQwn+kiju5ZJOGj6AyCfzfFe6oWRRvS3WHGxnip1hpuoVI
W8xJ49ixhOP8pQMM4f7bkrrI6PjrFiRCAk3kCApiqXFxc7LCdjAQS/KE4WGm/mkVPo1XWgXbei3P
mDFXc8Sbxsp8XjFmQOevgWvJRZANXUG7AYrruXUNkSsraBoDYx8JQy7Fk/58iH91h5H7lGE2+hP3
9RJ47ahbJTYaI1eYGvGY4qQnU6uCPWpHa2J9gggHQKeQONViLMIgvkzVhaeaXgB67QOoDmoeL4jW
ZZ6KvcRARl2Aozb+khNjz1PA4S/LbhtbJXEoXYJyJb4GvYKXnHDyGQP4fFneIow15xcenKvLcHEt
l2aIxZzG8DDeusGlPLMQzUii5WzNJuGgFrrZwCypgP2YlQflLJ4sWFeMNPKH/qHCBJexIQ3FNCr0
uy54J+U1cLhXkdnYaFCH/4LP4QDhZ8P/4/BVoeomHCN/L57RHrOLrpm+7ZtfeYLVJDhpST00QXVi
YXaf7k6Ts8LORgwdKCRLg0vRSx3ZaT+o6aCMGwp6JIAZMDw40t+aafA0F9wOT+YrWXy1OOIpUX6y
ana/pYs5I9v+8mIPksp/Wn7vNA5lZ/2ho4IDe1DworCxyfejMSUKkjISHuuHXrY5g+GI9vziJIJt
ax7R6p67Znzse0uIVlpTswvNMViyh6/KLnVYGIRUlhtsQVIqnXyComRFGFNAy0y2sX5zv4EAoEZs
vM62xFNjUGMKlJk0w4bwLPEZq0YgDwNohF9t8Wdaa1rF/ioTfZX4jLcjFw6XvntwwuCxiLBVtkka
ef+ubO82rC9rpci/nyBn/bGznzWtOFaKjfqETgrvoOxOm8dEYt32KcWqhhob9qx41ggvrpAs6BUX
/Wh4yhdbpw2xuMYfekG7Yl1d0zusGv7U3InKTTgv/RWM8DpTgfjZyzs7OdABB2NPHxzxtuWHKlN/
NSa29m0w0d1mpSAXGo5cyjLUMzgUTte7nBUYoAnXxiVf/Y+7DMWqbsZxjUBbn4XwXQdul+pogBUH
8ZpiaiKJXHEYKNGfUaSsWa5po6Q61O8gQzkozMNTxJQ0bHGSnMamKiUrfYsLCYv+vSM1CqTNTgVM
mQvHwJQ9/9Jq9iEACYlff/U1VZgVcUO0hLZyEEtaMOJwzzederKfunBr7nsq71ZIjnayu43GqHBL
P0E8Vy/DPYbNHVSVBXgGAlBpN7QXwRjuORPqW9wD4cLEzZBP41x9OIBOMoIYJaiggS8MapRo0u1W
JXN3HejRa1Nnb0FZjRM2ln7DJc/is1JRu2B8khACee/6s1grTkC6bv9K3lRB46+sU9F4mJ6rtkZR
Cq7xjgTHc+xZN6a16zHXQVSQR2QeGLo/KCYMdR1DmZ+91+xaGjZnRgNgdr/dhRIPhxKBwGe7chaN
lJk96Xeph6/uNjwTDEp9ESJZkrInDy7p0TCi0WI3jHAqQZdE31In2Sgt805hto7fYzY7ydItp8Lp
lYEsXrqEcl+2e+NcWxzsRzZgguAXonyM4IEqXKA9aFTJ4/XFZZc3RZdIPwIxAikqroYKVem/3Fm8
AusmWNsNjNyVW6wWDrl4jJQqPDZCTKQNYfqtb8DMCzPwYMHVfJAYBCBWcNVHZbdgDiJItzVkvu2X
UcuHt9mkoZrGndK22SR0r6jPOxN+M0qYYNpzqV+KFv502ftskZx8/nnrA96W8M2s6gBp3D0o+jqd
zzsE2I6eHZ8XSkRrToXGmmO6Ld4BPzf3HVk1xbCvRfZL+CJQpHszkEwNJ2K6L+lfj+x3ZA2X3ptK
j1Jp6x7BdID+U87DHc+opNdSfo8YcDaXRPy7yp9UK2eco797bQs7TC0aCYz3o1aBfpQ0nz8MUnC2
0f1EifA1DqeSuVNN8Lzy2+V0TY+J/5y4FW1IThp7pZhEja5SPr2kzmNh0sg8EgHhwte147Bmzfg6
3sdp76dKxK7NhBiw3vv5nDaD/EzpZ/dIEcGnjKHR1EQAyEcDANGzGh6/Fv6mmBlQQYgY5N1Pt/Jc
dlVrc94U8TYA3G4ROT/jbrzm5TfoanKC2542O6838n0CNzm/XixQMRvJw+7UlIM4xObemqN81cCk
xBwZRuqgBSQK6yYrVxYsu355ByKqP/pXoYpP5RuV6UPcb84uN5ofjnCQW5BcyKzJrP04qxR/y+QU
K6Ka4kdktglUbZUQVUsCwvYGsjzZyYBAm3DKZJsx5MdtHLAGiGSVznyIH/+BQZ92EjG8vd7/3NOA
69idSz92vOs/1Yee/Y73YN7FTes1EQUl6pav5VA768fZ2H5pP9id0ZpnXrFdsnKRefcXAFxXl07d
dg6G+BztFr+ufGf0Sl4swK+um5kDyYFZnjvwEd4mnumfo4rPvJ2KUB9VjhL2LqoGtvtieWsYzzt5
yXTOmZ1h1saYOmNunB7NwvU7P2OqfUGB7/UkO73ANcjHC6bbDA4zS+KSnzi0fsz5LcvKQKj9oqr/
614N7dkml+3lmCikzpt95RUv92+iG/dUyVRRBSsvjSTFLvlcFGMCEpDItfWSEmvDR+CVs/nSw63Q
FesxJMGxOqv6HFNoTlFwAojwI8TtF4zq/ZNvL157eCkaOogcOBgcCGw0tO/FVXvGJFuFk47ImjK/
U0bCINzUWi/u8rKuL1k4Qdpj7p+Tyqv3xFr33cfoyOLjIF4NaWN8EJqXrDr7xmsFR0fEi3zPu2Pt
0tlCVoeCrbVAwhsUixg6trSPhN0iilW+BMWjhrSkg50vn7ihuI5WCyT3rM3GcKNpBBKtEaX3uPok
JmRFsY47PoG6uFuoG41GedPT34PAjxQRTcr4O40qk+0LuhaDLorklTEiklapCsRiSogHVGj/2tOU
2qFoTBl3jW0rNmRK9CDOSIdhOoAarde//+gUrsIRGb6aty3zWgCVJptajjH8iOFMljAzI6VUQC0J
adSr911ds5cP7Y9Ak8WEtV4eTcIBuHP6HpAG9V71aRA43FQqy5lzYBERtkuUxqLUEb3/Jj29rdxW
/6N30cRs4bDD5X4BECsa2azyr8/yg9mXdEY9sBZDObhVi4mVaKG8bGjFTimRITDt/T9OL39NvVdD
hvSELcnbanNyVFq3JrRC7lJLT5IguECJjm6ZVuUyIpzsOEQcK/hb/X6OCauINWF5TCh+hhFaRCHy
V9hW2ap6vuSOCyrDFqNUrMLOzYPtG6QqJgf4DKzcH31wYmWDLB5zBPN0xqX90E2F3wWiG7P+o1wR
29zLGD6U/5rn3xdj8I6gAO5Xpi5KeoZ48LuoRme7wM7pD3b15R8iM/f60/hzKRBnJWOFk4he/vfz
3wQ1aETixPn6uGyT4ecy4sU4R4RHLiZEgCL/u4vC0pihv6LLn5FHI08MpZTPtUL7ryutWxaDq8M4
BnwN2PB54mAQCr9Y3YBwgXBQO5zyBgB4B7J1WFxxDZkMkxa2wEXPqfpe4lFRMpnPM1leMIKhLJ3e
b0k85+askPa49DhGQc0o1xxKxSTgf9m4Rrj4ifzkM9/hbc9jJCAJFY0cdKMFK8sO44udqWTmZdTP
qGhkQ29ZL/gPEi7Lbbt+AUufXdk491QwL/Grw3u9gJiQCPU27xZ2Ym6pHujnF1PPq9OtIT1Fkmyf
dzLo3Wqv0Y/YfwOoXghLJxd7+6W8oZRDwH0gme0O3tt2maUQDm6krsxEh+mabIuShsk6b2WbSj4d
PKrHR2qZLv6bxyru6GnfGxHSJ2+6WYjfXFnJ/vmAzssA5VKK+JgZCxLviRbnvLskcAI0+QmdQwUl
asZwBVU3aiPRHdzbazod+kGNLlvYtRBeq++vZ+7t0LmCNBAv28WmmAt07jaI4r4VVMEqgbD66VJu
Qpl4HgBTUloDeqRT0pnf4l45oaLeN/aDBdOiL+ofqpc/n4f8pGic5n6fvKVR9aAPbbwgU0ZqbaMf
90yexLfz/TIz9Wz/4DbvR7sD5YJdo44MhxHG82ypeiKAtldIzXado/zZu6If/DSI7QPgfcrEslvA
yA9fWQw73WaoywQO60rgECjEA4Q9CWvJnAjLT6w68pKjjE5jbJlnki8URl8a2N5i/Fkm/VkrZ0jS
Wyg4gryRLj/EYEkqUTOVa/YveAJZPfxqfD++hdHifrvnyETLXjQYobe6exaUWv5UaCh7tOyQpgw2
6Qsl2W65DpNOLdrzF3M/1kKQ6bmuqmIA5HhP1BPTKzuBKToWBgTBIxAs9VzuPKZh/0c3HphSS8qV
5O0Tsa5qhOIVHwvCd990BwQbLiEqe+GIxGPDk7PQ098GPB7u4VwDbVRPD0Uv8eLdcf95O0qY8EJr
f2cn0ZXHYxh/Fj4eGUIm7LQbQ4kjDTbAmN6dnASYhZIf4y92xsQu0yhu41LEBYt2arrGd+Z5h0ia
EbIvQcOrt5vwP8oWGyR+sAaiEF1SgeoWiE3ZETViO5/GDYtRvQHBa+NRGyJHPLY05acbRhWwlLqm
8HXM2d7w6V5wcvxISe6OWAyuip31frYTHEakP71aBb8JvcMSfXXbw982zQjcICOoCEy8a/537UWQ
icsJb59rZ2iNBwD98uF6L3xMT8UN6AhGJjPkNeSxln4qHvpV7UyzlCEP1PSUctuf76cq4TYuOF9+
5RgFgF6H+Yrh2+fKimcQjqCSsc+qDNK2EjSMQ4e5439/W4RgawMHWBDx4RZuGiSV/A7w46gibgI1
iHVmVCMN8gylfuMPbheeh1Zbai/Oqyx1cOkuu6lzoOeToe1SCxNjRKdF7/whpb16nTzMHg80GBC4
GBGqRnpiE+xr0WDAxGRmeYSY4EnMLtAlHM2tUP29WwHr4qv1vmO9sCCZHJNqlgTYnmdzC5nOEW6q
rNpDQIbSAASzdCVLfE+no40EtHmVbmCwPEJseoyKczMNTqFR5g4pcAsbkr6QYP0N/BCKhvDRI2LQ
nYZWnVhIpOlD650j7b2+JpTtsxni4Ek8GQxgouXMbMHfPNLZn7HsG00jp+n+snT9U61GyJdS1E4h
8rTWWQEUA0SBVtnOzDbMu0TsF60SjPHK2BYIY4Fod/j7wkt/YYX+0RVqWhf9gK884rWoOKZOvbti
eOAmMVTNxOp4Gkbrm/tS11CiIeten5L53rsFkLyJVUyKuCECVw41gigogxsRLsKWqIHJRR61jOPG
I/lyO09Cg242li2zdlIWCr9jlUhDT80KXbgivB/U5aNw+jCM1brG0c/UxKCQN5khojyoroGDWiHQ
hixFku4+gH/uWM2mtZuM+CnB2E3wNt00GztITp9YL2gdNPTY9c2Bzm9Hgfgvlz8I1Z8EMfVOCvX+
p9pYH5+dInZKMQdgj7t+dqT69lhXHTC3GnaZHXK8zCldIpJDSvriJ0y8OEYFuengBLDJLhzmoOmE
zCuGkMNkZSghUa3LcoRmly13ouZ4OfSxnoQbOzBOyeTNV3ZMacCMB1CREhlfDxlZW5kgap/KfoH9
bFciV135VKV2XR4oBSIAQM7uckKGWKeZ2KYtdlAVhjDIk73CNXnhz85DnpwEhNKCsCUnJ++ONi8F
kr1D9a8EBXAT7+PEPLIFwFMI6+soll5V+pnUs2fQC7xbbUCrYzIY0GBoqYu0yEqDXwY5Q1EL3B6l
eka1k2MVozZIpISvGhMePWGxKO1hpcTN8R2ZLZFx9OcnNRkRUuAILcfLQRIHWt8Q/sTbyRDfEq3S
BgjYrtU0cIRvBSUZbmWoaiPv33iUTBxHupK7yoLL1Bt2aDdZ4C119sD6Wgu1/w2y/aLS6IlZ5p1b
of75nq+4IJJkDux32hoWnhlFFlGWZEkO16LnCbWBUvyQwS3v0pReRVXu/T7L1vIeOG2UPDDMerG/
5tjois0ivNgSIvurAPhojRpW6DJb392nGc3wP3l/LRy2ZUySZSz2mqUgMSqQqlNpMBrpRqld0xSC
6/HNxWHVsQU9FtTFBPPYW+mxA1vXS07EvvLNa4uH7JYRbSkCw/cz1+dlqhMX+7Ef380R23qhnU+K
ocYyNBnrLV4sKxTR2wrslfsIMBdH1A25jqst13W/UcgHttYUD6A15RifZSL7TQFjJBXAjRKPEGpm
nzUVwbXTG0+FPfKTUCzOJEVO8AoDO2YsjWSF/Ps4u8PUiTOtSJQSE106itNamqCB968l5fHd8Z7d
+BMzTJgUBVwJtAXWhcwLUf+QK7rf0+lyl2f0bQ2b7MlA3h1Y2wLMVEN5wvsJDHv8DqOhwGcefAC+
fHzVA9b6tkEcdmMP9TnUDUS/mY56C4F/CNli7/ZEC30VI6xYJMu5Mms2gm8+K4ox/WuAexDO8+nB
SqycoIlJmBQcGoy9/53L/+JcLm7fwyENBOO1N/oIuDQCMi1yMik4BUTndpyn2o14L3Q2LjjI9tdS
xB7JPRUxhWH4JN9SN8EVmxbcAshOt6qcGH1tetpmedIVtvHBPB590PtjGNqD37sq9/zFBsb9lWEf
xPcv/+gneizu0hPsh1h+IGFS1zwzk8A3sAR+RpqCr7LpdKeEYLgUXqdoqZqN/3So4GZswSrOYoHh
gJlTyhzO+S+Z2EAR21CWX0Kn75iI3RoBNpymMIQSUCSnXRsJtHCqdyzcrCRLef4Gq458Br4FNvzK
kByOehdKfReeZIaQss1+Jv3h8QBekm099aYAPG5cHeHtTM45FMvU+RbPLRCSnnhlHpq8zyZteHai
9OYmkT6WYlVeVc9Yb5BwUggIosqwEc33y6YakYKJ6GmvYUwmxg47NSZA4S744EOodXU4vPU/T691
i9MYpETUFPYKGBQYyevH0UCGibnbbNaXvWLPMMsPmrp+ZLhlv1U55g7mDCwN8ejAcgMGKuRv54qg
PBf69Ko0+Qmz8/2K/5CAMQgvaC74i+Z8Z0FGDBddWLCMAC/hChxl41iDdwkHZBb4l619iiKzJY9s
alF9/CKgCEVyJK/Tyg44J4fyUjYQr+GuNh3EPft8ga5ZhRHd91qUEqamBjkf5q9w6xEfpPgjwzLb
7oA2++E0TX2DoN2q9qBmINt5vgaERJzmbnbwMTjGuUktwIONGzkZwFKisYKq614s+4opoYlvom2D
tux0+BZRHFFhGBeUMzTuag0jFisd75LIe31fbBNiEszhoQ2qkRNLGNVm8Ss6YUk5aR8MGetMEX5f
gB2HNZYgPXy+YB6M/Ie46hWSzHbKEWY2JyJ28myDnhJKE7I71M8V1sTKbGB6RfOV2V6HZwnOr3ui
QiRDXI+BP6Oy4T6oFz7dgC53htPw454D5AjCyC5LOnzVl/c8CwwhBUgGTMgyG5yr3Y5FKtuAxFGV
rIxQhJg8jAgLegH3n8AzawAiNdUzP5OZRc7Mcq/aoyktD+fyndJEB6ySE3slSHvjr2GsN9NK014Q
IX1uSxH32v7pRuYq+B0mpv+sn97XYtM8DHm3bQIVsCYGZv0uIWZJQeyh/peSZWF9HOXFwaVu3S3i
1/PcGdBRZDHSSnLETW1guUJB6BpLhcugNjfeTHUXt/gRLo6mjQNonul4A7a+90pE+7YtTuaNdr+b
Y3csQEzWaCUk/wX49e+NMJSdn2LhlLntt/vtsOFf+KbIgCZGtE4qhdIoFSsowhLgnZPGHfvYR8jw
TeFoHolHW6qUT0KS5z9EIC9uvP0XxljXuUiWOjOJoYqkcrnC9OThi44AVj+750DwdZFSoBz4P96N
QxeLbXJ4Y9ZbdxJ3vJYCOO+rdzwTrgSs58Uqj8QF6A9GbwocWkDsLh6nPDC+kkIBaQz3SEII8ufq
pdfz6PCGiliu9T2o7T6YTHoqfcIIofirOFfnOpiGwPifMpeBzQrmYXma5ajZvG7aHB/voav1o49e
J29IFt3KJvWmNj07zR6FP9Jo94MyWdL8vnJM2BOS/JQS0/LwojMTElq99+uaPhUcpwX7lrIsGHUj
6usO0mHVRy7jzCvmxt0wV7ihqVf7tdJqdQHU6q9PyEQN8usvxGpTJVPeaN0liwoCLqAYEAxe3v9T
HTEd1N/J1BdL6MtSk8DtcFjJm+fhee4eEN/ZiGu4YFNHGuWrysXW/PgzBzZ5OMWscUvaQ3EgHwNn
AGsQl9fc6PtO23x5R4u+4Mr/aYSbPgHdm07r+cLaBLf7Hc9HP0wZC1LB++PDAVKGfGWmztna5GE6
kVBIuHzDWaMH2ydQe159NIx2CdfOLXICWQiSwVdruz6itZcpKRNHnOaK6tmaC5gdJzRj4NMzszeB
fMkWlhbtCZ2aKr/e4XVLt+3bYpauK9Kw50fdec9KmuH8e6rrYN/spkQTzZ29bhxVa/mK2EbK7dI8
JIrnS4sb1Hwic7O+6C22TLoqYvvdCq43LxxJ3311T5rU7SW68jbVp6KFK+N+i+s1OVrUbvLaaHF6
Ix19rxazInuk7t/eBcC39k/CH06A8DSVjWXJns4xNP/SxMRk3zrhL4DqqEXOBQx5y5PFK3LIUpi+
Ku59t06rK0C/ENenP3agtHkqdRStRNNfyL6SrtXUSIQ0BSguF4UCsJdSrbLOduGN5fmp7rRtK0V9
X8a4l/0QVTSExGUl1bmkXaUXeKraJABc4XQ087AtvDX5QBE3RDk2zBXagY9C5odgkel4SVbdbFF1
/EYfn8bdf2WRZ05Pr5hdqtghdvfnvKtMKEVBbZTKbx+J75GzwmcUeBe2YH2/fVB1yru9WqwiQpT6
cyY+5hDKkjqcLC02jJNfFS91bjoQPZuLXtlawDWjqJSkaH6ZSfAVh1nglsGsL02YUUVUy5sowIVo
7dsxOSCItpXx7wl23sfoT05tX3VRrO5jo79U+wV2GZEVXLbPVQBRcizRztEZUrzfLE3/+S+rE5wz
AVjIgJmj72TKMTF53qlJu+qYepbDs49gM/ijN35vRsbifIvk5LHjBqc6xYxyG4a4uyJ7RZB5LWZd
uJvc94X4PdgH0pV383uZ8jfHK8abTXpyyJJtli2zT0rzirwexUWIjjG7q/qB2tZgROd6a14KyELP
puqjaORX/xbOkBCp807ifylH0fasEP4JEcrFbreHfqDH5Jh4DJBeg9K8BlphNWV/aLazaUNTOPQV
+d2qcoGo9t/blL9X2TTX34uk5ZI+Gf+ICxniPPuMuT03Q7BCnZe1G5zmVS7kbexP4HcHyn5W99NN
HZVgOXFjQSGs0mGU1ZhzrxGyACshcrbMT191O2/5FmLpnMtVPlU1T/QKOnk0o06V1e+bWMZA5osn
plg8q6/SIZPPjZhtXwgvyDRsSHjTKAVCgFD5tadKMVbpn1FHLQjZrapoo22LXyqDeGl88AsWThqM
y1B7G34yGk0KjIx3Weo8bKvASabT/uv3pO8sTd/+0AEmPSqTDVe9MpHYxFdXrPDHyMFLO9MU68j7
UP8mlDM6ylB9TXEZv2ly58JJnOTtYlo/4N1L9Xk9vGcKqA2cMemDCBnYrufyE2jtQWt0v5RbYzY+
0lXeI3SyvXv8I2nj9wZoRWslMzAJJFcqKh612uko78AKkJxf3qeZboldLHvvGz7SJsQY7GCM37bv
JV9gmDJj1OPOSdcM40nrmcoHLnwWKt7LJ4/xrCd5VkZTkZsGkeArj4ywu69l13FxyoO11EHS/LoO
iXE2reHcSeOSi146eAFRIhs/4+q9YCGbjCr0pmRqfB8c6rbOlUWx5aHVbNhMS8C7ixLLZvOWbjRM
iqTAUQ+OsxReBn1D4qeWqV2E8hgCYr08uyu0PnN4rvtMEpJJC509DufqmxiE00NI44o8CdPDWok7
qKDMirdsbSu4IhHxC4XFns60gFAUhPDzhZ6sWwmw4+zR+Hoe2n6FfOY5eGlNunO5S80s0Ogu2B+k
h4lshj9XjhxveLOHy3k369NOAkfoEHr6/EhlK5yUYM/wCHE97hWImZIRQCM+wzMOcieilKK20HAK
6u4zOYTtDUHW/gWElGNOkVgfIXQFeRkx7mbwPv3vY46cd+0FchEevmLDGWE6A4DmSNQWN/RLhzj8
wMUUEIM4jBEDrIiZZH2oM9YY/qZq++GSPZjQGpKTJ8CaL7OrP6n5wS7va2xgFhh8PUzlOvX6nrbo
kFrFgdK2hAz9yuJQz2lEvLhSzgz+9XrWmTUht8V2OcixOYYtdu52Ulq/6ATxSh7aDjspSwOUw5/C
eLiCJfTYpX5J7V7kDWhN3LbLoW5RII5Eso/Kqn0cxMao8RV6fzGFqktody2tWcqNcV1rayB+vJHl
SVl1yc+IZa3c7QSpk9QEYXw+16QHeWiCvvLZf80GH8LxPES7c/inowUBn5o3iHspObiZ+W8DG8kV
eRHoaueNJ43NwV8BeQ21FOGVvyO/EcUwsj4sX0uo9OHhzMwkXWbBskMlOiRmfg/BmPl8GAPGh7cY
UlQwPVhsg0VTb9V+E1SUKT7E6gwwKJ6/eH04BLxQg6emv4elrxY7ndP8Uy2ZMDtzao1jmMCHQ3Iz
9ysMr0F7ibTrlxR21lspxwIDpLI5qVFqb4thkTCD/aZGdxET1zeoglRp6qaHh+R8JLlNn0+afTY2
plHhlCiNKqvoEk16Ly2wZpkY+/m9hJizb3t5UrVqmo1zjfHRQlN+Rl1sxz6T/C3XbK9le/We/aZc
79ugcgyfkkc8pj18FZ0Cvqhc8RaOAZAcrlibFtSzg7yZL2gL28HQvh/+Ld2v8/p1vYJxpiWnMlxS
d0E1HZuAAAHgBQc7kpfw667CFeNucI8pdpDnDoS2QlG+tTG+atXdVtP1wznfTKKIQF1MfqNh6jcg
v0B3TV3oyaF1d0qF2dFRikSm9M09joOT1h5M6z/svuoCHnVGmK/G474QHe5f0niHBck7Zloiphoj
MsBvzWsDPmFVckMhgoFpTgt2xm7SuJEI8fWLzk+4hhrEHhrW8HRtXppekAEfF8gd/89saYoh+VPr
IovOEi/U9vlC1pE89z3xg/jCDG9N6sh84jeMHVnlDoKAGbf07SgPHYdT4X52LQxvP2nV6MQfflWK
8Xq0thjKKjrRhx5Hj3TOyqbiML1vuBilJYKgrV24XFTsi1V/vgtmhGXfEF/7cYcET1l07b7LuM9A
+U792Jp6tLoCXEIH518VU8XAoOP41bT/5IV/5jTZZ4IeQ9TYs09gWkr7q4ai2BtFtDsEecMiyevZ
58FNoCGpkWWnDlAQ76rRB6NVTj4g+guVJV+VQy6QCO0v5M9dle+YVw0EOSRMkzoSck48nxTdq0lO
KbCG7XVE5gOzuv0inrasw78gpZPFPwFn+8K90Id8ceJpJ0lUvUhAbJYx+GlvxCO+oPgCCcnfRNiO
IT0H7a1H3VLhYqDA9HFISw6oflx3rK2ZIBmFJvWTWuAyYZDRjhRhSDw+Tha2xQN2qzlc1y/8NFiA
Nrn9yzQieLDvtWkSM4OD4h8NRUzDaQAkC0pdEQ0HXkdCtU7I/F3Sxgsf8F3rMzTef7Q5sgsLnAiz
/DiTUDVV0lcDvHqxRcsfcZQnBs0zXhHRpTAhsOPZmz81goivcOFod+QsMFs32sZpEfwEoPl04doO
binIzgwFe9+ppknV2Elqt8ckmtErTR2a5/eBEtJygsN2La/fw0Q6tzorGsVC1krdNIxflM4FssQi
Ij7EAX4HfMFQg9MNt/QWRsqkIR9Vyj0fBFpo+zG1D/kRshz6z6XYAQWvrG4T39pjNy0FRxRD5HAv
borK6KvihkCAB6KEIZ2GoY5Qj7PrrERKZ4t0LnvVBVRzikwuYdajexE0O3Mjtdjx+gIMHVEvMj77
/DqaZvVeAAhLuwUjYiUM7bIidFLNimvIgm9qrsOSazyzy+przVniJFakPGRU+vozEdRQym+5zzH9
lKanFbCXVP+B1qe/nrSO67O6jhvCqWNaRKjqQUXIFowckmk3n2vj85wEawcCvm3a+oHXyy1zluEc
9Zf1QtNfRDqvaIW7s9+1rNL8LGKt8V03wUSicf5dqj7SBC73ccagYhyafl91gd/EeCflDIQcFzZ5
pS+5cClGhha3zkPOVptmv8a4mtHC/APX2rsJe4hUQJ39ajZgOx8W9vA6VjAtVCk5PsfGG8cdn9Wr
eXiOftjjt8ytxNmVil8cCu0doHI2j1Gtyxcn4ytqu8LntqXTLC+i1PMXWEycGgwbSGuhLNxVpIWa
+7Pj0rbl0PnVQ/5KsB7ikKqm7ffEuFyUN/bpsJdX8VnMj8jWtS63fCIAFtCztWzM/eWUUUTyWlQY
R+CpmIePs9tbEQ1RKqhAY0IbTOrRXEPJpYoICheEpv7Mc6QfieEhXopKckGQZTRnj11B39bC703G
sPKZ8OLaeCd8ZEY1b6d3mVxEKozC12vLtF3GEVShXS8rxII5j1yWEBtXS3Z9AKtxXv3r5THP0hXU
EUSv+HNGApyIqB0qbPzMVJKX1i+wzc4Kh3ORcQqyat23QDfeOL/AiisHLpNYxoAF48hKrSxMffXX
GJCTV8eAG4bOpNEuXIouTsP3qRVEX/lzsxsYw5b2LYKQmHgkfUHdUzOQNekxEs/RH2KHBizocu1G
DiVVoD6ImI7xeqvcZA68dvDJsJqZsEQuDP/h9WYoON+y4aygZWTgokWYdsydCg2/DryAQgtkg57N
LvH7aS0UEp414QXYeifK98iq0PqkNSGcIh9OQQhYVMPhE50p+jl6Zh5iW81VOAc2nxMb80/K8BMs
xd1/qzV2MnJrGJDha0jgQd6cOCQA7HVC0+UDphLuSf5m5lmdI35Jd+y9L+nHWn0ReOfZigbjxx7R
p0fc5U+E1lGSaZwwgteOUWF7J/uq0yAJzkf/UvcR92bsTasBvRXghoSLeZjPErSz+uwrYj7s6GBM
a5TPvdYdnn8yXzMJBnsXUMz7kZqE647uwjqQ7x0uoAhdQ2ZNCoCIjAEadbBMMUnFUWiotZJDqcQi
WU++T6zlFzLWtQkh14KXU0ZDWuWd8cl+gzR2rVtpcfRAlRQleseT2kNeP3bG2gblZJRFXEsRGuAK
ubQhWIRzrjeQUf/oYBuvYY6U6B9LLVXzV6yaBjTr4EVHlfz6QFjKbmTArEcUim9HBnJaQUyvG0g7
sbXoBKSSbRYeSfy69Va2gs1q5XDcFbBpFJRPkvF2cmCziVoChUgrrjqTYhMk8YvtpOdfiSpW3Gpd
gzWxbC+dJiq7g/vXsmhesWUZMxFPztMLqvYx5E3XD3K6LMjTbFB4Wuy3SrNMD4x0TbNn3vFKtVng
ERo1TFyx+TlTpxkDsFLmsV6kngQYt5pEbHyMykSfj6xdrx34dL8zvgpSRxwn4g9k/ereRszMs+sA
sxHkr/cXegUMuqh6Fel6YpOAGn+0MN2b74k+pJfmYIKiiZrF08PEt5zVxXo/rxZNCeXZtXyc+S7Z
rkAaBPSRWZdL7f2+scywLJ8yFdst3EemFu10IUHZPBYvKrL0pqyS/kdH789LBqjxfwI24M47lSeb
CMySuuoZJEGsXnv3PpDUBagei58IOZsScOsaI/UH+tjuxFsqR25r+ksdpzB+E34NcYFBnj9LjGHi
uKNNL6YsTjbAPX3pLPG5oyo/5iwlbgZ6O1qIDUCQhHF+JH9crbdImm5kuYea/bFIsCWl7BCfPcLl
c9DckMNSLFs2b/7pE4unN/oN0HIefV5KBXxZrE/Hm5rAumPrs9LxAcYvzQs7QIV9gX4735ePnrAc
BTaSgn38G87GNrGMx+i0BrIcvNgNa2U+vbk5TO4haN1DDdaeoCtppisR/7GLDMjvJ6wW7Qt0pLYX
4B56yFvMHs31JlWEoAcBpi+bHx89uQ7tbblPznGcQTWhV5HTWuuk+JMxV+MT1QpJgSy0CU1cGaLs
VtzQ8RMB5IH2m1BquO1W/V9zp0dmH6Z0Nk4sulOgxmWlJEJaEQfrVMhc7vJ6fZTAvG4SM/Eq5tjj
VLHJZ62tHB18t2ylM/gIPcPduStUXywMwyTY+HK2VrNwqUq8AUe9Swawk7TUHYRs56Y/2w9LssZi
kSxArBo1BKuvI/5gEPGQvAdQ7u0jAmaemZfWTKXinxouY9o24b3AVo3b6ditbZU69NJFfZhzrxfz
3cj6QVtHnA7r8A1DizyI6kUbJyxhS5h+2mzixWFJ92tItTRB9S1VUndrIAYc3tKn8jJrAk4648MM
gzsl26vxxbEoZFSevEDUcQ01+cJ8LhZNqcrltC2wVkQwO1odb0P+cDfw6MogK8fKWb2G5kC+vhK3
DEbsAQb794Mq+is5Pus7P2uMJbpY+7wenSrqE1rSKto5qTAzrs/vVVE4tptCgCw80Jtm58FNSDxj
uyg0tkLOoK3tPbhBlXwDj7A1m++3a3wvEbEZFJ0kM7tHqNN3zO472T/zLEOAB8A8foZN5pv7Omgd
xmktUjYsrbnquyajyJoutBKYiA8j55P9ezn7Ie5/eauyRCYEwrazS74vyUDUB0ZYg2eYRgpWN7uB
Q3nL/WgjwDVTb2mwl5UUkA/cOs9Qqb9lj+2M1nvhT6T+P/1nRrkKS8iN6zqot3cmukjFLnT+/Sm4
eJRIx9JnfyGJwHKwtU5Y1FriIP9MnGMyvSWAFGGvo+QPZtjiSvaTNMgB0wGmdpzUjNvwejNPXCim
L1OGp/TMqK/r/pMbd3+aIKeQlM7p1CM6tImjRm3SnnRlMSS9yt1C6oleeotWtiJPwGpuQ6K/0QqY
v5532/S7KgoxvlrnR7D4T1CJ1o8LEGH2OCpV9QegZkN/pwI0Pd0TFbG4XwEt5P0DN4jCn2qYVBYO
+sYfVNJDEjOa3dkK4IcYh4QSkl/rNxMoBe6ffRRRxh3q1BFJ0N4KRlrKufuXUnCM7TUcGxtOYSBY
9659MIqKOZ2W11XaGnbFevtsvFO7lxLo0zV59lBAnC5afc57HH5NwUjDl8SvxR3v0BwhXvSzkFDk
8V89qDA5mbkXa99TUCtPqR5BCn8uHsnroE3dgZVNwrj4E9e5x7ecLpZjakhXm9mQrVf++2v5Z5wK
LfN/VZINlOeL2FI3xpcgVh1y64nzWA3aVIICU4rmslQt9yXwAa1vu5vNcXc2MFNbIAz69+iFsawU
oH882OSbOmqU4TmMwi74T2s8e29baudRAtIfcYTRH6BRoLQ7eFFMC1N3YjvR6v31c6AwGYDSn02/
2+BMAbLDKKChPK8TjgBNgBE1Q3rZZIhnyJjaY0DxNPRXP+cZRyAI/YTUXrXH6pZHAxnLGzpXyhVh
61jaffFJC7RtRTgizmvRPlAsw72Egd772IC26l6xzebck4FfwviIizkL5SCp8balXo6MO8FDS4aX
jM2eV27DRyv6+m+f0s89zCMrlxgo8n37E6E0wYaSh9Kxj5Nt4CD3Bibz9LppomYHGU8JmjcfEb19
Ysz59hf7PHKVdcrdTh3+4+9r5CVFvYpFGYvJGWcpd1e/D8sjT0fgjbU9HTKNJ+oliyIatkbGmgQr
/lP4WFf3FsehdNX7tlBBfFP63V24IUU7MDB0Cn73xgyG5W7zLRJ8+AEJjndySJp6nWkEU65F7AJC
0jyO38L4fcc4ogAbjaQFSu3Sz2jKYnHuocwKHktWRXQkx7MV4XKU0AfxSys5CRT58tuayO4To13F
eIw8zGmAfKno6EmCpvYsprNOTmvzSifcgC3hKs5WwTBFi+Vqg4COujZo3s2aNEVTKzEzCosFQ5dX
KJdWtkmDmVXPp9JXLLC5O2LhcUVKKqMVUToI6WnLgMI4XnYbKBEsGhV3KGI8asuuN1P6tnp4pcoz
yGN7W8G4rd7hgBXPNFrE8Do0XyDGChh1s0W+HXXnVa4/H1hTYFhxNI2iBZQnJWBr3vNWfY6RJtuV
qzZ9Dr/5y0dZmdZhv+HzyFvkGcZJavqTfmWrfzCpl3HnAs22277zB8IElTi2asgLtpJWw5tnpHIh
KAe/kd5oCuDf1qD8Cj9w+K5VtWSUuYUa6AKVScBIJPkpyboXG5ivZwY3Bozd+iKq7BCkOuxwwm1k
clsQmBNmjg+1ubuIBxs+vD/dcMVv9i47CcP2s29eATkcu3b0ds923ML+o+Knb0vI7mj6WjTmUTVs
FwEyXGwyfFbVtmuZWFExAPFodzfH5yH4GivMI0fum12++d6HA8wwP4FylVRE/TuosCRhfNDrMjQ+
Yi49+iXiOURhiS85j3w0QyJyHYjFMEmZk9WYmTquMrHRkUbQ+WdUeqKhUnalJHt3C4Uv6AXGDdad
Oa59sjsDuqQqjh5dXWPv6eujUZCqvP9Mf5t4TEribpCuats0/Wt05HB8GEy4VAJTsSxcNId2SJAs
dpWrfVlWdJ8XVwoP8/Cpt38vTeLwxkdOKfHjzYBwmtQAmWxvgEvZ/0cUdnY4n2lt92gpXVT1MC87
61Jo6//ivN1C47gf4NBUIebu9zts/CWoYw3YhckyY9h3Q/sIvRNPjsql+Xy2CR1Vfszh4JS4owSX
4bHSnjAsLXBiHoufUynkDri6Hnv+60I67UyEfElsBlHmKuV/ZIo7zXoT+vNW061HSFVocnxQGUkK
5FDYy/KQOdvEPMJlm4zuUbxkRyRBCG8AoexwJyKEiYicEVtvHEcNu6A8MJ+3paG+Q844EeEqxsS8
wCIEs5IronK3WpyOfprGH6/TnFP733R8NYt4FuZ+hGarhdX+C+7rHFV/f+Y5DOZnhpC9l3GI27N1
3ZhGy2EDke8JtH597iCbRKkT3fxZUGVddLgHeYkO6aMcDD0Gxz5Q0rzJDhKS7nEkOugLPPDpUQNl
7GA4QT8L9y1nngKYE6f7TMyPkpFOby0GmYFdztyPcUiWVFOEptCIQ9rb4SNR2C2nzzL3dcmrh1cw
JbddBb0ooFBtCs2rTVSivNksoCAykxHoBFdlhqJwwC0olT3MxWZwQ/claeO4nnqYRAJf/w/H27VD
fNqvz4EqrKxUgXJyPw==
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_proc_sys_reset_0_0/synth/OpenSSD2_proc_sys_reset_0_0.vhd | 4 | 6692 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_0_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_0_0_arch OF OpenSSD2_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_proc_sys_reset_0_0_arch : ARCHITECTURE IS "OpenSSD2_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "OpenSSD2_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_0_0_arch;
| gpl-3.0 |
luebbers/reconos | core/pcores/burst_ram_v2_01_a/hdl/vhdl/ram_single.vhd | 1 | 11415 | --
-- \file ram_single.vhd
--
-- Single-Port parametrizable local RAM block
--
-- Port A is thread-side, port b is osif-side.
--
-- Possible combinations of generics:
--
-- G_PORTA_DWIDTH = 32 (fixed)
-- G_PORTB_DWIDTH = 64 (fixed)
--
-- G_PORTA_AWIDTH | G_PORTB_AWIDTH | size
-- ----------------+----------------+-----
-- 10 | 9 | 4kB
-- 11 | 10 | 8kB
-- 12 | 11 | 16kB
-- 13 | 12 | 32kB
-- 14 | 13 | 64kB
--
-- To enable the use of byte enable signals from Port B, symmetric BRAM
-- blocks must be used, which are then multiplexed on the read port of
-- Port A to realize the lower data bus width:
--
-- _____ ____
-- _______| |________ sel | |
-- | 8 |_____| 8 | ------| FF |<--- addra(0)
-- | | | |____|
-- | ... |------- |
-- | _____ | 32 | |
-- |_______| |________| | |\
-- | 8 |_____| 8 | | \
-- 64 | ---|0|
-- -------| | |-------------> douta
-- | _____ ---|1|
-- |_______| |________ | | /
-- | 8 |_____| 8 | | |/
-- | | |
-- | ... |-------
-- | _____ | 32
-- |_______| |________|
-- 8 |_____| 8
--
-- Note that the sel signal for the read multiplexer must be delayed to match
-- the read delay of the synchronous BRAMs.
--
-- \author Enno Luebbers <[email protected]>
-- \date 11.05.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library reconos_v1_02_a;
--use reconos_v1_02_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram_single is
generic (
-- address and data widths, THREAD-side and OSIF-side
G_PORTA_AWIDTH : integer := 10;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTB_AWIDTH : integer := 10;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 0 -- use BEs on port B
);
port (
-- A is thread-side, AX is secondary thread-side, B is OSIF-side
addra : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrb : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
clka : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); -- these widths are fixed
dinb : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
douta : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutb : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
wea : in std_logic;
web : in std_logic;
ena : in std_logic;
enb : in std_logic;
beb : in std_logic_vector(G_PORTB_DWIDTH/8-1 downto 0)
);
end ram_single;
architecture Behavioral of ram_single is
--== DERIVED CONSTANTS ==--
-- RAM size derived from Port A
constant C_PORTA_SIZE_BYTES : natural := 2**G_PORTA_AWIDTH * (G_PORTA_DWIDTH/8);
-- RAM size derived from Port B
constant C_PORTB_SIZE_BYTES : natural := 2**G_PORTB_AWIDTH * (G_PORTB_DWIDTH/8);
constant C_RAM_SIZE_KB : natural := C_PORTA_SIZE_BYTES / 1024;
-- number of BRAM blocks
constant C_NUM_BRAMS : natural := C_RAM_SIZE_KB / 2;
-- thread-side data width of a single BRAM block
constant C_PORTA_BRAM_DWIDTH : natural := G_PORTA_DWIDTH / C_NUM_BRAMS;
constant C_PORTB_BRAM_DWIDTH : natural := G_PORTB_DWIDTH / C_NUM_BRAMS;
-- ratio of data widths
constant C_BRAM_DWIDTH_RATIO : natural := C_PORTB_BRAM_DWIDTH / C_PORTA_BRAM_DWIDTH; -- always 2
-- BRAM wrapper component
component bram_wrapper is
generic (
G_PORTA_DWIDTH : natural := 8;
G_PORTB_DWIDTH : natural := 16;
G_PORTA_AWIDTH : natural := 11;
G_PORTB_AWIDTH : natural := 10
);
port (
DOA : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DOB : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ADDRA : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
ADDRB : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DIB : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic;
WEB : in std_logic
);
end component;
subtype bram_vec_array_t is std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
-- helper signals for BRAM connection
signal dina_tmp : bram_vec_array_t;
signal douta_tmp : bram_vec_array_t;
signal ena_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal wea_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal enb_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal web_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal sel : std_logic; -- selector for PORTA BRAM multiplexer
begin
-- check generics for feasibility
assert G_PORTA_DWIDTH = 32
report "thread-side (PORTA) data width must be 32"
severity failure;
assert G_PORTB_DWIDTH = 64
report "OSIF-side (PORTB) data width must be 64"
severity failure;
-- this will not catch two-port/14 bit, which is not supported)
assert (G_PORTA_AWIDTH >= 10) and (G_PORTA_AWIDTH <= 14)
report "PORTA must have address width between 10 and 14 bits"
severity failure;
-- this will not catch two-port/9 bit, which is not supported)
assert (G_PORTB_AWIDTH >= 9) and (G_PORTA_AWIDTH <= 13)
report "PORTB must have address width between 9 and 13 bits"
severity failure;
assert (G_PORTB_AWIDTH = G_PORTA_AWIDTH-1)
report "PORTB must have an address width one greater than that of PORTA"
severity failure;
assert C_PORTA_SIZE_BYTES = C_PORTB_SIZE_BYTES
report "combination of data and address widths impossible"
severity failure;
assert (G_PORTB_USE_BE = 0) or (C_PORTB_BRAM_DWIDTH <= 8)
report "port B byte enables cannot be used with this memory size"
severity failure;
-- generate enable signals from byte enables for PORTB
WITH_BE: if G_PORTB_USE_BE /= 0 generate
PORTB: for i in C_NUM_BRAMS-1 downto 0 generate
enb_tmp(i) <= beb(i/(8/C_PORTB_BRAM_DWIDTH)) and ENB;
web_tmp(i) <= beb(i/(8/C_PORTB_BRAM_DWIDTH)) and WEB;
end generate;
end generate;
WITHOUT_BE: if G_PORTB_USE_BE = 0 generate
PORTB: for i in C_NUM_BRAMS-1 downto 0 generate
enb_tmp(i) <= ENB;
web_tmp(i) <= WEB;
end generate;
end generate;
-- generate enable/write enable signals for PORTA
TOP_HALF : for i in C_NUM_BRAMS-1 downto C_NUM_BRAMS/2 generate
ena_tmp(i) <= ENA and addra(0);
wea_tmp(i) <= WEA and addra(0);
end generate;
BOTTOM_HALF : for i in (C_NUM_BRAMS/2)-1 downto 0 generate
ena_tmp(i) <= ENA and not addra(0);
wea_tmp(i) <= WEA and not addra(0);
end generate;
-- delay multiplexer select signal for one cycle to match BRAM delay
sel_delay_proc: process(clka)
begin
if rising_edge(clka) then
sel <= addra(0);
end if;
end process;
-- multiplex PORTA RAM output
douta <= douta_tmp((G_PORTA_DWIDTH*2)-1 downto G_PORTA_DWIDTH) when sel = '1' else
douta_tmp( G_PORTA_DWIDTH -1 downto 0);
dina_tmp((G_PORTA_DWIDTH*2)-1 downto G_PORTA_DWIDTH) <= dina;
dina_tmp( G_PORTA_DWIDTH -1 downto 0) <= dina;
-- instantiate RAMs
rams: for i in C_NUM_BRAMS-1 downto 0 generate
bram_inst : bram_wrapper
generic map (
G_PORTA_DWIDTH => C_PORTB_BRAM_DWIDTH,
G_PORTA_AWIDTH => G_PORTB_AWIDTH,
G_PORTB_DWIDTH => C_PORTB_BRAM_DWIDTH,
G_PORTB_AWIDTH => G_PORTB_AWIDTH
)
port map (
DOA => douta_tmp((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
-- douta((i+1)*C_PORTA_BRAM_DWIDTH-1 downto i*C_PORTA_BRAM_DWIDTH),
DOB => doutb((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
ADDRA => addra(G_PORTA_AWIDTH-1 downto 1),
ADDRB => addrb,
CLKA => clka,
CLKB => clkb,
DIA => dina_tmp((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
-- dina((i+1)*C_PORTA_BRAM_DWIDTH-1 downto i*C_PORTA_BRAM_DWIDTH),
DIB => dinb((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
ENA => ena_tmp(i),
ENB => enb_tmp(i),
SSRA => '0',
SSRB => '0',
WEA => wea_tmp(i),
WEB => web_tmp(i)
);
end generate; -- rams
end Behavioral;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_if.vhd | 7 | 11332 | -------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
entity ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end entity ac97_if;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of ac97_if is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component ac97_core;
component ac97_command_rom is
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end component ac97_command_rom;
signal pcm_playback_accept_ac97clk : std_logic;
signal pcm_playback_accept_ClkIn_0 : std_logic;
signal pcm_playback_accept_ClkIn_1 : std_logic;
signal pcm_playback_accept_ClkIn : std_logic;
signal pcm_record_valid_ac97clk, pcm_record_valid_ClkIn_0, pcm_record_valid_ClkIn_1 : std_logic;
signal pcm_record_valid_ClkIn : std_logic;
signal command_addr : std_logic_vector(6 downto 0);
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal codec_rdy : std_logic;
signal debug_i : std_logic_vector(3 downto 0);
signal reg_write_strobe_ac97, reg_busy_ac97, reg_error_ac97 : std_logic;
signal get_next_command : std_logic;
signal valid_command : std_logic;
signal command_num : unsigned(3 downto 0) := "0000";
type read_access_states is (AC97_READY, WARM_START,
REVIEW_COMMAND,ISSUE_COMMAND,
WAIT_COMMAND, NEXT_COMMAND,
READ_COMMAND, DONE);
signal command_SM : read_access_states;
signal reset_counter : unsigned(10 downto 0) := (others => '0');
signal AC97Reset_n_i : std_logic := '0';
signal rom_data : std_logic_vector(24 downto 0);
signal command_addr_i : std_logic_Vector(3 downto 0);
signal start_frame_delay : natural range 0 to 3 := 0;
attribute rom_style: string;
--attribute rom_style of ac97_command_rom: entity is "distributed";
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Command loading
-----------------------------------------------------------------------------
load_commands_SM_PROCESS : process (AC97clk) is
begin
if AC97clk'event and AC97clk = '1' then
if Reset = '1' then
command_SM <= AC97_READY;
command_num <= "0000";
else
case command_SM is
-- Issue some reset?
when AC97_READY =>
-- wait until codec is ready
if codec_rdy = '1' then
command_SM <= REVIEW_COMMAND;
start_frame_delay <= 0;
end if;
when WARM_START =>
if pcm_playback_accept_ac97clk = '1' then
if start_frame_delay = 3 then
command_SM <= REVIEW_COMMAND;
else
start_frame_delay <= start_frame_delay + 1;
end if;
end if;
when REVIEW_COMMAND =>
-- if command is valid, go on to issue command. otherwise, go to
-- end state.
if valid_command = '1' then
command_SM <= ISSUE_COMMAND;
else
command_SM <= DONE;
end if;
when ISSUE_COMMAND =>
-- strobe is issued in output forming logic
command_SM <= WAIT_COMMAND;
when WAIT_COMMAND =>
if reg_busy_ac97 = '0' then
command_SM <= NEXT_COMMAND;
end if;
-- error processing?
when NEXT_COMMAND =>
command_SM <= READ_COMMAND;
command_num <= command_num + 1;
when READ_COMMAND =>
command_SM <= REVIEW_COMMAND;
when DONE =>
-- do nothing
when others => NULL;
end case;
end if;
end if;
end process;
reg_write_strobe_ac97 <= '1' when command_SM = ISSUE_COMMAND else
'0';
get_next_command <= '1' when command_SM = NEXT_COMMAND else
'0';
-- ClkIn processes
-- The AC97 reset signal needs to be driven by ClkIn
-- (AC97 clock does not operate when reset asserted)
reset_process : process (ClkIn) is
begin
if Reset = '1' then
reset_counter <= (others => '0');
AC97Reset_n_i <= '0';
elsif ClkIn'event and ClkIn='1' then
if reset_counter(10) = '1' then
AC97Reset_n_i <= '1';
else
reset_counter <= reset_counter+1;
AC97Reset_n_i <= '0';
end if;
end if;
end process;
AC97Reset_n <= AC97Reset_n_i;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_playback_accept_ClkIn_0 <= pcm_playback_accept_ac97clk; -- async
pcm_playback_accept_ClkIn_1 <= pcm_playback_accept_ClkIn_0;
pcm_playback_accept_ClkIn <= pcm_playback_accept_ClkIn_0 and not pcm_playback_accept_ClkIn_1;
end if;
end process;
PCM_Playback_Accept <= pcm_playback_accept_ClkIn;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_record_valid_ClkIn_0 <= pcm_record_valid_ac97clk; -- async
pcm_record_valid_ClkIn_1 <= pcm_record_valid_ClkIn_0;
pcm_record_valid_ClkIn <= pcm_record_valid_ClkIn_0 and not pcm_record_valid_ClkIn_1;
end if;
end process;
PCM_Record_Valid <= pcm_record_valid_ClkIn;
-----------------------------------------------------------------------------
-- Command ROM
-----------------------------------------------------------------------------
ROM : ac97_command_rom
port map (
ClkIn => AC97Clk,
ROMAddr => command_addr_i,
ROMData => rom_data
);
command_addr_i <= CONV_STD_LOGIC_VECTOR(command_num, 4);
write_data <= rom_data(15 downto 0);
command_addr <= rom_data(22 downto 16);
valid_command <= rom_data(24);
-- debug_i(0) <= codec_rdy;
-- debug_i(1) <= '1' when command_SM = DONE else
-- '0';
-- debug_i(2) <= AC97Reset_n_i;
-- debug_i(3) <= reg_error_ac97;
debug_i <= command_addr_i;
debug <= debug_i;
-----------------------------------------------------------------------------
-- Instantiating the core
-----------------------------------------------------------------------------
ac97_core_I : ac97_core
port map (
Reset => Reset,
AC97_Bit_Clk => AC97Clk,
AC97_Sync => Sync,
AC97_SData_Out => SData_Out,
AC97_SData_In => SData_In,
AC97_Reg_Addr => command_addr,
AC97_Reg_Write_Data => write_data,
AC97_Reg_Read_Data => open, -- No reading from AC97
AC97_Reg_Read_Strobe => '0', -- No reading from AC97
AC97_Reg_Write_Strobe => reg_write_strobe_ac97, -- do
AC97_Reg_Busy => reg_busy_ac97, -- do
AC97_Reg_Error => reg_error_ac97, -- do
AC97_Reg_Read_Data_Valid => open, -- No reading from AC97
PCM_Playback_Left => PCM_Playback_Left, -- async
PCM_Playback_Right => PCM_Playback_right, -- async
PCM_Playback_Left_Valid => '1',
PCM_Playback_Right_Valid => '1',
PCM_Playback_Left_Accept => pcm_playback_accept_ac97clk,
PCM_Playback_Right_Accept => open, -- use left_accept
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => pcm_record_valid_ac97clk,
PCM_Record_Right_Valid => open, -- use left_valid
CODEC_RDY => codec_rdy
);
-- leds(3) <= not codec_rdy; -- and (command_SM = DONE);
-- leds(2) <= '0' when command_SM = INIT else '1';
-- leds(1) <= '0';
-- leds(0) <= AC97Clk; -- '0' when command_SM = DONE else '1';
end architecture IMP;
| gpl-3.0 |
makestuff/vhdl | serialio/serialio.vhdl | 1 | 4652 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serialio is
port(
reset_in : in std_logic;
clk_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
load_in : in std_logic;
turbo_in : in std_logic;
busy_out : out std_logic;
sData_out : out std_logic;
sData_in : in std_logic;
sClk_out : out std_logic
);
end entity;
architecture behavioural of serialio is
type StateType is (
STATE_WAIT_FOR_DATA, -- idle state: wait for CPU to load some data
STATE_SCLK_LOW, -- drive LSB on sData whilst holding sClk low
STATE_SCLK_HIGH -- drive LSB on sData whilst holding sClk high
);
signal state, state_next : StateType;
signal shiftOut, shiftOut_next : std_logic_vector(7 downto 0); -- outbound shift reg
signal shiftIn, shiftIn_next : std_logic_vector(6 downto 0); -- inbound shift reg
signal inReg, inReg_next : std_logic_vector(7 downto 0); -- receive side dbl.buf
signal sClk, sClk_next : std_logic; -- serial clock
signal cycleCount, cycleCount_next : unsigned(5 downto 0); -- num cycles per 1/2 bit
signal bitCount, bitCount_next : unsigned(2 downto 0); -- num bits remaining
constant CLK_400kHz : unsigned(5 downto 0) := "111011"; -- count for 400kHz clk
constant CLK_24MHz : unsigned(5 downto 0) := "000000"; -- count for 24MHz clk
begin
-- All change!
process(clk_in, reset_in)
begin
if ( reset_in = '1' ) then
state <= STATE_WAIT_FOR_DATA;
shiftOut <= (others => '0');
shiftIn <= (others => '0');
inReg <= (others => '0');
sClk <= '1';
bitCount <= "000";
cycleCount <= (others => '0');
elsif ( clk_in'event and clk_in = '1' ) then
state <= state_next;
shiftOut <= shiftOut_next;
shiftIn <= shiftIn_next;
inReg <= inReg_next;
sClk <= sClk_next;
bitCount <= bitCount_next;
cycleCount <= cycleCount_next;
end if;
end process;
-- Next state logic
process(state, data_in, load_in, turbo_in, shiftOut, shiftIn, inReg, sData_in, sClk, cycleCount, bitCount)
begin
state_next <= state;
shiftOut_next <= shiftOut;
shiftIn_next <= shiftIn;
inReg_next <= inReg;
sClk_next <= sClk;
cycleCount_next <= cycleCount;
bitCount_next <= bitCount;
busy_out <= '1';
case state is
-- Wait for the CPU to give us some data to clock out
when STATE_WAIT_FOR_DATA =>
busy_out <= '0';
sClk_next <= '1';
sData_out <= '1';
if ( load_in = '1' ) then
-- The CPU has loaded some data...prepare to clock it out
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
shiftOut_next <= data_in;
bitCount_next <= "111";
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
end if;
-- Drive bit on sData, and hold sClk low for four cycles
when STATE_SCLK_LOW =>
sClk_next <= '0'; -- keep sClk low by default
sData_out <= shiftOut(0);
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move on to STATE_SCLK_HIGH
state_next <= STATE_SCLK_HIGH;
sClk_next <= '1';
shiftIn_next <= sData_in & shiftIn(6 downto 1);
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
if ( bitCount = 0 ) then
inReg_next <= sData_in & shiftIn(6 downto 0);
end if;
end if;
-- Carry on driving bit on sData, hold sClk high for four cycles
when STATE_SCLK_HIGH =>
sClk_next <= '1';
sData_out <= shiftOut(0);
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move back to STATE_SCLK_LOW or STATE_WAIT_FOR_DATA
shiftOut_next <= "0" & shiftOut(7 downto 1);
bitCount_next <= bitCount - 1;
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
if ( bitCount = 0 ) then
-- This was the last bit...go back to idle state
busy_out <= '0';
bitCount_next <= "111";
if ( load_in = '1' ) then
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
shiftOut_next <= data_in;
else
state_next <= STATE_WAIT_FOR_DATA;
sClk_next <= '1';
end if;
else
-- This was not the last bit...do another clock
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
end if;
end if;
end case;
end process;
sClk_out <= sClk;
data_out <= inReg;
end architecture;
| gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/XADC_Demo/src/hdl/UART_TX_CTRL.vhd | 4 | 4590 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| gpl-3.0 |
luebbers/reconos | core/pcores/osif_tlb_v2_01_a/hdl/vhdl/osif_tlb.vhd | 1 | 2855 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_tlb_v2_01_a;
use osif_tlb_v2_01_a.all;
entity osif_tlb is
generic
(
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
-- tlb interface
o_tlb_rdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_wdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_tag : in std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
o_tlb_match : out std_logic;
i_tlb_we : in std_logic;
o_tlb_busy : out std_logic;
--o_tlb_wdone : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH - 1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end entity;
architecture imp of osif_tlb is
signal tlb_invalidate : std_logic;
begin
i_tlb : entity osif_tlb_v2_01_a.tlb
port map
(
clk => sys_clk,
rst => sys_reset,
i_tag => i_tlb_tag,
i_data => i_tlb_wdata,
o_data => o_tlb_rdata,
i_we => i_tlb_we,
o_busy => o_tlb_busy,
--o_wdone => o_tlb_wdone,
o_match => o_tlb_match,
i_invalidate => tlb_invalidate
);
i_tlb_dcr : entity osif_tlb_v2_01_a.tlb_dcr
generic map
(
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH
)
port map
(
clk => sys_clk,
rst => sys_reset,
o_invalidate => tlb_invalidate,
-- dcr bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite
);
end architecture;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_proc_sys_reset_3_0/synth/OpenSSD2_proc_sys_reset_3_0.vhd | 4 | 6692 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_3_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_3_0_arch OF OpenSSD2_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_proc_sys_reset_3_0_arch : ARCHITECTURE IS "OpenSSD2_proc_sys_reset_3_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "OpenSSD2_proc_sys_reset_3_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_3_0_arch;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_proc_sys_reset_3_0/synth/OpenSSD2_proc_sys_reset_3_0.vhd | 4 | 6692 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_3_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_3_0_arch OF OpenSSD2_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_proc_sys_reset_3_0_arch : ARCHITECTURE IS "OpenSSD2_proc_sys_reset_3_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "OpenSSD2_proc_sys_reset_3_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_3_0_arch;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBDCFIFO64x16DR/synth/DPBDCFIFO64x16DR.vhd | 8 | 38573 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBDCFIFO64x16DR IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END DPBDCFIFO64x16DR;
ARCHITECTURE DPBDCFIFO64x16DR_arch OF DPBDCFIFO64x16DR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBDCFIFO64x16DR_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DPBDCFIFO64x16DR_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DPBDCFIFO64x16DR_arch : ARCHITECTURE IS "DPBDCFIFO64x16DR,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DPBDCFIFO64x16DR_arch: ARCHITECTURE IS "DPBDCFIFO64x16DR,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=3,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 3,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBDCFIFO64x16DR_arch;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/standalone/TESTBENCH_standalone.vhd | 4 | 2619 | -------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:26:29 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_standalone is
end TESTBENCH_standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_standalone is
component standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic; -- master clock for design
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal bit_clk, sync, sdata_out, sdata_in : std_logic;
signal ac97_reset_n, fast_clk, reset_n : std_logic;
begin -- behavioral
clk_PROCESS : process is
begin
fast_clk <= '0';
wait for 5 ns;
fast_clk <= '1';
wait for 5 ns;
end process;
reset_PROCESS : process is
begin
reset_n <= '0';
wait for 5 us;
reset_n <= '1';
wait;
end process;
uut : standalone
port map (
ClkIn => fast_clk,
Reset_n => reset_n,
LED => open,
Debug => open,
AC97Reset_n => ac97_reset_n,
AC97Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut_1 : ac97_model
port map (
-- CODEC signals
AC97Reset_n => ac97_reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
end behavioral;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_if.vhd | 4 | 3256 | -------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_standalone is
end TESTBENCH_standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_standalone is
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal bit_clk, sync, sdata_out, sdata_in : std_logic;
signal ac97_reset_n, fast_clk, reset : std_logic;
signal pcm_play_left, pcm_play_right : std_logic_vector(15 downto 0);
signal pcm_record_left, pcm_record_right : std_logic_vector(15 downto 0) := (others => '0');
begin -- behavioral
clk_PROCESS : process is
begin
fast_clk <= '0';
wait for 5 ns;
fast_clk <= '1';
wait for 5 ns;
end process;
reset_PROCESS : process is
begin
reset <= '1';
wait for 5 us;
reset <= '0';
wait;
end process;
uut : ac97_if
port map (
ClkIn => fast_clk,
Reset => reset,
PCM_Playback_Left => pcm_play_left,
PCM_Playback_Right => pcm_play_right,
PCM_Playback_Accept => open,
PCM_Record_Left => pcm_record_left,
PCM_Record_Right => pcm_record_right,
PCM_Record_Valid => open,
Debug => open,
AC97Reset_n => ac97_reset_n,
AC97Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut_1 : ac97_model
port map (
-- CODEC signals
AC97Reset_n => ac97_reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
end behavioral;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/command_fifo.vhd | 4 | 28631 | -------------------------------------------------------------------------------
-- $Id: command_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename:
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
use UNISIM.vcomponents.all;
entity command_fifo is
port (
Clk : in std_logic;
Reset : in std_logic;
NextCommand : in std_logic;
CommandNum : out std_logic_vector(8 downto 0);
Data : out std_logic_vector(15 downto 0);
Address : out std_logic_vector(6 downto 0);
ValidCommand: out std_logic
);
end entity command_fifo;
-- Commands for AC97:
-- WriteAC97Reg(0x0,0x0); // reset registers
-- WriteAC97Reg(0x2,0x808); // master volume (0db gain)
-- WriteAC97Reg(0xa,0x8000); // mute PC beep
-- WriteAC97Reg(0x4,0x808); // headphone vol (aux out)
-- WriteAC97Reg(0x18,0x808); // pcmoutvol (amp out line)
-- WriteAC97Reg(0x1a,0x404); // record source (line in for left and right)
-- WriteAC97Reg(0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
-- WriteAC97Reg(0x20,0x1); // bypass 3d sound
-- 80000000
-- 80020808
-- 800a8000
-- 80040808
-- 80180808
-- 801a0404
-- 801c0008
-- 80200001
-- 80200001801c0008801a04048018080880040808800a80008002080880000000
architecture IMP of command_fifo is
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0a : string;
attribute INIT_0b : string;
attribute INIT_0c : string;
attribute INIT_0d : string;
attribute INIT_0e : string;
attribute INIT_0f : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1a : string;
attribute INIT_1b : string;
attribute INIT_1c : string;
attribute INIT_1d : string;
attribute INIT_1e : string;
attribute INIT_1f : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2a : string;
attribute INIT_2b : string;
attribute INIT_2c : string;
attribute INIT_2d : string;
attribute INIT_2e : string;
attribute INIT_2f : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3a : string;
attribute INIT_3b : string;
attribute INIT_3c : string;
attribute INIT_3d : string;
attribute INIT_3e : string;
attribute INIT_3f : string;
attribute INIT_00 of u1 : label is
"80200001801c0008801a04048018080880040808800a80008002080880000000";
attribute INIT_01 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
component RAMB16_S36
generic (
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
signal xram_di : std_logic_vector(31 downto 0); -- BlockRAM data in (zero)
signal command_addr : unsigned(8 downto 0); -- BlockRAM data in (zero)
signal xram_addr : std_logic_vector(8 downto 0); -- BlockRAM data in (zero)
signal xram_dip : std_logic_vector(3 downto 0); -- BlockRAM data in (zero)
signal xram_dop : std_logic_vector(3 downto 0); -- BlockRAM data out
signal xram_en : std_logic; -- BlockRAM enable (always on)
signal xram_we : std_logic; -- BlockRAM write enable (zero)
signal xram_reset : std_logic; -- BlockRAM reset (zero)
signal xram_do : std_logic_vector(31 downto 0);
begin
-- address (need to define)
block_ram_address_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
command_addr <= (others => '0');
elsif NextCommand = '1' then
command_addr <= command_addr + 1;
end if;
end if;
end process;
-- Define input signals to BlockRam
xram_di <= (others => '0'); -- no data in
xram_dip <= (others => '0'); -- 2-bit data (not used)
xram_en <= '1'; -- always enabled
xram_we <= '0'; -- do not need to write
xram_reset <= '0';
Data <= xram_do(15 downto 0);
Address <= xram_do(22 downto 16);
ValidCommand <= xram_do(31);
-- Instance the BlockRam
u1: RAMB16_S36
--translate_off
-- Note that the these generic map values are used for simulation
-- only. To insure that the simulation matches the actual ram values,
-- make sure that the attributes used above are the same as the
-- generics used below.
generic map (
INIT_00 =>
X"80200001801c0008801a04048018080880040808800a80008002080880000000",
INIT_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f =>
X"0000000000000000000000000000000000000000000000000000000000000000"
)
--translate_on
port map(
di => xram_di,
dip => xram_dip,
addr => xram_addr,
do => xram_do,
dop => xram_dop,
clk => clk,
SSR => xram_reset,
EN => xram_en,
WE => xram_we
);
xram_addr <= CONV_STD_LOGIC_VECTOR(command_addr, command_addr'length);
CommandNum <= xram_addr;
end architecture IMP;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/12.3/ml605/ml605_light_pr/pcores/plbv46_dcr_bridge_v9_00_a/hdl/vhdl/plbv46_dcr_bridge.vhd | 7 | 24559 | -------------------------------------------------------------------------------
-- plbv46_dcr_bridge - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2004, 2005, 2006, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: plbv46_dcr_bridge.vhd
-- Version: v1.01.a
-- Description: Top level of plbv46_dcr Bridge core
-- Instantiates plbv46_dcr_bridge_core and plbv46_slave_single v1.01.a
-- as Component and interfacing
--
-------------------------------------------------------------------------------
-- Structure:
-- plbv46_dcr_bridge.vhd
-- -- plbv46_dcr_bridge_core.vhd
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Author : SK
-- History :
-- ~~~~~~
-- SK 2006/09/19 -- Initial version.
-- ^^^^^^
-- ~~~~~~
-- SK 2008/12/15 -- Updated version v1_01_a, based upon v1_00_a core.
-- -- updated proc_common_v3_00_a and plbv46_slave_
-- -- single_v1_01_a core libraries.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Short Description of the plbv46_dcr_bridge.vhd code.
-- This file includes the interfacing of plbv46_dcr_bridge.vhd and
-- plbv46_single_slave_v1_00_a signals.
-------------------------------------------------------------------------------
-- Generic & Port Declarations
-------------------------------------------------------------------------------
------------------------------------------
-- == Definition of Generics ==
------------------------------------------
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_SPLB_AWIDTH -- PLBv46 address bus width
-- C_SPLB_DWIDTH -- PLBv46 data bus width
-- C_FAMILY -- Default family
-- C_SPLB_P2P -- Selects point-to-point or shared plb topology
-- C_SPLB_MID_WIDTH -- PLB Master ID Bus Width
-- C_SPLB_NUM_MASTERS -- Number of PLB Masters
-- C_SPLB_NATIVE_DWIDTH -- Width of the slave data bus
-- C_SPLB_SUPPORT_BURSTS -- Burst support
-- Definition of Ports:
-- ==
------------------------------------------
-- PLB_ABus -- Each master is required to provide a valid 32-bit
-- -- address when its request signal is asserted. The PLB
-- -- will then arbitrate the requests and allow the highest
-- -- priority masters address to be gated onto the PLB_ABus
-- PLB_PAValid -- This signal is asserted by the PLB arbiter in response
-- -- to the assertion of Mn_request and to indicate
-- -- that there is a valid primary address and transfer
-- -- qualifiers on the PLB outputs
-- PLB_masterID -- These signals indicate to the slaves the identification
-- -- of the master of the current transfer
-- PLB_RNW -- This signal is driven by the master and is used to
-- -- indicate whether the request is for a read or a write
-- -- transfer
-- PLB_BE -- These signals are driven by the master. For a non-line
-- -- and non-burst transfer they identify which
-- -- bytes of the target being addressed are to be read
-- -- from or written to. Each bit corresponds to a byte
-- -- lane on the read or write data bus
-- PLB_size -- The PLB_size(0:3) signals are driven by the master
-- -- to indicate the size of the requested transfer.
-- PLB_type -- The Mn_type signals are driven by the master and are
-- -- used to indicate to the slave, via the PLB_type
-- -- signals, the type of transfer being requested
-- PLB_wrDBus -- This data bus is used to transfer data between a
-- -- master and a slave during a PLB write transfer
------------------------------------------
-- == SLAVE DCR BRIDGE RESPONSE SIGNALS ==
------------------------------------------
-- Sl_addrAck -- This signal is asserted to indicate that the
-- -- slave has acknowledged the address and will
-- -- latch the address
-- Sl_SSize -- The Sl_SSize(0:1) signals are outputs of all
-- -- non 32-bit PLB slaves. These signals are
-- -- activated by the slave with the assertion of
-- -- PLB_PAValid or SAValid and a valid slave
-- -- address decode and must remain negated at
-- -- all other times.
-- Sl_wait -- This signal is asserted to indicate that the
-- -- slave has recognized the PLB address as a valid address
-- Sl_rearbitrate -- This signal is asserted to indicate that the
-- -- slave is unable to perform the currently
-- -- requested transfer and require the PLB arbiter
-- -- to re-arbitrate the bus
-- Sl_wrDAck -- This signal is driven by the slave for a write
-- -- transfer to indicate that the data currently on the
-- -- PLB_wrDBus bus is no longer required by the slave
-- -- i.e. data is latched
-- Sl_wrComp -- This signal is asserted by the slave to
-- -- indicate the end of the current write transfer.
-- Sl_rdDBus -- Slave read bus
-- Sl_rdDAck -- This signal is driven by the slave to indicate
-- -- that the data on the Sl_rdDBus bus is valid and
-- -- must be latched at the end of the current clock cycle
-- Sl_rdComp -- This signal is driven by the slave and is used
-- -- to indicate to the PLB arbiter that the read
-- -- transfer is either complete, or will be complete
-- -- by the end of the next clock cycle
-- Sl_MBusy -- These signals are driven by the slave and
-- -- are used to indicate that the slave is either
-- -- busy performing a read or a write transfer, or
-- -- has a read or write transfer pending
-- Sl_MWrErr -- These signals are driven by the slave and
-- -- are used to indicate that the slave has encountered an
-- -- error during a write transfer that was initiated
-- -- by this master
-- Sl_MRdErr -- These signals are driven by the slave and are
-- -- used to indicate that the slave has encountered an
-- -- error during a read transfer that was initiated
-- -- by this master
------------------------------------------
-- == SIGNALS FROM PLBV46DCR_CORE TO THE DCR SLAVE DEVICE -- ==
------------------------------------------
-- DCR_plbAck -- DCR Slave ACK in
-- DCR_plbDBusIn -- DCR to PLB data bus in
-- PLB_dcrRead -- PLB to DCR read out to slave
-- PLB_dcrWrite -- PLB to DCR write out to slave
-- PLB_dcrABus -- PLB to DCR address bus out to slave
-- PLB_dcrDBusOut -- PLB to DCR data bus out to slave
-- PLB_dcrClk -- DCR clock for the slave devices
-- PLB_dcrRst -- DCR reset for the slave devices
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.ipif_pkg.SLV64_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.calc_num_ce;
library plbv46_slave_single_v1_01_a;
library plbv46_dcr_bridge_v9_00_a;
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity plbv46_dcr_bridge is
generic (
C_FAMILY : STRING := "virtex5";
C_BASEADDR : STD_LOGIC_VECTOR := X"FFFFFFFF";
C_HIGHADDR : STD_LOGIC_VECTOR := X"00000000";
-- PLBv46 slave single block generics
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 32;
C_SPLB_P2P : integer range 0 to 1 := 0;
C_SPLB_MID_WIDTH : integer range 0 to 4 := 1;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 1;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_SUPPORT_BURSTS : integer range 0 to 1 := 0
);
port (
--PLBv46 SLAVE SINGLE INTERFACE
-- system signals
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
-- Bus slave signals
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
--slave DCR Bridge response signals
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Unused Bus slave signals
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
-- Unused Slave Response Signals
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- signals from plbv46_dcr_core to DCR slaves
DCR_plbAck : in STD_LOGIC;
DCR_plbDBusIn : in STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrRead : out STD_LOGIC;
PLB_dcrWrite : out STD_LOGIC;
PLB_dcrABus : out STD_LOGIC_VECTOR(0 to 9);
PLB_dcrDBusOut : out STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrClk : out STD_LOGIC;
PLB_dcrRst : out STD_LOGIC
);
--fan-out attributes for XST
--fan-out attributes for MPD
-----------------------------------------------------------------------------
ATTRIBUTE CORE_STATE : string;
ATTRIBUTE CORE_STATE of plbv46_dcr_bridge : entity is "ACTIVE";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of plbv46_dcr_bridge : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of plbv46_dcr_bridge : entity is "BRIDGE";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of plbv46_dcr_bridge : entity is "HDL";
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of SPLB_Clk : signal is "10000";
ATTRIBUTE MAX_FANOUT of SPLB_Rst : signal is "10000";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of SPLB_Clk : signal is "Clk";
ATTRIBUTE SIGIS of SPLB_Rst : signal is "Rst";
ATTRIBUTE SIGIS of PLB_dcrClk : signal is "Clk";
ATTRIBUTE SIGVAL : string;
ATTRIBUTE SIGVAL of DCR_plbAck : signal is "DCR_Ack";
ATTRIBUTE SIGVAL of DCR_plbDBusIn : signal is "DCR_M_DBus";
ATTRIBUTE SIGVAL of PLB_dcrRead : signal is "M_dcrRead";
ATTRIBUTE SIGVAL of PLB_dcrWrite : signal is "M_dcrWrite";
ATTRIBUTE SIGVAL of PLB_dcrABus : signal is "M_dcrABus";
ATTRIBUTE SIGVAL of PLB_dcrDBusOut : signal is "M_dcrDBus";
ATTRIBUTE BUSIF : string;
ATTRIBUTE BUSIF of SPLB_Clk : signal is "SPLB";
ATTRIBUTE BUSIF of DCR_plbAck : signal is "MDCR";
ATTRIBUTE BUSIF of DCR_plbDBusIn : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrRead : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrWrite : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrABus : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrDBusOut : signal is "MDCR";
ATTRIBUTE BRIDGE_TO : string;
ATTRIBUTE BRIDGE_TO of C_BASEADDR : constant is "MDCR";
-----------------------------------------------------------------------------
end entity plbv46_dcr_bridge;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture implementation of plbv46_dcr_bridge is
-------------------------------------------------------------------------------
-- Constant Declarations
constant ZERO_PADS : std_logic_vector(0 to 31) := X"00000000";
-- Decoder address range definition constants starts
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_PADS & C_BASEADDR,
ZERO_PADS & C_HIGHADDR
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1
);
-- Decoder address range definition constants ends
-------------------------------------------------------------------------------
-- local signal declaration goes here
--bus2ip signals
signal bus2IP_Clk : std_logic;
signal bus2IP_Reset : std_logic;
signal bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1 );
signal bus2IP_BE : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 - 1 );
signal bus2IP_CS : std_logic_vector(0 to (ARD_ADDR_RANGE_ARRAY'LENGTH/2)-1);
signal bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal bus2IP_RNW : std_logic;
-- ip2bus signals
signal ip2Bus_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal ip2Bus_WrAck : std_logic;
signal ip2Bus_RdAck : std_logic;
signal ip2Bus_Error : std_logic;
-- end of local signal declaration
begin -- architecture implementation
----------------------------------
-- INSTANTIATE PLBv46 SLAVE SINGLE
----------------------------------
PLBv46_IPIF_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_BUS2CORE_CLK_RATIO => 1,
C_INCLUDE_DPHASE_TIMER => 1,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- System signals ---------------------------------------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
-- Bus Slave signals ------------------------------------------------
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
-- Slave Response Signals -------------------------------------------
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
-- IP Interconnect (IPIC) port signals ------------------------------
IP2Bus_Data => ip2Bus_Data,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_Error => ip2Bus_Error,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_RNW => bus2IP_RNW,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS,
Bus2IP_RdCE => bus2IP_RdCE,
Bus2IP_WrCE => bus2IP_WrCE,
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset
);
-- component plbv46_dcr_bridge_core interface starts here
plbv46_dcr_bridge_core_1 : entity plbv46_dcr_bridge_v9_00_a.plbv46_dcr_bridge_core
port map (
-- IP Interconnect (IPIC) port signals ----
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS(0),
Bus2IP_RdCE => bus2IP_RdCE(0),
Bus2IP_WrCE => bus2IP_WrCE(0),
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_Error => ip2Bus_Error,
IP2Bus_Data => ip2Bus_Data,
-- signals from plbv46dcr_core --
DCR_plbDBusIn => DCR_plbDBusIn,
DCR_plbAck => DCR_plbAck,
PLB_dcrABus => PLB_dcrABus,
PLB_dcrDBusOut => PLB_dcrDBusOut,
PLB_dcrRead => PLB_dcrRead,
PLB_dcrWrite => PLB_dcrWrite,
PLB_dcrRst => PLB_dcrRst,
PLB_dcrClk => PLB_dcrClk
);
-- component interfacing ends here.
end architecture implementation;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd | 8 | 9026 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
| gpl-3.0 |
luebbers/reconos | support/templates/coregen/fifo/fifo.vhd | 1 | 5272 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo IS
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synopsys translate_off
component wrapped_fifo
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo use entity XilinxCoreLib.fifo_generator_v3_2(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_implementation_type => 0,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synopsys translate_on
END fifo_a;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DRSCFIFO288x16WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 85 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ
F0QO+ZZlvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p
SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O
dw5/lv3XsuSXKGnf8V0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f
0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL
jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu
D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf
YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv
sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC
lN9AukRoCBpCWkU/kGY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl
m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8
ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig
hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR
Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR
N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z
78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq
GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY
5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s
B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn
97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9
1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW
p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+
BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ
dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD
LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2
3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV
2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr
H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC
IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl
D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1
LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY
tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC
kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0
zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ
Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq
gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw
80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5
VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7
DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH
JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz
NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI
wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf
F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA
OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s
djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK
4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es
OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO
g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7
h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH
IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB
F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5
UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji
mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP
Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB
gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3
/JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM
bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy
LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s
IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod
UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3
kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz
H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF
+jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/
F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX
1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj
ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M
tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y
OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr
WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn
fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH
b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn
MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ
OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa
UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8
2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ
js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7
iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz
Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF
Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3
w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX
27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt
Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++
eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS
qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3
lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq
8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak
jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq
NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi
RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP
9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v
Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW
mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G
QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL
E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o
nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ
frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A
zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2
Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o
5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL
aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8
0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ
tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE
BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo
GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl
Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB
BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H
dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8
K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K
cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP
MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV
i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw
TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ
3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW
k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0
VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S
rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n
xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj
fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH
CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM
EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk
L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh
99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2
zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6
bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24
bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf
+b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x
tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN
0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V
u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie
NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT
0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s
g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS
btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx
zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR
7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT
+30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54
4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7
bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj
rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG
ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7
bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F
kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9
19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm
9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt
C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp
YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH
k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN
J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr
ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u
Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU
3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM
lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8
1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd
T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL
dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B
p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8
T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY
fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G
azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig
MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8
hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV
rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30
WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA
WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1
Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW
DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ
p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy
8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ
j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C
G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH//
r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL
obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7
5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr
yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2
rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b
E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp
kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6
uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf
HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932
RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh
z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC
iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp
lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw
X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu
iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt
ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS
U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/
rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf
Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU
+KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY
yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM
1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18
M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd
KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq
8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx
XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5
YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk
mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD
+r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt
cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3
QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc
6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm
uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY
rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E
74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f
e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0
HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf
i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ
DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1
WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T
fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ
xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P
FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z
7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f
NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs
/LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl
+A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE
1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW
xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7
+S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J
4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj
vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94
Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA
nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z
tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC
xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU
WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE
1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa
l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ
ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf
QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7
th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f
20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY
udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB
XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB
bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA
8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz
RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj
klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j
VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv
I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9
yfNP8OseoF3PEoH5
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DCDPRAM16x1280WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 85 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ
F0QO+ZZlvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p
SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O
dw5/lv3XsuSXKGnf8V0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f
0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL
jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu
D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf
YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv
sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC
lN9AukRoCBpCWkU/kGY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl
m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8
ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig
hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR
Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR
N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z
78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq
GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY
5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s
B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn
97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9
1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW
p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+
BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ
dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD
LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2
3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV
2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr
H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC
IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl
D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1
LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY
tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC
kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0
zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ
Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq
gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw
80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5
VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7
DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH
JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz
NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI
wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf
F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA
OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s
djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK
4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es
OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO
g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7
h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH
IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB
F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5
UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji
mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP
Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB
gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3
/JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM
bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy
LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s
IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod
UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3
kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz
H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF
+jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/
F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX
1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj
ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M
tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y
OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr
WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn
fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH
b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn
MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ
OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa
UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8
2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ
js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7
iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz
Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF
Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3
w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX
27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt
Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++
eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS
qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3
lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq
8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak
jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq
NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi
RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP
9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v
Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW
mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G
QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL
E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o
nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ
frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A
zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2
Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o
5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL
aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8
0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ
tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE
BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo
GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl
Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB
BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H
dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8
K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K
cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP
MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV
i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw
TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ
3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW
k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0
VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S
rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n
xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj
fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH
CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM
EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk
L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh
99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2
zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6
bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24
bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf
+b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x
tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN
0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V
u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie
NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT
0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s
g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS
btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx
zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR
7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT
+30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54
4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7
bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj
rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG
ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7
bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F
kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9
19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm
9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt
C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp
YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH
k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN
J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr
ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u
Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU
3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM
lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8
1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd
T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL
dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B
p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8
T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY
fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G
azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig
MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8
hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV
rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30
WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA
WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1
Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW
DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ
p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy
8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ
j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C
G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH//
r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL
obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7
5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr
yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2
rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b
E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp
kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6
uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf
HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932
RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh
z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC
iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp
lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw
X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu
iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt
ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS
U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/
rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf
Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU
+KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY
yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM
1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18
M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd
KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq
8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx
XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5
YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk
mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD
+r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt
cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3
QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc
6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm
uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY
rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E
74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f
e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0
HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf
i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ
DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1
WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T
fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ
xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P
FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z
7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f
NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs
/LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl
+A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE
1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW
xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7
+S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J
4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj
vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94
Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA
nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z
tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC
xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU
WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE
1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa
l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ
ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf
QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7
th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f
20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY
udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB
XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB
bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA
8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz
RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj
klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j
VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv
I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9
yfNP8OseoF3PEoH5
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBDCFIFO64x16DR/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 85 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ
F0QO+ZZlvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p
SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O
dw5/lv3XsuSXKGnf8V0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f
0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL
jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu
D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf
YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv
sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC
lN9AukRoCBpCWkU/kGY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl
m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8
ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig
hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR
Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR
N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z
78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq
GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY
5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s
B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn
97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9
1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW
p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+
BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ
dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD
LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2
3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV
2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr
H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC
IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl
D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1
LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY
tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC
kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0
zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ
Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq
gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw
80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5
VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7
DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH
JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz
NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI
wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf
F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA
OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s
djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK
4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es
OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO
g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7
h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH
IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB
F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5
UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji
mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP
Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB
gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3
/JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM
bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy
LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s
IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod
UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3
kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz
H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF
+jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/
F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX
1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj
ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M
tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y
OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr
WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn
fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH
b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn
MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ
OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa
UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8
2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ
js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7
iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz
Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF
Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3
w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX
27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt
Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++
eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS
qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3
lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq
8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak
jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq
NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi
RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP
9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v
Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW
mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G
QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL
E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o
nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ
frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A
zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2
Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o
5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL
aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8
0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ
tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE
BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo
GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl
Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB
BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H
dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8
K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K
cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP
MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV
i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw
TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ
3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW
k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0
VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S
rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n
xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj
fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH
CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM
EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk
L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh
99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2
zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6
bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24
bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf
+b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x
tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN
0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V
u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie
NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT
0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s
g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS
btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx
zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR
7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT
+30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54
4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7
bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj
rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG
ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7
bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F
kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9
19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm
9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt
C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp
YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH
k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN
J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr
ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u
Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU
3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM
lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8
1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd
T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL
dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B
p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8
T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY
fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G
azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig
MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8
hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV
rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30
WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA
WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1
Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW
DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ
p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy
8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ
j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C
G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH//
r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL
obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7
5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr
yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2
rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b
E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp
kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6
uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf
HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932
RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh
z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC
iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp
lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw
X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu
iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt
ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS
U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/
rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf
Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU
+KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY
yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM
1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18
M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd
KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq
8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx
XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5
YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk
mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD
+r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt
cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3
QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc
6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm
uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY
rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E
74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f
e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0
HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf
i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ
DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1
WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T
fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ
xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P
FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z
7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f
NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs
/LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl
+A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE
1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW
xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7
+S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J
4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj
vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94
Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA
nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z
tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC
xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU
WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE
1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa
l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ
ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf
QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7
th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f
20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY
udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB
XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB
bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA
8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz
RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj
klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j
VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv
I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9
yfNP8OseoF3PEoH5
`protect end_protected
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBSCFIFO128x64WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 85 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ
F0QO+ZZlvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p
SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O
dw5/lv3XsuSXKGnf8V0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f
0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL
jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu
D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf
YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv
sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC
lN9AukRoCBpCWkU/kGY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl
m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8
ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig
hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR
Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR
N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z
78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq
GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY
5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s
B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn
97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9
1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW
p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+
BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ
dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD
LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2
3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV
2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr
H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC
IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl
D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1
LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY
tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC
kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0
zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ
Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq
gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw
80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5
VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7
DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH
JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz
NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI
wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf
F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA
OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s
djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK
4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es
OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO
g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7
h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH
IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB
F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5
UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji
mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP
Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB
gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3
/JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM
bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy
LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s
IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod
UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3
kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz
H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF
+jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/
F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX
1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj
ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M
tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y
OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr
WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn
fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH
b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn
MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ
OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa
UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8
2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ
js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7
iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz
Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF
Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3
w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX
27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt
Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++
eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS
qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3
lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq
8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak
jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq
NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi
RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP
9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v
Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW
mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G
QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL
E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o
nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ
frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A
zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2
Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o
5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL
aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8
0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ
tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE
BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo
GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl
Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB
BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H
dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8
K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K
cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP
MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV
i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw
TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ
3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW
k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0
VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S
rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n
xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj
fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH
CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM
EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk
L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh
99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2
zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6
bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24
bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf
+b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x
tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN
0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V
u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie
NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT
0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s
g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS
btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx
zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR
7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT
+30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54
4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7
bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj
rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG
ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7
bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F
kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9
19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm
9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt
C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp
YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH
k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN
J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr
ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u
Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU
3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM
lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8
1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd
T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL
dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B
p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8
T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY
fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G
azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig
MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8
hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV
rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30
WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA
WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1
Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW
DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ
p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy
8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ
j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C
G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH//
r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL
obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7
5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr
yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2
rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b
E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp
kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6
uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf
HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932
RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh
z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC
iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp
lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw
X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu
iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt
ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS
U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/
rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf
Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU
+KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY
yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM
1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18
M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd
KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq
8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx
XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5
YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk
mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD
+r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt
cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3
QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc
6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm
uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY
rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E
74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f
e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0
HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf
i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ
DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1
WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T
fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ
xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P
FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z
7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f
NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs
/LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl
+A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE
1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW
xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7
+S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J
4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj
vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94
Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA
nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z
tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC
xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU
WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE
1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa
l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ
ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf
QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7
th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f
20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY
udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB
XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB
bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA
8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz
RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj
klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j
VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv
I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9
yfNP8OseoF3PEoH5
`protect end_protected
| gpl-3.0 |
luebbers/reconos | demos/particle_filter_framework/hw/src/framework/sampling.vhd | 1 | 27850 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity sampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end sampling;
architecture Behavioral of sampling is
component uf_prediction is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT, STATE_READ_PARTICLES_ADDRESS, STATE_READ_N,
STATE_READ_PARTICLE_SIZE, STATE_READ_MAX_NUMBER_OF_PARTICLES, STATE_READ_BLOCK_SIZE,
STATE_READ_PARAMETER_ADDRESS, STATE_READ_PARAMETER ,STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1, STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3, STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_NEEDED_BURSTS_1, STATE_NEEDED_BURSTS_2, STATE_NEEDED_BURSTS_3,
STATE_NEEDED_BURSTS_4, STATE_COPY_PARTICLE_BURST_DECISION, STATE_COPY_PARTICLE_BURST,
--STATE_COPY_PARTICLE_BURST_2, STATE_COPY_PARTICLE_BURST_3, STATE_COPY_PARTICLE_BURST_4,
STATE_PREDICTION, STATE_PREDICTION_DONE,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST,
STATE_CALCULATE_WRITES_1, STATE_CALCULATE_WRITES_2, STATE_CALCULATE_WRITES_3,
STATE_CALCULATE_WRITES_4, STATE_WRITE_DECISION, STATE_READ, STATE_WRITE,
STATE_SEND_MESSAGE, STATE_SEND_MEASUREMENT_1, STATE_SEND_MEASUREMENT_2);
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter array address
signal parameter_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 4;
-- number of particles still to resample
signal remaining_particles : integer := 4;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered (for writing back)
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 48;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal offset : integer := 0;
-- start particle index
signal start_particle_index : integer := 0;
-- maximum number of particles, which fit into the local RAM (minus 128 byte)
signal max_number_of_particles : integer := 168;
-- number of bytes, which are not written with valid particle data
signal diff : integer := 0;
-- number of writes
signal number_of_writes : integer := 0;
-- local ram address for interface
signal local_ram_address_if_read : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
signal particle_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for prediction user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 4;
-- size of one particle
signal particle_size_2 : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrPrediction : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrSampling : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEPrediction : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWESampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataPrediction : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataSampling : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_prediction
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrPrediction, o_RAMData=>o_RAMDataPrediction,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEPrediction, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
particle_size=>particle_size_2, finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrPrediction(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrPrediction(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrSampling(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrSampling(C_TASK_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEPrediction when enable = '1' else o_RAMWESampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataPrediction when enable = '1' else o_RAMDataSampling;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Sampling:
--
-- 1) The Parameter are copied to the first 128 bytes of the local RAM
-- Other information are set
--
--
-- 2) Waiting for Message m (Start of a Sampling run)
-- Message m: sample particles of m-th particle block
--
--
-- 3) The number of needed bursts is calculated to fill the local RAM
-- The number only differs from 63, if it is for the last particles,
-- which fit into the local ram.
--
--
-- 4) The particles are copied into the local RAM by burst reads
--
--
-- 5) The user prediction process is run
--
--
-- 6) After prediction the particles are written back to Main Memory.
-- Since there can be several sampling threads, there has to be
-- special treatment for the last 128 byte, which are written
-- in 4 byte blocks and not in a 128 byte burst.
--
--
-- 7) If the user process is finished and more particle need to be
-- sampled, then go to step 3 else to step 8
--
--
-- 8) Send message m (Stop of a Sampling run)
-- Particles of m-th particle block are sampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable max_number_of_particles_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive particle array address
-- TODO: C H A N G E !!! (1 of 3)
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
enable <= '0';
local_ram_address <= (others => '0');
local_ram_start_address <= (others => '0');
init <= '1';
particles_loaded <= '0';
if done then
-- TODO: C H A N G E !!! (2 of 3)
state <= STATE_READ_PARTICLES_ADDRESS;
--state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_READ_PARTICLES_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_N;
end if;
when STATE_READ_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_MAX_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_MAX_NUMBER_OF_PARTICLES =>
--! read max number of particles, which fit into 63 bursts (128 bytes per burst)
reconos_read (done, o_osif, i_osif, information_struct+12, max_number_of_particles_var);
if done then
particle_size_2 <= particle_size / 4;
max_number_of_particles <= TO_INTEGER(SIGNED(max_number_of_particles_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read bock size, this is the size of how many particles are in one block.
-- A message sends the block number
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
--state <= STATE_WAIT_FOR_MESSAGE;
-- CHANGE BACK !!! (1 of 2)
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, parameter_array_address);
if done then
state <= STATE_READ_PARAMETER;
end if;
when STATE_READ_PARAMETER =>
--! copy all parameter in one burst
reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, parameter_array_address);
if done then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for message, that starts Sampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
particles_loaded <= '0';
enable <= '0';
init <= '1';
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
end if;
when STATE_CALCULATE_REMAINING_PARTICLES_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_PARTICLES_2;
when STATE_CALCULATE_REMAINING_PARTICLES_2 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_PARTICLES_3;
when STATE_CALCULATE_REMAINING_PARTICLES_3 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= N - remaining_particles;
particle_array_address <= particle_array_start_address;
state <= STATE_CALCULATE_REMAINING_PARTICLES_4;
when STATE_CALCULATE_REMAINING_PARTICLES_4 =>
--! calculates particle array address and number of particles to sample
if (remaining_particles > block_size) then
remaining_particles <= block_size;
end if;
current_particle_array_address <= particle_array_start_address;
state <= STATE_NEEDED_BURSTS_1;
when STATE_NEEDED_BURSTS_1 =>
--! decision how many bursts are needed
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_read <= local_ram_start_address_if + 32;
particles_loaded <= '0';
enable <= '0';
init <= '1';
--start_particle_index <= N - remaining_particles;
start_particle_index <= message2 * block_size;
if (remaining_particles <= 0) then
state <= STATE_SEND_MESSAGE;
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
temp <= remaining_particles * particle_size;
state <= STATE_NEEDED_BURSTS_2;
end if;
when STATE_NEEDED_BURSTS_2 =>
--! decision how many bursts are needed
offset <= start_particle_index * particle_size;
state <= STATE_NEEDED_BURSTS_3;
when STATE_NEEDED_BURSTS_3 =>
--! decision how many bursts are needed
current_particle_array_address <= particle_array_start_address + offset;
particle_array_address <= particle_array_start_address + offset;
if (temp >= 8064) then --8064 = 63*128
--copy as much particles as possible
number_of_bursts <= 63;
number_of_bursts_remember <= 63;
number_of_particles <= max_number_of_particles;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
else
-- copy only remaining particles
number_of_bursts <= temp / 128;
number_of_bursts_remember <= temp / 128;
number_of_particles <= remaining_particles;
state <= STATE_NEEDED_BURSTS_4;
end if;
when STATE_NEEDED_BURSTS_4 =>
--! decision how many bursts are needed
number_of_bursts <= number_of_bursts + 1;
number_of_bursts_remember <= number_of_bursts_remember + 1;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
when STATE_COPY_PARTICLE_BURST_DECISION =>
--! check if another burst is needed
if (number_of_bursts > 63) then
number_of_bursts <= 63;
elsif (number_of_bursts > 0) then
number_of_bursts <= number_of_bursts - 1;
state <= STATE_COPY_PARTICLE_BURST;
elsif (remaining_particles <= 0) then
-- check it
state <= STATE_SEND_MESSAGE;
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
remaining_particles <= remaining_particles - number_of_particles;
state <= STATE_PREDICTION;
enable <= '1';
particles_loaded <= '1';
init <= '0';
end if;
when STATE_COPY_PARTICLE_BURST =>
--! read another burst
-- NO MORE BURSTS
--temp3 <= 32;
--state <= STATE_COPY_PARTICLE_BURST_2;
reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_COPY_PARTICLE_BURST_DECISION;
--if (local_ram_address < 8064) then
local_ram_address <= local_ram_address + 128;
--end if;
current_particle_array_address <= current_particle_array_address + 128;
end if;
-- when STATE_COPY_PARTICLE_BURST_2 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- enable <= '0';
-- o_RAMWESampling<= '0';
-- if (temp3 > 0) then
--
-- state <= STATE_COPY_PARTICLE_BURST_3;
-- temp3 <= temp3 - 1;
-- else
--
-- state <= STATE_COPY_PARTICLE_BURST_DECISION;
-- end if;
--
--
-- when STATE_COPY_PARTICLE_BURST_3 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- --! load data to local ram
-- reconos_read_s (done, o_osif, i_osif, particle_array_address, particle_data);
-- if done then
-- state <= STATE_COPY_PARTICLE_BURST_4;
-- particle_array_address <= particle_array_address + 4;
-- end if;
--
--
-- when STATE_COPY_PARTICLE_BURST_4 =>
-- --! write particle data to local ram
-- o_RAMWESampling<= '1';
-- o_RAMAddrSampling <= local_ram_address_if_read;
-- o_RAMDataSampling <= particle_data;
-- local_ram_address_if_read <= local_ram_address_if_read + 1;
-- state <= STATE_COPY_PARTICLE_BURST_2;
when STATE_PREDICTION =>
--! start prediction user process and wait until prediction is finished
init <= '0';
enable <= '1';
particles_loaded <= '0';
if (finished = '1') then
state <= STATE_PREDICTION_DONE;
end if;
when STATE_PREDICTION_DONE =>
--! start prediction user process and wait until it is finished
init <= '1';
enable <= '0';
particles_loaded <= '0';
current_particle_array_address <= particle_array_address;
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_write <= local_ram_start_address_if + 32;
number_of_bursts <= number_of_bursts_remember;
state <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! if write burst is demanded by user process, it will be done
if (number_of_bursts > 63) then
number_of_bursts <= 63;
--else
-- NO MORE BURSTS
elsif (number_of_bursts > 1) then
state <= STATE_WRITE_BURST;
elsif (number_of_bursts <= 1) then
number_of_bursts <= 0;
state <= STATE_CALCULATE_WRITES_1;
diff <= (number_of_bursts_remember * 128);
end if;
when STATE_WRITE_BURST =>
--! write bursts from local ram into index array
reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
local_ram_address <= local_ram_address + 128;
local_ram_address_if_write <= local_ram_address_if_write + 32;
current_particle_array_address <= current_particle_array_address + 128;
number_of_bursts <= number_of_bursts - 1;
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_CALCULATE_WRITES_1 =>
--! calculates number of writes (1/4)
temp2 <= number_of_particles * particle_size;
--state <= STATE_CALCULATE_WRITES_4;
-- NO MORE BURSTS
state <= STATE_CALCULATE_WRITES_2;
when STATE_CALCULATE_WRITES_2 =>
--! calculates number of writes (2/4)
diff <= diff - temp2;
state <= STATE_CALCULATE_WRITES_3;
when STATE_CALCULATE_WRITES_3 =>
--! calculates number of writes (3/4)
number_of_writes <= 128 - diff;
state <= STATE_CALCULATE_WRITES_4;
when STATE_CALCULATE_WRITES_4 =>
--! calculates number of writes (4/4)
-- NO MORE BURSTS
number_of_writes <= number_of_writes / 4;
--number_of_writes <= temp2 / 4;
state <= STATE_WRITE_DECISION;
when STATE_WRITE_DECISION =>
--! decide if a reconos write is needed
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
-- read local ram data
state <= STATE_READ;
o_RAMAddrSampling <= local_ram_address_if_write;
end if;
when STATE_READ =>
--! read 4 byte from local RAM
number_of_writes <= number_of_writes - 1;
--local_ram_address_if <= local_ram_address_if + 1;
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_WRITE;
when STATE_WRITE =>
--! write 4 byte to particle array in main memory
reconos_write(done, o_osif, i_osif, current_particle_array_address, i_RAMData);
if done then
local_ram_address_if_write <= local_ram_address_if_write + 1;
current_particle_array_address <= current_particle_array_address + 4;
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_READ;
end if;
end if;
when STATE_SEND_MESSAGE =>
--! send message i (sampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | tests/simulation/plb/coop/test_coop.vhd | 1 | 6362 | --!
--! \file test_coop.vhd
--!
--! Simulation testbench thread for cooperative multithreading
--!
--! \author Enno Luebbers <[email protected]>
--! \date 23.04.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 23.04.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_coop is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_coop;
architecture Behavioral of test_coop is
-- OS synchronization state machine states
type state_t is (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07");
constant decode : decode_t := (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
-- resources used by thread
constant C_SEM_YIELD : std_logic_vector(0 to 31) := X"00000000";
constant C_SEM_DELAY : std_logic_vector(0 to 31) := X"00000001";
constant C_SEM_LOCK : std_logic_vector(0 to 31) := X"00000002";
constant C_MUTEX : std_logic_vector(0 to 31) := X"00000003";
constant C_DELAY : std_logic_vector(0 to 31) := X"0000007F"; -- delay for 128 ticks
signal state : state_t := STATE_CHECK;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_CHECK;
variable resume_state_enc : reconos_state_enc_t := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_CHECK;
next_state := STATE_CHECK;
resume_state_enc := (others => '0');
done := false;
success := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
next_state := decode(to_integer(unsigned(resume_state_enc)));
else
next_state := STATE_YIELD;
end if;
end if;
-- test thread_yield()
when STATE_YIELD =>
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_thread_yield(o_osif, i_osif, encode(STATE_POST_YIELD));
next_state := STATE_POST_YIELD;
when STATE_POST_YIELD =>
reconos_sem_post(o_osif, i_osif, C_SEM_YIELD);
next_state := STATE_DELAY;
-- test single-cycle blocking yielding call
when STATE_DELAY =>
reconos_thread_delay(o_osif, i_osif, C_DELAY); -- delay via OS
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_POST_DELAY));
next_state := STATE_POST_DELAY;
when STATE_POST_DELAY =>
reconos_sem_post(o_osif, i_osif, C_SEM_DELAY);
next_state := STATE_LOCK;
-- test multi-cycle blocking yielding call
when STATE_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX);
-- on multi-cycle calls, saved_state_enc must be set to the _current_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_LOCK));
if done then
if success then
next_state := STATE_POST_LOCK;
else
next_state := STATE_EXIT;
end if;
end if;
when STATE_POST_LOCK =>
reconos_sem_post(o_osif, i_osif, C_SEM_LOCK);
next_state := STATE_EXIT;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_command_rom.vhd | 7 | 3893 | -------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
| gpl-3.0 |
luebbers/reconos | support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/bfm_system.vhd | 1 | 31892 | -------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_ordered : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MErr : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 63);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMErr : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_ordered : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to 7);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_M_ABus : std_logic_vector(0 to 63);
signal plb_bus_M_BE : std_logic_vector(0 to 15);
signal plb_bus_M_MSize : std_logic_vector(0 to 3);
signal plb_bus_M_RNW : std_logic_vector(0 to 1);
signal plb_bus_M_abort : std_logic_vector(0 to 1);
signal plb_bus_M_busLock : std_logic_vector(0 to 1);
signal plb_bus_M_compress : std_logic_vector(0 to 1);
signal plb_bus_M_guarded : std_logic_vector(0 to 1);
signal plb_bus_M_lockErr : std_logic_vector(0 to 1);
signal plb_bus_M_ordered : std_logic_vector(0 to 1);
signal plb_bus_M_priority : std_logic_vector(0 to 3);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 1);
signal plb_bus_M_request : std_logic_vector(0 to 1);
signal plb_bus_M_size : std_logic_vector(0 to 7);
signal plb_bus_M_type : std_logic_vector(0 to 5);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 1);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 7);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_MErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 63);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_compress : std_logic;
signal plb_bus_PLB_guarded : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_ordered : std_logic;
signal plb_bus_PLB_pendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_pendReq : std_logic;
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 63);
signal plb_bus_PLB_wrPrim : std_logic;
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 3);
signal plb_bus_Sl_MErr : std_logic_vector(0 to 3);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 127);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize(0 to 1),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MErr => plb_bus_PLB_MErr(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(0 to 63),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(0 to 3),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority(0 to 1),
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE(0 to 7),
M_msize => plb_bus_M_MSize(0 to 1),
M_size => plb_bus_M_size(0 to 3),
M_type => plb_bus_M_type(0 to 2),
M_compress => plb_bus_M_compress(0),
M_guarded => plb_bus_M_guarded(0),
M_ordered => plb_bus_M_ordered(0),
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_ABus => plb_bus_M_ABus(0 to 31),
M_wrDBus => plb_bus_M_wrDBus(0 to 63),
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_ordered => plb_bus_PLB_ordered,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 63),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 1),
Sl_MErr => plb_bus_Sl_MErr(0 to 1)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request,
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock,
M_RNW => plb_bus_M_RNW,
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_compress => plb_bus_M_compress,
M_guarded => plb_bus_M_guarded,
M_ordered => plb_bus_M_ordered,
M_lockErr => plb_bus_M_lockErr,
M_abort => plb_bus_M_abort,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst,
M_rdBurst => plb_bus_M_rdBurst,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MErr => plb_bus_PLB_MErr,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_ordered => plb_bus_PLB_ordered,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MErr => plb_bus_Sl_MErr,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SMErr => plb_bus_PLB_SMErr,
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW,
M_abort => plb_bus_M_abort,
M_busLock => plb_bus_M_busLock,
M_compress => plb_bus_M_compress,
M_guarded => plb_bus_M_guarded,
M_lockErr => plb_bus_M_lockErr,
M_MSize => plb_bus_M_MSize,
M_ordered => plb_bus_M_ordered,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst,
M_request => plb_bus_M_request,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst,
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MErr => plb_bus_Sl_MErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
PLB_ABus => plb_bus_PLB_ABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MErr => plb_bus_PLB_MErr,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_ordered => plb_bus_PLB_ordered,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMErr => plb_bus_PLB_SMErr,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
ArbAddrVldReg => open,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
PLB_Clk => sys_clk,
PLB_Rst => plb_bus_PLB_Rst,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_MBusy => plb_bus_Sl_MBusy(2 to 3),
Sl_MErr => plb_bus_Sl_MErr(2 to 3),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(64 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
PLB_abort => plb_bus_PLB_abort,
PLB_ABus => plb_bus_PLB_ABus,
PLB_BE => plb_bus_PLB_BE,
PLB_busLock => plb_bus_PLB_busLock,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_ordered => plb_bus_PLB_ordered,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
M_abort => plb_bus_M_abort(1),
M_ABus => plb_bus_M_ABus(32 to 63),
M_BE => plb_bus_M_BE(8 to 15),
M_busLock => plb_bus_M_busLock(1),
M_compress => plb_bus_M_compress(1),
M_guarded => plb_bus_M_guarded(1),
M_lockErr => plb_bus_M_lockErr(1),
M_MSize => plb_bus_M_MSize(2 to 3),
M_ordered => plb_bus_M_ordered(1),
M_priority => plb_bus_M_priority(2 to 3),
M_rdBurst => plb_bus_M_rdBurst(1),
M_request => plb_bus_M_request(1),
M_RNW => plb_bus_M_RNW(1),
M_size => plb_bus_M_size(4 to 7),
M_type => plb_bus_M_type(3 to 5),
M_wrBurst => plb_bus_M_wrBurst(1),
M_wrDBus => plb_bus_M_wrDBus(64 to 127),
PLB_MBusy => plb_bus_PLB_MBusy(1),
PLB_MErr => plb_bus_PLB_MErr(1),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(1),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(1),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(1),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(1),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(1),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(64 to 127),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(4 to 7),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(1),
PLB_MSSize => plb_bus_PLB_MSSize(2 to 3),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_read.vhd | 1 | 7579 | --------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_read
-- Architectures: lipif_slv_read_rtl
-- Description:
--
-- Dependencies:
-- lipif_mst_pipeliner
--
-- Notes:
-- When Sl_rdBTerm is asserted at the end of a primary transfer,
-- M_rdBurst must be set according to the secondary transfer in
-- the following cycle.
-- M_rdBurst may not be set until after AddrAck!!!
--
-- Revision:
-- 11.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lipif_mst_read is
generic (
C_NUM_WIDTH : integer := 5;
C_EN_SRL16 : boolean := true;
C_EN_FAST_ABORT : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Arbiter
xfer_rdy_o : out std_logic;
xfer_init_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rearb_i : in std_logic;
xfer_retry_o : out std_logic;
xfer_abort_o : out std_logic;
-- LIS-IPIC Transfer Signals
M_rdNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdRearb_o : out std_logic;
M_rdAbort_i : in std_logic;
M_rdError_o : out std_logic;
M_rdData_o : out std_logic_vector(63 downto 0);
M_rdAck_o : out std_logic;
M_rdComp_o : out std_logic;
-- PLB Signals
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
M_rdBurst : out std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63)
);
end lipif_mst_read;
architecture lipif_mst_read_rtl of lipif_mst_read is
-- Pipebuf primary control signals
signal prim_valid : std_logic;
signal prim_last : std_logic;
signal prim_ack : std_logic;
signal prim_ack_p : std_logic;
signal prim_comp : std_logic;
-- Transfer termination requests from IP/PLB
signal mst_term : std_logic;
signal mst_term_r : std_logic; -- Track until transfer complete
signal plb_term : std_logic;
-- Burst will continue through next cycle
signal prim_burst_nxt : std_logic;
signal pipe_burst_nxt : std_logic;
begin
-- Generate PLB read burst signal (M_rdBurst)
-- TIMING(18%) M_rdBurst is a register, so no problem
-- TODO: When C_EN_FAST_ABORT, M_rdBurst must respond with M_rdAbort
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdBurst <= '0';
else
-- Burst must display pipelined value in response to PLB terminate
if(PLB_MRdBTerm='1') then
M_rdBurst <= pipe_burst_nxt;
-- Burst must go low in response to IP abort
elsif(M_rdAbort_i='1') then
M_rdBurst <= '0';
-- Update burst signal at start of transfer, or with each data ack
-- TODO: M_rdBurst may not be asserted until xfer_ack_i
elsif(xfer_init_i='1' or PLB_MRdDAck='1') then
M_rdBurst <= prim_burst_nxt;
end if;
end if;
end if;
end process;
-- process(plb_term, mst_term_r, prim_last, pipe_burst, pipe_valid) begin
-- if(plb_term='1') then
-- M_rdBurst <= pipe_burst and pipe_valid;
-- else
-- M_rdBurst <= not mst_term_r and not prim_last;
-- end if;
-- end process;
-- Assert prim_comp to complete transfer:
-- * with last d-ack of transfer
-- * with next d-ack when plb_term or mst_term are asserted
-- * with mst_term when primary transfer not acknowledged
process(PLB_MRdDAck, prim_last, plb_term, mst_term, prim_ack) begin
if(PLB_MRdDAck='1') then
prim_comp <= prim_last or plb_term or mst_term;
else
prim_comp <= mst_term and not prim_ack;
end if;
end process;
-- Latch IP termination request until completion of transfer
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
mst_term_r <= '0';
else
if(prim_comp='1') then
mst_term_r <= '0';
elsif(M_rdAbort_i='1') then
mst_term_r <= '1';
end if;
end if;
end if;
end process;
-- When not C_EN_FAST_ABORT, assert terminate signal immediately only if rearbitrating
NEN_FAST_ABORT: if(not C_EN_FAST_ABORT) generate
mst_term <= M_rdAbort_i when(xfer_rearb_i='1' and prim_ack_p='0') else mst_term_r;
end generate NEN_FAST_ABORT;
-- When C_EN_FAST_ABORT, always pass M_rdAbort_i through
EN_FAST_ABORT: if(C_EN_FAST_ABORT) generate
mst_term <= '1' when(mst_term_r='1') else M_rdAbort_i;
end generate EN_FAST_ABORT;
-- Wait until one cycle after prim_ack goes low before rearbitrating
M_rdRearb_o <= xfer_rearb_i and not prim_ack_p;
-- Control signals to arbiter (Affect arbiter only!)
xfer_retry_o <= xfer_rearb_i and not prim_ack_p;
xfer_abort_o <= mst_term and prim_valid and not prim_ack;
-- Various registers
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdData_o <= (others=>'0');
M_rdAck_o <= '0';
M_rdComp_o <= '0';
M_rdError_o <= '0';
plb_term <= '0';
else
M_rdAck_o <= PLB_MRdDAck;
if(PLB_MRdDAck='1') then
M_rdData_o <= PLB_MRdDBus;
end if;
-- Generate delayed prim_ack for rearbitration signal generation
prim_ack_p <= prim_ack;
-- IPIC's complete signal is pipeliner's complete signal delayed
M_rdComp_o <= prim_comp;
-- Error occurred if transfer completes before all data was transferred,
-- or if transfer was never acknowledged
M_rdError_o <= prim_comp and (not prim_last or not prim_ack);
-- Keep track of previous termination request by slave
-- Since PLB_MRdBTerm may already be asserted for a following transfer
-- with the last data item, give priority to asserting plb_term
if(PLB_MRdBTerm='1') then
plb_term <= '1';
elsif(prim_comp='1') then
plb_term <= '0';
end if;
end if;
end if;
end process;
-- Instantiate the request pipeliner
pipeliner_0: entity lisipif_master_v1_00_c.lipif_mst_pipeliner
generic map (
C_NUM_WIDTH => C_NUM_WIDTH
)
port map (
clk => clk,
reset => reset,
xfer_num_i => M_rdNum_i,
xfer_adv_i => PLB_MRdDAck,
xfer_nxt_i => prim_comp,
xfer_req_i => xfer_init_i,
xfer_ack_i => xfer_ack_i,
xfer_rdy_o => xfer_rdy_o,
prim_valid_o => prim_valid,
prim_last_o => prim_last,
prim_ack_o => prim_ack,
prim_nburst_o => prim_burst_nxt,
pipe_nburst_o => pipe_burst_nxt
);
end lipif_mst_read_rtl;
| gpl-3.0 |
luebbers/reconos | tests/simulation/plb/condvar/test_condvar.vhd | 1 | 3337 | -- condition variable test
-- modeled after the eCos condvar example
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_condvar is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_condvar;
architecture Behavioral of test_condvar is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
constant C_MY_CONDVAR : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_INIT, STATE_LOCK, STATE_READ, STATE_WAIT, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal res_count : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data); -- get address of res_count
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, res_count);
if done then
state <= STATE_WAIT;
end if;
when STATE_WAIT =>
if res_count = X"00000000" then
reconos_cond_wait(done, success, o_osif, i_osif, C_MY_CONDVAR);
if done and success then
state <= STATE_READ;
end if;
else
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, res_count - 1);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | tools/fsmLanguage/fpga_scripts/pr_scripts/parallel.vhd | 1 | 10408 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- Enable signal delayed by 1 clock cycle
signal enable_d1 : std_logic;
-- Encoder finished flag
signal encoder_finished, encoder_finished_next : std_logic;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
encoder_finished <= '0';
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
encoder_finished <= encoder_finished_next;
end if;
end if;
end process find_best_next;
delay_reg : process(clk) is
begin
if clk'event and clk = '1' then
if rst = '1' then
enable_d1 <= '0';
else
enable_d1 <= enable;
end if;
end if;
end process delay_reg;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable, enable_d1, encoder_finished ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
encoder_finished_next <= encoder_finished;
case find_current is
when narrow_search =>
-- Begin when there is an edge on the enable line
if( (enable xor enable_d1) = '1' ) then
encoder_finished_next <= '0';
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
encoder_finished_next <= '1';
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/synth/c_sub.vhd | 8 | 6227 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0;
USE c_addsub_v12_0.c_addsub_v12_0;
ENTITY c_sub IS
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END c_sub;
ARCHITECTURE c_sub_arch OF c_sub IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF c_sub_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF c_sub_arch: ARCHITECTURE IS "c_addsub_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF c_sub_arch : ARCHITECTURE IS "c_sub,c_addsub_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF c_sub_arch: ARCHITECTURE IS "c_sub,c_addsub_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=c_addsub,x_ipVersion=12.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_XDEVICEFAMILY=zynq,C_IMPLEMENTATION=0,C_A_WIDTH=15,C_B_WIDTH=15,C_OUT_WIDTH=15,C_CE_OVERRIDES_SCLR=0,C_A_TYPE=0,C_B_TYPE=0,C_LATENCY=0,C_ADD_MODE=1,C_B_CONSTANT=0,C_B_VALUE=000000000000000,C_AINIT_VAL=0,C_SINIT_VAL=0,C_CE_OVERRIDES_BYPASS=1,C_BYPASS_LOW=0,C_SCLR_OVERRIDES_SSET=1,C_HAS_C_IN=0,C_HAS_C_OUT=0,C_BORROW_LOW=1,C_HAS_CE=0,C_HAS_BYPASS=0,C_HAS_SCLR=0,C_HAS_SSET=0,C_HAS_SINIT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 15,
C_B_WIDTH => 15,
C_OUT_WIDTH => 15,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 1,
C_B_CONSTANT => 0,
C_B_VALUE => "000000000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END c_sub_arch;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/bram_fifo.vhd | 4 | 6636 | -------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
| gpl-3.0 |
luebbers/reconos | support/refdesigns/12.3/ml605/ml605_light_eth/pcores/dcr_v29_v9_00_a/hdl/vhdl/dcr_v29_wrp.vhd | 7 | 8671 | -------------------------------------------------------------------------------
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/dcr_v29/dcr_v29_v1_00_b/hdl/src/vhdl/Attic/dcr_v29_wrp.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
-- Updated Release For V5 Porting
-- END_CHANGELOG
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
ENTITY dcr_v29_wrp IS
-- Declare wrapper generic parameters here
generic (
C_DCR_NUM_SLAVES : INTEGER := 1;
C_DCR_AWIDTH : INTEGER := 10;
C_DCR_DWIDTH : INTEGER := 32;
C_USE_LUT_OR : INTEGER := 1
);
-- Declare wrapper ports here
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
END ENTITY dcr_v29_wrp;
architecture implementation of dcr_v29_wrp is
COMPONENT dcr_v29 IS
-- Declare generic parameters here
generic (
C_DCR_NUM_SLAVES : integer;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_USE_LUT_OR : integer
);
-- Declare ports here
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
END COMPONENT dcr_v29;
BEGIN -- architecture implementation
dcr_v29_imp : dcr_v29
GENERIC MAP ( -- Declare generic map here
C_DCR_NUM_SLAVES => C_DCR_NUM_SLAVES,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_USE_LUT_OR => C_USE_LUT_OR
)
PORT MAP ( -- Declare port map here
M_dcrABus => M_dcrABus,
M_dcrDBus => M_dcrDBus,
M_dcrRead => M_dcrRead,
M_dcrWrite => M_dcrWrite,
DCR_M_DBus => DCR_M_DBus,
DCR_Ack => DCR_Ack,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrDBus => Sl_dcrDBus,
Sl_dcrAck => Sl_dcrAck
);
END ARCHITECTURE implementation;
| gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/GPIO/src/hdl/RGB_controller.vhd | 1 | 5183 | ----------------------------------------------------------------------------
-- RGB_controller.vhd -- Nexys4 RGB LED controller
----------------------------------------------------------------------------
-- Author: Marshall Wingerson
-- Copyright 2013 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2013(MarshallW): Created
-- 08/30/2013(SamB): Modified RGB pattern
-- Added comments
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity RGB_controller is
port(
GCLK : in std_logic;
RGB_LED_1_O : out std_logic_vector(2 downto 0);
RGB_LED_2_O : out std_logic_vector(2 downto 0)
);
end RGB_controller;
architecture Behavioral of RGB_controller is
--counter signals
constant window: std_logic_vector(7 downto 0) := "11111111";
signal windowcount: std_logic_vector(7 downto 0) := (others => '0');
constant deltacountMax: std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(1000000, 20));
signal deltacount: std_logic_vector(19 downto 0) := (others => '0');
constant valcountMax: std_logic_vector(8 downto 0) := "101111111";
signal valcount: std_logic_vector(8 downto 0) := (others => '0');
--color intensity signals
signal incVal: std_logic_vector(7 downto 0);
signal decVal: std_logic_vector(7 downto 0);
signal redVal: std_logic_vector(7 downto 0);
signal greenVal: std_logic_vector(7 downto 0);
signal blueVal: std_logic_vector(7 downto 0);
signal redVal2: std_logic_vector(7 downto 0);
signal greenVal2: std_logic_vector(7 downto 0);
signal blueVal2: std_logic_vector(7 downto 0);
--PWM registers
signal rgbLedReg1: std_logic_vector(2 downto 0);
signal rgbLedReg2: std_logic_vector(2 downto 0);
begin
window_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if windowcount < (window) then
windowcount <= windowcount + 1;
else
windowcount <= (others => '0');
end if;
end if;
end process;
color_change_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if(deltacount < deltacountMax) then
deltacount <= deltacount + 1;
else
deltacount <= (others => '0');
end if;
end if;
end process;
color_intensity_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if(deltacount = 0) then
if(valcount < valcountMax) then
valcount <= valcount + 1;
else
valcount <= (others => '0');
end if;
end if;
end if;
end process;
incVal <= "0" & valcount(6 downto 0);
--The folowing code sets decVal to (128 - incVal)
decVal(7) <= '0';
decVal(6) <= not(valcount(6));
decVal(5) <= not(valcount(5));
decVal(4) <= not(valcount(4));
decVal(3) <= not(valcount(3));
decVal(2) <= not(valcount(2));
decVal(1) <= not(valcount(1));
decVal(0) <= not(valcount(0));
redVal <= incVal when (valcount(8 downto 7) = "00") else
decVal when (valcount(8 downto 7) = "01") else
(others => '0');
greenVal <= decVal when (valcount(8 downto 7) = "00") else
(others => '0') when (valcount(8 downto 7) = "01") else
incVal;
blueVal <= (others => '0') when (valcount(8 downto 7) = "00") else
incVal when (valcount(8 downto 7) = "01") else
decVal;
redVal2 <= incVal when (valcount(8 downto 7) = "00") else
decVal when (valcount(8 downto 7) = "01") else
(others => '0');
greenVal2 <= decVal when (valcount(8 downto 7) = "00") else
(others => '0') when (valcount(8 downto 7) = "01") else
incVal;
blueVal2 <= (others => '0') when (valcount(8 downto 7) = "00") else
incVal when (valcount(8 downto 7) = "01") else
decVal;
--red processes
red_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((redVal) > windowcount) then
rgbLedReg1(2) <= '1';
else
rgbLedReg1(2) <= '0';
end if;
end if;
end process;
--green processes
green_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((greenVal) > windowcount) then
rgbLedReg1(1) <= '1';
else
rgbLedReg1(1) <= '0';
end if;
end if;
end process;
--blue processes
blue_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((blueVal) > windowcount) then
rgbLedReg1(0) <= '1';
else
rgbLedReg1(0) <= '0';
end if;
end if;
end process;
--RGB2 processes---
--red2 processes
red2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((redVal2) > windowcount) then
rgbLedReg2(2) <= '1';
else
rgbLedReg2(2) <= '0';
end if;
end if;
end process;
--green2 processes
green2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((greenVal2) > windowcount) then
rgbLedReg2(1) <= '1';
else
rgbLedReg2(1) <= '0';
end if;
end if;
end process;
--blue2 processes
blue2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((blueVal2) > windowcount) then
rgbLedReg2(0) <= '1';
else
rgbLedReg2(0) <= '0';
end if;
end if;
end process;
RGB_LED_1_O <= rgbLedReg1;
RGB_LED_2_O <= rgbLedReg2;
end Behavioral;
| gpl-3.0 |
luebbers/reconos | support/pcores/message_manager_v1_00_a/hdl/vhdl/fast_queue_tb.vhd | 1 | 3986 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:16:35 10/31/2006
-- Design Name: fast_queue
-- Module Name: C:/fast_queueProject/src/fast_queue_tb.vhd
-- Project Name: myProj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fast_queue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fast_queue_tb IS
END fast_queue_tb;
ARCHITECTURE behavior OF fast_queue_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fast_queue
generic(
ADDRESS_BITS : integer := 2;
DATA_BITS : integer := 32
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : IN std_logic;
remove : IN std_logic;
entryToAdd : IN std_logic_vector(0 to 31);
headValid : INOUT std_logic;
full : INOUT std_logic;
empty : INOUT std_logic;
head : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL add : std_logic := '0';
SIGNAL remove : std_logic := '0';
SIGNAL entryToAdd : std_logic_vector(0 to 31) := (others=>'0');
--BiDirs
SIGNAL headValid : std_logic;
SIGNAL full : std_logic;
SIGNAL empty : std_logic;
signal add_busy : std_logic;
signal remove_busy : std_logic;
--Outputs
SIGNAL head : std_logic_vector(0 to 31);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fast_queue
GENERIC MAP(
ADDRESS_BITS => 2,
DATA_BITS => 32
)
PORT MAP(
clk => clk,
rst => rst,
add_busy => add_busy,
remove_busy => remove_busy,
add => add,
remove => remove,
entryToAdd => entryToAdd,
head => head,
headValid => headValid,
full => full,
empty => empty
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
rst <= '1'; -- Reset the FIFO
wait for 20 ns;
rst <= '0';
wait for 20 ns;
entryToAdd <= x"1111_1111"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"2222_2222"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"3333_3333"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"4444_4444"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
entryToAdd <= x"5555_5555"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
clockProcess : PROCESS
BEGIN
clk <= '1'; -- clock cycle 10 ns
wait for 5 ns;
clk <= '0';
wait for 5 ns;
END PROCESS;
END;
| gpl-3.0 |
luebbers/reconos | core/pcores/plb_osif_v2_03_a/hdl/vhdl/fifo_mgr.vhd | 3 | 3729 | --!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <[email protected]>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 04.10.2007 Enno Luebbers File created
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fifo_mgr is
generic (
C_FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- local FIFO access signals
i_local_read_remove : in std_logic;
o_local_read_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_read_wait : out std_logic; -- either empty or busy
i_local_write_add : in std_logic;
i_local_write_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_write_wait : out std_logic; -- either full or busy
-- "real" FIFO access signals
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic
-- TODO: signal to communicate with the bus_slave_regs module
);
end fifo_mgr;
architecture behavioral of fifo_mgr is
signal local_read_remove_d1 : std_logic := '0';
begin
-- delay read_remove for 1 clock cycle
process(clk, reset)
begin
if reset = '1' then
local_read_remove_d1 <= '0';
elsif rising_edge(clk) then
local_read_remove_d1 <= i_local_read_remove;
end if;
end process;
-- for now, the FIFO manager only services local accesses.
-- so we just need to pass the local access signals straight
-- through to the "real" FIFOs
o_fifo_read_en <= local_read_remove_d1; -- hack to fit slow OSIF request/busy handshake
-- this will be obsoleted once we connect the HW
-- FIFO to the burst RAM interface (mq)
o_local_read_data <= i_fifo_read_data;
o_local_read_wait <= not i_fifo_read_ready;
o_fifo_write_en <= i_local_write_add;
o_fifo_write_data <= i_local_write_data;
o_local_write_wait <= not i_fifo_write_ready;
end behavioral;
| gpl-3.0 |
makestuff/vhdl | package/gate/gate_tb.vhdl | 1 | 1963 | --
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.gate_pkg.all;
entity gate_tb is
end gate_tb;
architecture behavioural of gate_tb is
signal op : Operation;
signal a : std_logic;
signal b : std_logic;
signal x : std_logic;
begin
-- Instantiate the unit under test
uut: entity work.gate
port map(
op_in => op,
a_in => a,
b_in => b,
x_out => x
);
-- Drive the unit under test. Read stimulus from stimulus.txt and write results to results.txt
process
variable inLine, outLine : line;
variable inData : std_logic_vector(2 downto 0);
variable outData : std_logic;
file inFile : text open read_mode is "stimulus.txt";
file outFile : text open write_mode is "results.txt";
begin
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
if ( inData(2) = '1' ) then
op <= OP_AND;
else
op <= OP_OR;
end if;
a <= inData(1);
b <= inData(0);
wait for 10 ns;
outData := x;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait;
--assert false report "NONE. End of simulation." severity failure;
end process;
end architecture;
| gpl-3.0 |
luebbers/reconos | demos/huffman_demo/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd | 1 | 4660 |
------------
-- pcore top level wrapper
-- generated at 2008-01-29 13:02:52.513801 by 'mkhwtask.py hwt_memcopy 1 hwt_memcopy.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
library burst_ram_v2_01_a;
use burst_ram_v2_01_a.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 14; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 12; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
i_burstBE : in std_logic_vector(7 downto 0)
);
end hw_task;
architecture structural of hw_task is
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
constant C_GND_TASK_DATA : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_build_histo_i : entity hwt_build_histo
generic map (
C_BURST_AWIDTH => C_TASK_BURST_AWIDTH,
C_BURST_DWIDTH => C_TASK_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk
);
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => C_TASK_BURST_AWIDTH,
G_PORTA_DWIDTH => C_TASK_BURST_DWIDTH,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => C_BUS_BURST_AWIDTH-3,
G_PORTB_DWIDTH => C_BUS_BURST_DWIDTH,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkax => '0',
clkb => clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => i_burstData,
douta => burst2task_Data,
doutax => open,
doutb => o_burstData,
wea => task2burst_WE,
weax => '0',
web => i_burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => i_burstBE
);
end structural;
| gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/lpf.vhd | 23 | 17838 | -------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0;
--use lib_cdc_v1_0.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/cpu_unit/vhdl_source/dm_cache.vhd | 5 | 17774 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_mem_burst_req;
mem_resp : in t_mem_burst_resp;
hit_count : out unsigned(31 downto 0);
miss_count : out unsigned(31 downto 0) );
end dm_cache;
architecture gideon of dm_cache is
-- Our cache is 2K, and is one-set associative (direct mapped)
-- This means that the lower 11 bits are taken from the CPU address
-- while the upper address bits are matched against the tag ram.
-- Cache line size is 4 bytes, and hence we need 2K/4 = 512 tag entries.
-- Only the lower 32M is cachable, since I/O is above that range.
constant c_address_width : integer := client_req.address'length;
constant c_data_width : integer := client_req.data'length;
constant c_cache_size_bits : integer := 11;
constant c_line_size_bits : integer := 2; -- 4 words per line (entry)
constant c_tag_size_bits : integer := c_cache_size_bits - c_line_size_bits;
constant c_tag_width : natural := 2 + c_address_width - c_cache_size_bits;
function cache_index_of(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_cache_size_bits-1 downto 0);
end function;
function tag_index_of(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_cache_size_bits-1 downto c_line_size_bits);
end function;
function get_addr_high(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_address_width-1 downto c_cache_size_bits);
end function;
type t_tag is record
address_high : unsigned(c_address_width-1 downto c_cache_size_bits);
dirty : std_logic;
valid : std_logic;
end record;
function tag_pack(t : t_tag) return std_logic_vector is
variable ret : std_logic_vector(c_tag_width-1 downto 0);
begin
ret := t.dirty & t.valid & std_logic_vector(t.address_high);
return ret;
end function;
function tag_unpack(v : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.dirty := v(v'high);
ret.valid := v(v'high-1);
ret.address_high := unsigned(v(v'high-2 downto 0));
return ret;
end function;
signal any_request : std_logic := '0';
signal read_request : std_logic := '0';
signal read_request_d : std_logic := '0';
signal write_request : std_logic := '0';
signal write_request_d : std_logic := '0';
signal ready : std_logic := '0';
signal read_la : std_logic := '0';
signal write_la : std_logic := '0';
signal tag_la : std_logic_vector(client_req.tag'range);
signal do_query_d : std_logic;
signal rd_address : unsigned(c_address_width-1 downto 0);
signal wr_address : unsigned(c_address_width-1 downto 0);
signal cache_rd_index : unsigned(c_cache_size_bits-1 downto 0);
signal cache_wr_index : unsigned(c_cache_size_bits-1 downto 0);
signal cache_wdata : std_logic_vector(c_data_width-1 downto 0);
signal cache_data_out : std_logic_vector(c_data_width-1 downto 0);
signal cache_rdata : std_logic_vector(c_data_width-1 downto 0);
signal cache_we : std_logic;
signal cache_b_en : std_logic;
signal cache_rd_en : std_logic;
signal tag_rd_index : unsigned(c_cache_size_bits-1 downto c_line_size_bits);
signal tag_wr_index : unsigned(c_cache_size_bits-1 downto c_line_size_bits);
signal tag_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal rd_tag : t_tag;
signal wr_tag : t_tag;
signal fill_tag : t_tag;
signal last_write_tag : t_tag;
signal hit_i : std_logic := '0';
signal cache_miss : std_logic := '0';
signal cache_hit : std_logic := '0';
signal old_address : unsigned(c_address_width-1 downto 0);
signal address_la : unsigned(c_address_width-1 downto 0);
-- back office
signal fill_high : unsigned(c_address_width-1 downto c_line_size_bits) := (others => '0');
signal fill_address : unsigned(c_address_width-1 downto 0) := (others => '0');
signal fill_valid : std_logic;
signal fill_data : std_logic_vector(c_data_width-1 downto 0);
signal burst_count : unsigned(c_line_size_bits-1 downto 0);
signal burst_count_d : unsigned(c_line_size_bits-1 downto 0);
type t_state is (idle, check_dirty, fill, deferred);
signal state : t_state;
signal dirty_d : std_logic;
-- signals related to delayed write register
signal last_write_address : unsigned(c_address_width-1 downto 0);
signal last_write_data : std_logic_vector(c_data_width-1 downto 0);
signal last_write_hit : std_logic;
signal last_write_valid : std_logic;
signal store_reg : std_logic := '0';
signal store_after_fill : std_logic := '0';
-- memory interface
signal mem_busy : std_logic := '0';
signal need_mem_access : std_logic := '0';
signal mem_req_i : std_logic;
signal mem_rwn : std_logic;
signal mem_address : unsigned(c_address_width-1 downto 0);
signal mem_wdata : std_logic_vector(c_data_width-1 downto 0);
signal mem_wrfifo_put : std_logic;
signal mem_rdfifo_get : std_logic;
signal helper_data_to_ram : std_logic_vector(c_data_width-1 downto 0);
signal helper_data_from_ram : std_logic_vector(c_data_width-1 downto 0);
-- statistics
signal hit_count_i : unsigned(31 downto 0) := (others => '0');
signal miss_count_i : unsigned(31 downto 0) := (others => '0');
begin
any_request <= client_req.request and ready;
read_request <= client_req.request and client_req.read_writen and ready;
write_request <= client_req.request and not client_req.read_writen and ready;
ready <= '1' when mem_busy='0' and need_mem_access='0' else '0';
need_mem_access <= cache_miss;
process(clock)
begin
if rising_edge(clock) then
read_request_d <= read_request;
write_request_d <= write_request;
do_query_d <= '0';
if ready='1' then
do_query_d <= client_req.request;
tag_la <= client_req.tag;
address_la <= client_req.address;
read_la <= client_req.request and client_req.read_writen;
write_la <= client_req.request and not client_req.read_writen;
end if;
end if;
end process;
-- main address multiplexer
rd_address <= client_req.address;
wr_address <= fill_address when (fill_valid='1' or dirty_d='1') else
last_write_address;
cache_rd_index <= cache_index_of(rd_address);
cache_wr_index <= cache_index_of(wr_address);
cache_wdata <= fill_data when fill_valid='1' else
last_write_data;
wr_tag <= fill_tag when fill_valid='1' else
last_write_tag;
cache_we <= fill_valid or store_reg;
cache_b_en <= cache_we or dirty_d; -- dirty_d is set during fill operation and causes read enable here
cache_rd_en <= client_req.request and ready;
fill_tag.address_high <= get_addr_high(fill_address);
fill_tag.dirty <= '0';
fill_tag.valid <= '1';
last_write_tag.address_high <= get_addr_high(last_write_address);
last_write_tag.dirty <= '1';
last_write_tag.valid <= last_write_valid;
i_cache_ram: entity work.dpram_rdw
generic map (
g_width_bits => c_data_width,
g_depth_bits => c_cache_size_bits,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => cache_wdata,
b_en => cache_b_en,
b_we => cache_we );
tag_rd_index <= tag_index_of(rd_address);
tag_wr_index <= tag_index_of(wr_address);
rd_tag <= tag_unpack(tag_rdata);
tag_wdata <= tag_pack(wr_tag);
i_tag_ram: entity work.dpram_rdw
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits )
port map (
clock => clock,
a_address => tag_rd_index,
a_rdata => tag_rdata,
a_en => cache_rd_en,
b_address => tag_wr_index,
b_wdata => tag_wdata,
b_en => cache_we,
b_we => cache_we );
hit_i <= '1' when rd_tag.valid='1' and (rd_tag.address_high = get_addr_high(address_la)) else '0';
cache_hit <= hit_i and do_query_d;
cache_miss <= not hit_i and do_query_d;
old_address <= rd_tag.address_high & address_la(c_cache_size_bits-1 downto 0); -- recombine
-- handle writes
process(clock)
begin
if rising_edge(clock) then
last_write_hit <= '0';
if client_req.request='1' and client_req.read_writen='1' and ready='1' then -- hit only occurs on reads
if (last_write_address = client_req.address) and last_write_valid='1' then -- address equal and valid?
last_write_hit <= '1';
end if;
end if;
if client_req.request='1' and client_req.read_writen='0' and ready='1' then
last_write_data <= client_req.data;
last_write_address <= client_req.address;
last_write_valid <= '1';
elsif store_reg='1' then
last_write_valid <= '0';
end if;
end if;
end process;
store_reg <= '1' when (last_write_valid='1' and (cache_hit='1' or store_after_fill='1')) else
'0';
-- end handle writes
-- read data multiplexer
fill_valid <= mem_resp.rdata_av;
fill_data <= mem_resp.data;
client_resp.rack <= client_req.request and ready;
client_resp.rack_tag <= client_req.tag when client_req.request='1' and ready='1' else (others => '0');
process(read_request_d, tag_la, cache_hit, cache_rdata,
fill_data, fill_valid, burst_count, read_la, address_la)
begin
client_resp.dack_tag <= (others => '0');
if cache_hit='1' then
client_resp.data <= cache_rdata;
if read_request_d='1' then
client_resp.dack_tag <= tag_la;
end if;
else
client_resp.data <= fill_data;
-- Generate dack when correct word passes by (not necessary, but will increase performance)
-- (In this setup it is necessary, because there is no other cause to let the client continue,
-- as 'hit' will not automatically become '1', as we already acknowledged the request itself.)
if fill_valid='1' and burst_count = address_la(burst_count'range) and read_la='1' then
client_resp.dack_tag <= tag_la;
end if;
end if;
end process;
-- end read data multiplexer
p_cache_control: process(clock)
begin
if rising_edge(clock) then
burst_count_d <= burst_count;
store_after_fill <= '0';
mem_req_i <= '0';
if cache_miss='1' then
miss_count_i <= miss_count_i + 1;
end if;
if cache_hit='1' then
hit_count_i <= hit_count_i + 1;
end if;
case state is
when idle =>
-- There are a few scenarios that could cause a miss:
-- Read miss: last_write_register is not valid, because it should already have been written in the cache!
-- Write miss: last_write_register is always valid, since it was just set. In this scenario the last write register
-- holds data that still needs to be written to the cache, BUT couldn't do it because of the miss. The data in the cache
-- that is flushed to DRAM is never the data in the register, otherwise it would have been a hit. The fill cycle that
-- follows will check dirty, do a write out of the dirty data from cache, and then fills the cacheline with data from
-- the DRAM, and then will issue the command to store the register. Obviously this immediately sets the line to dirty.
if cache_miss='1' then
if mem_resp.ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_address <= address_la;
state <= check_dirty;
else
state <= deferred;
end if;
end if;
dirty_d <= rd_tag.dirty and cache_miss; -- dirty will be our read enable from cache :)
--fill_high <= old_address(old_address'high downto c_line_size_bits); -- high bits don't matter here (this is correct!)
--fill_high <= address_la(old_address'high downto c_line_size_bits); -- high bits don't matter here (optimization!!)
when deferred =>
if mem_resp.ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_address <= address_la;
state <= check_dirty;
end if;
when check_dirty => -- sequences through 'line_size' words
mem_address <= old_address;
mem_rwn <= '0'; -- write
if dirty_d='0' then
--fill_high <= address_la(address_la'high downto c_line_size_bits); -- high bits do matter here
state <= fill;
else -- dirty_d='1'
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
mem_req_i <= '1'; -- issue the write request to memctrl
dirty_d <= '0';
--fill_high <= address_la(address_la'high downto c_line_size_bits); -- high bits do matter here
state <= fill;
end if;
end if;
when fill =>
if mem_resp.rdata_av='1' then
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
state <= idle;
store_after_fill <= last_write_valid; -- this will occur during idle
end if;
end if;
-- asynchronously: mem_rdfifo_get <= '1' when state = fill and mem_resp.rdata_av='1'.
when others =>
null;
end case;
mem_wrfifo_put <= dirty_d; -- latency of blockram
if reset='1' then
burst_count <= (others => '0');
dirty_d <= '0';
state <= idle;
mem_rwn <= '1';
mem_req_i <= '0';
end if;
end if;
end process;
mem_rdfifo_get <= '1' when state = fill and mem_resp.rdata_av='1' else '0';
-- index to the cache for back-office operations (line in, line out)
fill_high <= address_la(old_address'high downto c_line_size_bits);
fill_address <= fill_high & burst_count;
mem_busy <= '1' when (state/= idle) else '0';
mem_wdata <= cache_data_out;
mem_req.request <= mem_req_i;
mem_req.read_writen <= mem_rwn;
mem_req.address <= mem_address(mem_address'high downto c_line_size_bits) & to_unsigned(0, c_line_size_bits);
mem_req.data <= mem_wdata;
mem_req.data_pop <= mem_rdfifo_get;
mem_req.data_push <= mem_wrfifo_put;
helper_data_to_ram <= mem_wdata when mem_wrfifo_put='1' else (others => 'Z');
helper_data_from_ram <= mem_resp.data when mem_rdfifo_get='1' else (others => 'Z');
hit_count <= hit_count_i;
miss_count <= miss_count_i;
end gideon;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/1541/vhdl_source/gcr_encoder.vhd | 5 | 1636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/6502/vhdl_sim/tb_implied_hi.vhd | 5 | 2448 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tb_implied_hi is
end tb_implied_hi;
architecture tb of tb_implied_hi is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal z_in : std_logic := 'Z';
signal d_in : std_logic := 'Z';
signal v_in : std_logic := 'Z';
signal reg_a : std_logic_vector(7 downto 0) := X"11";
signal reg_x : std_logic_vector(7 downto 0) := X"01";
signal reg_y : std_logic_vector(7 downto 0) := X"FF";
signal reg_s : std_logic_vector(7 downto 0) := X"44";
signal n_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal v_out : std_logic;
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal opcode : string(1 to 3);
type t_implied_opcode is array(0 to 15) of string(1 to 3);
constant implied_opcodes : t_implied_opcode := (
"DEY", "TAY", "INY", "INX",
"TXA", "TAX", "DEX", "NOP",
"TYA", "CLV", "CLD", "SED",
"TXS", "TSX", "---", "---" );
begin
mut: entity work.implied_hi
port map (
inst => inst,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => reg_a,
reg_x => reg_x,
reg_y => reg_y,
reg_s => reg_s,
n_out => n_out,
z_out => z_out,
d_out => d_out,
v_out => v_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => data_out );
test: process
variable inst_thumb : std_logic_vector(3 downto 0);
begin
for i in 0 to 15 loop
inst_thumb := conv_std_logic_vector(i, 4);
inst <= '1' & inst_thumb(1 downto 0) & inst_thumb(3) & "10" & inst_thumb(2) & '0';
opcode <= implied_opcodes(i);
wait for 1 us;
end loop;
wait;
end process;
end tb;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/cart_slot/vhdl_source/slot_server_v4.vhd | 3 | 27534 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.cart_slot_pkg.all;
entity slot_server_v4 is
generic (
g_tag_slot : std_logic_vector(7 downto 0) := X"08";
g_tag_reu : std_logic_vector(7 downto 0) := X"10";
g_ram_base_reu : unsigned(27 downto 0) := X"1000000"; -- should be on 16M boundary, or should be limited in size
g_ram_base_cart : unsigned(27 downto 0) := X"0F70000"; -- should be on a 64K boundary
g_rom_base_cart : unsigned(27 downto 0) := X"0F80000"; -- should be on a 512K boundary
g_control_read : boolean := true;
g_command_intf : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_sampler : boolean := false;
g_implement_sid : boolean := true;
g_sid_voices : natural := 3;
g_vic_copper : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : inout std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
PHI2 : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
DMAn : out std_logic := '1';
BA : in std_logic := '0';
ROMLn : in std_logic;
ROMHn : in std_logic;
GAMEn : inout std_logic;
EXROMn : inout std_logic;
RWn : inout std_logic;
ADDRESS : inout std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
-- other hardware pins
BUFFER_ENn : out std_logic;
buttons : in std_logic_vector(2 downto 0);
cart_led_n : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
-- debug
freezer_state : out std_logic_vector(1 downto 0);
-- audio output
sid_pwm_left : out std_logic := '0';
sid_pwm_right : out std_logic := '0';
samp_pwm_left : out std_logic := '0';
samp_pwm_right : out std_logic := '0';
-- timing output
phi2_tick : out std_logic;
c64_stopped : out std_logic;
-- master on memory bus
memctrl_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- slave on io bus
io_req : in t_io_req;
io_resp : out t_io_resp );
end slot_server_v4;
architecture structural of slot_server_v4 is
signal phi2_tick_i : std_logic;
signal phi2_recovered : std_logic;
signal vic_cycle : std_logic;
signal do_sample_addr : std_logic;
signal do_sample_io : std_logic;
signal do_io_event : std_logic;
signal do_probe_end : std_logic;
signal timing_inhibit : std_logic;
signal slave_dout : std_logic_vector(7 downto 0);
signal slave_dtri : std_logic := '0';
signal master_dout : std_logic_vector(7 downto 0);
signal master_dtri : std_logic := '0';
signal address_tri_l : std_logic;
signal address_tri_h : std_logic;
signal address_out : std_logic_vector(15 downto 0);
signal rwn_tri : std_logic;
signal rwn_out : std_logic;
signal control : t_cart_control;
signal status : t_cart_status;
signal allow_serve : std_logic;
-- interface with freezer (cartridge) logic
signal serve_enable : std_logic := '0'; -- from cartridge emulation logic
signal serve_vic : std_logic := '0';
signal serve_rom : std_logic := '0'; -- ROML or ROMH
signal serve_io1 : std_logic := '0'; -- IO1n
signal serve_io2 : std_logic := '0'; -- IO2n
signal allow_write : std_logic := '0';
-- kernal replacement logic
signal kernal_area : std_logic := '0';
signal kernal_probe : std_logic := '0';
signal kernal_addr_out : std_logic := '0';
signal force_ultimax : std_logic := '0';
signal cpu_write : std_logic;
signal epyx_timeout : std_logic;
signal reu_dma_n : std_logic := '1'; -- direct from REC
signal cmd_if_freeze : std_logic := '0'; -- same function as reu_dma_n, but then from CI
signal mask_buttons : std_logic := '0';
signal reset_button : std_logic;
signal freeze_button : std_logic;
signal actual_c64_reset : std_logic;
signal dma_n : std_logic := '1';
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal exrom_n : std_logic := '1';
signal game_n : std_logic := '1';
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal unfreeze : std_logic;
signal freeze_trig : std_logic;
signal freeze_act : std_logic;
signal io_req_dma : t_io_req;
signal io_resp_dma : t_io_resp := c_io_resp_init;
signal io_req_peri : t_io_req;
signal io_resp_peri : t_io_resp := c_io_resp_init;
signal io_req_sid : t_io_req;
signal io_resp_sid : t_io_resp := c_io_resp_init;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_cmd : t_io_req;
signal io_resp_cmd : t_io_resp := c_io_resp_init;
signal io_req_copper : t_io_req;
signal io_resp_copper : t_io_resp := c_io_resp_init;
signal io_req_samp_cpu : t_io_req;
signal io_resp_samp_cpu : t_io_resp := c_io_resp_init;
signal dma_req_io : t_dma_req;
signal dma_resp_io : t_dma_resp := c_dma_resp_init;
signal dma_req_reu : t_dma_req;
signal dma_resp_reu : t_dma_resp := c_dma_resp_init;
signal dma_req_copper : t_dma_req;
signal dma_resp_copper : t_dma_resp := c_dma_resp_init;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp := c_dma_resp_init;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp := c_slot_resp_init;
signal slot_resp_reu : t_slot_resp := c_slot_resp_init;
signal slot_resp_cart : t_slot_resp := c_slot_resp_init;
signal slot_resp_sid : t_slot_resp := c_slot_resp_init;
signal slot_resp_cmd : t_slot_resp := c_slot_resp_init;
signal slot_resp_samp : t_slot_resp := c_slot_resp_init;
signal mem_req_slot : t_mem_req := c_mem_req_init;
signal mem_resp_slot : t_mem_resp := c_mem_resp_init;
signal mem_req_reu : t_mem_req := c_mem_req_init;
signal mem_resp_reu : t_mem_resp := c_mem_resp_init;
signal mem_req_samp : t_mem_req := c_mem_req_init;
signal mem_resp_samp : t_mem_resp := c_mem_resp_init;
-- signal mem_req_trace : t_mem_req;
-- signal mem_resp_trace : t_mem_resp;
signal mem_rack_slot : std_logic;
signal mem_dack_slot : std_logic;
signal sid_sample_left : signed(17 downto 0);
signal sid_sample_right : signed(17 downto 0);
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
begin
reset_button <= buttons(0) when control.swap_buttons='0' else buttons(2);
freeze_button <= buttons(2) when control.swap_buttons='0' else buttons(0);
i_split_64K: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_peri, -- 4040000
reqs(1) => io_req_dma, -- 4050000
resps(0) => io_resp_peri,
resps(1) => io_resp_dma );
i_bridge: entity work.io_to_dma_bridge
port map (
clock => clock,
reset => reset,
c64_stopped => status.c64_stopped,
io_req => io_req_dma,
io_resp => io_resp_dma,
dma_req => dma_req_io,
dma_resp => dma_resp_io );
i_split_8K: entity work.io_bus_splitter
generic map (
g_range_lo => 13,
g_range_hi => 15,
g_ports => 5 )
port map (
clock => clock,
req => io_req_peri,
resp => io_resp_peri,
reqs(0) => io_req_regs, -- 4040000
reqs(1) => io_req_sid, -- 4042000
reqs(2) => io_req_cmd, -- 4044000
reqs(3) => io_req_copper, -- 4046000
reqs(4) => io_req_samp_cpu, -- 4048000
resps(0) => io_resp_regs,
resps(1) => io_resp_sid,
resps(2) => io_resp_cmd,
resps(3) => io_resp_copper,
resps(4) => io_resp_samp_cpu );
i_registers: entity work.cart_slot_registers
generic map (
g_rom_base => g_rom_base_cart,
g_ram_base => g_ram_base_cart,
-- g_control_read => g_control_read,
g_ram_expansion => g_ram_expansion )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_timing: entity work.slot_timing
port map (
clock => clock,
reset => reset,
-- Cartridge pins
PHI2 => PHI2,
BA => BA,
serve_vic => serve_vic,
serve_enable => serve_enable,
serve_inhibit => status.c64_stopped,
allow_serve => allow_serve,
timing_addr => control.timing_addr_valid,
edge_recover => control.phi2_edge_recover,
phi2_tick => phi2_tick_i,
phi2_recovered => phi2_recovered,
clock_det => status.clock_detect,
vic_cycle => vic_cycle,
inhibit => timing_inhibit,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_probe_end => do_probe_end,
do_io_event => do_io_event );
mem_req_slot.tag <= g_tag_slot;
mem_rack_slot <= '1' when mem_resp_slot.rack_tag = g_tag_slot else '0';
mem_dack_slot <= '1' when mem_resp_slot.dack_tag = g_tag_slot else '0';
i_slave: entity work.slot_slave
port map (
clock => clock,
reset => reset,
-- Cartridge pins
RSTn => RSTn,
IO1n => IO1n,
IO2n => IO2n,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
BA => BA,
ADDRESS => ADDRESS,
DATA_in => DATA,
DATA_out => slave_dout,
DATA_tri => slave_dtri,
-- interface with memory controller
mem_req => mem_req_slot.request,
mem_rwn => mem_req_slot.read_writen,
mem_wdata => mem_req_slot.data,
mem_size => mem_req_slot.size,
mem_rack => mem_rack_slot,
mem_dack => mem_dack_slot,
mem_rdata => mem_resp_slot.data,
mem_count => mem_resp.count,
-- mem_addr comes from cartridge logic
-- synchronized outputs
reset_out => actual_c64_reset,
-- timing inputs
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
do_probe_end => do_probe_end,
-- interface with freezer (cartridge) logic
allow_serve => allow_serve,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
-- kernal emulation
kernal_enable => control.kernal_enable,
kernal_probe => kernal_probe,
kernal_area => kernal_area,
force_ultimax => force_ultimax,
cpu_write => cpu_write,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp,
-- interface with hardware
BUFFER_ENn => BUFFER_ENn );
i_master: entity work.slot_master_v4
port map (
clock => clock,
reset => reset,
-- Cartridge pins
DMAn => dma_n,
BA => BA,
RWn_in => RWn,
RWn_out => rwn_out,
RWn_tri => rwn_tri,
ADDRESS_out => address_out,
ADDRESS_tri_h => address_tri_h,
ADDRESS_tri_l => address_tri_l,
DATA_in => DATA,
DATA_out => master_dout,
DATA_tri => master_dtri,
-- timing inputs
vic_cycle => vic_cycle,
phi2_recovered => phi2_recovered,
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
reu_dma_n => reu_dma_n,
cmd_if_freeze => cmd_if_freeze,
-- request from the cpu to do a cycle on the cart bus
dma_req => dma_req,
dma_resp => dma_resp,
-- system control
stop_cond => control.c64_stop_mode,
c64_stop => control.c64_stop,
c64_stopped => status.c64_stopped );
i_freeze: entity work.freezer
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
button_freeze => freeze_button,
cpu_cycle_done => do_io_event,
cpu_write => cpu_write,
freezer_state => freezer_state,
unfreeze => unfreeze,
freeze_trig => freeze_trig,
freeze_act => freeze_act );
i_cart_logic: entity work.all_carts_v4
generic map (
g_rom_base => std_logic_vector(g_rom_base_cart),
g_ram_base => std_logic_vector(g_ram_base_cart) )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
c64_reset => control.c64_reset,
ethernet_enable => control.eth_enable,
freeze_trig => freeze_trig,
freeze_act => freeze_act,
unfreeze => unfreeze,
cart_logic => control.cartridge_type,
cart_kill => control.cartridge_kill,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp_cart,
mem_addr => mem_req_slot.address,
serve_enable => serve_enable,
serve_vic => serve_vic,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
kernal_area => kernal_area,
kernal_enable => control.kernal_enable,
irq_n => irq_n,
nmi_n => nmi_n,
exrom_n => exrom_n,
game_n => game_n,
CART_LEDn => cart_led_n );
r_sid: if g_implement_sid generate
begin
-- i_trce: entity work.sid_trace
-- generic map (
-- g_mem_tag => X"CE" )
-- port map (
-- clock => clock,
-- reset => actual_c64_reset,
--
-- addr => unsigned(slot_addr(6 downto 0)),
-- wren => sid_write,
-- wdata => io_wdata,
--
-- phi2_tick => phi2_tick_i,
--
-- io_req => io_req_trace,
-- io_resp => io_resp_trace,
--
-- mem_req => mem_req_trace,
-- mem_resp => mem_resp_trace );
i_sid: entity work.sid_peripheral
generic map (
g_num_voices => g_sid_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_sid,
io_resp => io_resp_sid,
slot_req => slot_req,
slot_resp => slot_resp_sid,
start_iter => phi2_tick_i,
sample_left => sid_sample_left,
sample_right => sid_sample_right );
i_pdm_sid_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_left'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_left,
dac_out => sid_pwm_left );
i_pdm_sid_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_right'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_right,
dac_out => sid_pwm_right );
end generate;
g_cmd: if g_command_intf generate
i_cmd: entity work.command_interface
port map (
clock => clock,
reset => reset,
-- C64 side interface
slot_req => slot_req,
slot_resp => slot_resp_cmd,
freeze => cmd_if_freeze,
-- io interface for local cpu
io_req => io_req_cmd, -- we get an 8K range
io_resp => io_resp_cmd );
end generate;
g_reu: if g_ram_expansion generate
begin
i_reu: entity work.reu
generic map (
g_extended => g_extended_reu,
g_ram_base => g_ram_base_reu,
g_ram_tag => g_tag_reu )
port map (
clock => clock,
reset => actual_c64_reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp_reu,
-- system interface
phi2_tick => do_io_event,
reu_dma_n => reu_dma_n,
size_ctrl => control.reu_size,
enable => control.reu_enable,
-- memory interface
mem_req => mem_req_reu,
mem_resp => mem_resp_reu,
dma_req => dma_req_reu,
dma_resp => dma_resp_reu );
end generate;
r_copper: if g_vic_copper generate
i_copper: entity work.copper
port map (
clock => clock,
reset => reset,
irq_n => IRQn,
phi2_tick => phi2_tick_i,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
io_req => io_req_copper,
io_resp => io_resp_copper,
dma_req => dma_req_copper,
dma_resp => dma_resp_copper,
slot_req => slot_req,
slot_resp => open ); -- never required, just snoop!
end generate;
r_sampler: if g_sampler generate
signal local_io_req : t_io_req := c_io_req_init;
signal local_io_resp : t_io_resp;
signal io_req_samp : t_io_req;
signal io_resp_samp : t_io_resp;
signal irq_samp : std_logic;
begin
i_io_bridge: entity work.slot_to_io_bridge
generic map (
g_io_base => X"48000", -- dont care in this context
g_slot_start => "100100000",
g_slot_stop => "111111111" )
port map (
clock => clock,
reset => reset,
enable => control.sampler_enable,
irq_in => irq_samp,
slot_req => slot_req,
slot_resp => slot_resp_samp,
io_req => local_io_req,
io_resp => local_io_resp );
i_io_arb_sampler: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => io_req_samp_cpu,
reqs(1) => local_io_req,
resps(0) => io_resp_samp_cpu,
resps(1) => local_io_resp,
req => io_req_samp,
resp => io_resp_samp );
i_sampler: entity work.sampler
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => actual_c64_reset,
io_req => io_req_samp,
io_resp => io_resp_samp,
mem_req => mem_req_samp,
mem_resp => mem_resp_samp,
irq => irq_samp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => open );
i_pdm_samp_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_L,
dac_out => samp_pwm_left );
i_pdm_samp_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_R,
dac_out => samp_pwm_right );
end generate;
slot_resp <= or_reduce(slot_resp_reu & slot_resp_cart & slot_resp_sid & slot_resp_cmd & slot_resp_samp);
p_probe_address_delay: process(clock)
variable kernal_probe_d : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clock) then
kernal_addr_out <= kernal_probe_d(0);
kernal_probe_d := kernal_probe & kernal_probe_d(kernal_probe_d'high downto 1);
end if;
end process;
ADDRESS(7 downto 0) <= address_out(7 downto 0) when address_tri_l='1' else (others => 'Z');
ADDRESS(12 downto 8) <= address_out(12 downto 8) when address_tri_h='1' else (others => 'Z');
ADDRESS(15 downto 13) <= "101" when (kernal_addr_out='1' and kernal_probe='1') else
address_out(15 downto 13) when address_tri_h='1' else (others => 'Z');
RWn <= rwn_out when rwn_tri='1' else 'Z';
DATA <= slave_dout when (slave_dtri='1') else
master_dout when (master_dtri='1') else (others => 'Z');
-- open drain outputs
irq_oc <= '0' when irq_n='0' or slot_resp.irq='1' else '1';
nmi_oc <= '0' when (control.c64_nmi='1') or (nmi_n='0') else '1';
rst_oc <= '0' when (reset_button='1' and status.c64_stopped='0' and mask_buttons='0') or
(control.c64_reset='1') else '1';
dma_oc <= '0' when (dma_n='0' or kernal_probe='1') else '1';
-- dma_oc <= '0' when (dma_n='0') else '1';
process(control, serve_enable, exrom_n, game_n, force_ultimax, kernal_probe)
begin
exrom_oc <= '1';
game_oc <= '1';
if (force_ultimax = '1') or (control.c64_ultimax = '1') then
game_oc <= '0';
elsif kernal_probe = '1' then
game_oc <= '0';
exrom_oc <= '0';
else
if (serve_enable='1' and exrom_n='0') then
exrom_oc <= '0';
end if;
if (serve_enable='1' and game_n='0') then
game_oc <= '0';
end if;
end if;
end process;
irq_push: entity work.oc_pusher port map(clock => clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => clock, sig_in => nmi_oc, oc_out => NMIn);
rst_push: entity work.oc_pusher port map(clock => clock, sig_in => rst_oc, oc_out => RSTn);
dma_push: entity work.oc_pusher port map(clock => clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => clock, sig_in => game_oc, oc_out => GAMEn);
-- arbitration
i_dma_arb: entity work.dma_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => dma_req_io,
reqs(1) => dma_req_reu,
reqs(2) => dma_req_copper,
resps(0) => dma_resp_io,
resps(1) => dma_resp_reu,
resps(2) => dma_resp_copper,
req => dma_req,
resp => dma_resp );
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_slot,
reqs(1) => mem_req_reu,
reqs(2) => mem_req_samp,
-- reqs(3) => mem_req_trace,
resps(0) => mem_resp_slot,
resps(1) => mem_resp_reu,
resps(2) => mem_resp_samp,
-- resps(3) => mem_resp_trace,
req => mem_req,
resp => mem_resp );
-- Delay the inhibit one clock cycle, because our
-- arbited introduces one clock cycle delay as well.
process(clock)
begin
if rising_edge(clock) then
memctrl_inhibit <= timing_inhibit;
end if;
end process;
phi2_tick <= phi2_tick_i;
c64_stopped <= status.c64_stopped;
end structural;
| gpl-3.0 |
vtfr/somador-4bits-com-acumulador | src/vhdl/somador_4bits.vhdl | 1 | 912 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Somador de 4 bits
entity somador_4bits is
port (
a, b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
cin : in std_logic;
cout : out std_logic;
vdd : in std_logic;
vss : in std_logic
);
end somador_4bits;
-- Implementacao do Somador de 4 bits usando quatro somadores
-- de 1 bit
architecture structural of somador_4bits is
component somador_1bit
port (
a, b, cin : in std_logic;
s, cout : out std_logic;
vdd : in std_logic;
vss : in std_logic
);
end component;
signal c1, c2, c3: std_logic;
begin
S0: somador_1bit port map (a(0), b(0), cin, s(0), c1, vdd, vss);
S1: somador_1bit port map (a(1), b(1), c1, s(1), c2, vdd, vss);
S2: somador_1bit port map (a(2), b(2), c2, s(2), c3, vdd, vss);
S3: somador_1bit port map (a(3), b(3), c3, s(3), cout, vdd, vss);
end structural;
| gpl-3.0 |
davidhorrocks/1541UltimateII | target/simulation/vhdl_bfm/sram_model_8.vhd | 5 | 2119 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/1541/vhdl_source/floppy_mem.vhd | 5 | 3736 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy
-------------------------------------------------------------------------------
-- File : floppy_mem.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the interface to the buffer, for the
-- floppy model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_mem is
generic (
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
drv_wdata : in std_logic_vector(7 downto 0);
drv_rdata : out std_logic_vector(7 downto 0);
do_read : in std_logic;
do_write : in std_logic;
do_advance : in std_logic;
track_start : in std_logic_vector(25 downto 0);
max_offset : in std_logic_vector(13 downto 0);
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy_mem;
architecture gideon of floppy_mem is
type t_state is (idle, reading, writing);
signal state : t_state;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable offset_count : unsigned(13 downto 0);
procedure advance is
begin
if offset_count >= unsigned(max_offset) then
offset_count := (others => '0');
else
offset_count := offset_count + 1;
end if;
end procedure;
begin
if rising_edge(clock) then
case state is
when idle =>
if do_read='1' then
advance;
state <= reading;
mem_req.read_writen <= '1';
mem_req.request <= '1';
elsif do_write='1' then
advance;
state <= writing;
mem_req.read_writen <= '0';
mem_req.request <= '1';
elsif do_advance='1' then
advance;
end if;
mem_req.data <= drv_wdata;
mem_req.address <= unsigned(track_start) + offset_count;
when reading =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when writing =>
if mem_rack='1' then
mem_req.request <= '0';
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
offset_count := (others => '0');
state <= idle;
mem_req <= c_mem_req_init;
mem_req.tag <= g_tag;
drv_rdata <= X"FF";
end if;
end if;
end process;
end gideon;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5.vhd | 3 | 11994 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5 is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_burst_16_req;
resp : out t_mem_burst_16_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002A", "000" ), -- mode register, burstlen=4, writelen=4, CAS lat = 2, interleaved
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic_vector(1 downto 0) := "00";
signal r_valid : std_logic_vector(3 downto 0) := "0000";
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal cs_n_i : std_logic;
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_hi_d : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack : std_logic;
signal rack : std_logic;
signal dnext : std_logic;
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal addr_row : std_logic_vector(12 downto 0);
signal addr_column : std_logic_vector(9 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
-- attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
addr_bank <= std_logic_vector(req.address(3 downto 2));
addr_row <= std_logic_vector(req.address(24 downto 12));
addr_column <= std_logic_vector(req.address(11 downto 4)) & std_logic_vector(req.address(1 downto 0));
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_hi_d & rdata_lo;
resp.rack <= rack;
resp.dack <= dack;
resp.dnext <= dnext;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rwn_i <= req.read_writen;
last_bank <= addr_bank;
mem_a_i(12 downto 0) <= addr_row;
mem_a_i(14 downto 13) <= addr_bank;
col_addr <= addr_column;
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
dnext <= '1'; -- if we set delay to a value not equal to zero, we should not
-- set the dnext here.
end procedure;
begin
if rising_edge(clock) then
dack <= '0';
dnext <= '0';
inhibit_d <= inhibit;
rdata_hi_d <= rdata_hi;
cs_n_i <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
sram_d_t <= '0' & sram_d_t(1);
r_valid <= '0' & r_valid(3 downto 1);
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
cs_n_i <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
-- we always perform auto precharge.
-- If the next access is to ANOTHER bank, then
-- we do not have to wait AFTER issuing this CAS.
-- the delay after the CAS, causes the next RAS to
-- be further away in time. If there is NO access
-- pending, then we assume the same bank, and introduce
-- the delay.
if (req_i='1' and addr_bank=last_bank) or req_i='0' then
refr_delay <= 2;
end if;
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
if delay <= 1 then
dnext <= '1';
end if;
if delay = 0 then
if rwn_i='0' then
sram_d_t <= "11";
else
r_valid(3 downto 2) <= "11";
end if;
-- read or write with auto precharge
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 1;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
-- sram_d_t <= (others => '0');
delay <= 0;
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
process(state, do_refresh, inhibit, inhibit_d, req_i, refr_delay)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
null;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
MEM_D <= sram_d_o when sram_d_t(0)='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
select_out: FDDRRSE
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q0 => rdata_lo(i),
Q1 => rdata_hi(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D => MEM_D(i),
R => reset,
S => '0');
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sram_d_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => req.data(8+i),
D1 => req.data(i),
R => reset,
S => '0' );
end generate;
end Gideon;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/ip/video/vhdl_source/char_generator_rom_pkg.vhd | 4 | 16416 | library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"1F", X"1F", X"18", X"18", X"18", X"00", X"00", X"00", X"FF",
X"FF", X"00", X"00", X"00", X"00", X"00", X"00", X"F8", X"F8", X"18",
X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"00", X"00", X"00", X"18", X"18",
X"18", X"F8", X"F8", X"00", X"00", X"00", X"00", X"00", X"00", X"07",
X"0F", X"1C", X"18", X"18", X"00", X"00", X"00", X"FF", X"FF", X"18",
X"18", X"18", X"00", X"00", X"00", X"E0", X"F0", X"38", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"18", X"18", X"18", X"18", X"18",
X"18", X"FF", X"FF", X"18", X"18", X"18", X"18", X"18", X"18", X"F8",
X"F8", X"18", X"18", X"18", X"18", X"18", X"1C", X"0F", X"07", X"00",
X"00", X"00", X"18", X"18", X"18", X"FF", X"FF", X"00", X"00", X"00",
X"18", X"18", X"38", X"F0", X"E0", X"00", X"00", X"00", X"00", X"38",
X"6D", X"67", X"66", X"6E", X"3B", X"00", X"3C", X"66", X"66", X"6C",
X"66", X"66", X"6C", X"60", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"18", X"18", X"18", X"18", X"00", X"00",
X"18", X"00", X"66", X"66", X"66", X"00", X"00", X"00", X"00", X"00",
X"66", X"66", X"FF", X"66", X"FF", X"66", X"66", X"00", X"18", X"3E",
X"60", X"3C", X"06", X"7C", X"18", X"00", X"62", X"66", X"0C", X"18",
X"30", X"66", X"46", X"00", X"3C", X"66", X"3C", X"38", X"67", X"66",
X"3F", X"00", X"06", X"0C", X"18", X"00", X"00", X"00", X"00", X"00",
X"0C", X"18", X"30", X"30", X"30", X"18", X"0C", X"00", X"30", X"18",
X"0C", X"0C", X"0C", X"18", X"30", X"00", X"00", X"66", X"3C", X"FF",
X"3C", X"66", X"00", X"00", X"00", X"18", X"18", X"7E", X"18", X"18",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"30",
X"00", X"00", X"00", X"7E", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"18", X"18", X"00", X"00", X"03", X"06", X"0C",
X"18", X"30", X"60", X"00", X"3C", X"66", X"6E", X"76", X"66", X"66",
X"3C", X"00", X"18", X"18", X"38", X"18", X"18", X"18", X"7E", X"00",
X"3C", X"66", X"06", X"0C", X"30", X"60", X"7E", X"00", X"3C", X"66",
X"06", X"1C", X"06", X"66", X"3C", X"00", X"06", X"0E", X"1E", X"66",
X"7F", X"06", X"06", X"00", X"7E", X"60", X"7C", X"06", X"06", X"66",
X"3C", X"00", X"3C", X"66", X"60", X"7C", X"66", X"66", X"3C", X"00",
X"7E", X"66", X"0C", X"18", X"18", X"18", X"18", X"00", X"3C", X"66",
X"66", X"3C", X"66", X"66", X"3C", X"00", X"3C", X"66", X"66", X"3E",
X"06", X"66", X"3C", X"00", X"00", X"00", X"18", X"00", X"00", X"18",
X"00", X"00", X"00", X"00", X"18", X"00", X"00", X"18", X"18", X"30",
X"0E", X"18", X"30", X"60", X"30", X"18", X"0E", X"00", X"00", X"00",
X"7E", X"00", X"7E", X"00", X"00", X"00", X"70", X"18", X"0C", X"06",
X"0C", X"18", X"70", X"00", X"3C", X"66", X"06", X"0C", X"18", X"00",
X"18", X"00", X"3C", X"66", X"6E", X"6E", X"60", X"62", X"3C", X"00",
X"18", X"3C", X"66", X"7E", X"66", X"66", X"66", X"00", X"7C", X"66",
X"66", X"7C", X"66", X"66", X"7C", X"00", X"3C", X"66", X"60", X"60",
X"60", X"66", X"3C", X"00", X"78", X"6C", X"66", X"66", X"66", X"6C",
X"78", X"00", X"7E", X"60", X"60", X"78", X"60", X"60", X"7E", X"00",
X"7E", X"60", X"60", X"78", X"60", X"60", X"60", X"00", X"3C", X"66",
X"60", X"6E", X"66", X"66", X"3C", X"00", X"66", X"66", X"66", X"7E",
X"66", X"66", X"66", X"00", X"3C", X"18", X"18", X"18", X"18", X"18",
X"3C", X"00", X"1E", X"0C", X"0C", X"0C", X"0C", X"6C", X"38", X"00",
X"66", X"6C", X"78", X"70", X"78", X"6C", X"66", X"00", X"60", X"60",
X"60", X"60", X"60", X"60", X"7E", X"00", X"63", X"77", X"7F", X"6B",
X"63", X"63", X"63", X"00", X"66", X"76", X"7E", X"7E", X"6E", X"66",
X"66", X"00", X"3C", X"66", X"66", X"66", X"66", X"66", X"3C", X"00",
X"7C", X"66", X"66", X"7C", X"60", X"60", X"60", X"00", X"3C", X"66",
X"66", X"66", X"66", X"3C", X"0E", X"00", X"7C", X"66", X"66", X"7C",
X"78", X"6C", X"66", X"00", X"3C", X"66", X"60", X"3C", X"06", X"66",
X"3C", X"00", X"7E", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"66", X"66", X"66", X"66", X"66", X"66", X"3C", X"00", X"66", X"66",
X"66", X"66", X"66", X"3C", X"18", X"00", X"63", X"63", X"63", X"6B",
X"7F", X"77", X"63", X"00", X"66", X"66", X"3C", X"18", X"3C", X"66",
X"66", X"00", X"66", X"66", X"66", X"3C", X"18", X"18", X"18", X"00",
X"7E", X"06", X"0C", X"18", X"30", X"60", X"7E", X"00", X"3C", X"30",
X"30", X"30", X"30", X"30", X"3C", X"00", X"00", X"60", X"30", X"18",
X"0C", X"06", X"03", X"00", X"3C", X"0C", X"0C", X"0C", X"0C", X"0C",
X"3C", X"00", X"18", X"3C", X"66", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"18", X"0C",
X"06", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"3C", X"06",
X"3E", X"66", X"3E", X"00", X"00", X"60", X"60", X"7C", X"66", X"66",
X"7C", X"00", X"00", X"00", X"3C", X"60", X"60", X"60", X"3C", X"00",
X"00", X"06", X"06", X"3E", X"66", X"66", X"3E", X"00", X"00", X"00",
X"3C", X"66", X"7E", X"60", X"3C", X"00", X"00", X"0E", X"18", X"3E",
X"18", X"18", X"18", X"00", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"7C", X"00", X"60", X"60", X"7C", X"66", X"66", X"66", X"00",
X"00", X"18", X"00", X"38", X"18", X"18", X"3C", X"00", X"00", X"06",
X"00", X"06", X"06", X"06", X"06", X"3C", X"00", X"60", X"60", X"6C",
X"78", X"6C", X"66", X"00", X"00", X"38", X"18", X"18", X"18", X"18",
X"3C", X"00", X"00", X"00", X"66", X"7F", X"7F", X"6B", X"63", X"00",
X"00", X"00", X"7C", X"66", X"66", X"66", X"66", X"00", X"00", X"00",
X"3C", X"66", X"66", X"66", X"3C", X"00", X"00", X"00", X"7C", X"66",
X"66", X"7C", X"60", X"60", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"06", X"00", X"00", X"7C", X"66", X"60", X"60", X"60", X"00",
X"00", X"00", X"3E", X"60", X"3C", X"06", X"7C", X"00", X"00", X"18",
X"7E", X"18", X"18", X"18", X"0E", X"00", X"00", X"00", X"66", X"66",
X"66", X"66", X"3E", X"00", X"00", X"00", X"66", X"66", X"66", X"3C",
X"18", X"00", X"00", X"00", X"63", X"6B", X"7F", X"3E", X"36", X"00",
X"00", X"00", X"66", X"3C", X"18", X"3C", X"66", X"00", X"00", X"00",
X"66", X"66", X"66", X"3E", X"0C", X"78", X"00", X"00", X"7E", X"0C",
X"18", X"30", X"7E", X"00", X"0C", X"18", X"18", X"30", X"18", X"18",
X"0C", X"00", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"30", X"18", X"18", X"0C", X"18", X"18", X"30", X"00", X"00", X"70",
X"5A", X"0E", X"00", X"00", X"00", X"00", X"00", X"7E", X"42", X"42",
X"42", X"42", X"7E", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"E0", X"E0", X"E7", X"E7", X"E7",
X"FF", X"FF", X"FF", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"FF",
X"FF", X"FF", X"E7", X"E7", X"E7", X"07", X"07", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"F8", X"F0", X"E3", X"E7", X"E7", X"FF", X"FF",
X"FF", X"00", X"00", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF", X"1F",
X"0F", X"C7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"00", X"00", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E3", X"F0", X"F8", X"FF", X"FF", X"FF", X"E7", X"E7", X"E7", X"00",
X"00", X"FF", X"FF", X"FF", X"E7", X"E7", X"C7", X"0F", X"1F", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7",
X"E7", X"E7", X"FF", X"FF", X"E7", X"FF", X"99", X"99", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"99", X"99", X"00", X"99", X"00", X"99",
X"99", X"FF", X"E7", X"C1", X"9F", X"C3", X"F9", X"83", X"E7", X"FF",
X"9D", X"99", X"F3", X"E7", X"CF", X"99", X"B9", X"FF", X"C3", X"99",
X"C3", X"C7", X"98", X"99", X"C0", X"FF", X"F9", X"F3", X"E7", X"FF",
X"FF", X"FF", X"FF", X"FF", X"F3", X"E7", X"CF", X"CF", X"CF", X"E7",
X"F3", X"FF", X"CF", X"E7", X"F3", X"F3", X"F3", X"E7", X"CF", X"FF",
X"FF", X"99", X"C3", X"00", X"C3", X"99", X"FF", X"FF", X"FF", X"E7",
X"E7", X"81", X"E7", X"E7", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"E7", X"E7", X"CF", X"FF", X"FF", X"FF", X"81", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"FF",
X"FF", X"FC", X"F9", X"F3", X"E7", X"CF", X"9F", X"FF", X"C3", X"99",
X"91", X"89", X"99", X"99", X"C3", X"FF", X"E7", X"E7", X"C7", X"E7",
X"E7", X"E7", X"81", X"FF", X"C3", X"99", X"F9", X"F3", X"CF", X"9F",
X"81", X"FF", X"C3", X"99", X"F9", X"E3", X"F9", X"99", X"C3", X"FF",
X"F9", X"F1", X"E1", X"99", X"80", X"F9", X"F9", X"FF", X"81", X"9F",
X"83", X"F9", X"F9", X"99", X"C3", X"FF", X"C3", X"99", X"9F", X"83",
X"99", X"99", X"C3", X"FF", X"81", X"99", X"F3", X"E7", X"E7", X"E7",
X"E7", X"FF", X"C3", X"99", X"99", X"C3", X"99", X"99", X"C3", X"FF",
X"C3", X"99", X"99", X"C1", X"F9", X"99", X"C3", X"FF", X"FF", X"FF",
X"E7", X"FF", X"FF", X"E7", X"FF", X"FF", X"FF", X"FF", X"E7", X"FF",
X"FF", X"E7", X"E7", X"CF", X"F1", X"E7", X"CF", X"9F", X"CF", X"E7",
X"F1", X"FF", X"FF", X"FF", X"81", X"FF", X"81", X"FF", X"FF", X"FF",
X"8F", X"E7", X"F3", X"F9", X"F3", X"E7", X"8F", X"FF", X"C3", X"99",
X"F9", X"F3", X"E7", X"FF", X"E7", X"FF", X"C3", X"99", X"91", X"91",
X"9F", X"9D", X"C3", X"FF", X"E7", X"C3", X"99", X"81", X"99", X"99",
X"99", X"FF", X"83", X"99", X"99", X"83", X"99", X"99", X"83", X"FF",
X"C3", X"99", X"9F", X"9F", X"9F", X"99", X"C3", X"FF", X"87", X"93",
X"99", X"99", X"99", X"93", X"87", X"FF", X"81", X"9F", X"9F", X"87",
X"9F", X"9F", X"81", X"FF", X"81", X"9F", X"9F", X"87", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"9F", X"91", X"99", X"99", X"C3", X"FF",
X"99", X"99", X"99", X"81", X"99", X"99", X"99", X"FF", X"C3", X"E7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"E1", X"F3", X"F3", X"F3",
X"F3", X"93", X"C7", X"FF", X"99", X"93", X"87", X"8F", X"87", X"93",
X"99", X"FF", X"9F", X"9F", X"9F", X"9F", X"9F", X"9F", X"81", X"FF",
X"9C", X"88", X"80", X"94", X"9C", X"9C", X"9C", X"FF", X"99", X"89",
X"81", X"81", X"91", X"99", X"99", X"FF", X"C3", X"99", X"99", X"99",
X"99", X"99", X"C3", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"99", X"99", X"99", X"C3", X"F1", X"FF",
X"83", X"99", X"99", X"83", X"87", X"93", X"99", X"FF", X"C3", X"99",
X"9F", X"C3", X"F9", X"99", X"C3", X"FF", X"81", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"99", X"99", X"99", X"99", X"99", X"99",
X"C3", X"FF", X"99", X"99", X"99", X"99", X"99", X"C3", X"E7", X"FF",
X"9C", X"9C", X"9C", X"94", X"80", X"88", X"9C", X"FF", X"99", X"99",
X"C3", X"E7", X"C3", X"99", X"99", X"FF", X"99", X"99", X"99", X"C3",
X"E7", X"E7", X"E7", X"FF", X"81", X"F9", X"F3", X"E7", X"CF", X"9F",
X"81", X"FF", X"C3", X"CF", X"CF", X"CF", X"CF", X"CF", X"C3", X"FF",
X"FF", X"9F", X"CF", X"E7", X"F3", X"F9", X"FC", X"FF", X"C3", X"F3",
X"F3", X"F3", X"F3", X"F3", X"C3", X"FF", X"E7", X"C3", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"00", X"E7", X"F3", X"F9", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"C3", X"F9", X"C1", X"99", X"C1", X"FF", X"FF", X"9F",
X"9F", X"83", X"99", X"99", X"83", X"FF", X"FF", X"FF", X"C3", X"9F",
X"9F", X"9F", X"C3", X"FF", X"FF", X"F9", X"F9", X"C1", X"99", X"99",
X"C1", X"FF", X"FF", X"FF", X"C3", X"99", X"81", X"9F", X"C3", X"FF",
X"FF", X"F1", X"E7", X"C1", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"83", X"FF", X"9F", X"9F", X"83",
X"99", X"99", X"99", X"FF", X"FF", X"E7", X"FF", X"C7", X"E7", X"E7",
X"C3", X"FF", X"FF", X"F9", X"FF", X"F9", X"F9", X"F9", X"F9", X"C3",
X"FF", X"9F", X"9F", X"93", X"87", X"93", X"99", X"FF", X"FF", X"C7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"FF", X"FF", X"99", X"80",
X"80", X"94", X"9C", X"FF", X"FF", X"FF", X"83", X"99", X"99", X"99",
X"99", X"FF", X"FF", X"FF", X"C3", X"99", X"99", X"99", X"C3", X"FF",
X"FF", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"F9", X"FF", X"FF", X"83", X"99",
X"9F", X"9F", X"9F", X"FF", X"FF", X"FF", X"C1", X"9F", X"C3", X"F9",
X"83", X"FF", X"FF", X"E7", X"81", X"E7", X"E7", X"E7", X"F1", X"FF",
X"FF", X"FF", X"99", X"99", X"99", X"99", X"C1", X"FF", X"FF", X"FF",
X"99", X"99", X"99", X"C3", X"E7", X"FF", X"FF", X"FF", X"9C", X"94",
X"80", X"C1", X"C9", X"FF", X"FF", X"FF", X"99", X"C3", X"E7", X"C3",
X"99", X"FF", X"FF", X"FF", X"99", X"99", X"99", X"C1", X"F3", X"87",
X"FF", X"FF", X"81", X"F3", X"E7", X"CF", X"81", X"FF", X"F3", X"E7",
X"E7", X"CF", X"E7", X"E7", X"F3", X"FF", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"CF", X"E7", X"E7", X"F3", X"E7", X"E7",
X"CF", X"FF", X"FF", X"8F", X"A5", X"F1", X"FF", X"FF", X"FF", X"FF",
X"FF", X"81", X"BD", X"BD", X"BD", X"BD", X"81", X"FF" );
end;
| gpl-3.0 |
sbourdeauducq/dspunit | rtl/dspalu_acc.vhd | 2 | 13985 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dsputil_pac.all;
-------------------------------------------------------------------------------
entity dspalu_acc is
generic (
sig_width : integer := 16;
acc_width : integer := 32;
acc_reduce_width : integer := 32);
port (
--@inputs
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : in std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
--@outputs
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end dspalu_acc;
--=----------------------------------------------------------------------------
architecture archi_dspalu_acc of dspalu_acc is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_result1 : signed((2*sig_width - 1) downto 0);
signal s_result2 : signed((2*sig_width - 1) downto 0);
signal s_mul_out1 : signed((2*sig_width - 1) downto 0);
signal s_mul_out2 : signed((2*sig_width - 1) downto 0);
signal s_result_acc1 : signed((acc_width - 1) downto 0);
signal s_result_acc2 : signed((acc_width - 1) downto 0);
signal s_back_acc1 : signed((acc_width - 1) downto 0);
signal s_back_acc2 : signed((acc_width - 1) downto 0);
signal s_cmp_reg : signed((acc_width - 1) downto 0);
signal s_cmp_in : signed((acc_width - 1) downto 0);
signal s_cmp_reg_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_cmp_in_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_mul_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2_in : std_logic_vector((sig_width - 1) downto 0);
type t_cmul_state is (cmul_step, cmul_end);
signal s_cmul_state : t_cmul_state;
signal s_cmp_greater : std_logic;
signal s_cmp_greater_inreg : std_logic;
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_cmp_store : std_logic;
begin -- archs_dspalu_acc
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- First accumulator
-------------------------------------------------------------------------------
p_acc1 : process (clk)
variable v_tmp_acc1 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc1 <= (others => '0');
else
v_tmp_acc1 := resize(s_result1, acc_width);
-- Accumulation mode
case s_acc_mode1 is
when acc_store =>
s_result_acc1 <= v_tmp_acc1;
when acc_sumstore =>
s_result_acc1 <= resize(signed(s_result1) + signed(s_result2), acc_width);
when acc_add =>
s_result_acc1 <= s_result_acc1 + v_tmp_acc1;
when acc_sub =>
s_result_acc1 <= s_result_acc1 - v_tmp_acc1;
when acc_back_add =>
s_result_acc1 <= s_back_acc1 + v_tmp_acc1;
when acc_minback_sub =>
s_result_acc1 <= - v_tmp_acc1 - s_back_acc1;
when others =>
s_result_acc1 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc1 <= s_result_acc1;
end if;
end if;
end process p_acc1;
-------------------------------------------------------------------------------
-- Second accumulator
-------------------------------------------------------------------------------
p_acc2 : process (clk)
variable v_tmp_acc2 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc2 <= (others => '0');
else
v_tmp_acc2 := resize(s_result2, acc_width);
-- Accumulation mode
case s_acc_mode2 is
when acc_store =>
s_result_acc2 <= v_tmp_acc2;
when acc_diff =>
-- s_result_acc2 <= resize(signed(a2) + signed(b2), acc_width);
s_result_acc2 <= s_result_acc2 - s_result_acc1;
when acc_abs =>
s_result_acc2 <= s_result_acc2 + dsp_abs(s_result_acc1);
when acc_add =>
s_result_acc2 <= s_result_acc2 + v_tmp_acc2;
when acc_sub =>
s_result_acc2 <= s_result_acc2 - v_tmp_acc2;
when acc_back_add =>
s_result_acc2 <= s_back_acc2 + v_tmp_acc2;
when acc_minback_sub =>
s_result_acc2 <= - v_tmp_acc2 - s_back_acc2;
when others =>
s_result_acc2 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc2 <= s_result_acc2;
end if;
end if;
end process p_acc2;
-------------------------------------------------------------------------------
-- Comparator
-------------------------------------------------------------------------------
-- p_cmp_in : process (cmp_mode, s_result_acc1, s_result_acc2, s_cmp_reg, s_cmp_in)
p_cmp_in : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then
case cmp_mode is
when cmp_acc1 =>
if(s_result_acc1(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc1;
else
s_cmp_in <= not s_result_acc1;
end if;
when cmp_acc2 =>
if(s_result_acc2(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc2;
else
s_cmp_in <= not s_result_acc2;
end if;
when others =>
s_cmp_in <= (others => '0');
end case;
s_cmp_greater <= s_cmp_greater_inreg;
end if;
end process p_cmp_in;
s_cmp_reg_r <= unsigned(s_cmp_reg((acc_width - 2) downto (acc_width - acc_reduce_width))) ;
s_cmp_in_r <= unsigned(s_cmp_in((acc_width - 2) downto (acc_width - acc_reduce_width)));
s_cmp_greater_inreg <= '1' when s_cmp_reg_r < s_cmp_in_r else '0';
-- s_cmp_greater_inreg <= '1' when s_cmp_reg < s_cmp_in else '0';
p_cmp : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then -- rising clock edge
s_cmp_store <= cmp_store;
-- if(((s_cmp_greater_inreg xor cmp_pol) or s_cmp_store) = '1') then
if(s_cmp_store = '1') then
s_cmp_reg <= s_cmp_in;
elsif(s_cmp_greater_inreg = '1') then
s_cmp_reg <= s_cmp_in;
else
s_cmp_reg <= s_cmp_reg;
end if;
end if;
end process p_cmp;
-------------------------------------------------------------------------------
-- Operation controller (manage the complex multiplication)
-------------------------------------------------------------------------------
p_alu_ctrl : process (clk)
begin -- process p_alu_ctrl
if rising_edge(clk) then -- rising clock edge
if (alu_select = alu_mul or alu_select = alu_none) then
s_cmul_state <= cmul_end;
elsif (s_cmul_state = cmul_step) then
s_cmul_state <= cmul_end;
else
s_cmul_state <= cmul_step;
end if;
end if;
end process p_alu_ctrl;
p_mul_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_result1 <= s_mul_out1;
s_result2 <= s_mul_out2;
s_acc_mode1 <= s_acc_mode1_n1;
s_acc_mode2 <= s_acc_mode2_n1;
s_acc_mode1_n1 <= s_acc_mode1_inreg;
s_acc_mode2_n1 <= s_acc_mode2_inreg;
end if;
end process p_mul_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
result1 <= std_logic_vector(s_result1((2*sig_width - 2) downto (sig_width - 1)));
result2 <= std_logic_vector(s_result2((2*sig_width - 2) downto (sig_width - 1)));
s_mul_out1 <= signed(s_mul_a1) * signed(s_mul_b1);
s_mul_out2 <= signed(s_mul_a2) * signed(s_mul_b2);
result_acc1 <= std_logic_vector(s_result_acc1);
result_acc2 <= std_logic_vector(s_result_acc2);
-- accumulation mode is given by acc_modex except during complex multiplication (modified for step 2)
s_cmul_acc_mode1 <= acc_add when acc_mode1 = acc_sub else acc_sub;
s_cmul_acc_mode2 <= acc_sub when acc_mode1 = acc_sub else acc_add;
-- TODO move the mux to s_acc_modeX_n1!!!!
s_acc_mode1_inreg <= s_cmul_acc_mode1 when s_cmul_state = cmul_step else acc_mode1;
s_acc_mode2_inreg <= s_cmul_acc_mode2 when s_cmul_state = cmul_step else acc_mode2;
-- multipliers inputs (special selection during complex multiplication)
p_mul_in_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_mul_a1 <= s_mul_a1_in;
s_mul_a2 <= s_mul_a2_in;
s_mul_b1 <= s_mul_b1_in;
s_mul_b2 <= s_mul_b2_in;
end if;
end process p_mul_in_reg;
s_mul_a1_in <= a2 when s_cmul_state = cmul_step else a1;
s_mul_a2_in <= a1 when s_cmul_state = cmul_step else a2;
s_mul_b1_in <= s_b2 when s_cmul_state = cmul_step else b1;
-- ! can be more time critical than other entries because depends on alu_select
s_mul_b2_in <= b1 when (s_cmul_state = cmul_end and (alu_select = alu_cmul or alu_select = alu_cmul_conj)) else s_b2;
-- ------------------------------------------------------------------------------------------------------------------------
s_b2 <= std_logic_vector(-signed(b2)) when alu_select = alu_cmul_conj else b2;
cmp_reg <= std_logic_vector(s_cmp_reg);
cmp_greater <= s_cmp_greater;
end archi_dspalu_acc;
-------------------------------------------------------------------------------
| gpl-3.0 |
adelapie/xtea | tb_xtea.vhd | 1 | 3023 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_xtea IS
END tb_xtea;
ARCHITECTURE behavior OF tb_xtea IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xtea
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : in std_logic;
block_in : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal v_0_out : std_logic_vector(31 downto 0);
signal v_1_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xtea PORT MAP (
clk => clk,
rst => rst,
enc => enc,
block_in => block_in,
key => key,
v_0_out => v_0_out,
v_1_out => v_1_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
enc <= '0';
rst <= '1';
block_in <= X"bbbbbbbb" & X"aaaaaaaa" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
wait for clk_period;
rst <= '0';
wait for 4*64*clk_period;
assert v_0_out = X"3a53039a"
report "ENCRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
assert v_1_out = X"fe2d9913"
report "ENCRYPT ERROR (v_1)" severity FAILURE;
wait for clk_period*10;
enc <= '1';
rst <= '1';
block_in <= X"fe2d9913" & X"3a53039a" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
wait for clk_period;
rst <= '0';
wait for 4*64*clk_period;
assert v_0_out = X"bbbbbbbb"
report "DECRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
assert v_1_out = X"aaaaaaaa"
report "DECRYPT ERROR (v_1)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 |
sbourdeauducq/dspunit | rtl/dsp_cmdregs.vhd | 2 | 10901 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdregs is
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end dsp_cmdregs;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdregs of dsp_cmdregs is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dsp_cmdpipe
port (
reset : in std_logic;
clk : in std_logic;
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_cmdregs : t_dsp_cmdregs;
signal s_dsp_cmdregs_buf : t_dsp_cmdregs;
signal s_dsp_cmdpipe_out : t_dsp_cmdregs;
signal s_dsp_bus : t_dsp_bus;
signal s_dsp_bus_conv_circ : t_dsp_bus;
signal s_op_conv_circ_en : std_logic;
signal s_opflag_select_inreg : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select_inreg : std_logic_vector((opcode_width - 1) downto 0);
signal s_op_run_resync : std_logic;
signal s_op_run_sync : std_logic;
signal s_op_done_sync : std_logic;
signal s_op_done_resync : std_logic;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_load_pipe : std_logic;
signal s_status_reg : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_read : std_logic;
signal s_empty : std_logic;
signal s_write : std_logic;
signal s_full : std_logic;
signal s_run_flag : std_logic;
signal s_pipe_loaded : std_logic;
signal s_op_run : std_logic;
signal s_op_done_irq : std_logic;
signal s_empty_irq : std_logic;
signal s_current_sr : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_empty_reg : std_logic;
signal s_op_done_reg : std_logic;
signal s_empty_ie : std_logic;
signal s_op_done_ie : std_logic;
begin -- archs_dsp_cmdregs
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dsp_cmdpipe_1 : dsp_cmdpipe
port map (
reset => reset,
clk => clk_cpu,
cmd_out => s_dsp_cmdpipe_out,
read => s_read,
empty => s_empty,
cmd_in => s_dsp_cmdregs_buf,
write => s_write,
full => s_full);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Register bank accessible from controler
-------------------------------------------------------------------------------
p_cmdreg_buf : process (clk_cpu, reset)
begin -- process p_cmdreg_buf
if reset = '0' then
s_dsp_cmdregs_buf <= dsp_cmdregs_init;
elsif rising_edge(clk_cpu) then -- rising clock edge
if(wr_en_cmdreg = '1') then
s_dsp_cmdregs_buf(conv_integer(addr_cmdreg)) <= data_in_cmdreg;
else
s_dsp_cmdregs_buf(DSPADDR_SR) <= s_status_reg;
end if;
data_out_cmdreg <= s_dsp_cmdregs_buf(conv_integer(addr_cmdreg));
end if;
end process p_cmdreg_buf;
-------------------------------------------------------------------------------
-- Bits of status register (readable from cpu)
-------------------------------------------------------------------------------
s_status_reg(DSP_SRBIT_LOADED) <= s_full;
s_status_reg(DSP_SRBIT_DONE) <= s_op_done_resync;
s_status_reg(DSP_SRBIT_RUN) <= s_run_flag and (not s_load_pipe);
s_run_flag <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_RUN);
s_status_reg(DSP_SRBIT_DONE_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IE);
s_status_reg(DSP_SRBIT_EMPTY_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IE);
s_status_reg(DSP_SRBIT_DONE_IF) <= s_op_done_irq;
s_status_reg(DSP_SRBIT_EMPTY_IF) <= s_empty_irq;
s_status_reg(cmdreg_width - 1 downto DSP_SRBIT_UNUSED) <= (others => '0');
s_op_done_irq <= '1' when op_done = '1' and s_op_done_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IF);
s_empty_irq <= '1' when s_empty = '1' and s_empty_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IF);
s_empty_ie <= s_status_reg(DSP_SRBIT_EMPTY_IE);
s_op_done_ie <= s_current_sr(DSP_SRBIT_DONE_IE);
irq <= (s_empty and s_empty_ie) or (op_done and s_op_done_ie);
p_irq : process (clk_cpu)
begin -- process p_irq
if rising_edge(clk_cpu) then -- rising clock edge
s_op_done_reg <= op_done;
s_empty_reg <= s_empty;
end if;
end process p_irq;
-------------------------------------------------------------------------------
-- Control injection of datas in pipe
-------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_cpu)
begin -- process p_cmdreg_buf
if rising_edge(clk_cpu) then -- rising clock edge
if s_load_pipe = '1' then
s_write <= '1';
s_pipe_loaded <= '1';
elsif s_run_flag = '0' then
s_pipe_loaded <= '0';
s_write <= '0';
else
s_write <= '0';
end if;
end if;
end process p_ctrl_pipe;
s_load_pipe <= s_run_flag and (not s_pipe_loaded) and (not s_full);
-------------------------------------------------------------------------------
-- Control the pipe output
-------------------------------------------------------------------------------
p_pipe_out : process (clk_cpu, reset)
begin -- process p_pipe_out
if reset = '0' then
s_op_run <= '0';
elsif rising_edge(clk_cpu) then -- rising clock edge
if s_op_done_resync = '1' then
s_op_run <= '0';
s_read <= '0';
elsif s_op_run = '0' and s_empty = '0' then
s_read <= '1';
s_op_run <= '1';
s_dsp_cmdregs <= s_dsp_cmdpipe_out;
else
s_read <= '0';
end if;
s_op_done_sync <= op_done;
s_op_done_resync <= s_op_done_sync;
end if;
end process p_pipe_out;
-------------------------------------------------------------------------------
-- Synchronization of command signals to the dspunit clock
-------------------------------------------------------------------------------
p_synccmd : process (clk)
begin -- process p_synccmd
if rising_edge(clk) then -- rising clock edge
s_op_run_sync <= s_op_run;
s_op_run_resync <= s_op_run_sync;
-- cmdregs can be considered as stable when s_op_run_resync='1'
if s_op_run_resync = '1' then
s_opcode_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opcode_width - 1) downto 0);
s_opflag_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opflag_width + opcode_width - 1) downto (opcode_width));
else
s_opcode_select_inreg <= (others => '0');
s_opflag_select_inreg <= (others => '0');
end if;
opcode_select <= s_opcode_select_inreg;
opflag_select <= s_opflag_select_inreg;
offset_0 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR0));
offset_1 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR1));
offset_2 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR2));
length0 <= s_dsp_cmdregs(DSPADDR_LENGTH0);
length1 <= s_dsp_cmdregs(DSPADDR_LENGTH1);
length2 <= s_dsp_cmdregs(DSPADDR_LENGTH2);
end if;
end process p_synccmd;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
debug <= s_dsp_cmdregs(DSPADDR_SR);
s_current_sr <= s_dsp_cmdregs(DSPADDR_SR);
end archi_dsp_cmdregs;
-------------------------------------------------------------------------------
| gpl-3.0 |
sbourdeauducq/dspunit | sim/gen_memoryf.vhd | 2 | 6490 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2006-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL ;
-------------------------------------------------------------------------------
entity gen_memoryf is
generic (
addr_width : natural := 11;
data_width : natural := 8;
init_file : STRING
);
port (
--@inputs
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
--@outputs;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end gen_memoryf;
--=----------------------------------------------------------------------------
architecture archi_gen_memoryf of gen_memoryf is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type memType is array((2**addr_width - 1) downto 0) of std_logic_vector((data_width - 1) downto 0);
-- Fonction d'initialisation du programme
function initialize_ram
return memType is
variable result : memType;
file data : TEXT IS init_file;
variable lineStr, msg : line;
variable i : natural := 0;
variable rom_buf : std_logic_vector((data_width - 1) downto 0);
variable ok : boolean;
begin
for i in 0 to (2**addr_width - 1) loop
if not endfile(data) then
readline(data, lineStr);
hread(lineStr, rom_buf, ok);
if ok then
result(i) := rom_buf;
-- result(i)((data_width - 2) downto 0) := rom_buf((data_width - 1) downto 1);
-- result(i)(data_width - 1) := rom_buf(data_width - 1);
else
write(msg, String'(" !!! FORMAT !!! : "));
-- write(msg, String'(line.all));
write(msg, String'(" @ line : "));
write(msg, i);
report msg.all;
end if;
else
result(i) := (others => '0');
end if;
end loop;
return result;
end initialize_ram;
signal s_ram_block : memType := initialize_ram;
signal s_address_a : std_logic_vector((addr_width - 1) downto 0);
signal s_address_b : std_logic_vector((addr_width - 1) downto 0);
signal s_w_clk : std_logic;
begin -- archs_gen_memoryf
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
ramProc_a : process (clock_a)
begin -- process ramProc
if rising_edge(clock_a) then -- rising clock edge
s_address_a <= address_a;
q_a <= s_ram_block(to_integer(unsigned(s_address_a)));
end if;
end process ramProc_a;
ramProc_b : process (clock_b)
begin -- process ramProc
if rising_edge(clock_b) then -- rising clock edge
s_address_b <= address_b;
q_b <= s_ram_block(to_integer(unsigned(s_address_b)));
end if;
end process ramProc_b;
-- -- Read initial content of the ram from file
-- file_read : process
-- file data : TEXT IS init_file;
-- variable lineStr, msg : line;
-- variable i : natural := 0;
-- variable rom_buf : std_logic_vector((data_width - 1) downto 0);
-- variable ok : boolean;
-- begin -- process file_read
-- while not endfile(data) loop
-- readline(data, lineStr);
-- hread(lineStr, rom_buf, ok);
-- if ok then
-- s_ram_block(i) <= rom_buf; -- no conversion
-- else
-- write(msg, String'(" !!! FORMAT !!! : "));
---- write(msg, String'(line.all));
-- write(msg, String'(" @ line : "));
-- write(msg, i);
-- report msg.all;
-- end if;
--
-- if i < (2**addr_width - 1) then
-- i := i + 1;
-- else
-- report "ram full";
-- exit;
-- end if;
-- end loop;
-- wait;
-- end process file_read;
--
ramWrite : process (clock_a)
begin -- process ramWrite
-- if rising_edge(s_w_clk) then -- rising clock edge
if falling_edge(clock_a) then -- rising clock edge
if wren_a = '1' then
s_ram_block(to_integer(unsigned(address_a))) <= data_a;
elsif wren_b = '1' then
s_ram_block(to_integer(unsigned(address_b))) <= data_b;
end if;
end if;
end process ramWrite;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_w_clk <= (clock_a and wren_a) or (clock_b and wren_b);
end archi_gen_memoryf;
-------------------------------------------------------------------------------
| gpl-3.0 |
sbourdeauducq/dspunit | rtl/bit_manipulation.vhdl | 2 | 12347 | -- bit_manipulation.vhdl - miscellaneous bit manipulation functions
-- Copyright (C) 2001, 2002 Michael Riepe <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id: bit_manipulation.vhdl,v 1.10 2002/07/05 21:36:57 michael Exp $
-- url : http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/common/bit_manipulation.vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package Bit_Manipulation is
-- reverse bits in a vector
function bit_reverse (A : in signed) return signed;
function bit_reverse (A : in unsigned) return unsigned;
function bit_reverse (A : in std_logic_vector) return std_logic_vector;
-- extract 1 bit of N, starting at offset O
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector;
-- duplicate all bits in a vector
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- duplicate vector
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- AND cascade
function cascade_and (A : in std_logic_vector) return std_logic_vector;
-- OR cascade
function cascade_or (A : in std_logic_vector) return std_logic_vector;
-- n:1 AND
function reduce_and (A : in std_logic_vector) return std_logic;
-- n:1 XOR
function reduce_xor (A : in std_logic_vector) return std_logic;
-- n:1 OR
function reduce_or (A : in std_logic_vector) return std_logic;
-- left shift w/ carry-in
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- left shift w/o carry-in
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic left shift
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right shift w/ carry-in
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- right shift w/o carry-in
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic right shift
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- left rotate
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right rotate
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned;
-- function bitbit_and(A : in signed; B : in signed) return signed;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector;
end Bit_Manipulation;
package body Bit_Manipulation is
function bit_reverse (A : in signed) return signed is
begin
return signed(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in unsigned) return unsigned is
begin
return unsigned(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, yy : std_logic_vector(L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in aa'range loop
yy(i) := aa(L - 1 - i);
end loop;
return yy;
end bit_reverse;
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector is
constant L : natural := A'length;
constant L2 : natural := (L - O + N - 1) / N;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L2-1 downto 0);
begin
--pragma synthesis_off
assert L > O;
--pragma synthesis_on
for i in L2-1 downto 0 loop
yy(i) := aa(N*i+O);
end loop;
return yy;
end bit_extract;
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i/N);
end loop;
return yy;
end bit_duplicate;
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i rem L);
end loop;
return yy;
end vector_duplicate;
function cascade_and (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) and aa(k1) and aa(k2) and aa(k3);
when 2 =>
bb(j) := aa(j) and aa(k1) and aa(k2);
when 1 =>
bb(j) := aa(j) and aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_and;
function cascade_or (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) or aa(k1) or aa(k2) or aa(k3);
when 2 =>
bb(j) := aa(j) or aa(k1) or aa(k2);
when 1 =>
bb(j) := aa(j) or aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_or;
function reduce_and (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) and aa(4*i+1) and aa(4*i+2) and aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) and aa(4*k+1) and aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) and aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_and;
function reduce_xor (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 31 loop -- should be enough
exit when len = 1;
k := len / 2;
for i in 0 to k-1 loop
aa(i) := aa(2*i+0) xor aa(2*i+1);
end loop;
case len mod 2 is
when 1 => aa(k) := aa(2*k+0);
when others => null;
end case;
len := (len + 1) / 2;
end loop;
return aa(0);
end reduce_xor;
function reduce_or (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) or aa(4*i+1) or aa(4*i+2) or aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) or aa(4*k+1) or aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) or aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_or;
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-1 downto N) := aa(L-N-1 downto 0);
end if;
return yy;
end lshift;
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, '0');
end lshift;
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, A(A'right));
end lshifta;
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-N-1 downto 0) := aa(L-1 downto N);
end if;
return yy;
end rshift;
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, '0');
end rshift;
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, A(A'left));
end rshifta;
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + L - N) rem L);
end loop;
return yy;
end lrotate;
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + N) rem L);
end loop;
return yy;
end rrotate;
-- function bitbit_and(A : in signed; B : in signed) return signed is
-- begin
-- return signed(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned is
-- begin
-- return unsigned(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and bb(i);
end loop;
return yy;
end bitbit_and;
function bitbit_or(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) or bb(i);
end loop;
return yy;
end bitbit_or;
end Bit_Manipulation;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please
| gpl-3.0 |
sbourdeauducq/dspunit | sim/clock_gen.vhd | 2 | 3063 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: clock_gen.vhdl,v $ $Revision: 2.1 $ Date: 1993/10/31 20:20:50 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for clock generator
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_gen is
generic (
Tpw : Time;
Tps : Time);
port (
--@inputs
--@outputs;
clk : out std_logic;
reset : out std_logic
);
end clock_gen;
--=----------------------------------------------------------------------------
architecture archi_clock_gen of clock_gen is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant clock_period : Time := 2*(Tpw+Tps);
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
begin -- archs_clock_gen
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_gen_clk : process
begin -- process p_gen_clk
clk <= '1', '0' after Tpw;
wait for clock_period;
end process p_gen_clk;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
reset_driver:
reset <= '0', '1' after 10*clock_period + Tpw+Tps;
end archi_clock_gen;
-------------------------------------------------------------------------------
| gpl-3.0 |
sbourdeauducq/dspunit | sim/bench_dotdiv.vhd | 2 | 12301 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dotdiv is
end bench_dotdiv;
--=----------------------------------------------------------------------------
architecture archi_bench_dotdiv of bench_dotdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dotdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "divden.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "divnum.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000110" after 131 ns, "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
--s_data_in_cmdreg <= x"0000", x"004F" after 141 ns, x"0040" after 151 ns, x"02D7" after 161 ns, x"0002" after 171 ns, -- dotdiv, muladd m0,1>m0
s_data_in_cmdreg <= x"0000", x"0003" after 131 ns, x"004F" after 141 ns, x"0040" after 151 ns, x"08C8" after 161 ns, x"0002" after 171 ns, -- dotdiv,m1 / m0 => m2.
-- num shift : 3
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 131 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_dotdiv;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=dotdiv.sav
-------------------------------------------------------------------------------
| gpl-3.0 |
adelapie/xtea | xtea.vhd | 1 | 3162 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity xtea is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
block_in : in std_logic_vector(63 downto 0);
key : in std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0));
end xtea;
architecture Behavioral of xtea is
signal delta_s : unsigned(31 downto 0);
component round_f is
port(v_in : in std_logic_vector(31 downto 0);
last_val : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(31 downto 0));
end component;
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0, enc) (1, dec)
val : in std_logic_vector(1 downto 0);
key : in std_logic_vector(127 downto 0);
subkey : out std_logic_vector(31 downto 0));
end component;
signal subkey_s : std_logic_vector(31 downto 0);
signal cnt_s : unsigned(1 downto 0);
signal v_0_s, v_1_s : unsigned(31 downto 0);
signal output_s : std_logic_vector(31 downto 0);
signal input_a_s : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, enc, std_logic_vector(cnt_s), key, subkey_s);
pr_cnt : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
cnt_s <= (others => '0');
else
cnt_s <= cnt_s + 1;
end if;
end if;
end process;
ROUND_F_0 : round_f port map (input_a_s, subkey_s, output_s);
pr_macc : process(clk, rst, enc, block_in, output_s, cnt_s)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
v_1_s <= unsigned(block_in(63 downto 32));
v_0_s <= unsigned(block_in(31 downto 0));
else
v_0_s <= unsigned(block_in(63 downto 32));
v_1_s <= unsigned(block_in(31 downto 0));
end if;
else
if cnt_s = "00" then -- v_0
input_a_s <= std_logic_vector(v_1_s);
elsif cnt_s = "01" then -- v_0
if enc = '0' then
v_0_s <= v_0_s + unsigned(output_s);
else
v_0_s <= v_0_s - unsigned(output_s);
end if;
elsif cnt_s = "10" then -- v_1
input_a_s <= std_logic_vector(v_0_s);
else -- v_1
if enc = '0' then
v_1_s <= v_1_s + unsigned(output_s);
else
v_1_s <= v_1_s - unsigned(output_s);
end if;
end if;
end if;
end if;
end process;
v_0_out <= std_logic_vector(v_0_s);
v_1_out <= std_logic_vector(v_1_s);
end Behavioral;
| gpl-3.0 |
JL-Grande/Ascensor_SED | ASCENSOR/tb_motor_puerta.vhd | 1 | 2072 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_motor_puerta IS
END tb_motor_puerta;
ARCHITECTURE behavior OF tb_motor_puerta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT motor_puerta
PORT(
CLK : IN std_logic;
RST : IN std_logic;
nivel : IN std_logic;
celula : IN std_logic;
accionar_puerta : IN std_logic;
actuador_puerta : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal nivel : std_logic := '0';
signal celula : std_logic := '0';
signal accionar_puerta : std_logic := '0';
--Outputs
signal actuador_puerta : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: motor_puerta PORT MAP (
CLK => CLK,
RST => RST,
nivel => nivel,
celula => celula,
accionar_puerta => accionar_puerta,
actuador_puerta => actuador_puerta
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
celula <= '0';
WAIT FOR 3 ns;
accionar_puerta <= '0';
WAIT FOR 20 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 5 ns;
RST <= '0';
WAIT FOR 5 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 20 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 10 ns;
nivel <= '1';
WAIT FOR 10 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 5 ns;
nivel <= '0';
WAIT FOR 15 ns;
ASSERT false
REPORT "Simulacion finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
| gpl-3.0 |
scottlbaker/Nova-SOC | src/addr.vhd | 1 | 1943 |
--========================================================================
-- addr.vhd :: Nova 16-bit address adder
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity ADDR is
port (
SX : out std_logic_vector(15 downto 0); -- result bus
BX : in std_logic_vector(15 downto 0); -- operand bus
DISP : in std_logic_vector( 7 downto 0); -- displacement
OP : in SX_OP_TYPE -- micro op
);
end ADDR;
architecture BEHAVIORAL of ADDR is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
-- internal busses
signal AX : std_logic_vector(15 downto 0);
signal DSE : std_logic_vector( 6 downto 0);
begin
--================================================================
-- Start of the behavioral description
--================================================================
--====================
-- Opcode Decoding
--====================
OPCODE_DECODING:
process(OP, DSE, DISP)
begin
case OP is
when REL => -- relative address
AX <= DSE & DISP & '0';
when DEC1 => -- decrement by 1
AX <= "1111111111111110";
when INC2 => -- increment by 2
AX <= "0000000000000100";
when others => -- increment by 1
AX <= "0000000000000010";
end case;
end process;
DSE <= (others => DISP(7));
SX <= AX + BX;
end BEHAVIORAL;
| gpl-3.0 |
pollow/Multi_Cycle_CPU | ipcore_dir/Mem_B/simulation/addr_gen.vhd | 30 | 4526 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
JL-Grande/Ascensor_SED | ASCENSOR/tb_antirrebote.vhd | 1 | 1555 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_antirrebote IS
END tb_antirrebote;
ARCHITECTURE behavior OF tb_antirrebote IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT antirrebote
PORT(
CLK : IN std_logic;
RST : IN std_logic;
logic_IN : IN std_logic;
logic_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal logic_IN : std_logic := '0';
--Outputs
signal logic_OUT : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: antirrebote PORT MAP (
CLK => CLK,
RST => RST,
logic_IN => logic_IN,
logic_OUT => logic_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
logic_IN <= '0';
WAIT FOR 40 ns;
logic_IN <= '1';
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 10 ns;
logic_IN <= '0';
WAIT FOR 2 ns;
logic_IN <= '1';
WAIT FOR 3 ns;
RST <= '0';
WAIT FOR 47 ns;
logic_IN <= '0';
WAIT FOR 4 ns;
logic_IN <= '1';
WAIT FOR 2 ns;
logic_IN <= '0';
WAIT FOR 3 ns;
logic_IN <= '1';
WAIT FOR 20 ns;
logic_IN <= '0';
WAIT FOR 50 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
| gpl-3.0 |
scottlbaker/Nova-SOC | src/soc.vhd | 1 | 18101 |
--========================================================================
-- soc.vhd :: Nova SOC for Latice experiments
--
-- contains:
--
-- (1) Nova core
-- (1) UART
-- (1) timer
-- (1) random number generator
-- (1) Digital I/O
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity SOC is
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- Reset and Clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end SOC;
architecture BEHAVIORAL of SOC is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
signal ADDR_15 : std_logic_vector(15 downto 1); -- for debug only
signal ADDR_OUT : std_logic_vector(15 downto 0);
signal DATA_IX : std_logic_vector(15 downto 0);
signal DATA_OX : std_logic_vector(15 downto 0);
signal DEVCODE : std_logic_vector( 5 downto 0);
signal IMSK_REG : std_logic_vector( 7 downto 0);
signal ISRC : std_logic_vector( 7 downto 0);
signal PHASE : std_logic_vector( 3 downto 0);
signal IO_RESET : std_logic; -- I/O reset (active high)
signal RESET1 : std_logic; -- short reset (active low)
signal RESET : std_logic; -- long reset (active low)
signal RW : std_logic; -- Mem 1==read 0==write
signal IORW : std_logic; -- I/O 1==read 0==write
signal IOM : std_logic; -- 1==I/O 0==memory
signal PWR_GOOD : std_logic; -- Power good
signal RDY : std_logic; -- Ready/Wait
signal BYTEOP : std_logic; -- byte operation
signal SYNC : std_logic; -- Opcode fetch status
signal FEN : std_logic; -- clock enable
signal BOOT_RE : std_logic; -- Boot RAM read enable
signal BOOT_WE : std_logic; -- Boot RAM write enable
signal IO_WE : std_logic; -- IO write enable
signal TIMR_IRQ : std_logic; -- Timer interrupt
signal UART_RRQ : std_logic; -- UART receive interrupt
signal UART_TRQ : std_logic; -- UART transmit interrupt
signal UART_RD : std_logic; -- UART read data valid
signal IRQ : std_logic; -- Interrupt (active-low)
signal TIMR_DATA : std_logic_vector(15 downto 0);
signal BOOT_DATA : std_logic_vector(15 downto 0);
signal UART_DATA : std_logic_vector( 7 downto 0);
signal PRTA_DATA : std_logic_vector( 7 downto 0);
signal RAND_DATA : std_logic_vector( 7 downto 0);
signal UART_CS : std_logic;
signal TIMR_CS : std_logic;
signal PRTA_CS : std_logic;
signal IMSK_CS : std_logic;
signal RAND_CS : std_logic;
signal DBUG1 : std_logic; -- for debug
signal DBUG2 : std_logic; -- for debug
signal DBUG3 : std_logic; -- for debug
signal DBUG4 : std_logic; -- for debug
signal DBUG5 : std_logic; -- for debug
signal DBUG6 : std_logic; -- for debug
signal DBUG7 : std_logic; -- for debug
--================================================================
-- Constant definition section
--================================================================
-- $0000 -> $3FFF Boot RAM (8kx16)
constant BOOT_SEL : std_logic_vector(15 downto 14) := "00";
-- $10 -> $17 UART registers
constant UART_SEL : std_logic_vector(5 downto 3) := "001";
-- $20 -> $21 Timer registers
constant TIMR_SEL : std_logic_vector(5 downto 1) := "01000";
-- $22 Output Register
constant PRTA_SEL : std_logic_vector(5 downto 0) := "010010";
-- $23 Interrupt mask register
constant IMSK_SEL : std_logic_vector(5 downto 0) := "010011";
-- $24 -> $25 Random number generator
constant RAND_SEL : std_logic_vector(5 downto 1) := "01010";
-- $26 Interrupt source register
constant ISRC_SEL : std_logic_vector(5 downto 0) := "010110";
--================================================================
-- Component definition section
--================================================================
--==================================
-- Nova
--==================================
component IP_NOVA
port (
ADDR_15 : out std_logic_vector(15 downto 1); -- for debug only
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DEVCODE : out std_logic_vector( 5 downto 0);
R_W : out std_logic; -- Mem 1==read 0==write
IORW : out std_logic; -- I/O 1==read 0==write
BYTE : out std_logic; -- Byte memory operation
IOM : out std_logic; -- 1==I/O 0==memory
SYNC : out std_logic; -- Opcode fetch status
IRQ : in std_logic; -- Interrupt Request (active-low)
PWR_GOOD : in std_logic; -- Power good
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- System Clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end component;
--===============================
-- UART (no handshake lines)
--===============================
component UART
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic_vector( 1 downto 0); -- register select
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector( 7 downto 0); -- read data
RX_IRQ : out std_logic; -- RX interrupt req
TX_IRQ : out std_logic; -- TX interrupt req
RXD : in std_logic; -- received data
TXD : out std_logic; -- transmit data
RESET : in std_logic; -- system reset
RDV : in std_logic; -- read data valid
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Timer
--==============================
component TIMER
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- DMA Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Random Number Generator
--==============================
component RAND8
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic; -- register select
WR_DATA : in std_logic_vector(7 downto 0); -- write data
RD_DATA : out std_logic_vector(7 downto 0); -- read data
RESET : in std_logic; -- system reset
FEN : in std_logic; -- clock enable
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Output Port
--==============================
component OUTPORT
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--=========================================
-- Boot RAM (8kx16)
--=========================================
component RAM
port (
RADDR : in std_logic_vector(12 downto 0);
WADDR : in std_logic_vector(12 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
BYTEOP : in std_logic; -- byte operation
REN : in std_logic; -- read enable
WEN : in std_logic; -- write enable
WCLK : in std_logic;
RCLK : in std_logic
);
end component;
--=========================================
-- Debounce and Sync Reset
--=========================================
component XRESET
port (
RST_OUT1 : out std_logic;
RST_OUT2 : out std_logic;
RST_IN : in std_logic;
CLK : in std_logic
);
end component;
begin
--=============================================
-- Clock Phase Divider (divide by 4)
-- S0=000 S1=001 S2=010 S3=100
--=============================================
CLOCK_PHASE_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- count
PHASE <= PHASE(2 downto 0) & PHASE(3);
-- reset state
if (RESET1 = '0') then
PHASE <= "0001";
end if;
end if;
end process;
--==========================================================
-- System Clock Enable
--==========================================================
SYSTEM_CLOCK_ENABLE:
process(FCLK)
begin
if (FCLK = '1' and FCLK'event) then
FEN <= PHASE(3);
end if;
end process;
--==========================================================
-- Address Decoder
--==========================================================
ADDRESS_DECODER:
process(ADDR_OUT, UART_DATA, TIMR_DATA, PRTA_DATA, ISRC,
IMSK_REG, RAND_DATA, BOOT_DATA, PHASE, RW, IORW,
IOM, DEVCODE)
begin
UART_CS <= '0';
TIMR_CS <= '0';
PRTA_CS <= '0';
IMSK_CS <= '0';
RAND_CS <= '0';
BOOT_RE <= '0';
BOOT_WE <= '0';
IO_WE <= '0';
UART_RD <= '0';
DATA_IX <= BOOT_DATA;
-- Boot RAM
if (ADDR_OUT(15 downto 14) = BOOT_SEL) then
BOOT_RE <= PHASE(0) and RW;
BOOT_WE <= PHASE(3) and not RW;
end if;
-- UART registers
if ((IOM = '1') and (DEVCODE(5 downto 3) = UART_SEL)) then
UART_CS <= '1';
DATA_IX <= "00000000" & UART_DATA;
UART_RD <= PHASE(3) and IORW;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Timer registers
if ((IOM = '1') and (DEVCODE(5 downto 1) = TIMR_SEL)) then
TIMR_CS <= '1';
DATA_IX <= TIMR_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
-- output Port
if ((IOM = '1') and (DEVCODE(5 downto 0) = PRTA_SEL)) then
PRTA_CS <= '1';
DATA_IX <= "00000000" & PRTA_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Interrupt Mask register
if ((IOM = '1') and (DEVCODE(5 downto 0) = IMSK_SEL)) then
IMSK_CS <= '1';
DATA_IX <= "00000000" & IMSK_REG;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Interrupt Source register
if ((IOM = '1') and (DEVCODE(5 downto 0) = ISRC_SEL)) then
DATA_IX <= "00000000" & ISRC;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Random Number registers
if ((IOM = '1') and (DEVCODE(5 downto 1) = RAND_SEL)) then
RAND_CS <= '1';
DATA_IX <= "00000000" & RAND_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
end process;
RDY <= '1'; -- Ready
IO_RESET <= not RESET;
PORTA <= PRTA_DATA;
PWR_GOOD <= '1';
--================================================
-- Interrupt mask register
--================================================
INTERRUPT_MASK_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((IMSK_CS = '1') and (IO_WE = '1')) then
IMSK_REG <= DATA_OX(7 downto 0);
end if;
-- reset state
if (RESET = '0') then
IMSK_REG <= (others => '0');
end if;
end if;
end process;
--================================================
-- Interrupt Source
--================================================
ISRC <= "00000" & UART_TRQ & UART_RRQ & TIMR_IRQ;
IRQ <= not ((IMSK_REG(7) and ISRC(7)) or
(IMSK_REG(6) and ISRC(6)) or
(IMSK_REG(5) and ISRC(5)) or
(IMSK_REG(4) and ISRC(4)) or
(IMSK_REG(3) and ISRC(3)) or
(IMSK_REG(2) and ISRC(2)) or
(IMSK_REG(1) and ISRC(1)) or
(IMSK_REG(0) and ISRC(0)));
--=========================================
-- Instantiate the nova
--=========================================
UPROC:
IP_NOVA port map (
ADDR_15 => ADDR_15,
ADDR_OUT => ADDR_OUT,
DATA_IN => DATA_IX,
DATA_OUT => DATA_OX,
DEVCODE => DEVCODE,
R_W => RW,
IORW => IORW,
BYTE => BYTEOP,
IOM => IOM,
SYNC => SYNC,
IRQ => IRQ,
PWR_GOOD => PWR_GOOD,
RDY => RDY,
RESET => RESET,
FEN => FEN,
CLK => FCLK,
DBUG7 => DBUG7,
DBUG6 => DBUG6,
DBUG5 => DBUG5,
DBUG4 => DBUG4,
DBUG3 => DBUG3,
DBUG2 => DBUG2,
DBUG1 => DBUG1
);
--===========================================
-- Instantiate the UART
--===========================================
UART1:
UART port map (
CS => UART_CS,
WE => IO_WE,
REG_SEL => DEVCODE(1 downto 0),
WR_DATA => DATA_OX,
RD_DATA => UART_DATA,
RX_IRQ => UART_RRQ,
TX_IRQ => UART_TRQ,
RXD => UART_RXD,
TXD => UART_TXD,
RESET => IO_RESET,
RDV => UART_RD,
FCLK => FCLK
);
--===========================================
-- Instantiate the TIMER
--===========================================
TIMER1:
TIMER port map (
CS => TIMR_CS,
WE => IO_WE,
WR_DATA => DATA_OX,
RD_DATA => TIMR_DATA,
IRQ => TIMR_IRQ,
SEL_IC => DEVCODE(0),
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the OUTPORT
--===========================================
PORT1:
OUTPORT port map (
CS => PRTA_CS,
WE => IO_WE,
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => PRTA_DATA,
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the RAND generator
--===========================================
RAND8X:
RAND8 port map (
CS => RAND_CS,
WE => IO_WE,
REG_SEL => DEVCODE(0),
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => RAND_DATA,
RESET => IO_RESET,
FEN => FEN,
FCLK => FCLK
);
--===========================================
-- Instantiate the BOOT RAM
--===========================================
BOOTRAM:
RAM port map (
RADDR => ADDR_OUT(12 downto 0),
WADDR => ADDR_OUT(12 downto 0),
DATA_IN => DATA_OX,
DATA_OUT => BOOT_DATA,
BYTEOP => BYTEOP,
REN => BOOT_RE,
WEN => BOOT_WE,
WCLK => FCLK,
RCLK => FCLK
);
--=========================================
-- Instantiate the Reset Sync
--=========================================
SDRESET:
XRESET port map (
RST_OUT1 => RESET1, -- short reset
RST_OUT2 => RESET, -- long reset
RST_IN => SYSRESET,
CLK => FCLK
);
end BEHAVIORAL;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cart_slot/vhdl_source/reu_pkg.vhd | 4 | 1402 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/rx.vhd | 4 | 2641 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Receiver: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
rxd : in std_logic;
rxchar : out std_logic_vector(7 downto 0);
rx_ack : out std_logic );
end rx;
architecture gideon of rx is
signal bitcnt : integer range 0 to 8;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, StartBit, Receiving);
signal state : state_t;
signal rxd_c : std_logic;
begin
process(clk, reset)
begin
if clk'event and clk='1' then
rxd_c <= rxd;
rx_ack <= '0';
case state is
when Idle =>
if rxd_c = '0' then
timer <= (clks_per_bit / 2) - 1;
state <= startbit;
end if;
when StartBit =>
if rxd_c = '1' then
state <= Idle;
elsif timer = 0 then
timer <= clks_per_bit - 1;
state <= receiving;
bitcnt <= 8;
else
timer <= timer - 1;
end if;
when Receiving =>
if timer=0 then
timer <= clks_per_bit - 1;
bitvec <= rxd_c & bitvec(8 downto 1);
if bitcnt = 0 then
state <= Idle;
rx_ack <= '1';
else
bitcnt <= bitcnt - 1;
end if;
else
timer <= timer - 1;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
rxchar <= bitvec(7 downto 0);
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_source/nano_alu.vhd | 3 | 1551 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_alu is
port (
clock : in std_logic;
reset : in std_logic;
value_in : in unsigned(15 downto 0);
ext_in : in unsigned(15 downto 0);
alu_oper : in std_logic_vector(15 downto 13);
update_accu : in std_logic;
update_flag : in std_logic;
accu : out unsigned(15 downto 0);
z : out boolean;
n : out boolean );
end entity;
architecture gideon of nano_alu is
signal accu_i : unsigned(15 downto 0) := (others => '0');
signal alu_out : unsigned(15 downto 0);
signal alu_z : boolean;
signal alu_n : boolean;
begin
with alu_oper select alu_out <=
value_in when c_alu_load,
value_in or accu_i when c_alu_or,
value_in and accu_i when c_alu_and,
value_in xor accu_i when c_alu_xor,
accu_i + value_in when c_alu_add,
accu_i - value_in when c_alu_sub,
ext_in when others;
alu_z <= (alu_out = 0);
alu_n <= (alu_out(alu_out'high)='1');
process(clock)
begin
if rising_edge(clock) then
if update_accu='1' then
accu_i <= alu_out;
end if;
if update_flag='1' then
z <= alu_z;
n <= alu_n;
end if;
end if;
end process;
accu <= accu_i;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi.vhd | 5 | 4344 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/sigma_delta_dac/vhdl_source/sine_osc.vhd | 5 | 901 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sine_osc is
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
sine : out signed(15 downto 0);
cosine : out signed(15 downto 0) );
end sine_osc;
architecture gideon of sine_osc is
signal cos_i : signed(15 downto 0);
signal sin_i : signed(15 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
sin_i <= X"0000";
cos_i <= X"7FFF";
elsif enable='1' then
sin_i <= sum_limit(shift_right(cos_i, 8), sin_i);
cos_i <= sub_limit(cos_i, shift_right(sin_i, 8));
end if;
end if;
end process;
sine <= sin_i;
cosine <= cos_i;
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_floppy_stream.vhd | 4 | 4531 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
entity tb_floppy_stream is
end tb_floppy_stream;
architecture tb of tb_floppy_stream is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal drv_rdata : std_logic_vector(7 downto 0) := X"01";
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
signal fifo_put : std_logic;
signal fifo_command : std_logic_vector(2 downto 0);
signal fifo_parameter : std_logic_vector(10 downto 0);
type t_buffer_array is array (natural range <>) of std_logic_vector(7 downto 0);
shared variable my_buffer : t_buffer_array(0 to 15) := (others => X"FF");
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy_stream
port map (
clock => clock,
clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
reset => reset,
drv_rdata => drv_rdata,
floppy_inserted => '1',
write_data => write_data,
fifo_put => fifo_put,
fifo_command => fifo_command,
fifo_parameter => fifo_parameter,
track => track,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
read_data => read_data );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
mode <= '0'; -- switch to write
wait;
end process;
fill: process
begin
wait until fifo_put='1';
wait for 10 ns;
if fifo_command = c_cmd_next then
drv_rdata <= drv_rdata + 1;
end if;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
end tb; | gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/ext_mem_test_v6.vhd | 5 | 4298 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v6 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_16_req;
resp : in t_mem_burst_16_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_v6 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(15 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 15) := (
X"1234", X"5678", X"9ABC", X"DEF0", -- 0
X"DEAD", X"BEEF", X"C0ED", X"BABE", -- 100
X"00FF", X"00FF", X"00FF", X"00FF", -- 64K
X"55AA", X"55AA", X"3366", X"CC99" ); -- 0, etc
-- constant c_read_data : t_datas(0 to 15) := (
-- X"1234", X"5678", X"9ABC", X"DEF0",
-- X"DEAD", X"BEEF", X"C0ED", X"BABE",
-- X"00FF", X"00FF", X"00FF", X"00FF",
-- X"55AA", X"55AA", X"3366", X"CC99" );
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_16_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/usb/vhdl_sim/token_crc_tb.vhd | 2 | 1527 | -------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/deserializer/vhdl_source/deserializer.vhd | 5 | 1272 |
library ieee;
use ieee.std_logic_1164.all;
entity deserializer is
port (
clock : in std_logic;
sync : in std_logic;
rxd : in std_logic;
txd : out std_logic;
io : inout std_logic_vector(11 downto 0) );
end deserializer;
architecture gideon of deserializer is
signal index : integer range 0 to 31;
signal io_t : std_logic_vector(io'range) := (others => '0');
signal io_o : std_logic_vector(io'range) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
if sync='1' then
index <= 0;
elsif index /= 31 then
index <= index + 1;
end if;
if index <= io'high then
txd <= io(index);
else
txd <= '0';
end if;
if index <= io'high then
io_o(index) <= rxd;
elsif index < (2*io'length) then
io_t(index - io'length) <= rxd;
end if;
end if;
end process;
r_out: for i in io'range generate
io(i) <= io_o(i) when io_t(i)='1' else 'Z';
end generate;
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi_peripheral_io.vhd | 5 | 5372 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity spi_peripheral_io is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
busy : out std_logic;
SD_DETECTn : in std_logic := '1';
SD_WRPROTn : in std_logic := '1';
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral_io;
architecture gideon of spi_peripheral_io is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy_i : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
type t_state is (idle, writing, reading, receive);
signal state : t_state;
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy_i,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
state <= writing;
elsif io_req.read='1' then
state <= reading;
end if;
when writing =>
if busy_i='0' then
io_resp.ack <= '1';
state <= idle;
case io_req.address(3 downto 2) is
when "00" =>
do_send <= '1';
wdata <= io_req.data;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= io_req.data;
rate(8) <= io_req.data(7);
end if;
when "10" =>
force_ss <= io_req.data(0);
level_ss <= io_req.data(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
when reading =>
if busy_i='0' then
case io_req.address(3 downto 2) is
when "00" =>
do_send <= '1';
wdata <= X"FF";
state <= receive;
when "01" =>
io_resp.data <= rate(7 downto 0);
io_resp.ack <= '1';
state <= idle;
when "10" =>
io_resp.data <= "0000" & not SD_WRPROTn & not SD_DETECTn & level_ss & force_ss;
io_resp.ack <= '1';
state <= idle;
when "11" =>
io_resp.data <= crc_out;
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
end if;
when receive =>
if do_send = '0' and busy_i = '0' then
io_resp.data <= rdata;
io_resp.ack <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
if not g_fixed_rate then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
end if;
force_ss <= '0';
level_ss <= '1';
wdata <= X"FF";
end if;
end if;
end process;
busy <= busy_i;
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | target/simulation/vhdl_bfm/sram_model_8.vhd | 5 | 2119 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 |
KB777/1541UltimateII | target/simulation/vhdl_sim/mb_model_tb.vhd | 2 | 2882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model_tb is
end entity;
architecture test of mb_model_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(31 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal io_byte_en : std_logic_vector(3 downto 0);
signal io_wdata : std_logic_vector(31 downto 0);
signal io_rdata : std_logic_vector(31 downto 0) := (others => 'Z');
signal io_ack : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
model: entity work.mb_model
port map (
clock => clock,
reset => reset,
io_addr => io_addr,
io_byte_en=> io_byte_en,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
io_ack => io_ack );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
io_ack <= '0';
if io_write = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := io_wdata(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(io_addr) & " dropped";
end case;
elsif io_read = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"0000C" => -- Capabilities
io_rdata <= X"00000002";
when X"00012" => -- UART_FLAGS
io_rdata <= X"40404040";
when X"2000A" => -- 1541_A memmap
io_rdata <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
io_rdata <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(io_addr) & " dropped";
io_rdata <= X"00000000";
end case;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_sim/tb_clockgen.vhd | 5 | 1105 | library ieee;
use ieee.std_logic_1164.all;
entity tb_clockgen is
end;
architecture tb of tb_clockgen is
signal clk_50 : std_logic := '0';
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic; -- 48 MHz
signal sys_reset : std_logic;
signal drv_clock_en : std_logic; -- 1/12 (4 MHz)
signal cpu_clock_en : std_logic; -- 1/48 (1 MHz)
begin
clk_50 <= not clk_50 after 10 ns;
reset_in <= '1', '0' after 100 ns;
gen: entity work.s3e_clockgen
generic map ( false )
port map (
clk_50 => clk_50,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 48 MHz
sys_reset => sys_reset,
drv_clock_en => drv_clock_en, -- 1/12 (4 MHz)
cpu_clock_en => cpu_clock_en, -- 1/48 (1 MHz)
cpu_speed => '0', -- 0 = 1 MHz, 1 = max.
mem_ready => '1' );
end tb;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v5.vhd | 2 | 2988 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v5 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
DISK_ACTn : out std_logic );
end fpga_mem_test_v5;
architecture tb of fpga_mem_test_v5 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_req_32 := c_mem_req_32_init;
signal resp : t_mem_resp_32;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_v5
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
inhibit => inhibit,
run => MOTOR_LEDn,
okay => okay );
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
DISK_ACTn <= not okay;
end;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/video/vhdl_source/char_generator_rom_pkg.vhd | 4 | 16416 | library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"1F", X"1F", X"18", X"18", X"18", X"00", X"00", X"00", X"FF",
X"FF", X"00", X"00", X"00", X"00", X"00", X"00", X"F8", X"F8", X"18",
X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"00", X"00", X"00", X"18", X"18",
X"18", X"F8", X"F8", X"00", X"00", X"00", X"00", X"00", X"00", X"07",
X"0F", X"1C", X"18", X"18", X"00", X"00", X"00", X"FF", X"FF", X"18",
X"18", X"18", X"00", X"00", X"00", X"E0", X"F0", X"38", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"18", X"18", X"18", X"18", X"18",
X"18", X"FF", X"FF", X"18", X"18", X"18", X"18", X"18", X"18", X"F8",
X"F8", X"18", X"18", X"18", X"18", X"18", X"1C", X"0F", X"07", X"00",
X"00", X"00", X"18", X"18", X"18", X"FF", X"FF", X"00", X"00", X"00",
X"18", X"18", X"38", X"F0", X"E0", X"00", X"00", X"00", X"00", X"38",
X"6D", X"67", X"66", X"6E", X"3B", X"00", X"3C", X"66", X"66", X"6C",
X"66", X"66", X"6C", X"60", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"18", X"18", X"18", X"18", X"00", X"00",
X"18", X"00", X"66", X"66", X"66", X"00", X"00", X"00", X"00", X"00",
X"66", X"66", X"FF", X"66", X"FF", X"66", X"66", X"00", X"18", X"3E",
X"60", X"3C", X"06", X"7C", X"18", X"00", X"62", X"66", X"0C", X"18",
X"30", X"66", X"46", X"00", X"3C", X"66", X"3C", X"38", X"67", X"66",
X"3F", X"00", X"06", X"0C", X"18", X"00", X"00", X"00", X"00", X"00",
X"0C", X"18", X"30", X"30", X"30", X"18", X"0C", X"00", X"30", X"18",
X"0C", X"0C", X"0C", X"18", X"30", X"00", X"00", X"66", X"3C", X"FF",
X"3C", X"66", X"00", X"00", X"00", X"18", X"18", X"7E", X"18", X"18",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"30",
X"00", X"00", X"00", X"7E", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"18", X"18", X"00", X"00", X"03", X"06", X"0C",
X"18", X"30", X"60", X"00", X"3C", X"66", X"6E", X"76", X"66", X"66",
X"3C", X"00", X"18", X"18", X"38", X"18", X"18", X"18", X"7E", X"00",
X"3C", X"66", X"06", X"0C", X"30", X"60", X"7E", X"00", X"3C", X"66",
X"06", X"1C", X"06", X"66", X"3C", X"00", X"06", X"0E", X"1E", X"66",
X"7F", X"06", X"06", X"00", X"7E", X"60", X"7C", X"06", X"06", X"66",
X"3C", X"00", X"3C", X"66", X"60", X"7C", X"66", X"66", X"3C", X"00",
X"7E", X"66", X"0C", X"18", X"18", X"18", X"18", X"00", X"3C", X"66",
X"66", X"3C", X"66", X"66", X"3C", X"00", X"3C", X"66", X"66", X"3E",
X"06", X"66", X"3C", X"00", X"00", X"00", X"18", X"00", X"00", X"18",
X"00", X"00", X"00", X"00", X"18", X"00", X"00", X"18", X"18", X"30",
X"0E", X"18", X"30", X"60", X"30", X"18", X"0E", X"00", X"00", X"00",
X"7E", X"00", X"7E", X"00", X"00", X"00", X"70", X"18", X"0C", X"06",
X"0C", X"18", X"70", X"00", X"3C", X"66", X"06", X"0C", X"18", X"00",
X"18", X"00", X"3C", X"66", X"6E", X"6E", X"60", X"62", X"3C", X"00",
X"18", X"3C", X"66", X"7E", X"66", X"66", X"66", X"00", X"7C", X"66",
X"66", X"7C", X"66", X"66", X"7C", X"00", X"3C", X"66", X"60", X"60",
X"60", X"66", X"3C", X"00", X"78", X"6C", X"66", X"66", X"66", X"6C",
X"78", X"00", X"7E", X"60", X"60", X"78", X"60", X"60", X"7E", X"00",
X"7E", X"60", X"60", X"78", X"60", X"60", X"60", X"00", X"3C", X"66",
X"60", X"6E", X"66", X"66", X"3C", X"00", X"66", X"66", X"66", X"7E",
X"66", X"66", X"66", X"00", X"3C", X"18", X"18", X"18", X"18", X"18",
X"3C", X"00", X"1E", X"0C", X"0C", X"0C", X"0C", X"6C", X"38", X"00",
X"66", X"6C", X"78", X"70", X"78", X"6C", X"66", X"00", X"60", X"60",
X"60", X"60", X"60", X"60", X"7E", X"00", X"63", X"77", X"7F", X"6B",
X"63", X"63", X"63", X"00", X"66", X"76", X"7E", X"7E", X"6E", X"66",
X"66", X"00", X"3C", X"66", X"66", X"66", X"66", X"66", X"3C", X"00",
X"7C", X"66", X"66", X"7C", X"60", X"60", X"60", X"00", X"3C", X"66",
X"66", X"66", X"66", X"3C", X"0E", X"00", X"7C", X"66", X"66", X"7C",
X"78", X"6C", X"66", X"00", X"3C", X"66", X"60", X"3C", X"06", X"66",
X"3C", X"00", X"7E", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"66", X"66", X"66", X"66", X"66", X"66", X"3C", X"00", X"66", X"66",
X"66", X"66", X"66", X"3C", X"18", X"00", X"63", X"63", X"63", X"6B",
X"7F", X"77", X"63", X"00", X"66", X"66", X"3C", X"18", X"3C", X"66",
X"66", X"00", X"66", X"66", X"66", X"3C", X"18", X"18", X"18", X"00",
X"7E", X"06", X"0C", X"18", X"30", X"60", X"7E", X"00", X"3C", X"30",
X"30", X"30", X"30", X"30", X"3C", X"00", X"00", X"60", X"30", X"18",
X"0C", X"06", X"03", X"00", X"3C", X"0C", X"0C", X"0C", X"0C", X"0C",
X"3C", X"00", X"18", X"3C", X"66", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"18", X"0C",
X"06", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"3C", X"06",
X"3E", X"66", X"3E", X"00", X"00", X"60", X"60", X"7C", X"66", X"66",
X"7C", X"00", X"00", X"00", X"3C", X"60", X"60", X"60", X"3C", X"00",
X"00", X"06", X"06", X"3E", X"66", X"66", X"3E", X"00", X"00", X"00",
X"3C", X"66", X"7E", X"60", X"3C", X"00", X"00", X"0E", X"18", X"3E",
X"18", X"18", X"18", X"00", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"7C", X"00", X"60", X"60", X"7C", X"66", X"66", X"66", X"00",
X"00", X"18", X"00", X"38", X"18", X"18", X"3C", X"00", X"00", X"06",
X"00", X"06", X"06", X"06", X"06", X"3C", X"00", X"60", X"60", X"6C",
X"78", X"6C", X"66", X"00", X"00", X"38", X"18", X"18", X"18", X"18",
X"3C", X"00", X"00", X"00", X"66", X"7F", X"7F", X"6B", X"63", X"00",
X"00", X"00", X"7C", X"66", X"66", X"66", X"66", X"00", X"00", X"00",
X"3C", X"66", X"66", X"66", X"3C", X"00", X"00", X"00", X"7C", X"66",
X"66", X"7C", X"60", X"60", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"06", X"00", X"00", X"7C", X"66", X"60", X"60", X"60", X"00",
X"00", X"00", X"3E", X"60", X"3C", X"06", X"7C", X"00", X"00", X"18",
X"7E", X"18", X"18", X"18", X"0E", X"00", X"00", X"00", X"66", X"66",
X"66", X"66", X"3E", X"00", X"00", X"00", X"66", X"66", X"66", X"3C",
X"18", X"00", X"00", X"00", X"63", X"6B", X"7F", X"3E", X"36", X"00",
X"00", X"00", X"66", X"3C", X"18", X"3C", X"66", X"00", X"00", X"00",
X"66", X"66", X"66", X"3E", X"0C", X"78", X"00", X"00", X"7E", X"0C",
X"18", X"30", X"7E", X"00", X"0C", X"18", X"18", X"30", X"18", X"18",
X"0C", X"00", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"30", X"18", X"18", X"0C", X"18", X"18", X"30", X"00", X"00", X"70",
X"5A", X"0E", X"00", X"00", X"00", X"00", X"00", X"7E", X"42", X"42",
X"42", X"42", X"7E", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"E0", X"E0", X"E7", X"E7", X"E7",
X"FF", X"FF", X"FF", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"FF",
X"FF", X"FF", X"E7", X"E7", X"E7", X"07", X"07", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"F8", X"F0", X"E3", X"E7", X"E7", X"FF", X"FF",
X"FF", X"00", X"00", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF", X"1F",
X"0F", X"C7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"00", X"00", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E3", X"F0", X"F8", X"FF", X"FF", X"FF", X"E7", X"E7", X"E7", X"00",
X"00", X"FF", X"FF", X"FF", X"E7", X"E7", X"C7", X"0F", X"1F", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7",
X"E7", X"E7", X"FF", X"FF", X"E7", X"FF", X"99", X"99", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"99", X"99", X"00", X"99", X"00", X"99",
X"99", X"FF", X"E7", X"C1", X"9F", X"C3", X"F9", X"83", X"E7", X"FF",
X"9D", X"99", X"F3", X"E7", X"CF", X"99", X"B9", X"FF", X"C3", X"99",
X"C3", X"C7", X"98", X"99", X"C0", X"FF", X"F9", X"F3", X"E7", X"FF",
X"FF", X"FF", X"FF", X"FF", X"F3", X"E7", X"CF", X"CF", X"CF", X"E7",
X"F3", X"FF", X"CF", X"E7", X"F3", X"F3", X"F3", X"E7", X"CF", X"FF",
X"FF", X"99", X"C3", X"00", X"C3", X"99", X"FF", X"FF", X"FF", X"E7",
X"E7", X"81", X"E7", X"E7", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"E7", X"E7", X"CF", X"FF", X"FF", X"FF", X"81", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"FF",
X"FF", X"FC", X"F9", X"F3", X"E7", X"CF", X"9F", X"FF", X"C3", X"99",
X"91", X"89", X"99", X"99", X"C3", X"FF", X"E7", X"E7", X"C7", X"E7",
X"E7", X"E7", X"81", X"FF", X"C3", X"99", X"F9", X"F3", X"CF", X"9F",
X"81", X"FF", X"C3", X"99", X"F9", X"E3", X"F9", X"99", X"C3", X"FF",
X"F9", X"F1", X"E1", X"99", X"80", X"F9", X"F9", X"FF", X"81", X"9F",
X"83", X"F9", X"F9", X"99", X"C3", X"FF", X"C3", X"99", X"9F", X"83",
X"99", X"99", X"C3", X"FF", X"81", X"99", X"F3", X"E7", X"E7", X"E7",
X"E7", X"FF", X"C3", X"99", X"99", X"C3", X"99", X"99", X"C3", X"FF",
X"C3", X"99", X"99", X"C1", X"F9", X"99", X"C3", X"FF", X"FF", X"FF",
X"E7", X"FF", X"FF", X"E7", X"FF", X"FF", X"FF", X"FF", X"E7", X"FF",
X"FF", X"E7", X"E7", X"CF", X"F1", X"E7", X"CF", X"9F", X"CF", X"E7",
X"F1", X"FF", X"FF", X"FF", X"81", X"FF", X"81", X"FF", X"FF", X"FF",
X"8F", X"E7", X"F3", X"F9", X"F3", X"E7", X"8F", X"FF", X"C3", X"99",
X"F9", X"F3", X"E7", X"FF", X"E7", X"FF", X"C3", X"99", X"91", X"91",
X"9F", X"9D", X"C3", X"FF", X"E7", X"C3", X"99", X"81", X"99", X"99",
X"99", X"FF", X"83", X"99", X"99", X"83", X"99", X"99", X"83", X"FF",
X"C3", X"99", X"9F", X"9F", X"9F", X"99", X"C3", X"FF", X"87", X"93",
X"99", X"99", X"99", X"93", X"87", X"FF", X"81", X"9F", X"9F", X"87",
X"9F", X"9F", X"81", X"FF", X"81", X"9F", X"9F", X"87", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"9F", X"91", X"99", X"99", X"C3", X"FF",
X"99", X"99", X"99", X"81", X"99", X"99", X"99", X"FF", X"C3", X"E7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"E1", X"F3", X"F3", X"F3",
X"F3", X"93", X"C7", X"FF", X"99", X"93", X"87", X"8F", X"87", X"93",
X"99", X"FF", X"9F", X"9F", X"9F", X"9F", X"9F", X"9F", X"81", X"FF",
X"9C", X"88", X"80", X"94", X"9C", X"9C", X"9C", X"FF", X"99", X"89",
X"81", X"81", X"91", X"99", X"99", X"FF", X"C3", X"99", X"99", X"99",
X"99", X"99", X"C3", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"99", X"99", X"99", X"C3", X"F1", X"FF",
X"83", X"99", X"99", X"83", X"87", X"93", X"99", X"FF", X"C3", X"99",
X"9F", X"C3", X"F9", X"99", X"C3", X"FF", X"81", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"99", X"99", X"99", X"99", X"99", X"99",
X"C3", X"FF", X"99", X"99", X"99", X"99", X"99", X"C3", X"E7", X"FF",
X"9C", X"9C", X"9C", X"94", X"80", X"88", X"9C", X"FF", X"99", X"99",
X"C3", X"E7", X"C3", X"99", X"99", X"FF", X"99", X"99", X"99", X"C3",
X"E7", X"E7", X"E7", X"FF", X"81", X"F9", X"F3", X"E7", X"CF", X"9F",
X"81", X"FF", X"C3", X"CF", X"CF", X"CF", X"CF", X"CF", X"C3", X"FF",
X"FF", X"9F", X"CF", X"E7", X"F3", X"F9", X"FC", X"FF", X"C3", X"F3",
X"F3", X"F3", X"F3", X"F3", X"C3", X"FF", X"E7", X"C3", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"00", X"E7", X"F3", X"F9", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"C3", X"F9", X"C1", X"99", X"C1", X"FF", X"FF", X"9F",
X"9F", X"83", X"99", X"99", X"83", X"FF", X"FF", X"FF", X"C3", X"9F",
X"9F", X"9F", X"C3", X"FF", X"FF", X"F9", X"F9", X"C1", X"99", X"99",
X"C1", X"FF", X"FF", X"FF", X"C3", X"99", X"81", X"9F", X"C3", X"FF",
X"FF", X"F1", X"E7", X"C1", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"83", X"FF", X"9F", X"9F", X"83",
X"99", X"99", X"99", X"FF", X"FF", X"E7", X"FF", X"C7", X"E7", X"E7",
X"C3", X"FF", X"FF", X"F9", X"FF", X"F9", X"F9", X"F9", X"F9", X"C3",
X"FF", X"9F", X"9F", X"93", X"87", X"93", X"99", X"FF", X"FF", X"C7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"FF", X"FF", X"99", X"80",
X"80", X"94", X"9C", X"FF", X"FF", X"FF", X"83", X"99", X"99", X"99",
X"99", X"FF", X"FF", X"FF", X"C3", X"99", X"99", X"99", X"C3", X"FF",
X"FF", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"F9", X"FF", X"FF", X"83", X"99",
X"9F", X"9F", X"9F", X"FF", X"FF", X"FF", X"C1", X"9F", X"C3", X"F9",
X"83", X"FF", X"FF", X"E7", X"81", X"E7", X"E7", X"E7", X"F1", X"FF",
X"FF", X"FF", X"99", X"99", X"99", X"99", X"C1", X"FF", X"FF", X"FF",
X"99", X"99", X"99", X"C3", X"E7", X"FF", X"FF", X"FF", X"9C", X"94",
X"80", X"C1", X"C9", X"FF", X"FF", X"FF", X"99", X"C3", X"E7", X"C3",
X"99", X"FF", X"FF", X"FF", X"99", X"99", X"99", X"C1", X"F3", X"87",
X"FF", X"FF", X"81", X"F3", X"E7", X"CF", X"81", X"FF", X"F3", X"E7",
X"E7", X"CF", X"E7", X"E7", X"F3", X"FF", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"CF", X"E7", X"E7", X"F3", X"E7", X"E7",
X"CF", X"FF", X"FF", X"8F", X"A5", X"F1", X"FF", X"FF", X"FF", X"FF",
X"FF", X"81", X"BD", X"BD", X"BD", X"BD", X"81", X"FF" );
end;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_rom_pkg.vhd | 4 | 16416 | library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"1F", X"1F", X"18", X"18", X"18", X"00", X"00", X"00", X"FF",
X"FF", X"00", X"00", X"00", X"00", X"00", X"00", X"F8", X"F8", X"18",
X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"00", X"00", X"00", X"18", X"18",
X"18", X"F8", X"F8", X"00", X"00", X"00", X"00", X"00", X"00", X"07",
X"0F", X"1C", X"18", X"18", X"00", X"00", X"00", X"FF", X"FF", X"18",
X"18", X"18", X"00", X"00", X"00", X"E0", X"F0", X"38", X"18", X"18",
X"18", X"18", X"18", X"1F", X"1F", X"18", X"18", X"18", X"18", X"18",
X"18", X"FF", X"FF", X"18", X"18", X"18", X"18", X"18", X"18", X"F8",
X"F8", X"18", X"18", X"18", X"18", X"18", X"1C", X"0F", X"07", X"00",
X"00", X"00", X"18", X"18", X"18", X"FF", X"FF", X"00", X"00", X"00",
X"18", X"18", X"38", X"F0", X"E0", X"00", X"00", X"00", X"00", X"38",
X"6D", X"67", X"66", X"6E", X"3B", X"00", X"3C", X"66", X"66", X"6C",
X"66", X"66", X"6C", X"60", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"18", X"18", X"18", X"18", X"00", X"00",
X"18", X"00", X"66", X"66", X"66", X"00", X"00", X"00", X"00", X"00",
X"66", X"66", X"FF", X"66", X"FF", X"66", X"66", X"00", X"18", X"3E",
X"60", X"3C", X"06", X"7C", X"18", X"00", X"62", X"66", X"0C", X"18",
X"30", X"66", X"46", X"00", X"3C", X"66", X"3C", X"38", X"67", X"66",
X"3F", X"00", X"06", X"0C", X"18", X"00", X"00", X"00", X"00", X"00",
X"0C", X"18", X"30", X"30", X"30", X"18", X"0C", X"00", X"30", X"18",
X"0C", X"0C", X"0C", X"18", X"30", X"00", X"00", X"66", X"3C", X"FF",
X"3C", X"66", X"00", X"00", X"00", X"18", X"18", X"7E", X"18", X"18",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"30",
X"00", X"00", X"00", X"7E", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"18", X"18", X"00", X"00", X"03", X"06", X"0C",
X"18", X"30", X"60", X"00", X"3C", X"66", X"6E", X"76", X"66", X"66",
X"3C", X"00", X"18", X"18", X"38", X"18", X"18", X"18", X"7E", X"00",
X"3C", X"66", X"06", X"0C", X"30", X"60", X"7E", X"00", X"3C", X"66",
X"06", X"1C", X"06", X"66", X"3C", X"00", X"06", X"0E", X"1E", X"66",
X"7F", X"06", X"06", X"00", X"7E", X"60", X"7C", X"06", X"06", X"66",
X"3C", X"00", X"3C", X"66", X"60", X"7C", X"66", X"66", X"3C", X"00",
X"7E", X"66", X"0C", X"18", X"18", X"18", X"18", X"00", X"3C", X"66",
X"66", X"3C", X"66", X"66", X"3C", X"00", X"3C", X"66", X"66", X"3E",
X"06", X"66", X"3C", X"00", X"00", X"00", X"18", X"00", X"00", X"18",
X"00", X"00", X"00", X"00", X"18", X"00", X"00", X"18", X"18", X"30",
X"0E", X"18", X"30", X"60", X"30", X"18", X"0E", X"00", X"00", X"00",
X"7E", X"00", X"7E", X"00", X"00", X"00", X"70", X"18", X"0C", X"06",
X"0C", X"18", X"70", X"00", X"3C", X"66", X"06", X"0C", X"18", X"00",
X"18", X"00", X"3C", X"66", X"6E", X"6E", X"60", X"62", X"3C", X"00",
X"18", X"3C", X"66", X"7E", X"66", X"66", X"66", X"00", X"7C", X"66",
X"66", X"7C", X"66", X"66", X"7C", X"00", X"3C", X"66", X"60", X"60",
X"60", X"66", X"3C", X"00", X"78", X"6C", X"66", X"66", X"66", X"6C",
X"78", X"00", X"7E", X"60", X"60", X"78", X"60", X"60", X"7E", X"00",
X"7E", X"60", X"60", X"78", X"60", X"60", X"60", X"00", X"3C", X"66",
X"60", X"6E", X"66", X"66", X"3C", X"00", X"66", X"66", X"66", X"7E",
X"66", X"66", X"66", X"00", X"3C", X"18", X"18", X"18", X"18", X"18",
X"3C", X"00", X"1E", X"0C", X"0C", X"0C", X"0C", X"6C", X"38", X"00",
X"66", X"6C", X"78", X"70", X"78", X"6C", X"66", X"00", X"60", X"60",
X"60", X"60", X"60", X"60", X"7E", X"00", X"63", X"77", X"7F", X"6B",
X"63", X"63", X"63", X"00", X"66", X"76", X"7E", X"7E", X"6E", X"66",
X"66", X"00", X"3C", X"66", X"66", X"66", X"66", X"66", X"3C", X"00",
X"7C", X"66", X"66", X"7C", X"60", X"60", X"60", X"00", X"3C", X"66",
X"66", X"66", X"66", X"3C", X"0E", X"00", X"7C", X"66", X"66", X"7C",
X"78", X"6C", X"66", X"00", X"3C", X"66", X"60", X"3C", X"06", X"66",
X"3C", X"00", X"7E", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"66", X"66", X"66", X"66", X"66", X"66", X"3C", X"00", X"66", X"66",
X"66", X"66", X"66", X"3C", X"18", X"00", X"63", X"63", X"63", X"6B",
X"7F", X"77", X"63", X"00", X"66", X"66", X"3C", X"18", X"3C", X"66",
X"66", X"00", X"66", X"66", X"66", X"3C", X"18", X"18", X"18", X"00",
X"7E", X"06", X"0C", X"18", X"30", X"60", X"7E", X"00", X"3C", X"30",
X"30", X"30", X"30", X"30", X"3C", X"00", X"00", X"60", X"30", X"18",
X"0C", X"06", X"03", X"00", X"3C", X"0C", X"0C", X"0C", X"0C", X"0C",
X"3C", X"00", X"18", X"3C", X"66", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"18", X"0C",
X"06", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"3C", X"06",
X"3E", X"66", X"3E", X"00", X"00", X"60", X"60", X"7C", X"66", X"66",
X"7C", X"00", X"00", X"00", X"3C", X"60", X"60", X"60", X"3C", X"00",
X"00", X"06", X"06", X"3E", X"66", X"66", X"3E", X"00", X"00", X"00",
X"3C", X"66", X"7E", X"60", X"3C", X"00", X"00", X"0E", X"18", X"3E",
X"18", X"18", X"18", X"00", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"7C", X"00", X"60", X"60", X"7C", X"66", X"66", X"66", X"00",
X"00", X"18", X"00", X"38", X"18", X"18", X"3C", X"00", X"00", X"06",
X"00", X"06", X"06", X"06", X"06", X"3C", X"00", X"60", X"60", X"6C",
X"78", X"6C", X"66", X"00", X"00", X"38", X"18", X"18", X"18", X"18",
X"3C", X"00", X"00", X"00", X"66", X"7F", X"7F", X"6B", X"63", X"00",
X"00", X"00", X"7C", X"66", X"66", X"66", X"66", X"00", X"00", X"00",
X"3C", X"66", X"66", X"66", X"3C", X"00", X"00", X"00", X"7C", X"66",
X"66", X"7C", X"60", X"60", X"00", X"00", X"3E", X"66", X"66", X"3E",
X"06", X"06", X"00", X"00", X"7C", X"66", X"60", X"60", X"60", X"00",
X"00", X"00", X"3E", X"60", X"3C", X"06", X"7C", X"00", X"00", X"18",
X"7E", X"18", X"18", X"18", X"0E", X"00", X"00", X"00", X"66", X"66",
X"66", X"66", X"3E", X"00", X"00", X"00", X"66", X"66", X"66", X"3C",
X"18", X"00", X"00", X"00", X"63", X"6B", X"7F", X"3E", X"36", X"00",
X"00", X"00", X"66", X"3C", X"18", X"3C", X"66", X"00", X"00", X"00",
X"66", X"66", X"66", X"3E", X"0C", X"78", X"00", X"00", X"7E", X"0C",
X"18", X"30", X"7E", X"00", X"0C", X"18", X"18", X"30", X"18", X"18",
X"0C", X"00", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"00",
X"30", X"18", X"18", X"0C", X"18", X"18", X"30", X"00", X"00", X"70",
X"5A", X"0E", X"00", X"00", X"00", X"00", X"00", X"7E", X"42", X"42",
X"42", X"42", X"7E", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"E0", X"E0", X"E7", X"E7", X"E7",
X"FF", X"FF", X"FF", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"FF",
X"FF", X"FF", X"E7", X"E7", X"E7", X"07", X"07", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"F8", X"F0", X"E3", X"E7", X"E7", X"FF", X"FF",
X"FF", X"00", X"00", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF", X"1F",
X"0F", X"C7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E0", X"E0", X"E7",
X"E7", X"E7", X"E7", X"E7", X"E7", X"00", X"00", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"07", X"07", X"E7", X"E7", X"E7", X"E7", X"E7",
X"E3", X"F0", X"F8", X"FF", X"FF", X"FF", X"E7", X"E7", X"E7", X"00",
X"00", X"FF", X"FF", X"FF", X"E7", X"E7", X"C7", X"0F", X"1F", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7",
X"E7", X"E7", X"FF", X"FF", X"E7", X"FF", X"99", X"99", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"99", X"99", X"00", X"99", X"00", X"99",
X"99", X"FF", X"E7", X"C1", X"9F", X"C3", X"F9", X"83", X"E7", X"FF",
X"9D", X"99", X"F3", X"E7", X"CF", X"99", X"B9", X"FF", X"C3", X"99",
X"C3", X"C7", X"98", X"99", X"C0", X"FF", X"F9", X"F3", X"E7", X"FF",
X"FF", X"FF", X"FF", X"FF", X"F3", X"E7", X"CF", X"CF", X"CF", X"E7",
X"F3", X"FF", X"CF", X"E7", X"F3", X"F3", X"F3", X"E7", X"CF", X"FF",
X"FF", X"99", X"C3", X"00", X"C3", X"99", X"FF", X"FF", X"FF", X"E7",
X"E7", X"81", X"E7", X"E7", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"E7", X"E7", X"CF", X"FF", X"FF", X"FF", X"81", X"FF", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"FF",
X"FF", X"FC", X"F9", X"F3", X"E7", X"CF", X"9F", X"FF", X"C3", X"99",
X"91", X"89", X"99", X"99", X"C3", X"FF", X"E7", X"E7", X"C7", X"E7",
X"E7", X"E7", X"81", X"FF", X"C3", X"99", X"F9", X"F3", X"CF", X"9F",
X"81", X"FF", X"C3", X"99", X"F9", X"E3", X"F9", X"99", X"C3", X"FF",
X"F9", X"F1", X"E1", X"99", X"80", X"F9", X"F9", X"FF", X"81", X"9F",
X"83", X"F9", X"F9", X"99", X"C3", X"FF", X"C3", X"99", X"9F", X"83",
X"99", X"99", X"C3", X"FF", X"81", X"99", X"F3", X"E7", X"E7", X"E7",
X"E7", X"FF", X"C3", X"99", X"99", X"C3", X"99", X"99", X"C3", X"FF",
X"C3", X"99", X"99", X"C1", X"F9", X"99", X"C3", X"FF", X"FF", X"FF",
X"E7", X"FF", X"FF", X"E7", X"FF", X"FF", X"FF", X"FF", X"E7", X"FF",
X"FF", X"E7", X"E7", X"CF", X"F1", X"E7", X"CF", X"9F", X"CF", X"E7",
X"F1", X"FF", X"FF", X"FF", X"81", X"FF", X"81", X"FF", X"FF", X"FF",
X"8F", X"E7", X"F3", X"F9", X"F3", X"E7", X"8F", X"FF", X"C3", X"99",
X"F9", X"F3", X"E7", X"FF", X"E7", X"FF", X"C3", X"99", X"91", X"91",
X"9F", X"9D", X"C3", X"FF", X"E7", X"C3", X"99", X"81", X"99", X"99",
X"99", X"FF", X"83", X"99", X"99", X"83", X"99", X"99", X"83", X"FF",
X"C3", X"99", X"9F", X"9F", X"9F", X"99", X"C3", X"FF", X"87", X"93",
X"99", X"99", X"99", X"93", X"87", X"FF", X"81", X"9F", X"9F", X"87",
X"9F", X"9F", X"81", X"FF", X"81", X"9F", X"9F", X"87", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"9F", X"91", X"99", X"99", X"C3", X"FF",
X"99", X"99", X"99", X"81", X"99", X"99", X"99", X"FF", X"C3", X"E7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"E1", X"F3", X"F3", X"F3",
X"F3", X"93", X"C7", X"FF", X"99", X"93", X"87", X"8F", X"87", X"93",
X"99", X"FF", X"9F", X"9F", X"9F", X"9F", X"9F", X"9F", X"81", X"FF",
X"9C", X"88", X"80", X"94", X"9C", X"9C", X"9C", X"FF", X"99", X"89",
X"81", X"81", X"91", X"99", X"99", X"FF", X"C3", X"99", X"99", X"99",
X"99", X"99", X"C3", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F",
X"9F", X"FF", X"C3", X"99", X"99", X"99", X"99", X"C3", X"F1", X"FF",
X"83", X"99", X"99", X"83", X"87", X"93", X"99", X"FF", X"C3", X"99",
X"9F", X"C3", X"F9", X"99", X"C3", X"FF", X"81", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"99", X"99", X"99", X"99", X"99", X"99",
X"C3", X"FF", X"99", X"99", X"99", X"99", X"99", X"C3", X"E7", X"FF",
X"9C", X"9C", X"9C", X"94", X"80", X"88", X"9C", X"FF", X"99", X"99",
X"C3", X"E7", X"C3", X"99", X"99", X"FF", X"99", X"99", X"99", X"C3",
X"E7", X"E7", X"E7", X"FF", X"81", X"F9", X"F3", X"E7", X"CF", X"9F",
X"81", X"FF", X"C3", X"CF", X"CF", X"CF", X"CF", X"CF", X"C3", X"FF",
X"FF", X"9F", X"CF", X"E7", X"F3", X"F9", X"FC", X"FF", X"C3", X"F3",
X"F3", X"F3", X"F3", X"F3", X"C3", X"FF", X"E7", X"C3", X"99", X"FF",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"00", X"E7", X"F3", X"F9", X"FF", X"FF", X"FF", X"FF", X"FF",
X"FF", X"FF", X"C3", X"F9", X"C1", X"99", X"C1", X"FF", X"FF", X"9F",
X"9F", X"83", X"99", X"99", X"83", X"FF", X"FF", X"FF", X"C3", X"9F",
X"9F", X"9F", X"C3", X"FF", X"FF", X"F9", X"F9", X"C1", X"99", X"99",
X"C1", X"FF", X"FF", X"FF", X"C3", X"99", X"81", X"9F", X"C3", X"FF",
X"FF", X"F1", X"E7", X"C1", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"83", X"FF", X"9F", X"9F", X"83",
X"99", X"99", X"99", X"FF", X"FF", X"E7", X"FF", X"C7", X"E7", X"E7",
X"C3", X"FF", X"FF", X"F9", X"FF", X"F9", X"F9", X"F9", X"F9", X"C3",
X"FF", X"9F", X"9F", X"93", X"87", X"93", X"99", X"FF", X"FF", X"C7",
X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", X"FF", X"FF", X"99", X"80",
X"80", X"94", X"9C", X"FF", X"FF", X"FF", X"83", X"99", X"99", X"99",
X"99", X"FF", X"FF", X"FF", X"C3", X"99", X"99", X"99", X"C3", X"FF",
X"FF", X"FF", X"83", X"99", X"99", X"83", X"9F", X"9F", X"FF", X"FF",
X"C1", X"99", X"99", X"C1", X"F9", X"F9", X"FF", X"FF", X"83", X"99",
X"9F", X"9F", X"9F", X"FF", X"FF", X"FF", X"C1", X"9F", X"C3", X"F9",
X"83", X"FF", X"FF", X"E7", X"81", X"E7", X"E7", X"E7", X"F1", X"FF",
X"FF", X"FF", X"99", X"99", X"99", X"99", X"C1", X"FF", X"FF", X"FF",
X"99", X"99", X"99", X"C3", X"E7", X"FF", X"FF", X"FF", X"9C", X"94",
X"80", X"C1", X"C9", X"FF", X"FF", X"FF", X"99", X"C3", X"E7", X"C3",
X"99", X"FF", X"FF", X"FF", X"99", X"99", X"99", X"C1", X"F3", X"87",
X"FF", X"FF", X"81", X"F3", X"E7", X"CF", X"81", X"FF", X"F3", X"E7",
X"E7", X"CF", X"E7", X"E7", X"F3", X"FF", X"E7", X"E7", X"E7", X"E7",
X"E7", X"E7", X"E7", X"FF", X"CF", X"E7", X"E7", X"F3", X"E7", X"E7",
X"CF", X"FF", X"FF", X"8F", X"A5", X"F1", X"FF", X"FF", X"FF", X"FF",
X"FF", X"81", X"BD", X"BD", X"BD", X"BD", X"81", X"FF" );
end;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/config_pkg.vhd | 2 | 3337 | ----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package config_Pkg is
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
constant CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
constant CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
constant CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 32; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := false; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2;
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
end config_Pkg;
| gpl-3.0 |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_mb_700a.vhd | 1 | 9995 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_version : unsigned(7 downto 0) := X"04" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- memory
SDRAM_A : out std_logic_vector(12 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- LED Interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture structural of ultimate_mb_700a is
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
-- signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3a_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_clock_2x => sys_clock_2x );
i_logic: entity work.ultimate_logic_32
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_analyzer => false,
g_profiler => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- LED interface
LED_CLK => LED_CLK,
LED_DATA => LED_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 |
emabello42/FREAK-on-FPGA | embeddedretina_ise/DoG.vhd | 1 | 2147 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_OuyKy6
-- /___/ /\ Timestamp : 04/06/2014 00:34:07
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity DoG is
port ( clk : in std_logic;
enableIn : in std_logic;
point1 : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
point2 : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
enableOut : out std_logic;
test : out std_logic);
end DoG;
architecture BEHAVIORAL of DoG is
begin
process(clk)
begin
if rising_edge(clk) then
if enableIn = '1' then
if unsigned(point1) > unsigned(point2) then
test <= '1';
else
test <= '0';
end if;
end if;
enableOut <= enableIn;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_sim/harness_dm_cache.vhd | 5 | 4099 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_sim/tb_tx.vhd | 5 | 2109 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Testbench for Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_tx is
end tb_tx;
architecture tb of tb_tx is
component tx is
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
txd : out std_logic;
done : out std_logic );
end component;
signal clk : std_logic;
signal reset : std_logic;
signal dotx : std_logic;
signal txchar : character;
signal txd : std_logic;
signal done : std_logic;
constant teststring : string := "Gideon is gek";
begin
ck: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
test: process
begin
reset <= '1';
dotx <= '0';
txchar <= NUL; --StdToChar("00000000");
wait for 80 ns;
reset <= '0';
wait until clk='1';
for i in teststring'range loop
txchar <= teststring(i);
dotx <= '1';
wait until clk='1';
dotx <= '0';
wait until clk='1';
while done='0' loop
wait until clk='1';
end loop;
end loop;
wait;
end process;
my_tx: tx port map (
clk => clk,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
end tb;
| gpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.