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KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4b.vhd | 3 | 12673 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4b is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4b;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4b is
-- SRCW
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0222", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=1, CAS lat = 2
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
type t_state is (boot, init, idle, sd_read, read_single, read_single_end, sd_write, wait_for_precharge, delay_to_terminate);
signal state : t_state;
signal sdram_cmd : std_logic_vector(3 downto 0) := "1111";
signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sdram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal refresh_inhibit: std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack_count : unsigned(1 downto 0) := "00";
signal count_out : unsigned(1 downto 0) := "00";
signal dack : std_logic := '0';
signal dack_pre : std_logic := '0';
signal rack : std_logic := '0';
signal dack_tag_pre : std_logic_vector(req.tag'range) := (others => '0');
signal rack_tag : std_logic_vector(req.tag'range) := (others => '0');
signal dack_tag : std_logic_vector(req.tag'range) := (others => '0');
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of sdram_cmd : signal is "true";
attribute iob of mem_a_i : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
resp.count <= count_out;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
sdram_cmd <= c_cmd_refresh;
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
dack_count <= req.size;
sdram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
sdram_cmd <= c_cmd_active;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
rack_tag <= (others => '0');
dack_pre <= '0';
dack_tag_pre <= (others => '0');
dack <= dack_pre;
dack_tag <= dack_tag_pre;
if dack='1' then
count_out <= count_out + 1;
else
count_out <= "00";
end if;
dout_sel <= '0';
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
sdram_cmd <= c_cmd_inactive;
SDRAM_CKE <= enable_sdram;
sdram_d_t <= '0';
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
if inhibit='1' then
refresh_inhibit <= '1';
end if;
case state is
when boot =>
refresh_inhibit <= '0';
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
sdram_cmd(3) <= '1';
sdram_cmd(2 downto 0) <= c_init_array(init_cnt).cmd(2 downto 0);
if delay = 0 then
delay <= 7;
sdram_cmd(3) <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if do_refresh='1' and refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req_i='1' and refr_delay = 0 then
accept_req;
refresh_inhibit <= '0';
if req.read_writen = '1' then
state <= sd_read;
else
state <= sd_write;
end if;
end if;
end if;
when sd_read =>
mem_a_i(10) <= '0'; -- no auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_read;
if dack_count = "00" then
state <= read_single;
else
state <= delay_to_terminate;
end if;
when read_single =>
dack_pre <= '1';
dack_tag_pre <= tag;
sdram_cmd <= c_cmd_bterm;
state <= read_single_end;
when read_single_end =>
sdram_cmd <= c_cmd_precharge;
state <= idle;
when delay_to_terminate =>
dack_pre <= '1';
dack_tag_pre <= tag;
dack_count <= dack_count - 1;
delay <= 2;
if dack_count = "00" then
sdram_cmd <= c_cmd_precharge;
state <= idle;
end if;
when sd_write =>
if delay = 0 then
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_write;
sdram_d_t <= '1';
delay <= 2;
state <= wait_for_precharge;
end if;
when wait_for_precharge =>
if delay = 0 then
state <= idle;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sdram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
refresh_inhibit <= '0';
end if;
end if;
end process;
MEM_D <= sdram_d_o when sdram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
SDRAM_CSn <= sdram_cmd(3);
SDRAM_RASn <= sdram_cmd(2);
SDRAM_CASn <= sdram_cmd(1);
SDRAM_WEn <= sdram_cmd(0);
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
-- ACT to READ: tRCD = 20 ns ( = 1 CLK)
-- ACT to PRCH: tRAS = 44 ns ( = 3 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 4 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 1 CLK)
-- PRCH time; tRP = 20 ns ( = 1 CLK)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A R P +
-- - - - D
-- +: ONLY if same bank, otherwise we don't meet tRC.
-- BL2 A R - P
-- - - - D D
-- BL3 A R - - P
-- - - - D D D
-- BL4 A r - - - p
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
-- BL4 A r - - - p - A
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
| gpl-3.0 |
KB777/1541UltimateII | target/simulation/vhdl_bfm/bram_model_32sp.vhd | 5 | 2062 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : BRAM model
-------------------------------------------------------------------------------
-- File : bram_model_32sp.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple BRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity bram_model_32sp is
generic (
g_given_name : string;
g_depth : positive := 18 );
port (
CLK : in std_logic;
SSR : in std_logic;
EN : in std_logic;
WE : in std_logic;
ADDR : in std_logic_vector(g_depth-1 downto 0);
DI : in std_logic_vector(31 downto 0);
DO : out std_logic_vector(31 downto 0) );
end bram_model_32sp;
architecture bfm of bram_model_32sp is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(bram_model_32sp'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(CLK)
variable vaddr : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
vaddr(g_depth+1 downto 2) := ADDR;
if EN='1' then
if bound then
DO <= read_memory_32(this, vaddr);
if WE='1' then
write_memory_32(this, vaddr, DI);
end if;
end if;
end if;
if SSR='1' then
DO <= (others => '0');
end if;
end if;
end process;
end bfm;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_250e.vhd | 4 | 9654 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_250e is
generic (
g_simulation : boolean := false;
g_version : unsigned(7 downto 0) := X"F2" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(21 downto 0); -- 4M linear space
LB_DATA : inout std_logic_vector(7 downto 0);
FLASH_CSn : out std_logic;
SRAM_CSn : out std_logic;
MEM_WEn : out std_logic;
MEM_OEn : out std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USB
USB_IOP : inout std_logic;
USB_ION : inout std_logic;
USB_SEP : in std_logic;
USB_SEN : in std_logic;
USB_DET : inout std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_WP : in std_logic;
SD_CARDDETn : in std_logic;
-- 1-wire Interface
ONE_WIRE : inout std_logic;
-- Ethernet Interface
ETH_CLK : inout std_logic := '0';
ETH_IRQ : in std_logic := '0';
ETH_CSn : out std_logic;
ETH_CS : out std_logic;
ETH_RST : out std_logic;
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic;
CAS_READ : inout std_logic;
CAS_WRITE : inout std_logic;
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
-- attribute iob : string;
-- attribute iob of CAS_SENSE : signal is "false";
end ultimate_1541_250e;
architecture structural of ultimate_1541_250e is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => ETH_CLK );
i_logic: entity work.ultimate_logic
generic map (
g_fpga_type => 2,
g_version => g_version,
g_simulation => g_simulation,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => false,
g_uart => false,
g_drive_1541 => true, --
g_drive_1541_2 => false, --
g_hardware_gcr => true,
g_ram_expansion => true, --
g_hardware_iec => false, --
g_iec_prog_tim => false,
g_stereo_sid => false,
g_command_intf => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => true, --
g_drive_sound => false, --
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_spi_flash => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => sys_clock, -- just in case anything is connected
ulpi_reset => sys_reset, -- just in case anything is connected
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- RTC Interface
RTC_CS => open,
RTC_SCK => open,
RTC_MOSI => open,
RTC_MISO => '0',
-- Flash Interface
FLASH_CSn => open,
FLASH_SCK => open,
FLASH_MOSI => open,
FLASH_MISO => '0',
-- USB Interface (ULPI)
ULPI_NXT => '0',
ULPI_STP => open,
ULPI_DIR => '0',
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Unused
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4_u1
generic map (
g_simulation => g_simulation,
A_Width => LB_ADDR'length )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
ETH_CSn => ETH_CSn,
SRAM_CSn => SRAM_CSn,
FLASH_CSn => FLASH_CSn,
MEM_OEn => MEM_OEn,
MEM_WEn => MEM_WEn,
MEM_BEn => open,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
ETH_RST <= sys_reset;
ETH_CS <= '1'; --config.eth_enable; --'1'; -- addr 8/9
-- tie offs
SDRAM_DQM <= '0';
-- USB
USB_IOP <= USB_SEP;
USB_ION <= USB_SEN;
USB_DET <= 'Z';
ONE_WIRE <= 'Z';
end structural;
| gpl-3.0 |
KB777/1541UltimateII | fpga/1541/vhdl_sim/tb_cpu_part_1541.vhd | 5 | 3636 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/oscillator.vhd | 6 | 3277 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_tx.vhd | 3 | 5761 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_ulpi_tx is
end entity;
architecture tb of tb_ulpi_tx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"40";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '1';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_command : std_logic;
signal rx_register : std_logic;
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
signal busy : std_logic;
-- Interface to send tokens
signal send_handsh : std_logic := '0';
signal send_token : std_logic := '0';
signal pid : std_logic_vector(3 downto 0) := X"0";
signal token : std_logic_vector(10 downto 0) := (others => '0');
-- Interface to send data packets
signal send_data : std_logic := '0';
signal user_data : std_logic_vector(7 downto 0) := X"00";
signal user_last : std_logic := '0';
signal user_valid : std_logic := '0';
signal user_next : std_logic := '0';
-- Interface to read/write registers
signal read_reg : std_logic := '0';
signal write_reg : std_logic := '0';
signal address : std_logic_vector(5 downto 0) := (others => '0');
signal write_data : std_logic_vector(7 downto 0) := (others => '0');
signal read_data : std_logic_vector(7 downto 0) := (others => '0');
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
signal set : std_logic_vector(7 downto 0) := X"00";
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_tx: entity work.ulpi_tx
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => busy,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => pid,
token => token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_bus: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 500 )
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
P_data: process(clock)
begin
if rising_edge(clock) then
if set /= X"00" then
user_data <= set;
elsif user_next='1' then
user_data <= std_logic_vector(unsigned(tx_data) + 1);
end if;
end if;
end process;
p_test: process
begin
wait until reset='0';
wait until clock='1';
write_data <= X"21";
address <= "010101";
write_reg <= '1';
wait until clock='1';
write_reg <= '0';
wait until busy='0';
wait until clock='1';
address <= "101010";
read_reg <= '1';
wait until clock='1';
read_reg <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_sof;
token <= "00101100011";
send_token <= '1';
wait until clock='1';
send_token <= '0';
wait until busy='0';
wait until clock='1';
send_data <= '1';
pid <= c_pid_data0;
wait until clock='1';
send_data <= '0';
wait until user_data = X"10";
user_last <= '1';
wait until clock = '1';
user_last <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_ack;
token <= "00101100011";
send_handsh <= '1';
wait until clock='1';
send_handsh <= '0';
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_proc_control.vhd | 5 | 7221 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
entity tb_proc_control is
end tb_proc_control;
architecture tb of tb_proc_control is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal inst : std_logic_vector(7 downto 0);
signal force_sync : std_logic;
signal index_carry : std_logic := '1';
signal pc_carry : std_logic := '1';
signal branch_taken : boolean := true;
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal dummy_cycle : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal opcode : string(1 to 13);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_store_a_from_alu : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal adh, adl : std_logic_vector(7 downto 0) := X"00";
signal pch, pcl : std_logic_vector(7 downto 0) := X"11";
signal addr : std_logic_vector(15 downto 0);
signal sp : std_logic_vector(7 downto 0) := X"FF";
signal dreg : std_logic_vector(7 downto 0) := X"FF";
signal databus : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
mut: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => '0',
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
dummy_cycle => dummy_cycle,
latch_dreg => latch_dreg,
reg_update => reg_update,
copy_d2p => copy_d2p,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
clock <= not clock after 50 ns;
clock_en <= '1';
reset <= '1', '0' after 500 ns;
test: process
begin
inst <= X"00";
force_sync <= '0';
wait until reset='0';
for i in 0 to 255 loop
inst <= conv_std_logic_vector(i, 8);
wait until sync='1' for 2 us;
if sync='0' then
wait until clock='1';
force_sync <= '1';
wait until clock='1';
force_sync <= '0';
else
wait until sync='0';
end if;
end loop;
wait;
end process;
opcode <= opcode_array(conv_integer(i_reg));
process(clock)
begin
if rising_edge(clock) and clock_en='1' then
if latch_dreg='1' then
dreg <= databus;
end if;
if sync='1' or force_sync='1' then
i_reg <= databus;
end if;
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= databus;
when from_alu =>
pcl <= pcl + 40;
when others =>
null;
end case;
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl <= adl + 5;
when load_bus =>
adl <= databus;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= databus;
when others =>
null;
end case;
case s_oper is
when increment =>
sp <= sp + 1;
when decrement =>
sp <= sp - 1;
when others =>
null;
end case;
end if;
end process;
with a_mux select addr <=
X"FFFF" when 0,
adh & adl when 1,
X"01" & sp when 2,
pch & pcl when 3;
with dout_mux select dout <=
dreg when reg_d,
X"11" when reg_axy,
X"22" when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
X"33" when shift_res,
X"FF" when others;
databus <= inst when (sync='1' or force_sync='1') else X"D" & addr(3 downto 0);
end tb;
| gpl-3.0 |
KB777/1541UltimateII | fpga/zpu/vhdl_source/zpu_profiler.vhd | 5 | 4692 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zpu_profiler is
port (
clock : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(26 downto 0);
cpu_instr : in std_logic;
cpu_req : in std_logic;
cpu_write : in std_logic;
cpu_rack : in std_logic;
cpu_dack : in std_logic;
enable : in std_logic;
clear : in std_logic;
section : in std_logic_vector(3 downto 0);
match : in std_logic_vector(3 downto 0);
my_read : in std_logic;
my_rack : out std_logic;
my_dack : out std_logic;
rdata : out std_logic_vector(7 downto 0) );
end zpu_profiler;
architecture gideon of zpu_profiler is
type t_count_array is array (natural range <>) of unsigned(31 downto 0);
signal counters : t_count_array(0 to 7) := (others => (others => '0'));
signal emulation_access : std_logic;
signal io_access : std_logic;
signal instruction_access : std_logic;
signal other_access : std_logic;
signal writes : std_logic;
signal req_d : std_logic;
signal count_out : std_logic_vector(31 downto 0) := (others => '0');
signal cpu_address_d : std_logic_vector(1 downto 0);
signal section_d : std_logic_vector(section'range);
signal section_entry : std_logic;
signal section_match : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
emulation_access <= '0';
io_access <= '0';
instruction_access <= '0';
other_access <= '0';
writes <= '0';
section_entry <= '0';
section_match <= '0';
-- first, split time in different "enables" for the counters
if cpu_rack='1' then
if cpu_address(26 downto 10) = "00000000000000000" then
emulation_access <= '1';
elsif cpu_address(26)='1' then
io_access <= '1';
elsif cpu_instr = '1' then
instruction_access <= '1';
else
other_access <= '1';
end if;
if cpu_write = '1' then
writes <= '1';
end if;
end if;
section_d <= section;
if section = match and section_d /= match then
section_entry <= '1';
end if;
if section = match then
section_match <= '1';
end if;
-- now, count our stuff
if clear='1' then
counters <= (others => (others => '0'));
elsif enable='1' then
counters(0) <= counters(0) + 1;
if emulation_access = '1' then
counters(1) <= counters(1) + 1;
end if;
if io_access = '1' then
counters(2) <= counters(2) + 1;
end if;
if instruction_access = '1' then
counters(3) <= counters(3) + 1;
end if;
if other_access = '1' then
counters(4) <= counters(4) + 1;
end if;
if writes = '1' then
counters(5) <= counters(5) + 1;
end if;
if section_entry='1' then
counters(6) <= counters(6) + 1;
end if;
if section_match = '1' then
counters(7) <= counters(7) + 1;
end if;
end if;
-- output register (read)
if my_read='1' then
if cpu_address(1 downto 0)="00" then
count_out <= std_logic_vector(counters(to_integer(unsigned(cpu_address(4 downto 2)))));
end if;
end if;
cpu_address_d <= cpu_address(1 downto 0);
case cpu_address_d is
when "00" => rdata <= count_out(31 downto 24);
when "01" => rdata <= count_out(23 downto 16);
when "10" => rdata <= count_out(15 downto 8);
when others => rdata <= count_out(7 downto 0);
end case;
req_d <= my_read;
my_dack <= req_d;
end if;
end process;
my_rack <= my_read;
end gideon; | gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_sim/mblite_simu_cached.vhd | 2 | 4760 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_cached is
end entity;
architecture test of mblite_simu_cached is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mmem_o : dmem_out_type;
signal mmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_core: entity work.cached_mblite
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
mmem_o => mmem_o,
mmem_i => mmem_i,
irq_i => irq_i,
irq_o => irq_o );
-- IRQ generation @ 100 kHz (every 10 us)
process
begin
for i in 1 to 50 loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
wait;
end process;
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
mmem_i.dat_i <= (others => 'X');
if mmem_o.ena_o = '1' then
if mmem_o.adr_o(31 downto 25) = "0000000" then
if mmem_o.we_o = '1' then
for i in 0 to 3 loop
if mmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := mmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
mmem_i.dat_i <= memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if mmem_o.we_o = '1' then -- write
case mmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := mmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(mmem_o.adr_o) & " dropped";
end case;
else -- read
case mmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
mmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
mmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
mmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
mmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(mmem_o.adr_o) & " dropped";
mmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
mmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/c2n_record/vhdl_sim/c2n_record_tb.vhd | 5 | 3986 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/148/132/1
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity c2n_record_tb is
end c2n_record_tb;
architecture tb of c2n_record_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal phi2_tick : std_logic := '0';
signal c64_stopped : std_logic := '0';
signal c2n_motor : std_logic := '0';
signal c2n_sense : std_logic := '0';
signal c2n_read : std_logic := '0';
signal c2n_write : std_logic := '0';
type t_int_vec is array(natural range <>) of integer;
constant c_test_vector : t_int_vec := ( 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53,
100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
2000, 2010, 2020, 2030, 2040, 2041, 2042, 2043, 2044, 2045,
2046, 2046, 2046, 2047, 2047, 2047, 2047, 2047, 2047, 2048,
2048, 2048, 2048, 2048, 2048, 2050, 2060, 2070, 2080,
2090, 2090, 2090, 2090, 2090, 2090, 2090, 2090 );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.c2n_record
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
phi2_tick => phi2_tick,
c64_stopped => c64_stopped,
c2n_motor => c2n_motor,
c2n_sense => c2n_sense,
c2n_read => c2n_read,
c2n_write => c2n_write );
i_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
if count = 9 then
count := 0;
phi2_tick <= '1';
else
count := count + 1;
phi2_tick <= '0';
end if;
end if;
end process;
p_generate: process
begin
-- for i in 0 to 511 loop
-- wait for 3200 ns; -- 02
-- c2n_read <= '1', '0' after 600 ns;
-- end loop;
for i in c_test_vector'range loop
wait for c_test_vector(i) * 200 ns; -- 200 ns is one phi2_tick.
c2n_read <= '1', '0' after 600 ns;
end loop;
wait;
end process;
p_test: process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable received : integer := 0;
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"00", X"01"); -- enable rising edge recording
wait for 1 us;
c2n_sense <= '1';
wait for 1 us;
c2n_motor <= '1';
while true loop
io_read(io, X"00", data);
if data(7)='1' then
io_read(io, X"800", data);
report hstr(data);
received := received + 1;
if received = 50 then
wait for 10 us;
io_write(io, X"00", X"00"); -- disable
wait;
end if;
end if;
end loop;
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper_pkg.vhd | 5 | 3337 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package copper_pkg is
constant c_copper_command : unsigned(3 downto 0) := X"0";
constant c_copper_status : unsigned(3 downto 0) := X"1";
constant c_copper_measure_l : unsigned(3 downto 0) := X"2";
constant c_copper_measure_h : unsigned(3 downto 0) := X"3";
constant c_copper_framelen_l : unsigned(3 downto 0) := X"4";
constant c_copper_framelen_h : unsigned(3 downto 0) := X"5";
constant c_copper_break : unsigned(3 downto 0) := X"6";
constant c_copper_cmd_play : std_logic_vector(3 downto 0) := X"1"; -- starts program in ram
constant c_copper_cmd_record : std_logic_vector(3 downto 0) := X"2"; -- waits for sync, records all writes until next sync.
constant c_copcode_write_reg : std_logic_vector(7 downto 0) := X"00"; -- starting from 00-2F or so.. takes 1 argument
constant c_copcode_read_reg : std_logic_vector(7 downto 0) := X"40"; -- starting from 40-6F or so.. no arguments
constant c_copcode_wait_irq : std_logic_vector(7 downto 0) := X"81"; -- waits until falling edge of IRQn
constant c_copcode_wait_sync : std_logic_vector(7 downto 0) := X"82"; -- waits until sync pulse from timer
constant c_copcode_timer_clr : std_logic_vector(7 downto 0) := X"83"; -- clears timer
constant c_copcode_capture : std_logic_vector(7 downto 0) := X"84"; -- copies timer to measure register
constant c_copcode_wait_for : std_logic_vector(7 downto 0) := X"85"; -- takes a 1 byte argument
constant c_copcode_wait_until: std_logic_vector(7 downto 0) := X"86"; -- takes 2 bytes argument (wait until timer match)
constant c_copcode_repeat : std_logic_vector(7 downto 0) := X"87"; -- restart at program address 0.
constant c_copcode_end : std_logic_vector(7 downto 0) := X"88"; -- ends operation and return to idle
constant c_copcode_trigger_1 : std_logic_vector(7 downto 0) := X"89"; -- pulses on trigger_1 output
constant c_copcode_trigger_2 : std_logic_vector(7 downto 0) := X"8A"; -- pulses on trigger_1 output
type t_copper_control is record
command : std_logic_vector(3 downto 0);
frame_length : unsigned(15 downto 0);
stop : std_logic;
end record;
constant c_copper_control_init : t_copper_control := (
command => X"0",
frame_length => X"4D07", -- 313 lines of 63.. (is incorrect, is one line too long, but to init is fine!)
stop => '0' );
type t_copper_status is record
running : std_logic;
measured_time : unsigned(15 downto 0);
end record;
constant c_copper_status_init : t_copper_status := (
running => '0',
measured_time => X"FFFF" );
end package;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/simple_sram.vhd | 5 | 5597 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd | 4 | 1974 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_write : std_logic;
io_address : unsigned(15 downto 0); -- for late reads/writes
io_read : std_logic;
io_read_early : std_logic;
io_write : std_logic;
late_write : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_slot_resp is record
data : std_logic_vector(7 downto 0);
reg_output : std_logic;
irq : std_logic;
end record;
constant c_slot_req_init : t_slot_req := (
bus_address => X"0000",
bus_write => '0',
io_read_early => '0',
io_address => X"0000",
io_read => '0',
io_write => '0',
late_write => '0',
data => X"00" );
constant c_slot_resp_init : t_slot_resp := (
data => X"00",
reg_output => '0',
irq => '0' );
type t_slot_req_array is array(natural range <>) of t_slot_req;
type t_slot_resp_array is array(natural range <>) of t_slot_resp;
function or_reduce(ar: t_slot_resp_array) return t_slot_resp;
end package;
package body slot_bus_pkg is
function or_reduce(ar: t_slot_resp_array) return t_slot_resp is
variable ret : t_slot_resp;
begin
ret := c_slot_resp_init;
for i in ar'range loop
ret.reg_output := ret.reg_output or ar(i).reg_output;
if ar(i).reg_output='1' then
ret.data := ret.data or ar(i).data;
end if;
ret.irq := ret.irq or ar(i).irq;
end loop;
return ret;
end function or_reduce;
end package body;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/oc_pusher/vhdl_source/oc_pusher.vhd | 5 | 535 | library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/6502/vhdl_source/implied.vhd | 3 | 4764 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
enable : in std_logic;
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
d_in : in std_logic;
v_in : in std_logic;
reg_a : in std_logic_vector(7 downto 0);
reg_x : in std_logic_vector(7 downto 0);
reg_y : in std_logic_vector(7 downto 0);
reg_s : in std_logic_vector(7 downto 0);
c_out : out std_logic;
i_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
d_out : out std_logic;
v_out : out std_logic;
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end implied;
architecture gideon of implied is
type t_int4_array is array(natural range <>) of integer range 0 to 3;
-- ROMS for the upper (negative) implied instructions
constant reg_sel_rom : t_int4_array(0 to 15) := ( 2,0,2,1,1,0,1,1,2,0,2,1,1,3,1,1 ); -- 0=A, 1=X, 2=Y, 3=S
constant decr_rom : std_logic_vector(0 to 15) := "1000001000000000";
constant incr_rom : std_logic_vector(0 to 15) := "0011000000000000";
constant nz_flags : std_logic_vector(0 to 15) := "1111111010000100";
constant v_flag : std_logic_vector(0 to 15) := "0000000001000000";
constant d_flag : std_logic_vector(0 to 15) := "0000000000110000";
constant set_a_rom : std_logic_vector(0 to 15) := "0000100010000000";
constant set_x_rom : std_logic_vector(0 to 15) := "0001011000000100";
constant set_y_rom : std_logic_vector(0 to 15) := "1110000000000000";
constant set_s_rom : std_logic_vector(0 to 15) := "0000000000001000";
-- ROMS for the lower (positive) implied instructions
constant shft_rom : std_logic_vector(0 to 15) := "0000111100000000";
constant c_flag : std_logic_vector(0 to 15) := "0000000011000000";
constant i_flag : std_logic_vector(0 to 15) := "0000000000110000";
signal selected_reg : std_logic_vector(7 downto 0) := X"00";
signal operation : integer range 0 to 15;
signal reg_sel : integer range 0 to 3;
signal result : std_logic_vector(7 downto 0) := X"00";
signal add : std_logic_vector(7 downto 0) := X"00";
signal carry : std_logic := '0';
signal zero : std_logic := '0';
signal n_hi : std_logic;
signal z_hi : std_logic;
signal v_hi : std_logic;
signal d_hi : std_logic;
signal n_lo : std_logic;
signal z_lo : std_logic;
signal c_lo : std_logic;
signal i_lo : std_logic;
begin
operation <= conv_integer(inst(4) & inst(1) & inst(6 downto 5));
reg_sel <= reg_sel_rom(operation);
with reg_sel select selected_reg <=
reg_a when 0,
reg_x when 1,
reg_y when 2,
reg_s when others;
add <= (others => decr_rom(operation));
carry <= incr_rom(operation);
result <= selected_reg + add + carry;
zero <= '1' when result = X"00" else '0';
data_out <= result;
n_hi <= result(7) when nz_flags(operation)='1' else n_in;
z_hi <= zero when nz_flags(operation)='1' else z_in;
v_hi <= '0' when v_flag(operation)='1' else v_in;
d_hi <= inst(5) when d_flag(operation)='1' else d_in;
-- in high, C and I are never set
c_lo <= inst(5) when c_flag(operation)='1' else c_in;
i_lo <= inst(5) when i_flag(operation)='1' else i_in;
-- in low, V, N, Z and D are never set
set_a <= set_a_rom(operation) and inst(7) and enable;
set_x <= set_x_rom(operation) and inst(7) and enable;
set_y <= set_y_rom(operation) and inst(7) and enable;
set_s <= set_s_rom(operation) and inst(7) and enable;
c_out <= c_in when inst(7)='1' else c_lo; -- C can only be set in lo
i_out <= i_in when inst(7)='1' else i_lo; -- I can only be set in lo
v_out <= v_hi when inst(7)='1' else v_in; -- V can only be set in hi
d_out <= d_hi when inst(7)='1' else d_in; -- D can only be set in hi
n_out <= n_hi when inst(7)='1' else n_in; -- N can only be set in hi
z_out <= z_hi when inst(7)='1' else z_in; -- Z can only be set in hi
end gideon; | gpl-3.0 |
KB777/1541UltimateII | fpga/io/usb/vhdl_source/usb1_pkg.vhd | 2 | 10575 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb1_pkg is
type t_transaction_type is ( control, bulk, interrupt, isochronous );
type t_transaction_state is ( none, busy, done, error );
type t_pipe_state is ( invalid, initialized, stalled, aborted );
type t_direction is ( dir_in, dir_out );
type t_transfer_mode is ( direct, use_preamble, use_split );
type t_pipe is record
state : t_pipe_state;
direction : t_direction;
device_address : std_logic_vector(6 downto 0);
device_endpoint : std_logic_vector(3 downto 0);
max_transfer : unsigned(10 downto 0); -- could be encoded in less (3) bits (only 2^x)
data_toggle : std_logic;
control : std_logic; -- '1' if this pipe is treated as a control pipe
timeout : std_logic;
--transfer_mode : t_transfer_mode;
end record; -- 18 bits now with encoded max transfer, otherwise 26
type t_transaction is record
transaction_type : t_transaction_type;
state : t_transaction_state;
pipe_pointer : unsigned(4 downto 0); -- 32 pipes enough?
transfer_length : unsigned(10 downto 0); -- max 2K
buffer_address : unsigned(10 downto 0); -- 2K buffer
link_to_next : std_logic; -- when '1', no other events will take place (such as sof)
end record; -- 32 bits now
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe;
function t_pipe_to_data(i: t_pipe) return std_logic_vector;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction;
function t_transaction_to_data(i: t_transaction) return std_logic_vector;
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
constant c_cmd_get_status : std_logic_vector(3 downto 0) := X"1";
constant c_cmd_get_speed : std_logic_vector(3 downto 0) := X"2";
constant c_cmd_get_done : std_logic_vector(3 downto 0) := X"3";
constant c_cmd_do_reset_hs : std_logic_vector(3 downto 0) := X"4";
constant c_cmd_do_reset_fs : std_logic_vector(3 downto 0) := X"5";
constant c_cmd_disable_host : std_logic_vector(3 downto 0) := X"6";
constant c_cmd_abort : std_logic_vector(3 downto 0) := X"7";
constant c_cmd_sof_enable : std_logic_vector(3 downto 0) := X"8";
constant c_cmd_sof_disable : std_logic_vector(3 downto 0) := X"9";
constant c_cmd_set_gap : std_logic_vector(3 downto 0) := X"A";
constant c_cmd_set_busy : std_logic_vector(3 downto 0) := X"B";
constant c_cmd_clear_busy : std_logic_vector(3 downto 0) := X"C";
constant c_cmd_set_debug : std_logic_vector(3 downto 0) := X"D";
constant c_cmd_disable_scan : std_logic_vector(3 downto 0) := X"E";
constant c_cmd_enable_scan : std_logic_vector(3 downto 0) := X"F";
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector;
end package;
package body usb1_pkg is
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe is
variable ret : t_pipe;
begin
case i(1 downto 0) is
when "01" =>
ret.state := initialized;
when "10" =>
ret.state := stalled;
when "11" =>
ret.state := aborted;
when others =>
ret.state := invalid;
end case;
if i(2) = '1' then
ret.direction := dir_out;
else
ret.direction := dir_in;
end if;
ret.device_address := i(9 downto 3);
ret.device_endpoint := i(13 downto 10);
ret.max_transfer := unsigned(i(24 downto 14));
-- max_transfer(3 + to_integer(unsigned(i(16 downto 14)))) <= '1'; -- set one bit
ret.data_toggle := i(25);
ret.control := i(26);
ret.timeout := i(31);
-- case i(28 downto 27) is
-- when "00" =>
-- ret.transfer_mode := direct;
-- when "01" =>
-- ret.transfer_mode := use_preamble;
-- when "10" =>
-- ret.transfer_mode := use_split;
-- when others =>
-- ret.transfer_mode := direct;
-- end case;
return ret;
end function;
function t_pipe_to_data(i: t_pipe) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when initialized => ret(1 downto 0) := "01";
when stalled => ret(1 downto 0) := "10";
when aborted => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "00";
end case;
if i.direction = dir_out then
ret(2) := '1';
else
ret(2) := '0';
end if;
ret(9 downto 3) := i.device_address;
ret(13 downto 10) := i.device_endpoint;
ret(24 downto 14) := std_logic_vector(i.max_transfer);
ret(25) := i.data_toggle;
ret(26) := i.control;
ret(31) := i.timeout;
-- case i.transfer_mode is
-- when direct => ret(28 downto 27) := "00";
-- when use_preamble => ret(28 downto 27) := "01";
-- when use_split => ret(28 downto 27) := "10";
-- when others => ret(28 downto 27) := "00";
-- end case;
return ret;
end function;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction is
variable ret : t_transaction;
begin
case i(1 downto 0) is
when "00" => ret.state := none;
when "01" => ret.state := busy;
when "10" => ret.state := done;
when others => ret.state := error;
end case;
case i(3 downto 2) is
when "00" => ret.transaction_type := control;
when "01" => ret.transaction_type := bulk;
when "10" => ret.transaction_type := interrupt;
when others => ret.transaction_type := isochronous;
end case;
ret.pipe_pointer := unsigned(i(8 downto 4));
ret.transfer_length := unsigned(i(19 downto 9));
ret.buffer_address := unsigned(i(30 downto 20));
ret.link_to_next := i(31);
return ret;
end function;
function t_transaction_to_data(i: t_transaction) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when none => ret(1 downto 0) := "00";
when busy => ret(1 downto 0) := "01";
when done => ret(1 downto 0) := "10";
when error => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "11";
end case;
case i.transaction_type is
when control => ret(3 downto 2) := "00";
when bulk => ret(3 downto 2) := "01";
when interrupt => ret(3 downto 2) := "10";
when isochronous => ret(3 downto 2) := "11";
when others => ret(3 downto 2) := "11";
end case;
ret(8 downto 4) := std_logic_vector(i.pipe_pointer);
ret(19 downto 9) := std_logic_vector(i.transfer_length);
ret(30 downto 20):= std_logic_vector(i.buffer_address);
ret(31) := i.link_to_next;
return ret;
end function;
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_split => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused!
when others => return false;
end case;
return false;
end function;
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
case i is
when "00" =>
return X"46"; -- LS mode
when "01" =>
return X"45"; -- FS mode
when "10" =>
return X"40"; -- HS mode
when others =>
return X"50"; -- stay in chirp mode
end case;
return X"00";
end function;
end;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/dpram_rdw_byte.vhd | 5 | 2599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw_byte is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 32;
g_depth_bits : positive := 9;
g_init_file : string := "none";
g_storage : string := "block" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_byte_en : in std_logic_vector((g_width_bits/8)-1 downto 0) := (others => '1');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw_byte : entity is "yes";
end entity;
architecture xilinx of dpram_rdw_byte is
signal b_we_i : std_logic_vector(b_byte_en'range) := (others => '0');
begin
assert (g_width_bits mod 8) = 0
report "Width of ram with byte enables should be a multiple of 8."
severity failure;
b_we_i <= b_byte_en when b_we='1' else (others => '0');
r_byte: for i in b_we_i'range generate
i_byte_ram: entity work.dpram_rdw
generic map (
g_rdw_check => g_rdw_check,
g_width_bits => 8,
g_depth_bits => g_depth_bits,
g_init_value => X"00",
g_init_file => g_init_file,
g_init_width => (g_width_bits/8),
g_init_offset => i,
g_storage => g_storage )
port map (
clock => clock,
a_address => a_address,
a_rdata => a_rdata(8*i+7 downto 8*i),
a_en => a_en,
b_address => b_address,
b_rdata => b_rdata(8*i+7 downto 8*i),
b_wdata => b_wdata(8*i+7 downto 8*i),
b_en => b_en,
b_we => b_we_i(i) );
end generate;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/usb_io_bank.vhd | 5 | 8681 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_sim/tb_adsr.vhd | 5 | 1510 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_adsr is
end tb_adsr;
architecture tb of tb_adsr is
signal clk : std_logic := '0';
signal reset : std_logic;
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
signal env_out : std_logic_vector(7 downto 0);
signal env_state: std_logic_vector(1 downto 0);
begin
clk <= not clk after 500 ns;
mut: entity work.adsr
port map(
clk => clk,
reset => reset,
gate => gate,
attack => X"5",
decay => X"7",
sustain => X"A",
release => X"5",
env_state=> env_state,
env_out => env_out );
reset <= '1', '0' after 20 us;
process
begin
gate <= '0';
wait for 100 us;
gate <= '1';
wait for 150 ms;
gate <= '0';
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | fpga/6502/vhdl_source/pkg_6502_decode.vhd | 3 | 9508 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/mem4k.vhd | 5 | 2199 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrite : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
rack : out std_logic;
dack : out std_logic;
claimed : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of mem4k : entity is "yes";
end mem4k;
architecture gideon of mem4k is
subtype t_byte is std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of t_byte;
shared variable my_mem : t_byte_array(0 to 4095);
signal claimed_i : std_logic;
signal do_write : std_logic;
-- attribute ram_style : string;
-- attribute ram_style of my_mem : signal is "block";
begin
claimed_i <= '1' when address(26 downto 12) = "000000000000000"
else '0';
claimed <= claimed_i;
rack <= claimed_i and request;
do_write <= claimed_i and request and mwrite;
-- synthesis translate_off
model: if simulation generate
mram: entity work.bram_model_8sp
generic map("intram", 12) -- 4k
port map (
CLK => clock,
SSR => reset,
EN => request,
WE => do_write,
ADDR => address(11 downto 0),
DI => wdata,
DO => rdata );
end generate;
-- synthesis translate_on
process(clock)
begin
if rising_edge(clock) then
if do_write='1' then
my_mem(to_integer(unsigned(address(11 downto 0)))) := wdata;
end if;
if not simulation then
rdata <= my_mem(to_integer(unsigned(address(11 downto 0))));
else
rdata <= (others => 'Z');
end if;
dack <= claimed_i and request;
end if;
end process;
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/memory/vhdl_source/spram.vhd | 5 | 1660 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
address : in unsigned(g_depth_bits-1 downto 0);
rdata : out std_logic_vector(g_width_bits-1 downto 0);
wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
en : in std_logic := '1';
we : in std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of spram : entity is "yes";
end entity;
architecture xilinx of spram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_port: process(clock)
begin
if rising_edge(clock) then
if en = '1' then
if g_read_first then
rdata <= ram(to_integer(address));
end if;
if we = '1' then
ram(to_integer(address)) := wdata;
end if;
if not g_read_first then
rdata <= ram(to_integer(address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/adsr_multi.vhd | 5 | 8478 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sid_debug_pkg.all;
-- LUT: 195, FF:68
entity adsr_multi is
generic (
g_num_voices : integer := 8 );
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
gate : in std_logic;
attack : in std_logic_vector(3 downto 0);
decay : in std_logic_vector(3 downto 0);
sustain : in std_logic_vector(3 downto 0);
release : in std_logic_vector(3 downto 0);
env_state: out std_logic_vector(1 downto 0); -- for testing only
env_out : out unsigned(7 downto 0) );
end adsr_multi;
-- 158 1 62 .. FF
-- 45 2 35 .. 61
-- 26 4 1C .. 34
-- 13 8 0D .. 1B
-- 6 16 07 .. 0C
-- 7 30 00 .. 06
architecture gideon of adsr_multi is
type presc_array_t is array(natural range <>) of unsigned(15 downto 0);
constant prescalers : presc_array_t(0 to 15) := (
X"0008", X"001F", X"003E", X"005E",
X"0094", X"00DB", X"010A", X"0138",
X"0187", X"03D0", X"07A1", X"0C35",
X"0F42", X"2DC7", X"4C4B", X"7A12" );
signal enveloppe : unsigned(7 downto 0) := (others => '0');
signal state : unsigned(1 downto 0) := (others => '0');
constant st_release : unsigned(1 downto 0) := "00";
constant st_attack : unsigned(1 downto 0) := "01";
constant st_decay : unsigned(1 downto 0) := "11";
type state_array_t is array(natural range <>) of unsigned(29 downto 0);
signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_dbg : t_voice_debug_array(0 to g_num_voices-1);
begin
env_out <= enveloppe;
env_state <= std_logic_vector(state);
-- FF-5E 01
-- 5D-37 02
-- 36-1B 04
-- 1A-0F 08
-- 0E-07 10
-- 06-01 1E
process(clock)
function logarithmic(lev: unsigned(7 downto 0)) return unsigned is
variable res : unsigned(4 downto 0);
begin
if lev = X"00" then
res := "00000"; -- prescaler off
elsif lev < X"07" then
res := "11101"; -- 1E-1
elsif lev < X"0F" then
res := "01111"; -- 10-1
elsif lev < X"1B" then
res := "00111"; -- 08-1
elsif lev < X"37" then
res := "00011"; -- 04-1
elsif lev < X"5E" then
res := "00001"; -- 02-1
else
res := "00000"; -- 01-1
end if;
return res;
end function logarithmic;
variable presc_select : integer range 0 to 15;
variable cur_state : unsigned(1 downto 0);
variable cur_env : unsigned(7 downto 0);
variable cur_pre15 : unsigned(14 downto 0);
variable cur_pre5 : unsigned(4 downto 0);
variable next_state : unsigned(1 downto 0);
variable next_env : unsigned(7 downto 0);
variable next_pre15 : unsigned(14 downto 0);
variable next_pre5 : unsigned(4 downto 0);
variable presc_val : unsigned(14 downto 0);
variable log_div : unsigned(4 downto 0);
variable do_count_15 : std_logic;
variable do_count_5 : std_logic;
variable voice_x : integer;
begin
if rising_edge(clock) then
cur_state := state_array(0)(1 downto 0);
cur_env := state_array(0)(9 downto 2);
cur_pre15 := state_array(0)(24 downto 10);
cur_pre5 := state_array(0)(29 downto 25);
voice_o <= voice_i;
enable_o <= enable_i;
next_state := cur_state;
next_env := cur_env;
next_pre15 := cur_pre15;
next_pre5 := cur_pre5;
-- PRESCALER LOGIC, output: do_count --
-- 15 bit prescaler select --
case cur_state is
when st_attack =>
presc_select := to_integer(unsigned(attack));
when st_decay =>
presc_select := to_integer(unsigned(decay));
when others => -- includes release and idle
presc_select := to_integer(unsigned(release));
end case;
presc_val := prescalers(presc_select)(14 downto 0);
-- 15 bit prescaler counter --
do_count_15 := '0';
if cur_pre15 = presc_val then
next_pre15 := (others => '0');
do_count_15 := '1';
else
next_pre15 := cur_pre15 + 1;
end if;
-- 5 bit prescaler --
log_div := logarithmic(cur_env);
do_count_5 := '0';
if do_count_15='1' then
if (cur_state = st_attack) or cur_pre5 = log_div then
next_pre5 := "00000";
do_count_5 := '1';
else
next_pre5 := cur_pre5 + 1;
end if;
end if;
-- END PRESCALER LOGIC --
case cur_state is
when st_attack =>
if gate = '0' then
next_state := st_release;
elsif cur_env = X"FF" then
next_state := st_decay;
end if;
if do_count_15='1' then
next_env := cur_env + 1;
-- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!!
-- next_state := st_decay;
-- end if;
end if;
when st_decay =>
if gate = '0' then
next_state := st_release;
end if;
if do_count_15='1' and do_count_5='1' and
std_logic_vector(cur_env) /= (sustain & sustain) and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when st_release =>
if gate = '1' then
next_state := st_attack;
end if;
if do_count_15='1' and do_count_5='1' and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when others =>
next_state := st_release;
end case;
if enable_i='1' then
state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1);
state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state;
enveloppe <= next_env;
state <= next_state;
voice_x := to_integer(voice_i);
voice_dbg(voice_x).state <= next_state;
voice_dbg(voice_x).enveloppe <= next_env;
voice_dbg(voice_x).pre15 <= next_pre15;
voice_dbg(voice_x).pre5 <= next_pre5;
voice_dbg(voice_x).presc <= presc_val;
voice_dbg(voice_x).gate <= gate;
voice_dbg(voice_x).attack <= attack;
voice_dbg(voice_x).decay <= decay;
voice_dbg(voice_x).sustain <= sustain;
voice_dbg(voice_x).release <= release;
end if;
if reset='1' then
state <= "00";
enveloppe <= (others => '0');
enable_o <= '0';
end if;
end if;
end process;
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/std/dsram.vhd | 2 | 1759 | ----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.std_Pkg.all;
entity dsram is generic
(
WIDTH : positive := 32;
SIZE : positive := 8
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end dsram;
architecture arch of dsram is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of ram : signal is "auto";
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
if wre_i = '1' then
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
end if;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
| gpl-3.0 |
emabello42/FREAK-on-FPGA | embeddedretina_ise/RAM_MEMORY.vhd | 1 | 2560 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F9LRRL
-- /___/ /\ Timestamp : 04/06/2014 00:33:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity RAM_MEMORY is
port (
clk : IN std_logic;
address : IN std_logic_vector(31 downto 0);
read_en : IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
end RAM_MEMORY;
architecture BEHAVIORAL of PointBuffer is
signal sPointSet: T_POINT_SET := others => (others => '0'));
signal enables: std_logic_vector(N_POINTS-2 downto 0);
signal counter1: integer range 0 to N_POINTS*NUMBER_OF_SCALES-1 = 0;
signal counter2: integer range 0 to NUMBER_OF_SCALES-1 := 0;
component PointFifo
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputValue: out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
begin
pointFifo0: PointFifo
port map(
clk => clk,
enableIn => enableIn,
inputValue => inputValue,
rst => rst,
enableOut => enables(0),
outputValue => sPointSet(1)
);
genPointBuffer: for i in 1 to N_POINTS-2 generate
pointFifoX: PointFifo
port map(
clk => clk,
enableIn => enables(i-1),
inputValue => sPointSet(i),
rst => rst,
enableOut => enables(i),
outputValue => sPointSet(i+1)
);
end generate genPointBuffer;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter1 <= 0;
counter2 <= 0;
enableOut <= '0';
else
if enableIn = '1' then
sPointSet(0) <= inputValue;
if counter1 = N_POINTS*NUMBER_OF_SCALES-1 then
if counter2 = NUMBER_OF_SCALES-1 then
counter2 <= 0;
counter1 <= 0;
else
counter2 <= counter2+1;
end if;
enableOut <= '1';
else
counter1 <= counter1+1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
pointSet <= sPointSet;
end BEHAVIORAL;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_sim/char_generator_tb.vhd | 5 | 1699 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity char_generator_tb is
end;
architecture tb of char_generator_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req := c_io_req_init;
signal io_resp : t_io_resp;
signal h_sync : std_logic := '0';
signal v_sync : std_logic := '0';
signal pixel_active : std_logic;
signal pixel_data : std_logic;
begin
clock <= not clock after 35714 ps;
reset <= '1', '0' after 100 ns;
i_char_gen: entity work.char_generator
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
h_sync => h_sync,
v_sync => v_sync,
pixel_active => pixel_active,
pixel_data => pixel_data );
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_medium.vhdl | 5 | 50197 | ------------------------------------------------------------------------------
---- ----
---- ZPU Medium ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the medium size version. ----
---- Supports external memories. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- write_en_o - set to '1' for a single cycle to send off a write request.
-- data_o is valid only while write_en_o='1'.
-- read_en_o - set to '1' for a single cycle to send off a read request.
-- mem_busy_i - It is illegal to send off a read/write request when
-- mem_busy_i='1'.
-- Set to '0' when data_i is valid after a read request.
-- If it goes to '1'(busy), it is on the cycle after read/
-- write_en_o is '1'.
-- addr_o - address for read/write request
-- data_i - read data. Valid only on the cycle after mem_busy_i='0'
-- after read_en_o='1' for a single cycle.
-- data_o - data to write
-- break_o - set to '1' when CPU hits break instruction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end entity ZPUMediumCore;
architecture Behave of ZPUMediumCore is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W;
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):=
SP_START_1(ADDR_W-1 downto BYTE_BITS);
-- Update [SP+1]. We hold it in b_r, this writes the value to memory.
procedure FlushB(signal we : out std_logic;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS);
signal data : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
we <= '1';
addr <= inc_sp;
data <= b;
end procedure FlushB;
-- Do a simple stack push, it is performed in the internal cache registers,
-- not in the real memory.
procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : in unsigned(WORD_SIZE-1 downto 0);
signal b : out unsigned(WORD_SIZE-1 downto 0)) is
begin
b <= a; -- Update cache [SP+1]=[SP]
sp <= sp-1;
end procedure Push;
-- Do a simple stack pop, it is performed in the internal cache registers,
-- not in the real memory.
procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
a <= b; -- Update cache [SP]=[SP+1]
sp <= sp+1;
end procedure Pop;
-- Expand a PC value to WORD_SIZE
function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
variable nv : unsigned(WORD_SIZE-1 downto 0);
begin
nv:=(others => '0');
nv(ADDR_W-1 downto 0):=v;
return nv;
end function ExpandPC;
-- Program counter
signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
-- SP+1, SP+2 and SP-1 are very used, these are shortcuts
signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
-- a_r is a cache for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_r : unsigned(WORD_SIZE-1 downto 0);
-- b_r is a cache for the next value in the stack [SP+1]
signal b_r : unsigned(WORD_SIZE-1 downto 0);
signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal idim_r : std_logic;
signal write_en_r : std_logic;
signal read_en_r : std_logic;
signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0);
type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
st_fetch, st_execute, st_decode, st_decode2, st_resync,
st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2,
st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
st_binary_op_res, st_idle);
signal state : state_t:=st_resync;
-- Go to st_fetch state or just do its work
procedure DoFetch(constant FAST : boolean;
signal state : out state_t;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal pc : in unsigned(ADDR_W-1 downto 0);
signal re : out std_logic;
signal busy : in std_logic) is
begin
if FAST then
-- Equivalent to st_fetch
if busy='0' then
addr <= pc(ADDR_W-1 downto BYTE_BITS);
re <= '1';
state <= st_decode;
end if;
else
state <= st_fetch;
end if;
end procedure DoFetch;
-- Perform a "binary operation" (2 operands)
procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0);
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
begin
if DEPTH=2 then
-- 2 clocks: st_binary_op_res+st_binary_op_res2
state <= st_binary_op_res;
dest_p <= result;
elsif DEPTH=1 then
-- 1 clock: st_binary_op_res2
state <= st_binary_op_res2;
dest_p <= result;
else -- 0 clocks
re <= '1';
addr <= sp+2;
sp <= sp+1;
dest <= result;
state <= st_popped;
end if;
end procedure DoBinOp;
-- Perform a boolean "binary operation" (2 operands)
procedure DoBinOpBool(result : in boolean;
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
begin
if result then
res(0):='1';
end if;
DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
end procedure DoBinOpBool;
type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
dec_less_than, dec_less_than_or_equal, dec_lshr,
dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
dec_insn_fetch, dec_pop_down);
signal insn : insn_t;
type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
signal insns : insn_array_t;
type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
signal opcode_r : opcode_array_t;
begin
-- the memory subsystem will tell us one cycle later whether or
-- not it is busy
write_en_o <= write_en_r;
read_en_o <= read_en_r;
addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
addr_o(BYTE_BITS-1 downto 0) <= (others => '0');
-- SP+1 and +2
inc_sp <= sp_r+1;
inc_inc_sp <= sp_r+2;
opcode_control:
process (clk_i)
variable topcode : unsigned(OPCODE_W-1 downto 0);
variable ex_opcode : unsigned(OPCODE_W-1 downto 0);
variable sp_offset : unsigned(4 downto 0);
variable tsp_offset : unsigned(4 downto 0);
variable next_pc : unsigned(ADDR_W-1 downto 0);
variable tdecoded : insn_t;
variable tinsns : insn_array_t;
variable mult_res : unsigned(WORD_SIZE*2-1 downto 0);
variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r)
variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc)
variable h_bit : integer;
variable l_bit : integer;
variable not_lshr : std_logic:='1';
begin
if rising_edge(clk_i) then
break_o <= '0';
if reset_i='1' then
if ENA_IDLE then
state <= st_idle;
else
state <= st_resync;
end if;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
write_en_r <= '0';
read_en_r <= '0';
mult_a_r <= (others => '0');
mult_b_r <= (others => '0');
dbg_o.b_inst <= '0';
-- Reseting add_r here makes XST fail to use BRAMs ?!
else -- reset_i='1'
if MULT_PIPE then
-- We must multiply unconditionally to get pipelined multiplication
mult_res:=mult_a_r*mult_b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
mult_res2_r <= mult_res1_r;
mult_res3_r <= mult_res2_r;
mult_a_r <= (others => D_CARE_VAL);
mult_b_r <= (others => D_CARE_VAL);
end if;
if BINOP_PIPE=2 then
bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
end if;
read_en_r <='0';
write_en_r <='0';
-- Allow synthesis tools to load bogus values when we don't
-- care about the address and output data.
addr_r <= (others => D_CARE_VAL);
data_o <= (others => D_CARE_VAL);
if (write_en_r='1') and (read_en_r='1') then
report "read/write collision" severity failure;
end if;
ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
sp_offset(4):=not opcode_r(ipc_low)(4);
sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
next_pc:=pc_r+1;
-- Prepare trace snapshot
dbg_o.opcode <= opcode_r(ipc_low);
dbg_o.pc <= resize(pc_r,32);
dbg_o.stk_a <= resize(a_r,32);
dbg_o.stk_b <= resize(b_r,32);
dbg_o.b_inst <= '0';
dbg_o.sp <= (others => '0');
dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
case state is
when st_idle =>
if enable_i='1' then
state <= st_resync;
end if;
-- Initial state of ZPU, fetch top of stack (A/B) + first instruction
when st_resync =>
if mem_busy_i='0' then
addr_r <= sp_r;
read_en_r <= '1';
state <= st_resync2;
end if;
when st_resync2 =>
if mem_busy_i='0' then
a_r <= data_i;
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_resync3;
end if;
when st_resync3 =>
if mem_busy_i='0' then
b_r <= data_i;
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
when st_decode =>
if mem_busy_i='0' then
-- Here we latch the fetched word to give one full clock
-- cycle to the instruction decoder. This could be removed
-- if using BRAMs and the decoder delay isn't important.
fetched_w_r <= data_i;
state <= st_decode2;
end if;
when st_decode2 =>
-- decode 4 instructions in parallel
for i in 0 to WORD_BYTES-1 loop
topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
tsp_offset(4):=not topcode(4);
tsp_offset(3 downto 0):=topcode(3 downto 0);
opcode_r(i) <= topcode;
if topcode(7 downto 7)=OPCODE_IM then
tdecoded:=dec_im;
elsif topcode(7 downto 5)=OPCODE_STORESP then
if tsp_offset=0 then
-- Special case, we can avoid a write
tdecoded:=dec_pop;
elsif tsp_offset=1 then
-- Special case, collision
tdecoded:=dec_pop_down;
else
tdecoded:=dec_store_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_LOADSP then
if tsp_offset=0 then
tdecoded:=dec_dup;
elsif tsp_offset=1 then
tdecoded:=dec_dup_stk_b;
else
tdecoded:=dec_load_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_EMULATE then
tdecoded:=dec_emulate;
if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
tdecoded:=dec_neq_branch;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
tdecoded:=dec_eq;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
tdecoded:=dec_loadb;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
tdecoded:=dec_push_sp_add;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
tdecoded:=dec_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
tdecoded:=dec_u_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
tdecoded:=dec_mult;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
tdecoded:=dec_storeb;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
tdecoded:=dec_call_pc_rel;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
tdecoded:=dec_sub;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
tdecoded:=dec_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
tdecoded:=dec_u_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
tdecoded:=dec_call;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
tdecoded:=dec_pop_pc_rel;
elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
tdecoded:=dec_lshr;
end if;
elsif topcode(7 downto 4)=OPCODE_ADDSP then
if tsp_offset=0 then
tdecoded:=dec_shift;
elsif tsp_offset=1 then
tdecoded:=dec_add_top;
else
tdecoded:=dec_add_sp;
end if;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
tdecoded:=dec_break;
when OPCODE_PUSHSP =>
tdecoded:=dec_push_sp;
when OPCODE_POPPC =>
tdecoded:=dec_pop_pc;
when OPCODE_ADD =>
tdecoded:=dec_add;
when OPCODE_OR =>
tdecoded:=dec_or;
when OPCODE_AND =>
tdecoded:=dec_and;
when OPCODE_LOAD =>
tdecoded:=dec_load;
when OPCODE_NOT =>
tdecoded:=dec_not;
when OPCODE_FLIP =>
tdecoded:=dec_flip;
when OPCODE_STORE =>
tdecoded:=dec_store;
when OPCODE_POPSP =>
tdecoded:=dec_pop_sp;
when others => -- OPCODE_NOP and others
tdecoded:=dec_nop;
end case;
end if;
tinsns(i):=tdecoded;
end loop;
insn <= tinsns(ipc_low);
-- once we wrap, we need to fetch
tinsns(0):=dec_insn_fetch;
insns <= tinsns;
state <= st_execute;
-- Each instruction must:
--
-- 1. increase pc_r if applicable
-- 2. set next state if applicable
-- 3. do it's operation
when st_execute =>
-- Some shortcut to make the code readable:
inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
ex_opcode:=opcode_r(ipc_low);
insn <= insns(inpc_low);
-- Defaults used by most instructions
if insn/=dec_insn_fetch and insn/=dec_im then
dbg_o.b_inst <= '1';
idim_r <= '0';
end if;
case insn is
when dec_insn_fetch =>
-- Not a real instruction, fetch new instructions
DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
when dec_im =>
-- Push(immediate value), IDIM=1
-- if IDIM=0 Push(signed(opcode & 0x7F)) else
-- Push((Pop()<<7)|(opcode&0x7F))
if mem_busy_i='0' then
dbg_o.b_inst <= '1';
idim_r <= '1';
pc_r <= pc_r+1;
if idim_r='1' then
-- We already started an IM sequence
-- Shift left 7 bits
a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
-- Put the new value
a_r(6 downto 0) <= ex_opcode(6 downto 0);
else
-- First IM, push the value sign extended
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
Push(sp_r,a_r,b_r);
end if;
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
if mem_busy_i='0' then
write_en_r <= '1';
addr_r <= sp_r+sp_offset;
data_o <= a_r;
Pop(sp_r,a_r,b_r);
-- We need to fetch B
state <= st_store_sp2;
end if;
when dec_load_sp =>
-- Push([SP+Offset])
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
Push(sp_r,a_r,b_r);
-- We are flushing B cache, so we need more time to
-- read the value.
state <= st_load_sp2;
end if;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
Push(sp_r,a_r,b_r);
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= ex_opcode(4 downto 0);
end if;
when dec_call_pc_rel =>
-- t=Pop(), Push(PC+1), PC=PC+t
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= pc_r+a_r(ADDR_W-1 downto 0);
end if;
when dec_call =>
-- t=Pop(), Push(PC+1), PC=t
if mem_busy_i='0' and ENA_LEVEL2 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= a_r(ADDR_W-1 downto 0);
end if;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
if mem_busy_i='0' then
-- Read SP+Offset
state <= st_add_sp2;
read_en_r <= '1';
addr_r <= sp_r+sp_offset;
pc_r <= pc_r+1;
end if;
when dec_push_sp =>
-- Push(SP)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
Push(sp_r,a_r,b_r);
end if;
when dec_pop_pc =>
-- PC=Pop() (return)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0);
sp_r <= inc_sp;
end if;
when dec_pop_pc_rel =>
-- PC=PC+Pop()
if mem_busy_i='0' and ENA_LEVEL2 then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
sp_r <= inc_sp;
end if;
when dec_add =>
-- Push(Pop()+Pop()) [A=A+B, SP++, update B]
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r+b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_sub =>
-- a=Pop(), b=Pop(), Push(b-a)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_pop =>
-- Pop()
if mem_busy_i='0' then
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
Pop(sp_r,a_r,b_r);
end if;
when dec_pop_down =>
-- t=Pop(), Pop(), Push(t)
if mem_busy_i='0' then
-- PopDown leaves top of stack unchanged
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
sp_r <= inc_sp;
end if;
when dec_or =>
-- Push(Pop() or Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r or b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_and =>
-- Push(Pop() and Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r and b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_eq =>
-- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL0 then
DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than =>
-- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than_or_equal =>
-- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_less_than =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_less_than_or_equal =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_load =>
-- Push([Pop()])
if mem_busy_i='0' then
state <= st_load2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_dup =>
-- t=Pop(), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
-- A is dupped, no change
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_dup_stk_b =>
-- Pop(), t=Pop(), Push(t), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
a_r <= b_r;
-- B goes to A
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
if mem_busy_i='0' then
state <= st_resync;
pc_r <= pc_r+1;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= b_r;
write_en_r <= '1';
sp_r <= inc_inc_sp;
end if;
when dec_pop_sp =>
-- SP=Pop()
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= pc_r+1;
sp_r <= a_r(ADDR_W-1 downto BYTE_BITS);
end if;
when dec_nop =>
pc_r <= pc_r+1;
when dec_not =>
-- Push(not(Pop()))
pc_r <= pc_r+1;
a_r <= not a_r;
when dec_flip =>
-- Push(flip(Pop()))
pc_r <= pc_r+1;
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_r(WORD_SIZE-1-i);
end loop;
when dec_add_top =>
-- a=Pop(), b=Pop(), Push(b), Push(a+b)
pc_r <= pc_r+1;
a_r <= a_r+b_r;
when dec_shift =>
-- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
pc_r <= pc_r+1;
a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
a_r(0) <= '0';
when dec_push_sp_add =>
-- Push(Pop()+SP)
if ENA_LEVEL0 then
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <=
a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
end if;
when dec_neq_branch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
if ENA_LEVEL0 then
sp_r <= inc_inc_sp;
-- Need to fetch stack again.
state <= st_resync;
if b_r/=0 then
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
else
pc_r <= pc_r+1;
end if;
end if;
when dec_mult =>
-- Push(Pop()*Pop())
if ENA_LEVEL1 then
if MULT_PIPE then
mult_a_r <= a_r;
mult_b_r <= b_r;
state <= st_mult2;
else
mult_res:=a_r*b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
state <= st_mult5;
end if;
end if;
when dec_break =>
-- Assert the break_o signal
--report "Break instruction encountered" severity failure;
break_o <= '1';
pc_r <= pc_r+1;
when dec_loadb =>
-- Push([Pop()] & 0xFF) (byte address)
if mem_busy_i='0' and ENA_LEVEL0 then
state <= st_loadb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_storeb =>
-- [Pop()]=Pop() & 0xFF (byte address)
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_storeb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_lshr =>
-- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
if ENA_LSHR then
-- This instruction takes more than one cycle.
-- We must avoid duplications in the trace log.
dbg_o.b_inst <= not_lshr;
not_lshr:='0';
if a_r(5 downto 0)=0 then -- Only 6 bits used
-- No more shifts
if mem_busy_i='0' then
state <= st_popped;
a_r <= b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
not_lshr:='1';
end if;
else -- More shifts needed
b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
a_r(5 downto 0) <= a_r(5 downto 0)-1;
insn <= insn;
end if;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal decode instruction?!" severity failure;
--break_o <= '1';
end case;
-- The followup of operations that takes more than one execution clock
when st_store_sp2 =>
if mem_busy_i='0' then
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_popped;
end if;
when st_load_sp2 =>
if mem_busy_i='0' then
state <= st_load_sp3;
-- Now we can read SP+Offset (SP already decremented)
read_en_r <= '1';
addr_r <= sp_r+sp_offset+1;
end if;
when st_load_sp3 =>
if mem_busy_i='0' then
-- Note: We can't increment PC in the decode stage
-- because it will modify sp_offset.
pc_r <= pc_r+1;
-- Finally we have the result in A
state <= st_execute;
a_r <= data_i;
end if;
when st_add_sp2 =>
if mem_busy_i='0' then
state <= st_execute;
a_r <= a_r+data_i;
end if;
when st_load2 =>
if mem_busy_i='0' then
a_r <= data_i;
state <= st_execute;
end if;
when st_loadb2 =>
if mem_busy_i='0' then
a_r <= (others => '0');
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
a_r(7 downto 0) <= data_i(h_bit downto l_bit);
state <= st_execute;
end if;
when st_storeb2 =>
if mem_busy_i='0' then
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= data_i;
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
data_o(h_bit downto l_bit) <= b_r(7 downto 0);
write_en_r <= '1';
sp_r <= inc_inc_sp;
state <= st_resync;
end if;
when st_fetch =>
if mem_busy_i='0' then
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
-- The following states can be used to leave cycles free for
-- tools that can automagically decompose the multiplication
-- in various stages. Xilinx tools can do it to increase the
-- multipliers performance.
when st_mult2 =>
state <= st_mult3;
when st_mult3 =>
state <= st_mult4;
when st_mult4 =>
state <= st_mult5;
when st_mult5 =>
if mem_busy_i='0' then
if MULT_PIPE then
a_r <= mult_res3_r;
else
a_r <= mult_res1_r;
end if;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
end if;
when st_binary_op_res =>
-- BINOP_PIPE=2
state <= st_binary_op_res2;
when st_binary_op_res2 =>
-- BINOP_PIPE>=1
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
if BINOP_PIPE=2 then
a_r <= bin_op_res2_r;
else -- 1
a_r <= bin_op_res1_r;
end if;
when st_popped =>
if mem_busy_i='0' then
-- Note: Moving this PC++ to the decoder seems to
-- consume more LUTs.
pc_r <= pc_r+1;
b_r <= data_i;
state <= st_execute;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal state?!" severity failure;
--break_o <= '1';
end case; -- state
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: ZPUMediumCore
| gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE115/bus_tristate.vhd | 1 | 653 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY busTriState IS
PORT(
clk : in std_logic;
rst : in std_logic;
rw : in std_logic;
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
dq : inout std_logic_vector
);
END busTriState;
ARCHITECTURE main OF busTriState IS
BEGIN
PROCESS(clk, rst)
BEGIN
if (rst ='1') then
dq <= (others => 'Z');
elsif (rising_edge(clk)) then
if (rw = '1') then
dq <= d;
else
dq <= (others => 'Z');
q <= dq;
end if;
end if;
END PROCESS;
END main; | gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/lpm_ram_dq1.vhd | 3 | 7084 | -- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq1 IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq1;
ARCHITECTURE SYN OF lpm_ram_dq1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem2.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 14,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem2.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem2.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/CU.vhd | 3 | 1847 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY CU IS
PORT(
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
INMEM : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FRIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sM1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sM2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sM3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sM4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sM5 : OUT STD_LOGIC;
sM6 : OUT STD_LOGIC;
ULAOP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LoadFR : OUT STD_LOGIC;
LoadMAR : OUT STD_LOGIC;
LIDPC : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
LIDSP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
LoadMBR : OUT STD_LOGIC;
LoadREG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HALT_ACK : OUT STD_LOGIC;
DRAW : OUT STD_LOGIC;
RW : OUT STD_LOGIC
);
END CU;
ARCHITECTURE main OF CU IS
CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111";
TYPE STATES IS (fetch, decode, exec, halted);
SIGNAL IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL STATE : STATES;
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
STATE <= fetch;
DRAW <= '0';
RW <= '0';
IR <= x"0000";
LoadFR <= '0';
LoadMAR <= '0';
LIDPC <= "000";
LIDSP <= "100";
LoadMBR <= '0';
LoadREG <= x"00";
HALT_ACK <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE STATE IS
WHEN fetch =>
DRAW <= '0';
RW <= '0';
LoadFR <= '0';
LIDSP <= "000";
LoadREG <= x"00";
HALT_ACK <= '0';
sM1 <= "10";
LoadMBR <= '1';
IR <= INMEM;
LIDPC <= "010";
STATE <= decode;
WHEN decode =>
CASE IR(15 DOWNTO 10) IS
WHEN HALT =>
STATE <= halted;
WHEN OTHERS =>
END CASE;
WHEN exec =>
WHEN halted =>
HALT_ACK <= '1';
END CASE;
END IF;
END PROCESS;
END main; | gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/ASCII_CONV.vhd | 3 | 491 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ASCII_CONV IS
PORT( ASCII : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CMAP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ASCII_CONV;
ARCHITECTURE main OF ASCII_CONV IS
BEGIN
PROCESS(ASCII)
BEGIN
--IF(ASCII < x"20") THEN
-- CMAP <= "1011111";
--ELSE
-- CMAP <= ASCII(6 DOWNTO 0) - "0100000"; -- ASCII - 32
--END IF;
CMAP <= ASCII(6 DOWNTO 0);
END PROCESS;
END main; | gpl-3.0 |
markusC64/1541ultimate2 | fpga/devices/vhdl_source/amd_flash.vhd | 1 | 7167 | --------------------------------------------------------------------------------
-- Entity: amd_flash
-- Date:2018-08-12
-- Author: gideon
--
-- Description: Emulation of AMD flash, in this case 29F040 (512K)
-- This is a behavioral model of a Flash chip. It does not store the actual data
-- The 'allow_write' signal tells the client of this model to store the data
-- into the array. Erase functions will need to be performed by software to
-- modify the array accordingly. For this purpose, the erase byte can be polled
-- and cleared by software. A non-zero value indicates the sector that needs
-- to be erased. One bit for each sector. When 'FF' a chip-erase is requested.
-- In case of a pending erase, the rdata indicates whether the erase is done.
-- When rdata_valid is active, the client should forward the rdata from this
-- module, rather than the data from the array.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity amd_flash is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
allow_write : out std_logic;
-- flash bus
address : in unsigned(18 downto 0);
wdata : in std_logic_vector(7 downto 0);
write : in std_logic;
read : in std_logic;
rdata : out std_logic_vector(7 downto 0);
rdata_valid : out std_logic );
end entity;
architecture arch of amd_flash is
type t_state is (idle, prot1, prot2, program, erase1, erase2, erase3, erasing, suspend, auto_select);
signal state : t_state;
signal toggle : std_logic;
signal dirty : std_logic;
signal erase_sectors : std_logic_vector(7 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.read = '1' then
io_resp.ack <= '1';
if io_req.address(0) = '0' then
io_resp.data <= erase_sectors;
else
io_resp.data(0) <= dirty;
end if;
elsif io_req.write = '1' then
io_resp.ack <= '1';
erase_sectors <= X"00";
io_irq <= '0';
dirty <= '0';
end if;
if write = '1' then
if wdata = X"F0" then
allow_write <= '0';
state <= idle;
else
case state is
when idle =>
if address(14 downto 0) = "101010101010101" and wdata = X"AA" then
state <= prot1;
end if;
when prot1 =>
if address(14 downto 0) = "010101010101010" and wdata = X"55" then
state <= prot2;
else
state <= idle;
end if;
when prot2 =>
if address(14 downto 0) = "101010101010101" then
case wdata is
when X"90" =>
state <= auto_select;
when X"A0" =>
allow_write <= '1';
state <= program;
when X"80" =>
state <= erase1;
when others =>
state <= idle;
end case;
else
state <= idle;
end if;
when program =>
allow_write <= '0';
dirty <= '1';
state <= idle;
when erase1 =>
if address(14 downto 0) = "101010101010101" and wdata = X"AA" then
state <= erase2;
else
state <= idle;
end if;
when erase2 =>
if address(14 downto 0) = "010101010101010" and wdata = X"55" then
state <= erase3;
else
state <= idle;
end if;
when erase3 =>
if address(14 downto 0) = "101010101010101" and wdata = X"10" then
erase_sectors <= (others => '1');
state <= erasing;
io_irq <= '1';
elsif wdata = X"30" then
erase_sectors(to_integer(address(18 downto 16))) <= '1';
state <= erasing;
io_irq <= '1';
else
state <= idle;
end if;
when erasing =>
if wdata = X"B0" then
state <= suspend;
end if;
when suspend =>
if wdata = X"30" then
state <= erasing;
end if;
when others =>
null;
end case;
end if;
elsif read = '1' then
case state is
when idle | prot1 | prot2 | auto_select | erase1 | erase2 | erase3 =>
state <= idle;
toggle <= '0';
when erasing =>
toggle <= not toggle;
when others =>
null;
end case;
end if;
if state = erasing and erase_sectors = X"00" then
state <= idle;
end if;
if reset = '1' then
state <= idle;
allow_write <= '0';
erase_sectors <= (others => '0');
io_irq <= '0';
toggle <= '0';
dirty <= '0';
end if;
end if;
end process;
process(state, address, toggle)
begin
rdata_valid <= '0';
rdata <= X"00";
case state is
when erasing =>
rdata_valid <= '1';
rdata <= '0' & toggle & "000000";
when auto_select =>
rdata_valid <= '1';
if address(7 downto 0) = X"00" then
rdata <= X"01";
elsif address(7 downto 0) = X"01" then
rdata <= X"A4";
end if;
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/case1.vhd | 5 | 409 | entity case1 is
end entity;
architecture test of case1 is
begin
process is
variable x : integer;
begin
x := 5;
wait for 1 ns;
case x is
when 1 =>
assert false;
when 5 =>
report "five!";
when others =>
assert false;
end case;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/perf/tounsigned.vhd | 3 | 513 | entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s <= to_unsigned(j, WIDTH);
end loop;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/c1571_startup_tc.vhd | 1 | 11222 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity c1571_startup_tc is
end;
architecture tc of c1571_startup_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(15 downto 0) := X"1800";
constant c_wd177x_track : unsigned(15 downto 0) := X"1801";
constant c_wd177x_sector : unsigned(15 downto 0) := X"1802";
constant c_wd177x_datareg : unsigned(15 downto 0) := X"1803";
constant c_wd177x_status_clear : unsigned(15 downto 0) := X"1804";
constant c_wd177x_status_set : unsigned(15 downto 0) := X"1805";
constant c_wd177x_irq_ack : unsigned(15 downto 0) := X"1806";
constant c_wd177x_dma_mode : unsigned(15 downto 0) := X"1807";
constant c_wd177x_dma_addr : unsigned(15 downto 0) := X"1808"; -- DWORD
constant c_wd177x_dma_len : unsigned(15 downto 0) := X"180C"; -- WORD
constant c_param_ram : unsigned(15 downto 0) := X"1000";
begin
i_harness: entity work.harness_c1571
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
variable value : unsigned(31 downto 0);
variable params : std_logic_vector(31 downto 0);
variable rotation_speed : natural;
variable bit_time : natural;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1571-rom.310654-05.bin", dram, X"00008000");
-- load_memory("../../../roms/sounds.bin", dram, X"00000000");
load_memory("../../../disks/cpm.g71", dram, X"00100000" ); -- 1 MB offset
wait for 20 us;
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
rotation_speed := (31250000 / 20);
for i in 0 to 34 loop
value := unsigned(read_memory_32(dram, std_logic_vector(to_unsigned(16#100000# + 12 + i*8, 32))));
value := value + X"00100000";
params(15 downto 0) := read_memory_16(dram, std_logic_vector(value));
value := value + 2;
bit_time := rotation_speed / to_integer(unsigned(params(15 downto 0)));
params(31 downto 16) := std_logic_vector(to_unsigned(bit_time, 16));
report "Track " & integer'image(i+1) & ": " & hstr(value) & " - " & hstr(params);
io_write_32(io, c_param_ram + 16*i, std_logic_vector(value) );
io_write_32(io, c_param_ram + 16*i + 4, params );
io_write_32(io, c_param_ram + 16*i + 12, params );
end loop;
wait for 800 ms;
io_write(io, c_drvreg_inserted, X"01");
-- iec_drf(bfm);
-- iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
-- iec_send_atn(bfm, X"6F"); -- Open channel 15
-- iec_turnaround(bfm); -- start to listen
-- iec_get_message(bfm, msg);
-- iec_print_message(msg);
iec_send_atn(bfm, X"28"); -- Drive 8, Listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_send_message(bfm, "U0>M1"); -- 1571 Mode!
wait for 10 ms;
iec_send_atn(bfm, X"3F", true); -- UnListen
-- wait for 20 ms;
-- iec_drf(bfm);
-- iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
-- iec_send_atn(bfm, X"6F"); -- Open channel 15
-- iec_turnaround(bfm); -- start to listen
-- iec_get_message(bfm, msg);
-- iec_print_message(msg);
--
-- io_write(io, c_drvreg_inserted, X"01");
-- io_write(io, c_drvreg_diskchng, X"01");
wait for 1000 ms;
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_filter.vhd | 1 | 13356 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity sid_filter is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req := c_io_req_init;
io_resp : out t_io_resp;
filt_co : in unsigned(10 downto 0);
filt_res : in unsigned(3 downto 0);
valid_in : in std_logic := '0';
error_out : out std_logic;
input : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
valid_out : out std_logic );
end entity;
architecture dsvf of sid_filter is
signal filter_q : signed(17 downto 0);
signal filter_f : signed(17 downto 0);
signal input_sc : signed(21 downto 0);
signal filt_ram : std_logic_vector(15 downto 0);
signal xa : signed(17 downto 0);
signal xb : signed(17 downto 0);
signal sum_b : signed(21 downto 0);
signal sub_a : signed(21 downto 0);
signal sub_b : signed(21 downto 0);
signal x_reg : signed(21 downto 0) := (others => '0');
signal bp_reg : signed(21 downto 0);
signal hp_reg : signed(21 downto 0);
signal lp_reg : signed(21 downto 0);
signal temp_reg : signed(21 downto 0);
signal error : std_logic := '0';
signal program_counter : integer range 0 to 15;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
signal io_rdata : std_logic_vector(7 downto 0);
signal io_coef_en : std_logic;
signal io_coef_en_d : std_logic;
begin
-- Derive the actual 'f' and 'q' parameters
i_q_table: entity work.Q_table
port map (
Q_reg => filt_res,
filter_q => filter_q ); -- 2.16 format
-- I prefer to infer ram than to instantiate a vendor specific
-- block, but this is the fastest, as the sizes of the ports differ.
-- Secondly, a nice init value can be given, for as long as we don't connect
-- the IO bus.
i_filt_coef: RAMB16_S9_S18
generic map (
INIT_00 => X"0329032803280327032703260326032503240324032303230322032203210320",
INIT_01 => X"03320332033103300330032f032f032e032e032d032c032c032b032b032a032a",
INIT_02 => X"033b033b033a033a033903380338033703370336033603350334033403330333",
INIT_03 => X"034403440343034303420341034103400340033f033f033e033e033d033c033c",
INIT_04 => X"035603550354035303510350034f034e034d034c034b03490348034703460345",
INIT_05 => X"03680367036603650364036203610360035f035e035d035c035b035903580357",
INIT_06 => X"037a037903780377037603750374037203710370036f036e036d036c036a0369",
INIT_07 => X"038d038b038a038903880387038603850383038203810380037f037e037d037c",
INIT_08 => X"03b803b603b303b003ad03aa03a703a403a2039f039c0399039603930391038e",
INIT_09 => X"03e603e303e003dd03db03d803d503d203cf03cc03c903c703c403c103be03bb",
INIT_0A => X"04130411040e040b04080405040203ff03fd03fa03f703f403f103ee03ec03e9",
INIT_0B => X"0441043e043b0438043604330430042d042a042704240422041f041c04190416",
INIT_0C => X"04aa04a3049d0496048f04880481047a0474046d0466045f04580451044b0444",
INIT_0D => X"05170511050a050304fc04f504ee04e804e104da04d304cc04c504bf04b804b1",
INIT_0E => X"0585057e0577057005690562055c0555054e05470540053a0533052c0525051e",
INIT_0F => X"05f205eb05e405dd05d705d005c905c205bb05b405ae05a705a005990592058b",
INIT_10 => X"072c0717070306ee06da06c506b1069d06880674065f064b06360622060d05f9",
INIT_11 => X"0874085f084b08360822080d07f907e407d007bb07a70792077e076907550740",
INIT_12 => X"09bb09a70992097e096909550940092c0917090308ee08da08c508b1089c0888",
INIT_13 => X"0b030aee0ada0ac50ab10a9c0a880a740a5f0a4b0a360a220a0d09f909e409d0",
INIT_14 => X"0dd30da40d760d470d190cea0cbb0c8d0c5e0c2f0c010bd20ba30b750b460b17",
INIT_15 => X"10bd108f1060103210030fd40fa60f770f480f1a0eeb0ebc0e8e0e5f0e300e02",
INIT_16 => X"13a81379134b131c12ed12bf129012611233120411d511a711781149111b10ec",
INIT_17 => X"169216641635160615d815a9157a154c151d14ee14c0149114621434140513d7",
INIT_18 => X"1b6c1b1c1acc1a7d1a2d19dd198e193e18ee189f184f17ff17b01760171116c1",
INIT_19 => X"206620161fc71f771f271ed81e881e381de91d991d491cfa1caa1c5a1c0b1bbb",
INIT_1A => X"26b5264f25e92582251c24b5244f23e92382231c22b5224f21e92182211c20b5",
INIT_1B => X"2d1c2cb52c4f2be92b822b1c2ab52a4f29e92982291c28b5284f27e92782271c",
INIT_1C => X"34d8345a33dd336032e3326631e9316b30ee30712ff42f772efa2e7d2dff2d82",
INIT_1D => X"3caa3c2d3bb03b333ab53a3839bb393e38c1384437c7374936cc364f35d23555",
INIT_1E => X"467d45dd453e449f43ff436042c14222418240e340443fa43f053e663dc63d27",
INIT_1F => X"54b95381524851104fff4eee4ddd4ccc4c164b604aaa49f4493e488847d2471c",
INIT_20 => X"4ac84a3149994901486a47d2473a46a2460b457344db4444438e42d84222416b",
INIT_21 => X"54b55416537752d85238519950fa505a4fbb4f1c4e7d4ddd4d3e4c9f4bff4b60",
INIT_22 => X"5d555ccc5c445bbb5b335aaa5a2159995910588857ff577756ee566655dd5555",
INIT_23 => X"65dd655564cc644463bb633362aa62216199611060885fff5f775eee5e665ddd",
INIT_24 => X"6e106d8e6d0b6c886c056b826aff6a7c69fa697768f4687167ee676b66e96666",
INIT_25 => X"763e75bb753874b5743273b0732d72aa722771a47121709f701c6f996f166e93",
INIT_26 => X"7e6b7de87d667ce37c607bdd7b5a7ad77a5579d2794f78cc784977c6774476c1",
INIT_27 => X"8699861685938510848d840b83888305828281ff817c80fa80777ff47f717eee",
INIT_28 => X"8f718ee38e558dc68d388caa8c1c8b8d8aff8a7189e3895588c6883887aa871c",
INIT_29 => X"985597c6973896aa961c958d94ff947193e3935592c6923891aa911c908d8fff",
INIT_2A => X"a138a0aaa01c9f8d9eff9e719de39d559cc69c389baa9b1c9a8d99ff997198e3",
INIT_2B => X"aa1ca98da8ffa871a7e3a755a6c6a638a5aaa51ca48da3ffa371a2e3a255a1c6",
INIT_2C => X"b2ffb271b1e3b154b0c6b038afaaaf1cae8dadffad71ace3ac54abc6ab38aaaa",
INIT_2D => X"bbe3bb54bac6ba38b9aab91cb88db7ffb771b6e3b654b5c6b538b4aab41cb38d",
INIT_2E => X"c4c6c438c3aac31cc28dc1ffc171c0e3c054bfc6bf38beaabe1cbd8dbcffbc71",
INIT_2F => X"cdaacd1ccc8dcbffcb71cae3ca54c9c6c938c8aac81cc78dc6ffc671c5e3c554",
INIT_30 => X"d338d2e3d28dd238d1e3d18dd138d0e3d08dd038cfe3cf8dcf38cee3ce8dce38",
INIT_31 => X"d88dd838d7e3d78dd738d6e3d68dd638d5e3d58dd538d4e3d48dd438d3e3d38d",
INIT_32 => X"dde3dd8ddd38dce3dc8ddc38dbe3db8ddb38dae3da8dda38d9e3d98dd938d8e3",
INIT_33 => X"e338e2e3e28de238e1e3e18de138e0e3e08de038dfe3df8ddf38dee3de8dde38",
INIT_34 => X"e738e6f9e6bbe67ce63ee5ffe5c0e582e543e505e4c6e488e449e40ae3cce38d",
INIT_35 => X"eb21eae3eaa4ea65ea27e9e8e9aae96be92de8eee8afe871e832e7f4e7b5e777",
INIT_36 => X"ef0aeeccee8dee4fee10edd2ed93ed54ed16ecd7ec99ec5aec1bebddeb9eeb60",
INIT_37 => X"f2f4f2b5f276f238f1f9f1bbf17cf13ef0fff0c0f082f043f005efc6ef88ef49",
INIT_38 => X"f532f510f4eef4ccf4aaf488f465f443f421f3fff3ddf3bbf399f376f354f332",
INIT_39 => X"f754f732f710f6eef6ccf6aaf688f665f643f621f5fff5ddf5bbf599f576f554",
INIT_3A => X"f976f954f932f910f8eef8ccf8aaf888f865f843f821f7fff7ddf7bbf799f776",
INIT_3B => X"fb99fb76fb54fb32fb10faeefaccfaaafa88fa65fa43fa21f9fff9ddf9bbf999",
INIT_3C => X"fcbdfcacfc9afc89fc78fc67fc56fc44fc33fc22fc11fc00fbeefbddfbccfbbb",
INIT_3D => X"fdd0fdbffdaefd9cfd8bfd7afd69fd58fd46fd35fd24fd13fd02fcf0fcdffcce",
INIT_3E => X"fee3fed2fec1feb0fe9efe8dfe7cfe6bfe5afe48fe37fe26fe15fe04fdf2fde1",
INIT_3F => X"fff6ffe5ffd4ffc3ffb2ffa0ff8fff7eff6dff5cff4aff39ff28ff17ff06fef4" )
port map (
DOA => io_rdata,
DOPA => open,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
CLKA => clock,
DIA => io_req.data,
DIPA => "0",
ENA => io_coef_en,
SSRA => '0',
WEA => io_req.write,
DOB => filt_ram,
DOPB => open,
ADDRB => std_logic_vector(filt_co(10 downto 1)),
CLKB => clock,
DIB => X"0000",
DIPB => "00",
ENB => '1',
SSRB => '0',
WEB => '0' );
io_coef_en <= io_req.read or io_req.write;
io_coef_en_d <= io_coef_en when rising_edge(clock);
io_resp.ack <= io_coef_en_d;
io_resp.data <= X"00"; --io_rdata when io_coef_en_d = '1' else X"00";
process(clock)
begin
if rising_edge(clock) then
filter_f <= "00" & signed(filt_ram(15 downto 0));
end if;
end process;
--input_sc <= input;
input_sc <= shift_right(input, 1) & "0000";
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg(21 downto 4) when xb_select='0' else hp_reg (21 downto 4);
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(21 downto 0);
variable sub_result : signed(21 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 12);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
program_counter <= 0;
elsif valid_in = '1' then
program_counter <= 0;
else
if program_counter /= 15 then
program_counter <= program_counter + 1;
end if;
if program_counter < c_program'length then
instruction <= c_program(program_counter);
end if;
end if;
if program_counter = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg(21 downto 4);
band_pass <= bp_reg(21 downto 4);
low_pass <= lp_reg(21 downto 4);
error_out <= error;
end dsvf;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/cached_mblite.vhd | 1 | 3012 | library ieee;
use ieee.std_logic_1164.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
entity cached_mblite is
generic (
g_icache : boolean := true;
g_dcache : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
disable_i : in std_logic := '0';
disable_d : in std_logic := '0';
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
dmem_o : out dmem_out_type;
dmem_i : in dmem_in_type;
imem_o : out dmem_out_type;
imem_i : in dmem_in_type;
irq_i : in std_logic;
irq_o : out std_logic );
end entity;
architecture structural of cached_mblite is
-- signals from processor to cache
signal cimem_o : imem_out_type;
signal cimem_i : imem_in_type;
signal cdmem_o : dmem_out_type;
signal cdmem_i : dmem_in_type;
BEGIN
core0 : core
port map (
imem_o => cimem_o,
imem_i => cimem_i,
dmem_o => cdmem_o,
dmem_i => cdmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
r_icache: if g_icache generate
i_cache: entity work.dm_simple
generic map (
g_data_register => true,
g_mem_direct => true )
port map (
clock => clock,
reset => reset,
disable => disable_i,
dmem_i.adr_o => cimem_o.adr_o,
dmem_i.ena_o => cimem_o.ena_o,
dmem_i.sel_o => "0000",
dmem_i.we_o => '0',
dmem_i.dat_o => (others => '0'),
dmem_o.ena_i => cimem_i.ena_i,
dmem_o.dat_i => cimem_i.dat_i,
mem_o => imem_o,
mem_i => imem_i );
end generate;
r_no_icache: if not g_icache generate
imem_o.adr_o <= cimem_o.adr_o;
imem_o.ena_o <= cimem_o.ena_o;
imem_o.sel_o <= X"F";
imem_o.we_o <= '0';
imem_o.dat_o <= (others => '0');
cimem_i.dat_i <= imem_i.dat_i;
cimem_i.ena_i <= imem_i.ena_i;
end generate;
r_dcache: if g_dcache generate
d_cache: entity work.dm_with_invalidate
-- generic map (
-- g_data_register => true,
-- g_mem_direct => true )
port map (
clock => clock,
reset => reset,
disable => disable_d,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_i => cdmem_o,
dmem_o => cdmem_i,
mem_o => dmem_o,
mem_i => dmem_i );
end generate;
r_no_dcache: if not g_dcache generate
-- direct connection to outside world
dmem_o <= cdmem_o;
cdmem_i <= dmem_i;
end generate;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/sem/const.vhd | 5 | 1268 | entity e is
end entity;
architecture a of e is
constant x : integer := 5;
function f_pure(n : in integer) return integer is
begin
return n + 1;
end function;
impure function f_impure return integer is
begin
return x;
end function;
signal s : integer;
begin
process is
variable v : integer;
begin
v := x; -- OK
x := v; -- Error
end process;
process is
constant c : integer; -- Error
begin
end process;
process is
constant c : integer := f_pure(5); -- OK
begin
end process;
process is
constant c : integer := f_impure; -- OK (LRM 93 7.4.2 note 2)
begin
end process;
end architecture;
-------------------------------------------------------------------------------
package p is
constant c : integer; -- OK
constant d : integer;
constant e : integer := c + 1; -- OK
constant f : integer;
end package;
package body p is
constant c : integer := 6; -- OK
constant c : integer := 6; -- Error
constant f : bit := '1'; -- Error
-- Missing definition for d
end package body;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1541_pkg.vhd | 1 | 1221 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_sensor : unsigned(3 downto 0) := X"3";
constant c_drvreg_inserted : unsigned(3 downto 0) := X"4";
constant c_drvreg_rammap : unsigned(3 downto 0) := X"5";
constant c_drvreg_side : unsigned(3 downto 0) := X"6";
constant c_drvreg_man_write : unsigned(3 downto 0) := X"7";
constant c_drvreg_track : unsigned(3 downto 0) := X"8";
constant c_drvreg_status : unsigned(3 downto 0) := X"9";
constant c_drvreg_memmap : unsigned(3 downto 0) := X"A";
constant c_drvreg_audiomap : unsigned(3 downto 0) := X"B";
constant c_drvreg_diskchng : unsigned(3 downto 0) := X"C";
constant c_drvreg_drivetype : unsigned(3 downto 0) := X"D";
constant c_drvreg_sound : unsigned(3 downto 0) := X"E";
constant c_drv_dirty_base : unsigned(15 downto 0) := X"0800";
constant c_drv_param_base : unsigned(15 downto 0) := X"1000";
end;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/altera/testbench/mem_io_synth_tb.vhd | 1 | 2571 | --------------------------------------------------------------------------------
-- Entity: mem_io_synth
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_io_synth_tb is
generic (
g_out_delay : time := 8.5 ns;
g_in_delay : time := 2.0 ns );
end entity;
architecture arch of mem_io_synth_tb is
signal ref_clock : std_logic := '0';
signal ref_reset : std_logic;
signal SDRAM_CLK : std_logic := 'Z';
signal SDRAM_CLKn : std_logic := 'Z';
signal SDRAM_A : std_logic_vector(7 downto 0);
signal SDRAM_DQ : std_logic_vector(3 downto 0) := (others => 'Z');
signal SDRAM_DQS : std_logic;
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal do_read : std_logic;
signal delayed_clock : std_logic;
signal delayed_addr : std_logic_vector(7 downto 0);
begin
ref_clock <= not ref_clock after 10 ns; -- 20 ns cycle time
ref_reset <= '1', '0' after 100 ns;
i_mut: entity work.mem_io_synth
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
write_data => write_data,
read_data => read_data,
do_read => do_read
);
delayed_clock <= transport SDRAM_CLK after g_out_delay;
delayed_addr <= transport SDRAM_A after g_out_delay;
process(delayed_clock)
variable delay : integer := -10;
begin
if rising_edge(delayed_clock) then
if delayed_addr(7 downto 4) = "0110" then
delay := 7;
end if;
end if;
delay := delay - 1;
case delay is
when 0 =>
SDRAM_DQ <= transport X"2" after g_in_delay;
when -1 =>
SDRAM_DQ <= transport X"3" after g_in_delay;
when -2 =>
SDRAM_DQ <= transport X"4" after g_in_delay;
when -3 =>
SDRAM_DQ <= transport X"5" after g_in_delay;
when others =>
SDRAM_DQ <= transport "ZZZZ" after g_in_delay;
end case;
end process;
end arch;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/cpu6502.vhd | 1 | 1431 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_clk_en : in std_logic;
cpu_reset : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
attribute optimize : string;
attribute optimize of cpu6502 : entity is "SPEED";
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_clk_en,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/sigma_delta_dac/vhdl_source/sine_osc.vhd | 5 | 901 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sine_osc is
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
sine : out signed(15 downto 0);
cosine : out signed(15 downto 0) );
end sine_osc;
architecture gideon of sine_osc is
signal cos_i : signed(15 downto 0);
signal sin_i : signed(15 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
sin_i <= X"0000";
cos_i <= X"7FFF";
elsif enable='1' then
sin_i <= sum_limit(shift_right(cos_i, 8), sin_i);
cos_i <= sub_limit(cos_i, shift_right(sin_i, 8));
end if;
end if;
end process;
sine <= sin_i;
cosine <= cos_i;
end gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502/vhdl_sim/tb_implied_hi.vhd | 5 | 2448 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tb_implied_hi is
end tb_implied_hi;
architecture tb of tb_implied_hi is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal z_in : std_logic := 'Z';
signal d_in : std_logic := 'Z';
signal v_in : std_logic := 'Z';
signal reg_a : std_logic_vector(7 downto 0) := X"11";
signal reg_x : std_logic_vector(7 downto 0) := X"01";
signal reg_y : std_logic_vector(7 downto 0) := X"FF";
signal reg_s : std_logic_vector(7 downto 0) := X"44";
signal n_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal v_out : std_logic;
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal opcode : string(1 to 3);
type t_implied_opcode is array(0 to 15) of string(1 to 3);
constant implied_opcodes : t_implied_opcode := (
"DEY", "TAY", "INY", "INX",
"TXA", "TAX", "DEX", "NOP",
"TYA", "CLV", "CLD", "SED",
"TXS", "TSX", "---", "---" );
begin
mut: entity work.implied_hi
port map (
inst => inst,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => reg_a,
reg_x => reg_x,
reg_y => reg_y,
reg_s => reg_s,
n_out => n_out,
z_out => z_out,
d_out => d_out,
v_out => v_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => data_out );
test: process
variable inst_thumb : std_logic_vector(3 downto 0);
begin
for i in 0 to 15 loop
inst_thumb := conv_std_logic_vector(i, 4);
inst <= '1' & inst_thumb(1 downto 0) & inst_thumb(3) & "10" & inst_thumb(2) & '0';
opcode <= implied_opcodes(i);
wait for 1 us;
end loop;
wait;
end process;
end tb;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cia_registers.vhd | 1 | 30333 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cia_pkg.all;
-- synthesis translate_off
use work.tl_string_util_pkg.all;
-- synthesis translate_on
entity cia_registers is
generic (
g_unit_name : string := "6526";
g_report : boolean := false );
port (
clock : in std_logic;
falling : in std_logic;
reset : in std_logic;
addr : in unsigned(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
turbo_en : in std_logic := '0';
wait_state : out std_logic;
-- PLD interface
pld_inhibit : in std_logic := '0';
pld_write : out std_logic;
pld_wdata : out std_logic_vector(7 downto 0);
pld_waddr : out std_logic;
pld_state : out std_logic_vector(15 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- serial pin
sp_o : out std_logic;
sp_i : in std_logic;
sp_t : out std_logic;
cnt_i : in std_logic;
cnt_o : out std_logic;
cnt_t : out std_logic;
tod_pin : in std_logic;
pc_o : out std_logic;
flag_i : in std_logic;
irq : out std_logic );
end cia_registers;
architecture Gideon of cia_registers is
signal pio_i : pio_t := pio_default;
signal timer_a_i : timer_t := timer_default;
signal timer_b_i : timer_t := timer_default;
signal tod_i : tod_t;
signal tod_copy : time_t;
signal tod_latch : std_logic;
signal tod_stop : std_logic;
signal tod_tick : std_logic;
signal irq_mask : std_logic_vector(4 downto 0);
signal irq_mask_r : std_logic_vector(4 downto 0);
signal irq_flags_r : std_logic_vector(4 downto 0);
signal irq_flags : std_logic_vector(4 downto 0);
signal irq_events : std_logic_vector(4 downto 0);
signal irq_out : std_logic;
signal irq_bit : std_logic;
signal irq_ack : std_logic;
signal irq_ack_d : std_logic := '0';
signal timer_a_reg : std_logic_vector(15 downto 0);
signal timer_a_in : std_logic_vector(15 downto 0);
signal timer_b_reg : std_logic_vector(15 downto 0);
signal timer_b_in : std_logic_vector(15 downto 0);
alias timer_a_evnt : std_logic is irq_events(0);
alias timer_b_evnt : std_logic is irq_events(1);
alias alarm_event : std_logic is irq_events(2);
alias serial_event : std_logic is irq_events(3);
alias flag_event : std_logic is irq_events(4);
signal timer_a_count : std_logic_vector(15 downto 0);
signal timer_b_count : std_logic_vector(15 downto 0);
signal timer_a_out : std_logic;
signal timer_b_out : std_logic;
signal timer_a_stop : std_logic;
signal timer_b_stop : std_logic;
signal timer_a_set_t : std_logic;
signal timer_b_set_t : std_logic;
signal cnt_out : std_logic;
signal sp_out : std_logic;
signal sr_buffer : std_logic_vector(7 downto 0);
signal spmode : std_logic;
signal flag_c : std_logic;
signal flag_d1 : std_logic;
signal flag_d2 : std_logic;
signal flag_d3 : std_logic;
signal ICR : std_logic_vector(7 downto 0);
signal cycle : natural := 0;
signal icr_modify : std_logic := '0';
signal pld_write_i : std_logic;
signal pld_wdata_i : std_logic_vector(7 downto 0);
signal pld_waddr_i : std_logic;
begin
irq <= irq_out;
process(clock)
variable v_data_out : std_logic_vector(7 downto 0);
variable flag_event_pre : std_logic := '0';
begin
if rising_edge(clock) then
if tod_latch='1' then
tod_copy <= tod_i.tod;
end if;
-- synthesis translate_off
if falling = '1' then
cycle <= cycle + 1;
end if;
-- synthesis translate_on
-- Interrupt logic
if falling = '1' then
-- by default ICR is not being modified
icr_modify <= '0';
-- keeping the mask register
irq_mask_r <= irq_mask;
-- keeping the flags in a register
irq_flags_r <= irq_flags;
if irq_ack = '1' then
irq_flags_r <= (others => '0');
end if;
if irq_ack_d = '1' then
irq_flags_r(1) <= '0'; -- Timer B fix
end if;
-- the actual IRQ output
if irq_ack = '1' then
irq_out <= '0';
elsif (irq_flags and irq_mask) /= "00000" then
irq_out <= '1';
end if;
irq_ack_d <= irq_ack;
-- the IRQ bit (MSB of ICR)
if (irq_flags and irq_mask) /= "00000" then
irq_bit <= '1';
elsif irq_ack = '1' or irq_ack_d = '1' then
irq_bit <= '0';
end if;
end if;
-- Time Of Day
if tod_tick='1' and falling='1' then
do_tod_tick(tod_i.tod);
end if;
-- PC output --
if falling='1' then
pc_o <= '1';
timer_a_i.load <= '0';
timer_b_i.load <= '0';
timer_a_reg <= timer_a_in;
timer_b_reg <= timer_b_in;
end if;
if timer_a_stop = '1' then timer_a_i.run <= '0'; end if;
if timer_b_stop = '1' then timer_b_i.run <= '0'; end if;
-- Writes --
if falling = '1' then
wait_state <= '0';
end if;
if wen='1' and falling = '1' then
-- synthesis translate_off
assert not g_report
report "Writing |" & g_unit_name & "| Reg |" & hstr(addr) & "| in cycle |" & integer'image(cycle) & "| to |" & hstr(data_in)
severity note;
-- synthesis translate_on
case addr is
when X"0" => -- PRA
pio_i.pra <= data_in;
when X"1" => -- PRB
pio_i.prb <= data_in;
pc_o <= '0';
when X"2" => -- DDRA
pio_i.ddra <= data_in;
when X"3" => -- DDRB
pio_i.ddrb <= data_in;
when X"4" => -- TA LO
when X"5" => -- TA HI
if timer_a_i.run = '0' then
timer_a_i.load <= '1';
end if;
when X"6" => -- TB LO
when X"7" => -- TB HI
if timer_b_i.run = '0' then
timer_b_i.load <= '1';
end if;
when X"8" => -- TOD 10ths
if tod_i.alarm_set='1' then
tod_i.alarm.tenths <= unsigned(data_in(3 downto 0));
else
tod_i.tod.tenths <= unsigned(data_in(3 downto 0));
tod_stop <= '0';
end if;
when X"9" => -- TOD SEC
if tod_i.alarm_set='1' then
tod_i.alarm.sech <= unsigned(data_in(6 downto 4));
tod_i.alarm.secl <= unsigned(data_in(3 downto 0));
else
tod_i.tod.sech <= unsigned(data_in(6 downto 4));
tod_i.tod.secl <= unsigned(data_in(3 downto 0));
end if;
when X"A" => -- TOD MIN
if tod_i.alarm_set='1' then
tod_i.alarm.minh <= unsigned(data_in(6 downto 4));
tod_i.alarm.minl <= unsigned(data_in(3 downto 0));
else
tod_i.tod.minh <= unsigned(data_in(6 downto 4));
tod_i.tod.minl <= unsigned(data_in(3 downto 0));
end if;
when X"B" => -- TOD HR
if tod_i.alarm_set='1' then
tod_i.alarm.pm <= data_in(7);
tod_i.alarm.hr <= unsigned(data_in(4 downto 0));
else
tod_stop <= '1';
-- What an idiocracy!
if data_in(4 downto 0) = "10010" then
tod_i.tod.pm <= not data_in(7);
else
tod_i.tod.pm <= data_in(7);
end if;
tod_i.tod.hr <= unsigned(data_in(4 downto 0));
end if;
when X"C" => -- SDR
when X"D" => -- ICR
if data_in(7)='0' then -- clear immediately
irq_mask_r <= irq_mask and not data_in(4 downto 0);
elsif data_in(7)='1' then -- set
irq_mask_r <= irq_mask or data_in(4 downto 0);
end if;
icr_modify <= '1';
when X"E" => -- CRA
timer_a_i.run <= data_in(0); -- '1' = run, one-shot underrun clears this bit
timer_a_i.pbon <= data_in(1); -- '1' forces ouput to PB6
timer_a_i.outmode <= data_in(2); -- '1' = toggle, '0' = pulse
timer_a_i.runmode <= data_in(3); -- '1' = one shot, '0' = cont
timer_a_i.load <= data_in(4); -- pulse
timer_a_i.inmode <= '0' & data_in(5); -- '1' = CNT(r), '0' = PHI2
spmode <= data_in(6); -- '1' = output
tod_i.freq_sel <= data_in(7); -- '1' = 50 Hz
wait_state <= turbo_en;
when X"F" => -- CRB
timer_b_i.run <= data_in(0); -- '1' = run, one-shot underrun clears this bit
timer_b_i.pbon <= data_in(1); -- '1' forces ouput to PB6
timer_b_i.outmode <= data_in(2); -- '1' = toggle, '0' = pulse
timer_b_i.runmode <= data_in(3); -- '1' = one shot, '0' = cont
timer_b_i.load <= data_in(4); -- pulse
timer_b_i.inmode <= data_in(6 downto 5); -- '01' = CNT(r), '00' = PHI2
-- '10' = timer_a underflow, '11' = underflow with CNT=high
tod_i.alarm_set <= data_in(7); -- '1' = alarm set, '0' = time set
wait_state <= turbo_en;
when others =>
null;
end case;
end if;
-- Reads --
v_data_out := X"FF";
case addr is
when X"0" => -- PRA
v_data_out := port_a_i;
when X"1" => -- PRB
v_data_out := port_b_i;
if ren='1' and falling='1' then
pc_o <= '0';
end if;
when X"2" => -- DDRA
v_data_out := pio_i.ddra;
when X"3" => -- DDRB
v_data_out := pio_i.ddrb;
when X"4" => -- TA LO
v_data_out := timer_a_count(7 downto 0);
when X"5" => -- TA HI
v_data_out := timer_a_count(15 downto 8);
when X"6" => -- TB LO
v_data_out := timer_b_count(7 downto 0);
when X"7" => -- TB HI
v_data_out := timer_b_count(15 downto 8);
when X"8" => -- TOD 10ths
v_data_out := X"0" & std_logic_vector(tod_copy.tenths);
if ren='1' and falling='1' then
tod_latch <= '1';
end if;
when X"9" => -- TOD SEC
v_data_out := '0' & std_logic_vector(tod_copy.sech & tod_copy.secl);
when X"A" => -- TOD MIN
v_data_out := '0' & std_logic_vector(tod_copy.minh & tod_copy.minl);
when X"B" => -- TOD HR
v_data_out := tod_copy.pm & "00" & std_logic_vector(tod_copy.hr);
if ren='1' and falling = '1' then
tod_latch <= '0';
end if;
when X"C" => -- SDR
v_data_out := sr_buffer;
when X"D" => -- ICR
v_data_out := irq_bit & "00" & (irq_flags or irq_events);
when X"E" => -- CRA
v_data_out(0) := timer_a_i.run; -- '1' = run, one-shot underrun clears this bit
v_data_out(1) := timer_a_i.pbon ; -- '1' forces ouput to PB6
v_data_out(2) := timer_a_i.outmode; -- '1' = toggle, '0' = pulse
v_data_out(3) := timer_a_i.runmode; -- '1' = one shot, '0' = cont
v_data_out(4) := '0';
v_data_out(5) := timer_a_i.inmode(0); -- '1' = CNT(r), '0' = PHI2
v_data_out(6) := spmode; -- '1' = output
v_data_out(7) := tod_i.freq_sel ; -- '1' = 50 Hz
when X"F" => -- CRB
v_data_out(0) := timer_b_i.run; -- '1' = run, one-shot underrun clears this bit
v_data_out(1) := timer_b_i.pbon ; -- '1' forces ouput to PB7
v_data_out(2) := timer_b_i.outmode; -- '1' = toggle, '0' = pulse
v_data_out(3) := timer_b_i.runmode; -- '1' = one shot, '0' = cont
v_data_out(4) := '0';
v_data_out(6 downto 5) := timer_b_i.inmode ; -- '01' = CNT(r), '00' = PHI2
-- '10' = timer_a underflow, '11' = underflow with CNT=high
v_data_out(7) := tod_i.alarm_set ; -- '1' = alarm set, '0' = time set
when others =>
null;
end case;
data_out <= v_data_out;
-- synthesis translate_off
assert not (g_report and falling = '1' and ren = '1')
report "Reading |" & g_unit_name & "| Reg |" & hstr(addr) & "| in cycle |" & integer'image(cycle) & "| val|" & hstr(v_data_out)
severity note;
-- synthesis translate_on
flag_c <= flag_i; -- synchronization flop
flag_d1 <= flag_c; -- flop 2; output is stable
flag_d2 <= flag_d1; -- flop 3: for edge detection
flag_d3 <= flag_d2; -- flop 4: for filtering
if flag_d3 = '1' and flag_d2 = '0' and flag_d1 = '0' then -- falling edge, minimum of two clock cycles low
flag_event_pre := '1';
end if;
if falling = '1' then
flag_event <= flag_event_pre;
flag_event_pre := '0';
end if;
if reset='1' then
flag_c <= '1'; -- resets avoid shift register
flag_d1 <= '1'; -- resets avoid shift register
flag_d2 <= '1'; -- resets avoid shift register
flag_d3 <= '1'; -- resets avoid shift register
spmode <= '0';
pc_o <= '1';
tod_latch <= '1';
tod_stop <= '1';
pio_i <= pio_default;
tod_i <= tod_default;
timer_a_i <= timer_default;
timer_b_i <= timer_default;
irq_ack_d <= '0';
irq_mask_r <= (others => '0');
irq_flags_r <= (others => '0');
irq_out <= '0';
irq_bit <= '0';
flag_event <= '0';
timer_a_reg <= (others => '1');
timer_b_reg <= (others => '1');
wait_state <= '0';
end if;
end if;
end process;
-- PLD data output
--process(wen, falling, addr, data_in, pio_i)
process(clock)
begin
if rising_edge(clock) then
pld_write_i <= '0';
pld_wdata_i <= (others => '1');
pld_waddr_i <= '0';
if wen='1' and falling = '1' then
case addr is
when X"0" => -- PRA
pld_write_i <= '1';
pld_wdata_i <= data_in or not pio_i.ddra;
pld_waddr_i <= '0'; -- Port A
when X"1" => -- PRB
pld_write_i <= '1';
pld_wdata_i <= data_in or not pio_i.ddrb;
pld_waddr_i <= '1'; -- Port B
when X"2" => -- DDRA
pld_write_i <= '1';
pld_wdata_i <= pio_i.pra or not data_in;
pld_waddr_i <= '0'; -- Port A
when X"3" => -- DDRB
pld_write_i <= '1';
pld_wdata_i <= pio_i.prb or not data_in;
pld_waddr_i <= '1'; -- Port B
when others =>
null;
end case;
end if;
if reset = '1' then
pld_state <= X"FFFF";
elsif pld_write_i = '1' then
if pld_waddr_i = '0' then
pld_state(7 downto 0) <= pld_wdata_i;
else
pld_state(15 downto 8) <= pld_wdata_i;
end if;
end if;
end if;
end process;
pld_write <= pld_write_i and not pld_inhibit;
pld_wdata <= pld_wdata_i;
pld_waddr <= pld_waddr_i;
-- write through of ta
process(addr, wen, data_in, timer_a_reg)
begin
timer_a_in <= timer_a_reg;
if addr = X"4" and wen = '1' then
timer_a_in(7 downto 0) <= data_in;
end if;
if addr = X"5" and wen = '1' then
timer_a_in(15 downto 8) <= data_in;
end if;
end process;
-- write through of tb
process(addr, wen, data_in, timer_b_reg)
begin
timer_b_in <= timer_b_reg;
if addr = X"6" and wen = '1' then
timer_b_in(7 downto 0) <= data_in;
end if;
if addr = X"7" and wen = '1' then
timer_b_in(15 downto 8) <= data_in;
end if;
end process;
-- write through of irq_mask, if and only if icr_modify is true
process(addr, wen, data_in, irq_mask_r, icr_modify)
begin
irq_mask <= irq_mask_r;
if addr = X"D" and wen = '1' and icr_modify = '1' then
if data_in(7)='0' then -- clear immediately
irq_mask <= irq_mask_r and not data_in(4 downto 0);
elsif data_in(7)='1' then -- set
irq_mask <= irq_mask_r or data_in(4 downto 0);
end if;
end if;
end process;
irq_ack <= '1' when addr = X"D" and ren = '1' else '0';
irq_flags <= irq_flags_r or irq_events;
ICR <= irq_bit & "00" & irq_flags;
-- combinatoric signal that indicates that the timer is about to start. Needed to set toggle to '1'.
timer_a_set_t <= '1' when (addr = X"E" and data_in(0) = '1' and wen = '1' and timer_a_i.run = '0') else '0';
timer_b_set_t <= '1' when (addr = X"F" and data_in(0) = '1' and wen = '1' and timer_b_i.run = '0') else '0';
-- Implement tod pin synchronization, edge detect and programmable prescaler
-- In addition, implement alarm compare logic with edge detect for event generation
b_tod: block
signal tod_c, tod_d : std_logic := '0';
signal tod_pre : unsigned(2 downto 0);
signal alarm_equal : boolean;
signal alarm_equal_d: boolean;
begin
-- alarm --
alarm_equal <= (tod_i.alarm = tod_i.tod);
--alarm_event <= '1' when alarm_equal else '0';
p_tod: process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
tod_c <= tod_pin;
tod_d <= tod_c;
tod_tick <= '0';
if tod_stop = '0' then
if tod_c = '1' and tod_d = '0' then
-- if (tod_pre = "100" and tod_i.freq_sel='1') or
-- (tod_pre = "101" and tod_i.freq_sel='0') then
-- tod_pre <= "000";
-- tod_tick <= '1';
-- else
-- tod_pre <= tod_pre + 1;
-- end if;
if tod_pre = "000" then
tod_tick <='1';
tod_pre <= "10" & not tod_i.freq_sel;
else
tod_pre <= tod_pre - 1;
end if;
end if;
else
tod_pre <= "10" & not tod_i.freq_sel;
-- tod_pre <= "000";
end if;
-- alarm --
alarm_equal_d <= alarm_equal;
alarm_event <= '0';
if alarm_equal and not alarm_equal_d then
alarm_event <= '1';
end if;
end if;
if reset='1' then
tod_pre <= "000";
tod_tick <= '0';
alarm_event <= '0';
end if;
end if;
end process;
end block;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(5 downto 0) <= pio_i.prb(5 downto 0);
port_b_o(6) <= pio_i.prb(6) when timer_a_i.pbon='0' else timer_a_out;
port_b_o(7) <= pio_i.prb(7) when timer_b_i.pbon='0' else timer_b_out;
port_a_t <= pio_i.ddra;
port_b_t(5 downto 0) <= pio_i.ddrb(5 downto 0);
port_b_t(6) <= pio_i.ddrb(6) or timer_a_i.pbon;
port_b_t(7) <= pio_i.ddrb(7) or timer_b_i.pbon;
-- Timer A
tmr_a: entity work.cia_timer
port map (
clock => clock,
reset => reset,
prescale_en => falling,
timer_ctrl => timer_a_i,
timer_set_t => timer_a_set_t,
timer_in => timer_a_in,
cnt => cnt_i,
othr_tmr_ev => '0',
timer_out => timer_a_out,
timer_stop => timer_a_stop,
timer_event => timer_a_evnt,
timer_count => timer_a_count );
-- Timer B
tmr_b: entity work.cia_timer
port map (
clock => clock,
reset => reset,
prescale_en => falling,
timer_ctrl => timer_b_i,
timer_set_t => timer_b_set_t,
timer_in => timer_b_in,
cnt => cnt_i,
othr_tmr_ev => timer_a_evnt,
timer_out => timer_b_out,
timer_stop => timer_b_stop,
timer_event => timer_b_evnt,
timer_count => timer_b_count );
ser: block
signal bit_cnt : integer range 0 to 7;
signal sr_shift : std_logic_vector(7 downto 0);
signal transmitting : std_logic := '0';
signal cnt_d1, cnt_d2, cnt_c : std_logic;
signal spmode_d : std_logic;
signal sr_dav : std_logic;
signal timer_a_evnt_d1 : std_logic := '0';
signal timer_a_evnt_d2 : std_logic := '0';
signal transmit_event : std_logic := '0';
signal transmit_event_d1: std_logic := '0';
signal receive_event : std_logic := '0';
signal receive_event_d1 : std_logic := '0';
begin
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
cnt_c <= cnt_i;
cnt_d1 <= cnt_c;
cnt_d2 <= cnt_d1;
spmode_d <= spmode;
receive_event <= '0';
transmit_event <= '0';
timer_a_evnt_d1 <= timer_a_evnt and transmitting;
timer_a_evnt_d2 <= timer_a_evnt_d1;
if spmode = '1' then -- output
if timer_a_evnt_d2='1' then
cnt_out <= not cnt_out;
if cnt_out='1' then -- was '1' -> falling edge
sp_out <= sr_shift(7);
sr_shift <= sr_shift(6 downto 0) & '0';
if bit_cnt = 0 then
transmit_event <= '1';
end if;
else
if bit_cnt=0 then
if sr_dav='1' then
sr_dav <= '0';
bit_cnt <= 7;
sr_shift <= sr_buffer;
transmitting <= '1';
else
transmitting <= '0';
end if;
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
elsif sr_dav = '1' and transmitting = '0' then
sr_dav <= '0';
bit_cnt <= 7;
sr_shift <= sr_buffer;
transmitting <= '1';
end if;
else -- input mode
cnt_out <= '1';
if cnt_d2='0' and cnt_d1='1' then
sr_shift <= sr_shift(6 downto 0) & sp_i;
if bit_cnt = 0 then
bit_cnt <= 7;
receive_event <= '1';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if wen='1' and addr=X"C" then
sr_dav <= '1';
sr_buffer <= data_in;
elsif receive_event = '1' then
sr_buffer <= sr_shift;
-- elsif wen='1' and addr=X"E" then
-- if transmitting='1' and data_in(6)='0' and spmode='1' then -- switching to input while transmitting
-- sr_buffer <= not sr_shift; -- ?
-- end if;
end if;
-- when switching to read mode, we assume there are 8 bits coming
if spmode='0' and spmode_d='1' then
sr_dav <= '0';
bit_cnt <= 7;
transmitting <= '0';
end if;
transmit_event_d1 <= transmit_event;
--transmit_event_d2 <= transmit_event_d1;
receive_event_d1 <= receive_event;
--receive_event_d2 <= receive_event_d1;
end if;
if reset='1' then
cnt_out <= '1';
sp_out <= '0';
bit_cnt <= 7;
transmitting <= '0';
sr_dav <= '0';
sr_shift <= (others => '0');
sr_buffer <= (others => '0');
transmit_event <= '0';
transmit_event_d1 <= '0';
receive_event <= '0';
receive_event_d1 <= '0';
end if;
end if;
end process;
serial_event <= receive_event_d1 or transmit_event_d1 or
'0';
-- (spmode and not spmode_d and not sr_dav) or -- when switching to output, and there is no data in the buffer
-- (not spmode and spmode_d and transmitting); -- when switching to input, and we are still in the transmit state
end block ser;
-- open drain
cnt_o <= '0';
sp_o <= '0';
cnt_t <= spmode and not cnt_out;
sp_t <= spmode and not sp_out;
end Gideon;
| gpl-3.0 |
chiggs/nvc | test/regress/concat1.vhd | 5 | 696 | entity concat1 is
end entity;
architecture test of concat1 is
type int_array is array (integer range <>) of integer;
begin
-- See LRM 93 section 9.2.5
process is
variable x : int_array(1 to 5);
variable y : int_array(1 to 2);
variable z : int_array(1 to 3);
variable s : string(1 to 5);
begin
y := (1, 2);
z := (3, 4, 5);
x := y & z;
assert x = (1, 2, 3, 4, 5);
s := "ab" & "cde";
assert s = "abcde";
z := 0 & y;
assert z = (0, 1, 2);
z := y & 3;
assert z = (1, 2, 3);
y := 8 & 9;
assert y = (8, 9);
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/bounds6.vhd | 5 | 378 | entity bounds6 is
end entity;
architecture test of bounds6 is
begin
process is
variable i : integer;
variable c : character;
begin
i := 32;
wait for 1 ns;
c := character'val(i);
assert c = ' ';
i := 1517262;
wait for 1 ns;
c := character'val(i);
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/icap/vhdl_source/icap.vhd | 5 | 2989 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/issue109.vhd | 5 | 599 | package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pack.all;
architecture test of issue109 is
function func return integer is
variable r : integer;
begin
proc(r);
return r;
end function;
begin
process is
begin
assert func = 5;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/wait1.vhd | 5 | 343 | -- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/case3.vhd | 5 | 1231 | entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/lower/record6.vhd | 5 | 362 | entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
begin
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/rxtx_to_buf.vhd | 5 | 3347 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
ram_we : out std_logic;
ram_en : out std_logic;
transferred : out unsigned(10 downto 0);
-- Interface from RX
user_rx_valid : in std_logic;
user_rx_start : in std_logic;
user_rx_data : in std_logic_vector(7 downto 0);
user_rx_last : in std_logic;
-- Interface to TX
send_data : in std_logic;
last_addr : in unsigned(10 downto 0);
no_data : in std_logic := '0';
user_tx_data : out std_logic_vector(7 downto 0);
user_tx_last : out std_logic;
user_tx_next : in std_logic );
end entity;
architecture gideon of rxtx_to_buf is
signal ram_addr_i : unsigned(10 downto 0);
signal ram_en_r : std_logic;
type t_state is (idle, tx_1, tx_2, tx_3, rx);
signal state : t_state;
signal trx_end : std_logic;
begin
ram_en <= ram_en_r or user_rx_valid or user_tx_next;
ram_we <= user_rx_valid;
ram_wdata <= user_rx_data;
user_tx_data <= ram_rdata;
ram_addr <= std_logic_vector(ram_addr_i);
process(clock)
begin
if rising_edge(clock) then
ram_en_r <= '0';
trx_end <= '0';
if trx_end = '1' then
transferred <= ram_addr_i;
end if;
case state is
when idle =>
ram_addr_i <= (others => '0');
if send_data='1' and no_data='0' then
ram_en_r <= '1';
state <= tx_1;
elsif user_rx_start='1' then
if user_rx_valid='1' then
ram_addr_i <= ram_addr_i + 1;
end if;
state <= rx;
end if;
when tx_1 =>
ram_addr_i <= ram_addr_i + 1;
state <= tx_2;
when tx_2 =>
if user_tx_next='1' then
ram_addr_i <= ram_addr_i + 1;
if ram_addr_i = last_addr then
user_tx_last <= '1';
state <= tx_3;
end if;
end if;
when tx_3 =>
if user_tx_next='1' then
trx_end <= '1';
state <= idle;
user_tx_last <= '0';
end if;
when rx =>
if user_rx_valid='1' then
ram_addr_i <= ram_addr_i + 1;
end if;
if user_rx_last='1' then
trx_end <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
user_tx_last <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/elab/const1.vhd | 5 | 954 | entity pwm is
generic (
CLK_FREQ : real;
PWM_FREQ : real );
end entity;
architecture rtl of pwm is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
constant DIVIDE : integer := integer(CLK_FREQ / PWM_FREQ);
constant BITS : integer := log2(DIVIDE);
signal ctr_r : bit_vector(BITS - 1 downto 0) := (others => '0');
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
pwm_1: entity work.pwm
generic map (
CLK_FREQ => 24.0e6,
PWM_FREQ => 1.0e3 );
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/pkg_6502_decode.vhd | 1 | 11600 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
-- function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean;
type t_result_select is (alu, shift, impl, row0, none);
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C" and inst(4) = '0';
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 0)=X"8" or inst(3 downto 0)=X"A";
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000 => 00, 08, 20, 28, 40, 48, 60, 68
-- BRK,PHP,JSR,PLP,RTI,PHA,RTS,PLA
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7 downto 5)="100" then
if inst(2) = '1' or inst(0) = '1' then
return true;
end if;
end if;
return false;
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0--0101-
return (inst(7)='0' and inst(4 downto 1) = "0101");
-- -- 16, 1e
-- -- 1--0 10-- => 8[89AB], A[89AB], C[89AB], E[89AB]
-- if inst(7)='1' and inst(4 downto 2)="010" then
-- return false;
-- end if;
-- return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- if inst(7)='0' and inst(4 downto 1)="0101" then
-- return false;
-- end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied) (shift select by 'is_shift'!)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst) and not is_relative(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst = X"AB" then -- LAX #$
return "00"; -- special case
elsif inst(4 downto 1)="0101" and inst(7)='0' then -- 0xx0101x: 0A, 0B, 2A, 2B, 4A, 4B, 6A, 6B
return inst(1 downto 0); -- 10 or 11
end if;
return "01";
end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(to_integer(unsigned(inst(7 downto 4))));
return (row(to_integer(unsigned(inst(3 downto 0)))) = '1');
end function;
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select is
begin
-- special case for ANC/ALR
if inst = X"0B" or inst = X"2B" or inst = X"4B" then
return shift;
-- special case for LAS (value and flags are calculated in implied handler)
elsif inst = X"BB" then
return impl;
-- special case for ANE (value and flags are calculated in implied handler, using set A)
elsif inst = X"8B" then
return impl;
elsif is_store(inst) then
return none;
elsif inst(0) = '1' then
return alu;
elsif is_shift(inst) then
return shift;
elsif (inst(3 downto 0) = X"0" or inst(3 downto 0) = X"4" or inst(3 downto 0) = X"C") and inst(4)='0' then
return row0;
elsif is_implied(inst) then
return impl;
elsif inst(7 downto 5) = "101" then -- load
return shift;
end if;
return none;
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if is_implied(inst) then
return true;
end if;
if (inst(7)='0' or inst(6)='1') and inst(2 downto 0) = "110" then
return false;
end if;
-- 7 downto 5 = 000 001 010 011 110 111
-- 2 downto 0 = 110
-- should not be true for 06 26 46 66 C6 E6
-- should not be true for 16 36 56 76 D6 F6
-- should not be true for 0E 2E 4E 6E CE EE
-- should not be true for 1E 3E 5E 7E DE FE
if is_stack(inst) or is_relative(inst) then
return false;
end if;
return true;
end function;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic is
begin
-- may be optimized
if inst = X"0B" or inst = X"2B" then
return '1';
end if;
return '0';
end function;
end;
| gpl-3.0 |
chiggs/nvc | test/lower/rectype.vhd | 4 | 430 | package rectype is
type r1 is record
x : integer;
end record;
end package;
entity e is
end entity;
use work.rectype.all;
architecture a of e is
type r2 is record
x : r1;
end record;
signal s : r2;
begin
process is
type r3 is record
x : r2;
end record;
variable v : r3;
begin
v.x := s;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/issue194.vhd | 5 | 547 | package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/issue116.vhd | 5 | 581 | entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
| gpl-3.0 |
chiggs/nvc | test/sem/protected.vhd | 1 | 3265 | entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/logic_analyzer.vhd | 5 | 5134 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
| gpl-3.0 |
chiggs/nvc | test/sem/issue53.vhd | 5 | 175 | entity c is
port (i : in bit);
begin
assert (i = '0') report "not '0'" severity note; -- OK
assert (i = '1') report "not '1'" severity note; -- OK
end entity c;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v5.vhd | 2 | 2988 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v5 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
DISK_ACTn : out std_logic );
end fpga_mem_test_v5;
architecture tb of fpga_mem_test_v5 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_req_32 := c_mem_req_32_init;
signal resp : t_mem_resp_32;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_v5
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
inhibit => inhibit,
run => MOTOR_LEDn,
okay => okay );
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
DISK_ACTn <= not okay;
end;
| gpl-3.0 |
chiggs/nvc | test/regress/elab3.vhd | 5 | 824 | entity sub is
end entity;
architecture test of sub is
signal p : integer;
begin
process is
begin
wait for 2 ns;
report p'instance_name;
report p'path_name;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab3 is
end entity;
architecture test of elab3 is
signal x : integer;
begin
s: entity work.sub;
b: block is
signal y : integer;
begin
process is
begin
wait for 1 ns;
report y'instance_name;
report y'path_name;
wait;
end process;
end block;
process is
begin
report x'instance_name;
report x'path_name;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/sampler/vhdl_source/sampler_accu.vhd | 5 | 2960 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.my_math_pkg.all;
entity sampler_accu is
port (
clock : in std_logic;
reset : in std_logic;
first_chan : in std_logic;
sample_in : in signed(15 downto 0);
volume_in : in unsigned(5 downto 0);
pan_in : in unsigned(3 downto 0);
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler_accu is
-- L R
-- 0000 = left 111 000
-- 0001 111 001
-- 0010 111 010
-- ...
-- 0111 = mid 111 111
-- 1000 = mid 111 111
-- ...
-- 1101 010 111
-- 1110 001 111
-- 1111 = right 000 111
signal pan_factor_L : signed(3 downto 0);
signal pan_factor_R : signed(3 downto 0);
signal sample_scaled : signed(16 downto 0);
signal first_scaled : std_logic;
signal accu_L : signed(20 downto 0);
signal accu_R : signed(20 downto 0);
signal current_L : signed(20 downto 0);
signal current_R : signed(20 downto 0);
attribute mult_style : string;
attribute mult_style of current_L : signal is "lut";
attribute mult_style of current_R : signal is "lut";
begin
--pan_factor_L <= "01000" when pan_in(3)='0' else "00" & signed(not(pan_in(2 downto 0)));
--pan_factor_R <= "01000" when pan_in(3)='1' else "00" & signed( pan_in(2 downto 0));
current_L <= sample_scaled * pan_factor_L;
current_R <= sample_scaled * pan_factor_R;
process(clock)
variable temp : signed(22 downto 0);
begin
if rising_edge(clock) then
-- stage 1
temp := sample_in * ('0' & signed(volume_in));
sample_scaled <= temp(21 downto 5);
first_scaled <= first_chan;
if pan_in(3)='0' then -- mostly left
pan_factor_L <= "0111";
pan_factor_R <= "0" & signed(pan_in(2 downto 0));
else -- mostly right
pan_factor_L <= "0" & signed(not pan_in(2 downto 0));
pan_factor_R <= "0111";
end if;
-- stage 2
if first_scaled='1' then
sample_L <= accu_L(accu_L'high downto accu_L'high-17);
sample_R <= accu_R(accu_R'high downto accu_R'high-17);
new_sample <= '1';
accu_L <= current_L;
accu_R <= current_R;
else
new_sample <= '0';
accu_L <= sum_limit(accu_L, current_L);
accu_R <= sum_limit(accu_R, current_R);
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/bounds/issue36.vhd | 5 | 441 | entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA, W);
end function fA;
begin
assert (fA(0) = 0) report "should not assert" severity failure;
end entity bounds18;
| gpl-3.0 |
jresendiz27/electronica | arquitectura/sumadorNBits/acarreoCascada/sumadorAcarreoCascada.vhdl | 2 | 641 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Prueba is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Prueba;
architecture A_Prueba of Prueba is
signal eb : std_logic_vector (3 downto 0);
signal c : std_logic_vector (4 downto 0);
begin
c(0) <= op;
sumador : for i in 0 to 3 generate
EB(i) <= B(i) xor OP;
S(i) <= A(i) xor EB(i) xor C(i);
C(i+1) <= (EB(i) and C(i)) or (A(i) and C(i)) or(A(i) and EB(i));
end generate;
cout <= c(4);
end A_Prueba;
| gpl-3.0 |
chiggs/nvc | test/regress/operator5.vhd | 5 | 819 | package pack is
type int_vec2 is array (integer range <>) of integer;
type int_vec is array (integer range <>) of integer;
function "<"(a, b : int_vec) return boolean;
end package;
package body pack is
function "<"(a, b : int_vec) return boolean is
begin
return false;
end function;
end package body;
entity operator5 is
end entity;
use work.pack.all;
architecture test of operator5 is
function ">="(a, b : int_vec) return boolean is
begin
return false;
end function;
begin
process is
variable x, y : int_vec(1 to 3);
begin
x := (1, 2, 3);
y := (4, 5, 6);
assert not (y >= x);
assert (int_vec2(y) >= int_vec2(x));
assert not (y < x) and not (x < y);
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_sim/rmii_transceiver_tb.vhd | 1 | 4041 | -------------------------------------------------------------------------------
-- Title : rmii_transceiver_tb
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Testbench for rmii transceiver
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity rmii_transceiver_tb is
end entity;
architecture testcase of rmii_transceiver_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
test: process
variable i : natural;
begin
eth_tx_data <= X"00";
eth_tx_sof <= '0';
eth_tx_eof <= '0';
eth_tx_valid <= '0';
ten_meg_mode <= '0';
wait until reset = '0';
wait until clock = '1';
i := 0;
L1: loop
wait until clock = '1';
if eth_tx_valid = '0' or eth_tx_ready = '1' then
if eth_tx_eof = '1' then
eth_tx_valid <= '0';
eth_tx_data <= X"00";
exit L1;
else
eth_tx_data <= c_frame_with_crc(i);
eth_tx_valid <= '1';
if i = c_frame_with_crc'left then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if i = c_frame_with_crc'right then
eth_tx_eof <= '1';
else
eth_tx_eof <= '0';
end if;
i := i + 1;
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/ip/connector/vhdl_source/connector.vhd | 1 | 1573 | --------------------------------------------------------------------------------
-- Entity: connector
-- Date:2018-08-05
-- Author: gideon
--
-- Description: This simple module connects two tristate "TTL" buffers
-- This module does not allow external drivers to the net.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity connector is
generic (
g_usedbus : boolean := true;
g_width : natural := 8 );
port (
a_o : in std_logic_vector(g_width-1 downto 0);
a_t : in std_logic_vector(g_width-1 downto 0);
a_i : out std_logic_vector(g_width-1 downto 0);
dbus : in std_logic_vector(g_width-1 downto 0) := (others => '1');
b_o : in std_logic_vector(g_width-1 downto 0);
b_t : in std_logic_vector(g_width-1 downto 0);
b_i : out std_logic_vector(g_width-1 downto 0);
connect : in std_logic );
end entity;
architecture arch of connector is
begin
process(a_o, a_t, b_o, b_t, connect, dbus)
begin
if connect = '0' then
if g_usedbus then
a_i <= dbus;
else
a_i <= a_o or not a_t;
end if;
b_i <= b_o or not b_t;
else -- connected
-- '0' when a_o = '0' and a_t = '1', or b_o = '0' and b_t = '1'
a_i <= not ((not a_o and a_t) or (not b_o and b_t));
b_i <= not ((not a_o and a_t) or (not b_o and b_t));
end if;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/parse/arch.vhd | 4 | 187 | architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
| gpl-3.0 |
chiggs/nvc | test/regress/generic1.vhd | 5 | 641 | entity bot is
generic ( constant N : integer );
port ( x : out integer );
end entity;
architecture test of bot is
begin
x <= N;
end architecture;
-------------------------------------------------------------------------------
entity generic1 is
end entity;
architecture test of generic1 is
signal xa, xb : integer;
begin
a: entity work.bot
generic map ( 5 )
port map ( xa );
b: entity work.bot
generic map ( 7 )
port map ( xb );
process is
begin
wait for 1 ns;
assert xa = 5;
assert xb = 7;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/perf/arraycase.vhd | 5 | 1448 | entity arraycase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of arraycase is
constant LOOPS : integer := 100;
begin
process is
variable vec : unsigned(15 downto 0) := (others => '0');
variable a, b, c, d, e, f : natural;
begin
for l in 1 to LOOPS loop
for i in 0 to integer'((2 ** 16) - 1) loop
vec := vec + X"0001";
case vec is
when X"0005" | X"ac3d" | X"9141" | X"2562" | X"0001" =>
a := a + 1;
when X"5101" | X"bbbb" | X"cccc" | X"dddd" =>
b := b + 1;
when X"0000" | X"ffff" =>
c := c + 1;
when X"2510" | X"1510" | X"babc" | X"aaad" | X"1591" =>
d := d + 1;
when X"9151" | X"abfd" | X"ab41" =>
e := e + 1;
when X"1111" | X"9150" =>
f := f + 1;
when others =>
null;
end case;
wait for 1 ns;
end loop;
end loop;
report integer'image(a) & " " & integer'image(b) & " "
& integer'image(c) & " " & integer'image(d) & " "
& integer'image(e) & " " & integer'image(f);
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/mm_startup_1571_tc.vhd | 1 | 10965 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity mm_startup_1571_tc is
end;
architecture tc of mm_startup_1571_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(15 downto 0) := X"1800";
constant c_wd177x_track : unsigned(15 downto 0) := X"1801";
constant c_wd177x_sector : unsigned(15 downto 0) := X"1802";
constant c_wd177x_datareg : unsigned(15 downto 0) := X"1803";
constant c_wd177x_status_clear : unsigned(15 downto 0) := X"1804";
constant c_wd177x_status_set : unsigned(15 downto 0) := X"1805";
constant c_wd177x_irq_ack : unsigned(15 downto 0) := X"1806";
constant c_wd177x_dma_mode : unsigned(15 downto 0) := X"1807";
constant c_wd177x_dma_addr : unsigned(15 downto 0) := X"1808"; -- DWORD
constant c_wd177x_dma_len : unsigned(15 downto 0) := X"180C"; -- WORD
constant c_param_ram : unsigned(15 downto 0) := X"1000";
begin
i_harness: entity work.harness_mm
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
variable value : unsigned(31 downto 0);
variable params : std_logic_vector(31 downto 0);
variable rotation_speed : natural;
variable bit_time : natural;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1571-rom.310654-05.bin", dram, X"00008000");
-- load_memory("../../../roms/sounds.bin", dram, X"00000000");
load_memory("../../../disks/cpm.g71", dram, X"00100000" ); -- 1 MB offset
wait for 20 us;
io_write(io, c_drvreg_drivetype, X"01"); -- switch to 1571 mode
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
rotation_speed := (31250000 / 20);
for i in 0 to 34 loop
value := unsigned(read_memory_32(dram, std_logic_vector(to_unsigned(16#100000# + 12 + i*8, 32))));
value := value + X"00100000";
params(15 downto 0) := read_memory_16(dram, std_logic_vector(value));
value := value + 2;
bit_time := rotation_speed / to_integer(unsigned(params(15 downto 0)));
params(31 downto 16) := std_logic_vector(to_unsigned(bit_time, 16));
report "Track " & integer'image(i+1) & ": " & hstr(value) & " - " & hstr(params);
io_write_32(io, c_param_ram + 16*i, std_logic_vector(value) );
io_write_32(io, c_param_ram + 16*i + 4, params );
io_write_32(io, c_param_ram + 16*i + 12, params );
end loop;
wait for 800 ms;
io_write(io, c_drvreg_inserted, X"01");
-- iec_drf(bfm);
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
iec_send_atn(bfm, X"5F", true); -- Drives, Untalk!
wait for 10 ms;
iec_send_atn(bfm, X"28"); -- Drive 8, Listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_send_message(bfm, "U0>M1"); -- 1571 Mode!
wait for 10 ms;
iec_send_atn(bfm, X"3F", true); -- UnListen
wait for 1000 ms;
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/c2n_record/vhdl_source/c2n_record.vhd | 1 | 8349 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor_in : in std_logic;
c2n_motor_out : out std_logic := '0'; -- not yet used
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
signal motor_en : std_logic;
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
attribute register_duplication of motor_en : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled; -- and c2n_motor;
motor_en <= c2n_motor_in;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif stream_en='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if (diff > 2040) or (motor_en = '0') then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
| gpl-3.0 |
keyru/hdl-make | tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl | 1 | 1693 | -------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <[email protected]> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
| gpl-3.0 |
chiggs/nvc | test/regress/wait11.vhd | 5 | 370 | entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/zpu/vhdl_source/zpu_profiler.vhd | 5 | 4692 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zpu_profiler is
port (
clock : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(26 downto 0);
cpu_instr : in std_logic;
cpu_req : in std_logic;
cpu_write : in std_logic;
cpu_rack : in std_logic;
cpu_dack : in std_logic;
enable : in std_logic;
clear : in std_logic;
section : in std_logic_vector(3 downto 0);
match : in std_logic_vector(3 downto 0);
my_read : in std_logic;
my_rack : out std_logic;
my_dack : out std_logic;
rdata : out std_logic_vector(7 downto 0) );
end zpu_profiler;
architecture gideon of zpu_profiler is
type t_count_array is array (natural range <>) of unsigned(31 downto 0);
signal counters : t_count_array(0 to 7) := (others => (others => '0'));
signal emulation_access : std_logic;
signal io_access : std_logic;
signal instruction_access : std_logic;
signal other_access : std_logic;
signal writes : std_logic;
signal req_d : std_logic;
signal count_out : std_logic_vector(31 downto 0) := (others => '0');
signal cpu_address_d : std_logic_vector(1 downto 0);
signal section_d : std_logic_vector(section'range);
signal section_entry : std_logic;
signal section_match : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
emulation_access <= '0';
io_access <= '0';
instruction_access <= '0';
other_access <= '0';
writes <= '0';
section_entry <= '0';
section_match <= '0';
-- first, split time in different "enables" for the counters
if cpu_rack='1' then
if cpu_address(26 downto 10) = "00000000000000000" then
emulation_access <= '1';
elsif cpu_address(26)='1' then
io_access <= '1';
elsif cpu_instr = '1' then
instruction_access <= '1';
else
other_access <= '1';
end if;
if cpu_write = '1' then
writes <= '1';
end if;
end if;
section_d <= section;
if section = match and section_d /= match then
section_entry <= '1';
end if;
if section = match then
section_match <= '1';
end if;
-- now, count our stuff
if clear='1' then
counters <= (others => (others => '0'));
elsif enable='1' then
counters(0) <= counters(0) + 1;
if emulation_access = '1' then
counters(1) <= counters(1) + 1;
end if;
if io_access = '1' then
counters(2) <= counters(2) + 1;
end if;
if instruction_access = '1' then
counters(3) <= counters(3) + 1;
end if;
if other_access = '1' then
counters(4) <= counters(4) + 1;
end if;
if writes = '1' then
counters(5) <= counters(5) + 1;
end if;
if section_entry='1' then
counters(6) <= counters(6) + 1;
end if;
if section_match = '1' then
counters(7) <= counters(7) + 1;
end if;
end if;
-- output register (read)
if my_read='1' then
if cpu_address(1 downto 0)="00" then
count_out <= std_logic_vector(counters(to_integer(unsigned(cpu_address(4 downto 2)))));
end if;
end if;
cpu_address_d <= cpu_address(1 downto 0);
case cpu_address_d is
when "00" => rdata <= count_out(31 downto 24);
when "01" => rdata <= count_out(23 downto 16);
when "10" => rdata <= count_out(15 downto 8);
when others => rdata <= count_out(7 downto 0);
end case;
req_d <= my_read;
my_dack <= req_d;
end if;
end process;
my_rack <= my_read;
end gideon; | gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/pkg_6502_opcodes.vhd | 1 | 5226 |
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"NOP*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ANC*# ",
"NOP*$nnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"NOP*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"NOP*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "ANC*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"NOP*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"NOP*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"NOP*$nn ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "ALR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"NOP*$nn,x ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn $$", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"NOP*$nn ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ARR*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"NOP*$nn,x ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*(ABS,X)$$", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"NOP*# ", "STA ($nn,X) ", "NOP*# ", "SAX*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "SAX*$nn ",
"DEY ", "NOP*# ", "TXA ", "XAA* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "SAX*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AHX*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "SAX*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "TAS*$nnnn,Y ",
"SHY*$nnnn,X ", "STA $nnnn,X ", "SHX*$nnnn,Y ", "AHX*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAS*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "NOP*# ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "AXS*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"NOP*$nn,X ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"NOP*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "NOP*# ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"NOP*$nn,S ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"NOP*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
type t_oper_array is array(0 to 7) of string(1 to 4);
constant c_shift_oper_array : t_oper_array := (
"ASL ", "ROL ", "LSR ", "ROR ", "NOP ", "TST ", "DEC ", "INC " );
constant c_alu_oper_array : t_oper_array := (
"OR ", "AND ", "XOR ", "ADD ", "NOP ", "TST ", "CMP ", "SUB " );
end;
| gpl-3.0 |
chiggs/nvc | test/regress/func12.vhd | 5 | 994 | entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if value(i) = '1' then
cnt := cnt + 1;
end if;
end loop;
return cnt;
end function;
function get_bits(v : in bit_vector(7 downto 0)) return bit_vector is
begin
for i in v'range loop
report integer'image(i) & " = " & bit'image(v(i));
end loop;
return v;
end function;
begin
process is
variable v : bit_vector(0 to 7) := X"05";
begin
assert popcnt_high(v) = 0;
v := X"f0";
assert popcnt_high(v) = 4;
assert popcnt_high(get_bits(X"20")) = 1;
--assert popcnt_high(v(0 to 3)) = 2;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/slice2.vhd | 6 | 854 | entity slice2 is
end entity;
architecture test of slice2 is
procedure set_it(signal v : out bit_vector(7 downto 0);
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
procedure set_it2(signal v : out bit_vector;
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
signal vec : bit_vector(7 downto 0);
begin
process is
begin
set_it(vec, 3, 0, X"a");
wait for 1 ns;
assert vec = X"0a";
set_it(vec, 4, 1, X"f");
wait for 1 ns;
assert vec = X"1e";
set_it2(vec, 7, 4, X"f");
wait for 1 ns;
assert vec = X"fe";
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cpu_part_1571.vhd | 1 | 20041 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_part_1571 is
generic (
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
falling : in std_logic;
rising : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- memory interface
mem_req_cpu : out t_mem_req;
mem_resp_cpu : in t_mem_resp;
mem_req_disk : out t_mem_req;
mem_resp_disk : in t_mem_resp;
mem_busy : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
motor_on : out std_logic;
mode : out std_logic;
write_prot_n : in std_logic;
step : out std_logic_vector(1 downto 0);
rate_ctrl : out std_logic_vector(1 downto 0);
byte_ready : in std_logic;
sync : in std_logic;
rdy_n : in std_logic;
disk_change_n : in std_logic;
side : out std_logic;
two_MHz : out std_logic;
track_0 : in std_logic;
drv_rdata : in std_logic_vector(7 downto 0);
drv_wdata : out std_logic_vector(7 downto 0);
act_led : out std_logic );
end entity;
architecture structural of cpu_part_1571 is
signal motor_on_i : std_logic;
signal soe : std_logic;
signal so_n : std_logic;
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal via1_data : std_logic_vector(7 downto 0);
signal via2_data : std_logic_vector(7 downto 0);
signal via1_wen : std_logic;
signal via1_ren : std_logic;
signal via2_wen : std_logic;
signal via2_ren : std_logic;
signal cia_data : std_logic_vector(7 downto 0);
signal cia_wen : std_logic;
signal cia_ren : std_logic;
signal wd_data : std_logic_vector(7 downto 0);
signal wd_wen : std_logic;
signal wd_ren : std_logic;
signal cia_port_a_o : std_logic_vector(7 downto 0);
signal cia_port_a_t : std_logic_vector(7 downto 0);
signal cia_port_a_i : std_logic_vector(7 downto 0);
signal cia_port_b_o : std_logic_vector(7 downto 0);
signal cia_port_b_t : std_logic_vector(7 downto 0);
signal cia_port_b_i : std_logic_vector(7 downto 0);
signal cia_sp_o : std_logic;
signal cia_sp_i : std_logic;
signal cia_sp_t : std_logic;
signal cia_cnt_o : std_logic;
signal cia_cnt_i : std_logic;
signal cia_cnt_t : std_logic;
signal cia_irq : std_logic;
signal via1_port_a_o : std_logic_vector(7 downto 0);
signal via1_port_a_t : std_logic_vector(7 downto 0);
signal via1_port_a_i : std_logic_vector(7 downto 0);
signal via1_ca2_o : std_logic;
signal via1_ca2_i : std_logic;
signal via1_ca2_t : std_logic;
signal via1_cb1_o : std_logic;
signal via1_cb1_i : std_logic;
signal via1_cb1_t : std_logic;
signal via1_port_b_o : std_logic_vector(7 downto 0);
signal via1_port_b_t : std_logic_vector(7 downto 0);
signal via1_port_b_i : std_logic_vector(7 downto 0);
signal via1_ca1 : std_logic;
signal via1_cb2_o : std_logic;
signal via1_cb2_i : std_logic;
signal via1_cb2_t : std_logic;
signal via1_irq : std_logic;
signal via2_port_b_o : std_logic_vector(7 downto 0);
signal via2_port_b_t : std_logic_vector(7 downto 0);
signal via2_port_b_i : std_logic_vector(7 downto 0);
signal via2_ca2_o : std_logic;
signal via2_ca2_i : std_logic;
signal via2_ca2_t : std_logic;
signal via2_cb1_o : std_logic;
signal via2_cb1_i : std_logic;
signal via2_cb1_t : std_logic;
signal via2_cb2_o : std_logic;
signal via2_cb2_i : std_logic;
signal via2_cb2_t : std_logic;
signal via2_irq : std_logic;
-- Local signals
signal fast_ser_dir : std_logic;
signal atn_ack : std_logic;
signal my_clk_out : std_logic;
signal my_data_out : std_logic;
signal my_fast_data_out : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_rising : std_logic;
type t_mem_state is (idle, newcycle, extcycle);
signal mem_state : t_mem_state;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
begin
mem_req_cpu.request <= mem_request;
mem_req_cpu.address <= mem_addr;
mem_req_cpu.read_writen <= mem_rwn;
mem_req_cpu.data <= mem_wdata;
mem_req_cpu.tag <= g_cpu_tag;
mem_req_cpu.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp_cpu.rack_tag = g_cpu_tag else '0';
mem_dack <= '1' when mem_resp_cpu.dack_tag = g_cpu_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_clk_en => cpu_clk_en,
cpu_reset => reset,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => so_n );
-- Generate an output stream to debug internal operation of 1541 CPU
process(clock)
begin
if rising_edge(clock) then
debug_valid <= '0';
if cpu_clk_en = '1' then
debug_data <= '0' & atn_i & data_i & clk_i & sync & so_n & cpu_irqn & not cpu_write & cpu_rdata & cpu_addr(15 downto 0);
debug_valid <= '1';
if cpu_write = '1' then
debug_data(23 downto 16) <= cpu_wdata;
end if;
end if;
end if;
end process;
via1: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via1_wen,
ren => via1_ren,
data_in => cpu_wdata,
data_out => via1_data,
-- pio --
port_a_o => via1_port_a_o,
port_a_t => via1_port_a_t,
port_a_i => via1_port_a_i,
port_b_o => via1_port_b_o,
port_b_t => via1_port_b_t,
port_b_i => via1_port_b_i,
-- handshake pins
ca1_i => via1_ca1,
ca2_o => via1_ca2_o, -- ignore, driven from LS14
ca2_i => via1_ca2_i, -- connects to write protect pin
ca2_t => via1_ca2_t, -- ignore, driven from LS14
cb1_o => via1_cb1_o,
cb1_i => via1_cb1_i,
cb1_t => via1_cb1_t,
cb2_o => via1_cb2_o,
cb2_i => via1_cb2_i,
cb2_t => via1_cb2_t,
irq => via1_irq );
via2: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via2_wen,
ren => via2_ren,
data_in => cpu_wdata,
data_out => via2_data,
-- pio --
port_a_o => drv_wdata,
port_a_t => open,
port_a_i => drv_rdata,
port_b_o => via2_port_b_o,
port_b_t => via2_port_b_t,
port_b_i => via2_port_b_i,
-- handshake pins
ca1_i => so_n,
ca2_o => via2_ca2_o,
ca2_i => via2_ca2_i,
ca2_t => via2_ca2_t,
cb1_o => via2_cb1_o,
cb1_i => via2_cb1_i,
cb1_t => via2_cb1_t,
cb2_o => via2_cb2_o,
cb2_i => via2_cb2_i,
cb2_t => via2_cb2_t,
irq => via2_irq );
i_cia1: entity work.cia_registers
generic map (
g_report => false,
g_unit_name => "CIA_1581" )
port map (
clock => clock,
falling => falling,
reset => reset,
tod_pin => '1', -- depends on jumper
addr => unsigned(cpu_addr(3 downto 0)),
data_in => cpu_wdata,
wen => cia_wen,
ren => cia_ren,
data_out => cia_data,
-- pio --
port_a_o => cia_port_a_o, -- unused
port_a_t => cia_port_a_t,
port_a_i => cia_port_a_i,
port_b_o => cia_port_b_o, -- unused
port_b_t => cia_port_b_t,
port_b_i => cia_port_b_i,
-- serial pin
sp_o => cia_sp_o, -- Burst mode IEC data
sp_i => cia_sp_i,
sp_t => cia_sp_t,
cnt_i => cia_cnt_i, -- Burst mode IEC clock
cnt_o => cia_cnt_o,
cnt_t => cia_cnt_t,
pc_o => open,
flag_i => atn_i, -- active low ATN in
irq => cia_irq );
cpu_irqn <= not(via1_irq or via2_irq);
cpu_clk_en <= falling;
cpu_rising <= rising;
mem_busy <= '0' when mem_state = idle else '1';
-- Fetch ROM byte
process(clock)
begin
if rising_edge(clock) then
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
case mem_state is
when idle =>
if cpu_clk_en = '1' then
mem_state <= newcycle;
end if;
when newcycle => -- we have a new address now
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
if cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM
if cpu_write = '0' then
mem_request <= '1';
mem_state <= extcycle;
else -- writing to rom -> ignore
mem_state <= idle;
end if;
-- It's not extended RAM, not ROM, so it must be internal RAM or I/O.
elsif cpu_addr(14 downto 11) = "0000" then -- Internal RAM
mem_request <= '1';
mem_state <= extcycle;
else -- this applies to anything 0000-07FF, thus 0800-7FFF!
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp_cpu.data;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
mem_request <= '0';
mem_state <= idle;
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- address decoding and data muxing
process(cpu_addr, ext_rdata, via1_data, via2_data, cia_data, wd_data)
begin
if cpu_addr(15) = '1' then -- 8000-FFFF
cpu_rdata <= ext_rdata;
elsif cpu_addr(14) = '1' then -- 4000-7FFF
cpu_rdata <= cia_data;
elsif cpu_addr(13) = '1' then -- 2000-3FFF
cpu_rdata <= wd_data;
elsif cpu_addr(12 downto 10) = "110" then -- 1800-1BFF
cpu_rdata <= via1_data;
elsif cpu_addr(12 downto 10) = "111" then -- 1C00-1FFF
cpu_rdata <= via2_data;
elsif cpu_addr(12 downto 11) = "00" then -- 0000-07FF
cpu_rdata <= ext_rdata;
else
cpu_rdata <= X"FF";
end if;
end process;
via1_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 10)="000110" else '0';
via1_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 10)="000110" else '0';
via2_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 10)="000111" else '0';
via2_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 10)="000111" else '0';
cia_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 14)="01" else '0';
cia_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 14)="01" else '0';
wd_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 13)="001" else '0';
wd_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 13)="001" else '0';
-- correctly attach the VIA pins to the outside world
via1_ca1 <= not atn_i;
via1_cb2_i <= via1_cb2_o or not via1_cb2_t;
-- Via Port A is used in the 1541 for the parallel interface (SpeedDos / DolphinDos), but in the 1571 some of the pins are connected internally
via1_port_a_i(7) <= (via1_port_a_o(7) or not via1_port_a_t(7)) and so_n; -- Byte ready in schematic. Our byte_ready signal is not yet masked with so_e
via1_port_a_i(6) <= (via1_port_a_o(6) or not via1_port_a_t(6)); -- ATN OUT (not connected)
via1_port_a_i(5) <= (via1_port_a_o(5) or not via1_port_a_t(5)); -- 2 MHz mode
via1_port_a_i(4) <= (via1_port_a_o(4) or not via1_port_a_t(4));
via1_port_a_i(3) <= (via1_port_a_o(3) or not via1_port_a_t(3));
via1_port_a_i(2) <= (via1_port_a_o(2) or not via1_port_a_t(2)); -- SIDE
via1_port_a_i(1) <= (via1_port_a_o(1) or not via1_port_a_t(1)); -- SER_DIR
via1_port_a_i(0) <= (via1_port_a_o(0) or not via1_port_a_t(0)) and not track_0;
side <= via1_port_a_i(2);
two_MHz <= via1_port_a_i(5);
fast_ser_dir <= via1_port_a_i(1);
-- Because Port B reads its own output when set to output, we do not need to consider the direction here
via1_port_b_i(7) <= not atn_i;
via1_port_b_i(6) <= drive_address(1); -- drive select
via1_port_b_i(5) <= drive_address(0); -- drive select;
via1_port_b_i(4) <= '1'; -- atn a - PUP
via1_port_b_i(3) <= '1'; -- clock out - PUP
via1_port_b_i(2) <= not (clk_i and not my_clk_out);
via1_port_b_i(1) <= '1'; -- data out - PUP
via1_port_b_i(0) <= not (data_i and not my_data_out and (not (atn_ack xor (not atn_i))));
via1_ca2_i <= write_prot_n;
via1_cb1_i <= via1_cb1_o or not via1_cb1_t;
atn_ack <= via1_port_b_o(4) or not via1_port_b_t(4);
my_data_out <= via1_port_b_o(1) or not via1_port_b_t(1);
my_clk_out <= via1_port_b_o(3) or not via1_port_b_t(3);
-- Do the same for VIA 2. Port A should read the pin, Port B reads the output internally, so for port B only actual input signals should be connected
via2_port_b_i(7) <= sync;
via2_port_b_i(6) <= '1'; --Density
via2_port_b_i(5) <= '1'; --Density
via2_port_b_i(4) <= write_prot_n;
via2_port_b_i(3) <= '1'; -- LED
via2_port_b_i(2) <= '1'; -- Motor
via2_port_b_i(1) <= '1'; -- Step
via2_port_b_i(0) <= '1'; -- Step
via2_cb1_i <= via2_cb1_o or not via2_cb1_t;
via2_cb2_i <= via2_cb2_o or not via2_cb2_t;
via2_ca2_i <= via2_ca2_o or not via2_ca2_t;
-- CIA ports are not used
cia_port_a_i <= cia_port_a_o or not cia_port_a_t;
cia_port_b_i <= cia_port_b_o or not cia_port_b_t;
act_led <= not (via2_port_b_o(3) or not via2_port_b_t(3)) or not power;
mode <= via2_cb2_i;
step(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
step(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
motor_on_i <= (via2_port_b_o(2) or not via2_port_b_t(2)) and power;
rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5);
rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6);
soe <= via2_ca2_i;
so_n <= byte_ready or not soe;
motor_on <= motor_on_i;
data_o <= not power or (not my_data_out and my_fast_data_out and (not (atn_ack xor (not atn_i))));
clk_o <= not power or not my_clk_out;
atn_o <= '1';
my_fast_data_out <= (cia_sp_o or not cia_sp_t) or not fast_ser_dir; -- active low!
cia_sp_i <= (cia_sp_o or not cia_sp_t) when fast_ser_dir = '1' else
data_i;
fast_clk_o <= (cia_cnt_o or not cia_cnt_t) or not fast_ser_dir; -- active low!
cia_cnt_i <= (cia_cnt_o or not cia_cnt_t) when fast_ser_dir = '1' else -- output
fast_clk_i; -- assume that 74LS241 wins
-- Floppy Controller
i_wd177x: entity work.wd177x
generic map (
g_tag => g_disk_tag
)
port map(
clock => clock,
clock_en => cpu_clk_en,
reset => reset,
addr => unsigned(cpu_addr(1 downto 0)),
wen => wd_wen,
ren => wd_ren,
wdata => cpu_wdata,
rdata => wd_data,
motor_en => motor_on_i,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
stepper_en => '0',
mem_req => mem_req_disk,
mem_resp => mem_resp_disk,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
end architecture;
-- Original mapping:
-- 0000-07FF RAM
-- 0800-17FF open
-- 1800-1BFF VIA 1
-- 1C00-1FFF VIA 2
-- 2000-3FFF WD17xx
-- 4000-7FFF CIA 6526
-- 8000-FFFF ROM image
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/ip/video/vhdl_source/sync_separator.vhd | 5 | 2599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_separator is
generic (
g_clock_mhz : natural := 50 );
port (
clock : in std_logic;
sync_in : in std_logic;
mute : out std_logic;
h_sync : out std_logic;
v_sync : out std_logic );
end sync_separator;
architecture low_level of sync_separator is
constant c_delay : integer := 50;
signal h_sync_i : std_logic := '0';
signal release : std_logic := '0';
signal sync_c : std_logic := '0';
signal sync_d1 : std_logic := '0';
signal sync_d2 : std_logic := '0';
signal v_sync_pre : std_logic := '0';
signal delay : integer range 0 to c_delay * g_clock_mhz := 0;
signal raw_c : std_logic;
signal raw_d1 : std_logic;
signal raw_d2 : std_logic;
signal line_count : unsigned(8 downto 0) := (others => '0');
begin
h_sync <= h_sync_i;
process(sync_in, release)
begin
if release='1' then
h_sync_i <= '0';
elsif falling_edge(sync_in) then
h_sync_i <= '1';
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
sync_c <= h_sync_i;
sync_d1 <= sync_c;
sync_d2 <= sync_d1;
-- raw_c <= sync_in;
-- raw_d1 <= raw_c;
-- raw_d2 <= raw_d1;
--
-- if raw_d1='0' and raw_d2='1' then -- falling edge
-- if delay /= 0 then
-- mute <= '1';
-- else
-- mute <= '0';
-- end if;
-- end if;
if (line_count < 4) or (line_count > 305) then
mute <= '1';
else
mute <= '0';
end if;
release <= '0';
if sync_d1='1' and sync_d2='0' then -- rising edge
delay <= c_delay * g_clock_mhz;
if v_sync_pre = '1' then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
elsif delay /= 0 then
delay <= delay - 1;
end if;
if delay = 1 then
v_sync_pre <= not sync_in; -- sample
release <= '1';
end if;
end if;
end process;
v_sync <= v_sync_pre;
end low_level;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v2.vhd | 5 | 15718 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity ext_mem_ctrl_v2 is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 1;
SRAM_Data_Width : integer := 8;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
ETH_Acc_Time : integer := 9;
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 3;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(25 downto 0); -- 64M Space
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
slot_req : in std_logic := '0';
dma_addr : out std_logic_vector(15 downto 0);
dma_rdata : in std_logic_vector(7 downto 0);
dma_wdata : out std_logic_vector(7 downto 0);
dma_req : out std_logic;
dma_rwn : out std_logic;
dma_ack : in std_logic := '0';
enable_refr : in std_logic := '0';
enable_sdram: in std_logic := '0';
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
ETH_CSn : out std_logic := '1';
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
MEM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end ext_mem_ctrl_v2;
-- ADDR: 25 24 23 ...
-- 0 0 0 ... SRAM
-- 0 0 1 ... C64 DMA
-- 0 1 0 ... Flash
-- 0 1 1 ... SDRAM command
-- 1 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v2 is
type t_state is (idle, setup, pulse, hold, dma_access, sd_cas, sd_wait, eth_pulse);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
signal memsel : std_logic_vector(1 downto 0);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal dma_rdata_c : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal suspend_dma : std_logic;
signal dma_tag : std_logic_vector(tag'range);
-- signal counter : std_logic_vector(7 downto 0) := X"00";
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
rdata <= rdata_i when dout_sel='0' else dma_rdata_c;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
mem_a_i <= address(MEM_A'range);
memsel <= address(25 downto 24);
sram_d_t <= not readwriten;
sram_d_o <= wdata;
dma_wdata <= wdata;
SRAM_CSn <= address(25) or address(24) or address(23); -- should be all '0' for CSn to become active
FLASH_CSn <= address(25) or not address(24) or address(23) or address(22); -- '0' when A25..23 = 010
ETH_CSn <= address(25) or not address(24) or address(23) or not address(22); -- '1' when A25..22 = 0101
if address(25)='1' then
mem_a_i(12 downto 0) <= address(24 downto 12); -- 13 row bits
mem_a_i(17 downto 16) <= address(11 downto 10); -- 2 bank bits
col_addr <= address( 9 downto 0); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
elsif address(24 downto 22)="100" then -- Flash
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif address(24 downto 22)="101" then -- Ethernet
delay <= ETH_Acc_Time;
state <= eth_pulse;
elsif address(24 downto 23)="11" then -- sdram command
SDRAM_CSn <= '0';
SDRAM_RASn <= address(13);
SDRAM_CASn <= address(14);
SDRAM_WEn <= address(15);
dack <= '1';
dack_tag <= req_tag;
state <= idle;
elsif address(24 downto 23)="01" then -- DMA
MEM_BEn <= (others => '1');
MEM_OEn <= '1';
MEM_WEn <= '1';
dma_req <= '1';
state <= dma_access;
else -- SRAM
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
dout_sel <= '0';
dma_rdata_c <= dma_rdata;
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when idle =>
if suspend_dma='1' then
tag <= dma_tag;
state <= dma_access;
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
elsif do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
send_refresh_cmd;
elsif inhibit='0' then
dma_req <= '0';
if req='1' and (refr_delay=0 or address(25)='0') then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= '1';
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 1;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
dack <= '1';
dack_tag <= tag;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel(0)='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if memsel(0)='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when eth_pulse =>
delay <= delay - 1;
case delay is
when 2 =>
dack <= '1';
dack_tag <= tag;
-- rdata_i <= counter;
-- counter <= counter + 1;
MEM_WEn <= '1';
MEM_OEn <= '1';
when 1 =>
sram_d_t <= '0';
ETH_CSn <= '1';
state <= idle;
when others =>
MEM_WEn <= rwn_i;
MEM_OEn <= not rwn_i;
end case;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
else
delay <= delay - 1;
end if;
when dma_access =>
suspend_dma <= '0';
dma_tag <= tag;
if dma_ack='1' then
dma_req <= '0';
sram_d_t <= '0';
dack <= '1';
dack_tag <= tag;
dout_sel <= '1';
state <= idle;
elsif slot_req='1' then
suspend_dma <= '1';
accept_req; -- exits this state, does an access and returns to idle.
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= enable_refr;
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= idle;
dma_req <= '0';
ETH_CSn <= '1';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
MEM_BEn <= (others => '1');
-- sram_d_o <= (others => '1');
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
suspend_dma <= '0';
end if;
end if;
end process;
dma_rwn <= rwn_i;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
dma_addr <= mem_a_i(15 downto 0);
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_memory_ctrl.vhd | 1 | 9278 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
--use work.tl_sctb_pkg.all;
--use work.tl_string_util_pkg.all;
-- This module performs the memory operations that are instructed
-- by the nano_cpu. This controller copies data to or from a
-- designated BRAM, and notifies the nano_cpu that the transfer
-- is complete.
entity usb_memory_ctrl is
generic (
g_big_endian : boolean;
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
clock : in std_logic;
reset : in std_logic;
-- cmd interface
cmd_addr : in std_logic_vector(3 downto 0);
cmd_valid : in std_logic;
cmd_write : in std_logic;
cmd_wdata : in std_logic_vector(15 downto 0);
cmd_ack : out std_logic;
cmd_done : out std_logic;
cmd_ready : out std_logic;
-- BRAM interface
ram_addr : out std_logic_vector(10 downto 2);
ram_en : out std_logic;
ram_we : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- memory interface
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture gideon of usb_memory_ctrl is
type t_state is (idle, reading, writing, data_wait, prefetch, init);
signal state : t_state;
signal mem_addr_r : unsigned(25 downto 0) := (others => '0');
signal mem_addr_i : unsigned(25 downto 2) := (others => '0');
signal ram_addr_i : unsigned(8 downto 2) := (others => '0');
signal size_r : unsigned(1 downto 0) := "00";
signal mreq : std_logic := '0';
signal rwn : std_logic := '1';
signal addr_do_load : std_logic := '0';
signal new_addr : std_logic := '0';
signal addr_do_inc : std_logic := '0';
signal rem_do_load : std_logic;
signal rem_do_dec : std_logic;
signal remain_is_0 : std_logic;
signal remain_is_1 : std_logic;
signal buffer_idx : std_logic_vector(10 downto 9) := "00";
signal ram_we_i : std_logic_vector(3 downto 0);
signal ram_wnext : std_logic;
signal rdata_valid : std_logic;
signal first_req : std_logic;
signal last_req : std_logic;
signal mem_rdata_le : std_logic_vector(31 downto 0);
begin
mem_req.tag(7) <= last_req;
mem_req.tag(6) <= first_req;
mem_req.tag(5 downto 0) <= g_tag(5 downto 0);
mem_req.request <= mreq;
mem_req.address <= mem_addr_i & mem_addr_r(1 downto 0);
mem_req.read_writen <= rwn;
mem_req.data <= ram_rdata;
mem_req.byte_en <= "1111";
-- pop from fifo when we process the access
cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0';
process(buffer_idx, state, mreq, mem_resp, ram_addr_i, ram_we_i)
begin
ram_addr <= buffer_idx & std_logic_vector(ram_addr_i);
ram_en <= '0';
-- for writing to memory, we enable the BRAM only when we are going to set
-- the request, such that the data and the request comes at the same time
case state is
when prefetch =>
ram_en <= '1';
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
ram_en <= '1';
end if;
when others =>
null;
end case;
rem_do_dec <= '0';
if mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0) then
rem_do_dec <= '1';
end if;
-- for reading from memory, it doesn't matter in which state we are:
if ram_we_i /= "0000" then
ram_en <= '1';
end if;
end process;
ram_we <= ram_we_i;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
rwn <= '1';
if cmd_valid='1' then
if cmd_write='1' then
cmd_done <= '0';
case cmd_addr is
when X"0" =>
mem_addr_r(15 downto 0) <= unsigned(cmd_wdata(15 downto 0));
new_addr <= '1';
when X"1" =>
mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0));
new_addr <= '1';
when X"2" =>
rwn <= '0';
size_r <= unsigned(cmd_wdata(1 downto 0));
state <= init;
when X"3" =>
size_r <= unsigned(cmd_wdata(1 downto 0));
state <= init;
when X"4" =>
buffer_idx <= cmd_wdata(15 downto 14);
when others =>
null;
end case;
end if;
end if;
when init =>
new_addr <= '0';
ram_addr_i <= (others => '0');
first_req <= '1';
if rwn='1' then
mreq <= '1';
state <= reading;
-- sctb_trace("Reading buffer " & hstr(buffer_idx) & " from memory address " & hstr(mem_addr_r));
else
state <= prefetch;
-- sctb_trace("Writing buffer " & hstr(buffer_idx) & " to memory address " & hstr(mem_addr_r));
end if;
when reading =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
first_req <= '0';
if last_req = '1' then
state <= data_wait;
cmd_done <= '1';
mreq <= '0';
end if;
end if;
when data_wait =>
-- just wait until we get a tag on data valid that indicates the last dataword of the transfer
if rdata_valid = '1' and mem_resp.dack_tag(7) = '1' then
state <= idle;
end if;
when prefetch =>
mreq <= '1';
ram_addr_i <= ram_addr_i + 1;
state <= writing;
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
first_req <= '0';
ram_addr_i <= ram_addr_i + 1;
if remain_is_1 = '1' then
state <= idle;
cmd_done <= '1';
mreq <= '0';
end if;
end if;
when others =>
null;
end case;
if ram_wnext = '1' then
ram_addr_i <= ram_addr_i + 1;
end if;
if reset='1' then
state <= idle;
mreq <= '0';
cmd_done <= '0';
new_addr <= '0';
first_req <= '0';
end if;
end if;
end process;
cmd_ready <= '1' when (state = idle) else '0';
addr_do_load <= new_addr when (state = init) else '0';
addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) else '0';
i_addr: entity work.mem_addr_counter
port map (
clock => clock,
load_value => mem_addr_r(25 downto 2),
do_load => addr_do_load,
do_inc => addr_do_inc,
address => mem_addr_i );
rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0';
i_rem: entity work.mem_remain_counter
port map (
clock => clock,
load_value => unsigned(cmd_wdata(9 downto 2)),
do_load => rem_do_load,
do_dec => rem_do_dec,
remain => open,
remain_is_1 => remain_is_1,
remain_is_0 => remain_is_0 );
last_req <= remain_is_1;
rdata_valid <= '1' when mem_resp.dack_tag(5 downto 0) = g_tag(5 downto 0) else '0';
mem_rdata_le <= byte_swap(mem_resp.data, g_big_endian);
i_align: entity work.align_read_to_bram
port map (
clock => clock,
reset => reset,
rdata => mem_rdata_le,
rdata_valid => rdata_valid,
first_word => mem_resp.dack_tag(6),
last_word => mem_resp.dack_tag(7),
offset => mem_addr_r(1 downto 0),
last_bytes => size_r,
wdata => ram_wdata,
wmask => ram_we_i,
wnext => ram_wnext );
end architecture;
| gpl-3.0 |
chiggs/nvc | test/sem/issue88.vhd | 5 | 729 | entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/sigma_delta_dac/vhdl_source/delta_sigma_2to5.vhd | 5 | 2460 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/freezer.vhd | 1 | 3036 | library ieee;
use ieee.std_logic_1164.all;
entity freezer is
generic (
g_ext_activate : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
button_freeze : in std_logic;
cpu_cycle_done : in std_logic;
cpu_write : in std_logic;
activate : in std_logic := '0';
freezer_state : out std_logic_vector(1 downto 0); -- debug
unfreeze : in std_logic; -- could be software driven, or automatic, depending on cartridge
freeze_trig : out std_logic;
freeze_act : out std_logic );
end freezer;
architecture gideon of freezer is
signal reset_in : std_logic;
signal wr_cnt : integer range 0 to 3;
signal do_freeze : std_logic;
signal do_freeze_d : std_logic;
signal activate_c : std_logic;
signal activate_d : std_logic;
type t_state is (idle, triggered, enter_freeze, button);
signal state : t_state;
begin
freeze_trig <= '1' when (state = triggered) else '0';
process(clock)
begin
if rising_edge(clock) then
activate_c <= activate;
activate_d <= activate_c;
do_freeze <= button_freeze;
do_freeze_d <= do_freeze;
reset_in <= reset or RST_in;
if cpu_cycle_done='1' then
if cpu_write='1' then
if wr_cnt/=3 then
wr_cnt <= wr_cnt + 1;
end if;
else
wr_cnt <= 0;
end if;
end if;
case state is
when idle =>
freeze_act <= '0';
if do_freeze_d='0' and do_freeze='1' then -- push
state <= triggered;
end if;
when triggered =>
if (g_ext_activate and activate_d='1') or (not g_ext_activate and wr_cnt=3) then
state <= enter_freeze;
freeze_act <= '1';
end if;
when enter_freeze =>
if unfreeze='1' then
freeze_act <= '0';
state <= button;
end if;
when button =>
if do_freeze='0' then -- wait until button is not pressed anymore
state <= idle;
end if;
when others =>
state <= idle;
end case;
if reset_in='1' then
state <= idle;
wr_cnt <= 0;
activate_d <= '0';
end if;
end if;
end process;
with state select freezer_state <=
"00" when idle,
"01" when triggered,
"10" when enter_freeze,
"11" when button,
"00" when others;
end gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_sim/nano_tb.vhd | 5 | 807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/alu.vhd | 1 | 4815 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic;
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : std_logic_vector(7 downto 0) := X"FF";
signal oper4 : std_logic_vector(3 downto 0);
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
with oper4 select data_out_i <=
data_a or data_b when "1000",
data_a and data_b when "1001",
data_a xor data_b when "1010",
sum_result when "1011" | "1110" | "1111",
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
sum: process(data_a, data_b, c_in, operation, d_in)
variable b : std_logic_vector(7 downto 0);
variable sum_l : std_logic_vector(4 downto 0);
variable sum_h : std_logic_vector(4 downto 0);
begin
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := not data_b;
else
b := data_b;
end if;
-- sum_l(4) = carry of lower end, carry in is masked to '1' for CMP
sum_l := ('0' & data_a(3 downto 0)) + ('0' & b(3 downto 0)) + (c_in or not operation(0));
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4)) + sum_l(4);
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= sum_h(4);
sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
-- fix up in decimal mode (not for CMP!)
if d_in='1' and support_bcd then
if operation(2)='0' then -- ADC
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4));
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_l := sum_l + ('0' & X"6");
sum_l(4) := '1';
end if;
-- negative when sum_h + sum_l(4) = 8
sum_h := sum_h + sum_l(4);
sum_n <= sum_h(3);
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" then --
sum_h := sum_h + 6;
sum_c <= '1';
end if;
-- carry and overflow are output after fix
-- sum_c <= sum_h(4);
-- sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
elsif operation(0)='1' then -- SBC
-- flags are not adjusted in subtract mode
if sum_l(4) = '0' then
sum_l := sum_l - 6;
end if;
if sum_h(4) = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
oper4 <= enable & operation;
with oper4 select c_out <=
sum_c when "1011" | "1111" | "1110",
c_in when others;
with oper4 select z_out <=
sum_z when "1011" | "1111" | "1110",
zero when "1000" | "1001" | "1010" | "1101",
z_in when others;
with oper4 select n_out <=
sum_n when "1011" | "1111",
data_out_i(7) when "1000" | "1001" | "1010" | "1101" | "1110",
n_in when others;
with oper4 select v_out <=
sum_v when "1011" | "1111",
v_in when others;
data_out <= data_out_i;
end gideon; | gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/token_crc_check.vhd | 2 | 1986 | -------------------------------------------------------------------------------
-- Title : token_crc_check.vhd
-------------------------------------------------------------------------------
-- File : token_crc_check.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_check is
port (
clock : in std_logic;
sync : in std_logic;
valid : in std_logic;
data_in : in std_logic_vector(7 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc_check;
architecture Gideon of token_crc_check is
constant polynom : std_logic_vector(4 downto 0) := "00100";
signal crc_reg : std_logic_vector(polynom'range);
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
if sync = '1' then
crc_reg <= (others => '1');
elsif valid = '1' then
tmp := crc_reg;
for i in data_in'reverse_range loop -- LSB first!
d := data_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d;
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
crc_reg <= tmp;
end if;
end if;
end process;
process(crc_reg)
begin
for i in crc_reg'range loop -- reverse and invert
crc(crc'high-i) <= not(crc_reg(i));
end loop;
end process;
end Gideon;
| gpl-3.0 |
asicguy/crash | fpga/src/bpsk_mod/bpsk_mod.vhd | 2 | 8635 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: tx_mod.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Transmit data modulator. Biphase modulates signal with
-- input binary data with option to trigger.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end entity;
architecture RTL of bpsk_mod is
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal mod_data : std_logic_vector(63 downto 0);
signal bit_cnt : integer range 0 to 63;
signal enable : std_logic;
signal external_enable : std_logic;
signal external_trigger_enable : std_logic;
signal packet_size_cnt : integer;
signal packet_size : integer;
signal trigger_stb_reg : std_logic;
signal transmitting : std_logic;
begin
axis_slave_irq <= '0';
axis_master_irq <= '0';
axis_master_tdest <= axis_master_tdest_safe;
proc_modulate : process(clk,enable,external_enable)
begin
if (enable = '0' AND external_enable = '0') then
axis_slave_tready <= '0';
axis_master_tvalid <= '0';
axis_master_tlast <= '0';
axis_master_tdata <= (others=>'0');
packet_size_cnt <= packet_size; -- This is intentional
transmitting <= '0';
else
if rising_edge(clk) then
transmitting <= '1';
-- TODO: This code takes 65 clock cycles to transfer 64 complex samples. Should look into
-- redoing this so the single clock cycle delay is avoided.
-- Grab the AXI-Stream data when enabled
if (axis_slave_tvalid = '1' AND bit_cnt = 0) then
axis_slave_tready <= '1';
axis_master_tvalid <= '1';
mod_data <= axis_slave_tdata;
else
axis_slave_tready <= '0';
end if;
-- Count the number of data bits sent
axis_master_tlast <= '0';
if (axis_master_tready = '1') then
if (bit_cnt = 63) then
if (packet_size_cnt = 1) then
axis_master_tlast <= '1';
packet_size_cnt <= packet_size;
else
packet_size_cnt <= packet_size_cnt - 1;
end if;
axis_master_tvalid <= '0';
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1;
end if;
end if;
-- Modulate I & Q
-- I
if (mod_data(bit_cnt) = '1') then
axis_master_tdata(31 downto 0) <= x"7FFFFFFF";
else
axis_master_tdata(31 downto 0) <= x"80000000";
end if;
-- Q
axis_master_tdata(63 downto 32) <= (others=>'0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
external_enable <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
trigger_stb_reg <= '0';
else
if rising_edge(clk) then
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination can only update when no data is being transmitted, i.e. FFT disabled
if (enable = '0' AND external_enable = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- Register sideband signals
trigger_stb_reg <= trigger_stb;
-- Enable on trigger and disable only when external_trigger_enable is deasserted
if (trigger_stb_reg = '1' AND external_trigger_enable = '1') then
external_enable <= '1';
end if;
if (external_trigger_enable = '0') then
external_enable <= '0';
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable and destination)
enable <= ctrl_reg(0)(0);
external_trigger_enable <= ctrl_reg(0)(1);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (Packet size)
packet_size <= to_integer(unsigned(ctrl_reg(1)(31 downto 0)));
-- Status Registers
-- Bank 0 (Enable and destination Readback)
status_reg(0)(0) <= enable;
status_reg(0)(1) <= external_trigger_enable;
status_reg(0)(31 downto 29) <= axis_master_tdest_hold;
-- Bank 1 (Packet size Readback)
status_reg(1) <= std_logic_vector(to_unsigned(packet_size,32));
-- Bank 2
status_reg(2)(0) <= transmitting;
end architecture; | gpl-3.0 |
chiggs/nvc | test/lower/sigvar.vhd | 5 | 471 | entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
procedure proc3(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y & "1";
end procedure;
begin
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/rmii_transceiver.vhd | 1 | 9545 | -------------------------------------------------------------------------------
-- Title : rmii_transceiver
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Receiver / transmitter for RMII
-- TODO: Implement 10 Mbps mode
--
-- NOTE: The receive stream will include the FCS, and also an
-- additional byte, which indicates the correctness of the FCS.
-- This byte will be FF when correct and 00 when incorrect. It
-- coincides with eof. So CRC checking is done, CRC stripping is
-- not. The transmit path appends CRC after receiving the last
-- byte through the stream bus (thus after eof).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_transceiver is
port (
clock : in std_logic; -- 50 MHz reference clock
reset : in std_logic;
rmii_crs_dv : in std_logic;
rmii_rxd : in std_logic_vector(1 downto 0);
rmii_tx_en : out std_logic;
rmii_txd : out std_logic_vector(1 downto 0);
-- stream bus alike interface to MAC
eth_rx_data : out std_logic_vector(7 downto 0);
eth_rx_sof : out std_logic;
eth_rx_eof : out std_logic;
eth_rx_valid : out std_logic;
eth_tx_data : in std_logic_vector(7 downto 0);
eth_tx_eof : in std_logic;
eth_tx_valid : in std_logic;
eth_tx_ready : out std_logic;
-- Mode switch
ten_meg_mode : in std_logic );
end entity;
architecture rtl of rmii_transceiver is
type t_state is (idle, preamble, data0, data1, data2, data3, crc, gap);
signal rx_state : t_state;
signal tx_state : t_state;
signal crs_dv : std_logic;
signal rxd : std_logic_vector(1 downto 0);
signal rx_valid : std_logic;
signal rx_first : std_logic;
signal rx_end : std_logic;
signal rx_shift : std_logic_vector(7 downto 0) := (others => '0');
signal bad_carrier : std_logic;
signal rx_crc_sync : std_logic;
signal rx_crc_dav : std_logic;
signal rx_crc_data : std_logic_vector(3 downto 0) := (others => '0');
signal rx_crc : std_logic_vector(31 downto 0);
signal crc_ok : std_logic;
signal tx_count : natural range 0 to 63;
signal tx_crc_dav : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_data : std_logic_vector(1 downto 0);
signal tx_crc : std_logic_vector(31 downto 0);
begin
p_receive: process(clock)
begin
if rising_edge(clock) then
-- synchronize
crs_dv <= rmii_crs_dv;
rxd <= rmii_rxd;
bad_carrier <= '0';
rx_valid <= '0';
rx_end <= '0';
rx_crc_dav <= '0';
eth_rx_valid <= '0';
if rx_valid = '1' or rx_end = '1' then
eth_rx_eof <= rx_end;
eth_rx_sof <= rx_first;
if rx_end = '1' then
eth_rx_data <= (others => crc_ok);
else
eth_rx_data <= rx_shift;
end if;
eth_rx_valid <= '1';
rx_first <= '0';
end if;
case rx_state is
when idle =>
if crs_dv = '1' then
if rxd = "01" then
rx_state <= preamble;
elsif rxd = "10" then
bad_carrier <= '1';
end if;
end if;
when preamble =>
rx_first <= '1';
if crs_dv = '0' then
rx_state <= idle;
else -- dv = 1
if rxd = "11" then
rx_state <= data0;
elsif rxd = "01" then
rx_state <= preamble;
else
bad_carrier <= '1';
rx_state <= idle;
end if;
end if;
when data0 => -- crs_dv = CRS
rx_shift(1 downto 0) <= rxd;
rx_state <= data1;
when data1 => -- crs_dv = DV
rx_shift(3 downto 2) <= rxd;
rx_state <= data2;
if crs_dv = '0' then
rx_end <= '1';
rx_state <= idle;
else
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(1 downto 0);
end if;
when data2 => -- crs_dv = CRS
rx_shift(5 downto 4) <= rxd;
rx_state <= data3;
when data3 => -- crs_dv = DV
rx_shift(7 downto 6) <= rxd;
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(5 downto 4);
rx_state <= data0;
rx_valid <= '1';
when others =>
null;
end case;
if reset='1' then
eth_rx_sof <= '0';
eth_rx_eof <= '0';
eth_rx_data <= (others => '0');
rx_first <= '0';
rx_state <= idle;
end if;
end if;
end process;
rx_crc_sync <= '1' when rx_state = preamble else '0';
i_receive_crc: entity work.crc32
generic map (
g_data_width => 4
)
port map(
clock => clock,
clock_en => '1',
sync => rx_crc_sync,
data => rx_crc_data,
data_valid => rx_crc_dav,
crc => rx_crc
);
crc_ok <= '1' when (rx_crc = X"2144DF1C") else '0';
p_transmit: process(clock)
begin
if rising_edge(clock) then
case tx_state is
when idle =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if eth_tx_valid = '1' then
tx_state <= preamble;
tx_count <= 13;
end if;
when preamble =>
rmii_tx_en <= '1';
if tx_count = 0 then
rmii_txd <= "11";
tx_state <= data0;
else
rmii_txd <= "01";
tx_count <= tx_count - 1;
end if;
when data0 =>
if eth_tx_valid = '0' then
tx_state <= idle;
rmii_tx_en <= '0';
rmii_txd <= "00";
else
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(1 downto 0);
tx_state <= data1;
end if;
when data1 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(3 downto 2);
tx_state <= data2;
when data2 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(5 downto 4);
tx_state <= data3;
when data3 =>
tx_count <= 15;
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(7 downto 6);
if eth_tx_eof = '1' then
tx_state <= crc;
else
tx_state <= data0;
end if;
when crc =>
rmii_tx_en <= '1';
rmii_txd <= tx_crc(31 - tx_count*2 downto 30 - tx_count*2);
if tx_count = 0 then
tx_count <= 63;
tx_state <= gap;
else
tx_count <= tx_count - 1;
end if;
when gap =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if tx_count = 0 then
tx_state <= idle;
else
tx_count <= tx_count - 1;
end if;
when others =>
null;
end case;
if reset='1' then
rmii_tx_en <= '0';
rmii_txd <= "00";
tx_state <= idle;
end if;
end if;
end process;
eth_tx_ready <= '1' when tx_state = data3 else '0';
tx_crc_sync <= '1' when tx_state = preamble else '0';
with tx_state select tx_crc_data <=
eth_tx_data(1 downto 0) when data0,
eth_tx_data(3 downto 2) when data1,
eth_tx_data(5 downto 4) when data2,
eth_tx_data(7 downto 6) when data3,
"00" when others;
with tx_state select tx_crc_dav <=
'1' when data0 | data1 | data2 | data3,
'0' when others;
i_transmit_crc: entity work.crc32
generic map (
g_data_width => 2
)
port map(
clock => clock,
clock_en => '1',
sync => tx_crc_sync,
data => tx_crc_data,
data_valid => tx_crc_dav,
crc => tx_crc
);
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd | 1 | 3059 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_cpu_pkg is
-- Instruction bit 14..12: alu operation
-- Instruction bit 11: when 1, accu is updated
-- Instruction bit 15: when 0, flags are updated
-- Instruction Set (bit 10...0) are address when needed
-- ALU
constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
constant c_addc : std_logic_vector(15 downto 11) := X"6" & '1'; -- addc
constant c_in : std_logic_vector(15 downto 11) := X"7" & '1'; -- ext
-- constant c_shr : std_logic_vector(15 downto 11) := X"7" & '1'; -- shr
-- no update flags
constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- Specials
constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
constant c_branch : std_logic_vector(15 downto 14) := "11";
-- Branches (bit 10..0) are address
constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
constant c_br_c : std_logic_vector(13 downto 11) := "110"; -- carry
constant c_br_nc : std_logic_vector(13 downto 11) := "111"; -- not carry
constant c_call : std_logic_vector(15 downto 11) := c_branch & c_br_call;
-- ALU operations
constant c_alu_load : std_logic_vector(2 downto 0) := "000";
constant c_alu_or : std_logic_vector(2 downto 0) := "001";
constant c_alu_and : std_logic_vector(2 downto 0) := "010";
constant c_alu_xor : std_logic_vector(2 downto 0) := "011";
constant c_alu_add : std_logic_vector(2 downto 0) := "100";
constant c_alu_sub : std_logic_vector(2 downto 0) := "101";
constant c_alu_addc : std_logic_vector(2 downto 0) := "110";
constant c_alu_ext : std_logic_vector(2 downto 0) := "111";
end;
| gpl-3.0 |
chiggs/nvc | test/regress/attr2.vhd | 5 | 617 | entity attr2 is
end entity;
architecture test of attr2 is
type int3d is array (natural range <>,
natural range <>,
natural range <>) of integer;
procedure foo(x : in int3d) is
begin
assert x'length(1) = 2;
assert x'length(2) = 2;
assert x'length(3) = 10;
end procedure;
begin
process is
variable v : int3d(1 to 2, 1 downto 0, 10 to 19);
begin
assert v'length(1) = 2;
assert v'length(2) = 2;
assert v'length(3) = 10;
foo(v);
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_debug_pkg.vhd | 6 | 1235 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_debug_pkg is
type t_voice_debug is record
state : unsigned(1 downto 0);
enveloppe : unsigned(7 downto 0);
pre15 : unsigned(14 downto 0);
pre5 : unsigned(4 downto 0);
presc : unsigned(14 downto 0);
gate : std_logic;
attack : std_logic_vector(3 downto 0);
decay : std_logic_vector(3 downto 0);
sustain : std_logic_vector(3 downto 0);
release : std_logic_vector(3 downto 0);
end record;
type t_voice_debug_array is array(natural range <>) of t_voice_debug;
end;
| gpl-3.0 |
chiggs/nvc | test/regress/func2.vhd | 4 | 1220 | entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/pkg_6502_decode.vhd | 3 | 9508 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
| gpl-3.0 |
hoglet67/ElectronFpga | src/common/AlanD/R65Cx2.vhd | 1 | 61146 | -- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- signal counter : unsigned(27 downto 0);
-- signal mask_irq : std_logic;
-- signal mask_enable : std_logic;
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant irq : addrDef := "0000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
--aluModeBRK
--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal B: std_logic; -- Break software interrupt
signal R: std_logic; -- always 1
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
signal realbrk : std_logic;
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, R, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable tsxBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others => null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others => null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others => null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- DMB Remove Pipelining
-- process(clk)
-- begin
-- if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
-- end if;
-- end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch => nextCpuCycle <= cycle2;
when cycle2 => if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 => nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect => nextCpuCycle <= cycleIndirect;
when cycleIndirect => nextCpuCycle <= cycle3;
when cycleBranchTaken => if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead => if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 => if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw => nextCpuCycle <= cycleWrite;
when cyclePreWrite => nextCpuCycle <= cycleWrite;
when cycleStack1 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 => nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 => nextCpuCycle <= cycleRead;
when cycleJump => if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others => null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 => T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 => T <= di;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 => updateFlag := true;
when cycleStack3 => updateFlag := true;
when cycleStack4 => updateFlag := true;
when cycleRead => if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite => if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others => null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 => doReg <= PC(7 downto 0);
when cycleRmw => doReg <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWe <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '0';
end if;
when cycleRmw => theWe <= '0';
when cycleWrite => theWe <= '0';
when others => null;
end case;
end if;
end if;
--nwe <= theWe;
end process;
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch => PC <= myAddr;
when cycle2 => if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 => if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed;
when cycleIndirect => nextAddr <= nextAddrIncrL;
when cycleBranchTaken => nextAddr <= nextAddrRelative;
when cycleBranchPage => if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead => nextAddr <= nextAddrZPIndexed;
when cycleRead => nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncr;
--nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 => nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw => nextAddr <= nextAddrHold;
when cyclePreWrite => nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite => nextAddr <= nextAddrPc;
when cycleStack1 => nextAddr <= nextAddrStack;
when cycleStack2 => nextAddr <= nextAddrStack;
when cycleStack3 => nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 => nextAddr <= nextAddrIrq;
when cycleJump => nextAddr <= nextAddrAbs;
when others => null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= di & T;
when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0);
if theOpcode = x"7C" then
myAddr <= (di & T) + (x"00"& X);
else
myAddr <= di & indexOut(7 downto 0);
end if;
when nextAddrZeroPage => myAddr <= "00000000" & di;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
--
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch => sync <= '1';
-- when others => sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
Regs <= std_logic_vector(PC) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/JTAG_OCD_Prg/Resync16b_TCK.vhd | 4 | 1103 | --**********************************************************************************************
-- Resynchronizer(16 bit,TCK clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end Resync16b_TCK;
architecture RTL of Resync16b_TCK is
signal DIn_Tmp : std_logic_vector(DIn'range);
begin
ResynchronizerStageOne:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(Falling edge)
DIn_Tmp <= DIn; -- Stage 1
end if;
end process;
ResynchronizerStageTwo:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(Rising edge)
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
| gpl-3.0 |
DreamIP/GPStudio | support/process/dynthreshold/hdl/dynthreshold.vhd | 1 | 4251 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynthreshold is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynthreshold;
architecture rtl of dynthreshold is
component dynthreshold_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
desired_ratio_reg : in std_logic_vector(31 downto 0);
border_research_type_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dynthreshold_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
desired_ratio_reg : out std_logic_vector(31 downto 0);
border_research_type_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal desired_ratio_reg : std_logic_vector (31 downto 0);
signal border_research_type_reg : std_logic_vector (31 downto 0);
begin
dynthreshold_process_inst : dynthreshold_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
desired_ratio_reg => desired_ratio_reg,
border_research_type_reg => border_research_type_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dynthreshold_slave_inst : dynthreshold_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
desired_ratio_reg => desired_ratio_reg,
border_research_type_reg => border_research_type_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 |
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